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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3151.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03151ent_a IS
END c05s02b02x00p08n01i03151ent_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_a OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_c OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_c;
ARCHITECTURE c05s02b02x00p08n01i03151arch_b OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03151"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_b;
--
ENTITY c05s02b02x00p08n01i03151ent IS
END c05s02b02x00p08n01i03151ent;
ARCHITECTURE c05s02b02x00p08n01i03151arch OF c05s02b02x00p08n01i03151ent IS
component c05s02b02x00p08n01i03151ent_a
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03151ent_a;
END c05s02b02x00p08n01i03151arch;
configuration c05s02b02x00p08n01i03151cfg of c05s02b02x00p08n01i03151ent is
for c05s02b02x00p08n01i03151arch
end for;
end c05s02b02x00p08n01i03151cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3151.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03151ent_a IS
END c05s02b02x00p08n01i03151ent_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_a OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_c OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_c;
ARCHITECTURE c05s02b02x00p08n01i03151arch_b OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03151"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_b;
--
ENTITY c05s02b02x00p08n01i03151ent IS
END c05s02b02x00p08n01i03151ent;
ARCHITECTURE c05s02b02x00p08n01i03151arch OF c05s02b02x00p08n01i03151ent IS
component c05s02b02x00p08n01i03151ent_a
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03151ent_a;
END c05s02b02x00p08n01i03151arch;
configuration c05s02b02x00p08n01i03151cfg of c05s02b02x00p08n01i03151ent is
for c05s02b02x00p08n01i03151arch
end for;
end c05s02b02x00p08n01i03151cfg;
|
-- Implementation of Filter H_a2(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
package analytic_filter_h_a2_pkg is
component analytic_filter_h_a2
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a2_pkg;
package body analytic_filter_h_a2_pkg is
end analytic_filter_h_a2_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.fsf_comb_filter_pkg.all;
use work.fsf_pole_filter_pkg.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
use work.complex_fsf_filter_c_90_pkg.all;
use work.complex_fsf_filter_inv_c_m30_m150_pkg.all;
use work.resize_tools_pkg.all;
entity analytic_filter_h_a2 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a2;
architecture analytic_filter_h_a2_arch of analytic_filter_h_a2 is
--signal y : std_logic_vector (data_width-1 downto 0);
--signal x : std_logic_vector (data_width-1 downto 0);
signal data_i_res : std_logic_vector (data_width-1 downto 0);
signal t1 : std_logic_vector (data_width-1 downto 0);
signal c1_i : std_logic_vector (data_width-1 downto 0);
signal c1_q : std_logic_vector (data_width-1 downto 0);
signal t1_str : std_logic;
signal c1_str : std_logic;
begin
data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),1)),data_width);
real_pole_filter_1 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => data_i_res,
data_str_i => data_str_i,
data_o => t1,
data_str_o => t1_str
);
complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => t1,
data_q_i => (others => '0'),
data_str_i => t1_str,
data_i_o => c1_i,
data_q_o => c1_q,
data_str_o => c1_str
);
data_i_o <= c1_i;
data_q_o <= c1_q;
data_str_o <= c1_str;
end analytic_filter_h_a2_arch; |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
--
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Wolfgang April 2014
-- Ver 303 Bugfixes for NMI from foft
-- Ver 302 Bugfix for BRK command
-- Wolfgang January 2014
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);--NOTE:Make sure DI equals DO when writing. This is important for DCP/DCM undoc instruction. TODO:convert to inout
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal ALUmore : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
signal R_W_n_i_d : std_logic;
signal NMIActClear : std_logic; -- MWW hack
begin
-- workaround for ready-handling
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
----
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
ALUmore => ALUmore,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n, Clk)
variable tmpP:std_logic_vector(7 downto 0);--ML:Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n = '0' then
P <= x"00"; -- ensure we have nothing set on reset (e.g. B flag!)
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
if LDP = '1' then
-- P <= ALU_Q;-- Replaced with: --ML:no need anymore: AND x"EF"; -- NEVER set B on RTI and PLP
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
-- P(Flag_C) <= '0';-- Replaced with:
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
-- P(Flag_C) <= '1';
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
-- P(Flag_I) <= '0';
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
-- P(Flag_V) <= '0';
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
-- P(Flag_D) <= '0';
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
-- P(Flag_D) <= '1';
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
--ML:Removed change of B flag, its constant '1' in P
--ML:The B flag appears to be locked to '1', but when pushed to stack, the SR data on the stack has the B flag cleared on interrupts, set on BRK instr.
--ML:The state of the B flag on warm reset apparently is unchanged (not confirmed, please do if you know)
--ML:The state of the B flag on cold reset is uncertain, but my guess would be set, unless it can be used to detect cold from warm reset.
--Since we cant (well, won't) simulate B=0 on cold reset, we just behave as if it was constant 1.
-- P(Flag_B) <= '1';
tmpP(Flag_B) := '1';
-- if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then -- BRK
-- P(Flag_B) <= '1';
-- elsif IR = "00001000" then -- PHP
-- P(Flag_B) <= '1';
-- else
-- P(Flag_B) <= '0'; --> not the best way, but we keep B zero except for BRK and PHP opcodes
-- end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --and (NMICycle = '1' or IRQCycle = '1') then
--This should happen after P has been pushed to stack
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
end if;
if SO_n_o = '1' and SO_n = '0' then
-- P(Flag_V) <= '1';
tmpP(Flag_V) := '1';
end if;
if RstCycle = '1' then
-- P(Flag_I) <= '0';
-- P(Flag_D) <= '0';
tmpP(Flag_I) := '0';
tmpP(Flag_D) := '0';
end if;
-- P(Flag_1) <= '1';
tmpP(Flag_1) := '1';
P<=tmpP;--new way
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
end if;
NMI_n_o <= NMI_n; -- MWW: detect nmi even if not rdy
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
--if (Rdy = '1') then
BusA_r <= BusA;
if ALUmore='1' then
BusB <= ALU_Q;
else
BusB <= DI;
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
NMIActClear <= '0';
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
elsif NMIAct = '1' then -- MWW, force this to be changed by NMI, even if in midstream IRQ/brk
BAL(2 downto 0) <= "010";
NMIActClear <= '1';
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_S,
DBR & "00000000" & AD when Set_Addr_To_AD,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
--ML:This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
with Write_Data_r select
DO <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if (NMIActClear = '1') then
NMIAct <= '0';
end if;
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
end if;
if NMI_n_o = '1' and NMI_n = '0' then -- MWW: detect nmi even if not rdy
NMIAct <= '1';
end if;
end if;
end if;
end process;
end;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SettingsReg0
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GpibStatusReg is
port (
data_out : out std_logic_vector (15 downto 0);
-- gpib
currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
att : in std_logic; -- addressed to talk(L or LE)
tac : in std_logic; -- talker active (T, TE)
atl : in std_logic; -- addressed to listen (T or TE)
lac : in std_logic; -- listener active (L, LE)
cwrc : in std_logic; -- controller write commands
cwrd : in std_logic; -- controller write data
spa : in std_logic; -- seriall poll active
isLocal : in std_logic -- device is local controlled
);
end GpibStatusReg;
architecture arch of GpibStatusReg is
begin
data_out(4 downto 0) <= currentSecAddr;
data_out(5) <= att;
data_out(6) <= tac;
data_out(7) <= atl;
data_out(8) <= lac;
data_out(9) <= cwrc;
data_out(10) <= cwrd;
data_out(11) <= spa;
data_out(12) <= isLocal;
data_out(15 downto 13) <= "000";
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VGA_Top is
Port ( R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
Clk : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
button : in STD_LOGIC;
reset : in STD_LOGIC;
LED : out STD_LOGIC;
Enables : out STD_LOGIC_VECTOR(3 downto 0);
Segments : out STD_LOGIC_VECTOR(6 downto 0);
inColor : in STD_LOGIC_VECTOR (2 downto 0);
MoveUp : in STD_LOGIC;
MoveDown : in STD_LOGIC;
MoveLeft : in STD_LOGIC;
MoveRight : in STD_LOGIC;
MoveP1 : in STD_LOGIC;
MoveP2 : in STD_LOGIC);
end VGA_Top;
architecture Behavioral of VGA_Top is
COMPONENT Debouncer
PORT(
Clk : IN std_logic;
Button : IN std_logic;
Dout : OUT std_logic);
END COMPONENT;
COMPONENT Bresenhamer
PORT(
X1 : IN std_logic_vector(9 downto 0);
Y1 : IN std_logic_vector(8 downto 0);
X2 : IN std_logic_vector(9 downto 0);
Y2 : IN std_logic_vector(8 downto 0);
Clk : IN std_logic;
StartDraw : IN std_logic;
WriteEnable : OUT std_logic;
SS : OUT STD_LOGIC_VECTOR (3 downto 0);
X : OUT std_logic_vector(9 downto 0);
Y : OUT std_logic_vector(8 downto 0);
Reset : in STD_LOGIC);
END COMPONENT;
Component Synchronizer is
Port ( R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
Clk : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (2 downto 0);
AddressX : out STD_LOGIC_VECTOR (9 downto 0);
AddressY : out STD_LOGIC_VECTOR (8 downto 0));
end Component;
Component FrameBuffer is
Port ( inX : in STD_LOGIC_VECTOR (9 downto 0);
inY : in STD_LOGIC_VECTOR (8 downto 0);
outX : in STD_LOGIC_VECTOR (9 downto 0);
outY : in STD_LOGIC_VECTOR (8 downto 0);
outColor : out STD_LOGIC_VECTOR (2 downto 0);
inColor : in STD_LOGIC_VECTOR (2 downto 0);
BufferWrite : in STD_LOGIC;
Clk : in STD_LOGIC);
end Component;
COMPONENT SevenSegment
PORT( Clk : IN std_logic;
data : IN std_logic_vector(15 downto 0);
Enables : OUT std_logic_vector(3 downto 0);
Segments : OUT std_logic_vector(6 downto 0));
END COMPONENT;
COMPONENT Pointer
Generic (initX : STD_LOGIC_VECTOR (9 downto 0);
initY : STD_LOGIC_VECTOR (8 downto 0));
PORT( MoveUp : IN std_logic;
MoveDown : IN std_logic;
MoveLeft : IN std_logic;
MoveRight : IN std_logic;
Move : IN std_logic;
Clk : IN std_logic;
X : OUT std_logic_vector(9 downto 0);
Y : OUT std_logic_vector(8 downto 0);
syncX : IN std_logic_vector(9 downto 0);
syncY : IN std_logic_vector(8 downto 0);
Here : OUT std_logic);
END COMPONENT;
COMPONENT FreqDiv
PORT( Clk : IN std_logic;
Clk2 : OUT std_logic);
END COMPONENT;
signal Adx,GPU_X : STD_LOGIC_VECTOR (9 downto 0);
signal Ady,GPU_Y : STD_LOGIC_VECTOR (8 downto 0);
signal data : STD_LOGIC_VECTOR (2 downto 0);
signal GIM : STD_LOGIC_VECTOR (22 downto 0);
signal GPU_COLOR_TO_BUFFER : STD_LOGIC_VECTOR (2 downto 0);
signal BufferWrite : STD_LOGIC;
signal Dout : STD_LOGIC;
signal SS : STD_LOGIC_VECTOR (3 downto 0);
signal Clk2 : STD_LOGIC;
signal P1Region,p2Region : STD_LOGIC;
signal Rt,Gt,Bt : STD_LOGIC;
signal X1,X2 : STD_LOGIC_VECTOR (9 downto 0);
signal Y1,Y2 : STD_LOGIC_VECTOR (8 downto 0);
begin
ins_FrameBuffer : FrameBuffer PORT MAP (
inX => GPU_X,
inY => GPU_Y,
outX => Adx,
outY => Ady,
outColor => data,
inColor => inColor,
BufferWrite => BufferWrite,
Clk => Clk);
ins_Synchronizer : Synchronizer PORT MAP (
R => Rt,
G => Gt,
B => Bt,
HS => HS,
VS => VS,
Clk => Clk,
dataIn => data,
AddressX => Adx,
AddressY => Ady);
Inst_Debouncer: Debouncer PORT MAP(
Clk => Clk,
Button => Button,
Dout => Dout);
Inst_Bresenhamer: Bresenhamer PORT MAP(
WriteEnable => BufferWrite,
X => GPU_X,
Y => GPU_Y,
X1 => X1,
Y1 => Y1,
X2 => X2,
Y2 => Y2,
Clk => Clk,
SS => SS,
Reset => reset,
StartDraw => Dout);
LED <= BufferWrite;
R <= Rt when (P1Region='0' and P2Region='0') else not Rt;
G <= Gt when (P1Region='0' and P2Region='0') else not Gt;
B <= Bt when (P1Region='0' and P2Region='0') else not Bt;
Inst_SevenSegment: SevenSegment PORT MAP(
Clk => Clk,
Enables => Enables,
Segments => Segments,
data(3 downto 0) => SS,
data(15 downto 4) => "000000000000");
Inst_Pointer1: Pointer
GENERIC MAP (initX => "0000000100",
initY => "011110000")
PORT MAP(
MoveUp => MoveUp,
MoveDown => MoveDown,
MoveLeft => MoveLeft,
MoveRight => MoveRight,
Move => MoveP1,
Clk => Clk2,
Here => P1Region,
X => X1,
Y => Y1,
syncX => Adx,
syncY => Ady);
Inst_FreqDiv: FreqDiv PORT MAP(
Clk => Clk,
Clk2 => Clk2);
Inst_Pointer2: Pointer
GENERIC MAP (InitX => "1001111000",
InitY => "011110000")
PORT MAP(
MoveUp => MoveUp,
MoveDown => MoveDown,
MoveLeft => MoveLeft,
MoveRight => MoveRight,
Move => MoveP2,
Clk => Clk2,
Here => P2Region,
X => X2,
Y => Y2,
syncX => Adx,
syncY => Ady);
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block3
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_2_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_10_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_10_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_9_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_10_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_10_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block3 IS
-- Signals
SIGNAL dout_2_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_2_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_10_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_10_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_9_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_9_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_10_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_10_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_2_re_signed <= signed(dout_2_re);
din1_re <= resize(dout_2_re_signed, 20);
dout_2_im_signed <= signed(dout_2_im);
din1_im <= resize(dout_2_im_signed, 20);
dout_10_re_signed <= signed(dout_10_re);
din2_re <= resize(dout_10_re_signed, 20);
dout_10_im_signed <= signed(dout_10_im);
din2_im <= resize(dout_10_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_9)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_9 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_9_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re_1 <= std_logic_vector(dout_10_re_tmp);
dout_10_im_1 <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
--
-- keymap.vhd
-- keymap ROM tables for eseps2.vhd
-- Revision 1.00
--
-- Copyright (c) 2006 Kazuhiro Tsujikawa (ESE Artists' factory)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- 2013.08.12 modified by KdL
-- Added RWIN and LWIN usable as alternatives to the space-bar.
--
-- 2015.05.20 - Brazilian ABNT2 keymap by Fabio Belavenuto
-- 2016.11 - Implemented Keymap change via software (SWIOPORTS)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity keymap is
port (
clock_i : in std_logic;
we_i : in std_logic;
addr_wr_i : in std_logic_vector(8 downto 0);
data_i : in std_logic_vector(7 downto 0);
addr_rd_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture RTL of keymap is
signal read_addr_q : unsigned(8 downto 0);
type ram_t is array (0 to 511) of std_logic_vector(7 downto 0);
signal ram_q : ram_t := (
--
-- bit 7 F 6 E 5 D 4 C 3 B 2 A 1 9 0 8
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 0 | 7 & | 6 ^ | 5 % | 4 $ | 3 # | 2 @ | 1 ! | 0 ) | 0
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 1 | ; : | ] } | [ { | \ | | = + | - _ | 9 ( | 8 * | 1
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 2 | B | A |DEAD | / ? | . > | , < | ` ~ | ' " | 2
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 3 | J | I | H | G | F | E | D | C | 3
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 4 | R | Q | P | O | N | M | L | K | 4
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 5 | Z | Y | X | W | V | U | T | S | 5
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 6 | F3 | F2 | F1 | Code|CapsL|Graph| Ctrl|Shift| 6
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 7 |Enter|Selec| BS | Stop| Tab | Esc | F5 | F4 | 7
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 8 |Right| Down| Up | Left| Del | Ins | Home|Space| 8
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 9 | [4] | [3] | [2] | [1] | [0] | [/] | [+] | [*] | 9
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 10| [.] | [,] | [-] | [9] | [8] | [7] | [6] | [5] | A
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- bit 7 F 6 E 5 D 4 C 3 B 2 A 1 9 0 8
--------------------------------------------
-- 108 Keys Brazilian keyboard: Scancode --
--------------------------------------------
-- F9 F5 F3 F1 F2 F12
X"FF", X"FF", X"FF", X"17", X"76", X"56", X"66", X"FF", -- 00..07
-- F10 F8 F6 F4 Tab '/"
X"FF", X"FF", X"FF", X"FF", X"07", X"37", X"02", X"FF", -- 08..0F
-- LAlt LShft LCtrl Q 1/!
X"FF", X"26", X"06", X"FF", X"16", X"64", X"10", X"FF", -- 10..17
-- Z S A W 2/@
X"FF", X"FF", X"75", X"05", X"62", X"45", X"20", X"FF", -- 18..1F
-- C X D E 4/$ 3/#
X"FF", X"03", X"55", X"13", X"23", X"40", X"30", X"FF", -- 20..27
-- Space V F T R 5/%
X"FF", X"08", X"35", X"33", X"15", X"74", X"50", X"FF", -- 28..2F
-- N B H G Y 6/¨
X"FF", X"34", X"72", X"53", X"43", X"65", X"60", X"FF", -- 30..37
-- M J U 7/& 8/*
X"FF", X"FF", X"24", X"73", X"25", X"70", X"01", X"FF", -- 38..3F
-- ,/< K I O 0/) 9/(
X"FF", X"22", X"04", X"63", X"44", X"00", X"11", X"FF", -- 40..47
-- ./> ;/: L Ç P -/_
X"FF", X"32", X"71", X"14", X"FF", X"54", X"21", X"FF", -- 48..4F
-- //? ~/^ ´/` =/+
X"FF", X"42", X"12", X"FF", X"52", X"31", X"FF", X"FF", -- 50..57
-- CapLk RShft Enter [/{ ]/}
X"36", X"06", X"77", X"51", X"FF", X"61", X"FF", X"FF", -- 58..5F
-- \/| BS
X"FF", X"14", X"FF", X"FF", X"FF", X"FF", X"57", X"FF", -- 60..67
-- [1] [4] [7] [.]
X"FF", X"49", X"FF", X"79", X"2A", X"7A", X"FF", X"FF", -- 68..6F
-- [0] [,] [2] [5] [6] [8] Esc NLock
X"39", X"6A", X"59", X"0A", X"1A", X"3A", X"27", X"FF", -- 70..77
-- F11 [+] [3] [-] [*] [9] ScrLk
X"FF", X"19", X"69", X"5A", X"09", X"4A", X"FF", X"FF", -- 78..7F
-- F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 80..87
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 88..8F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 90..97
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 98..9F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A0..A7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A8..AF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B0..B7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B8..BF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C0..C7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C8..CF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D0..D7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D8..DF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E0..E7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E8..EF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0..F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F8..FF
-------------------------------------------------
-- 108 Keys Brazilian keyboard: E0 + Scan Code --
-------------------------------------------------
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 00..07
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 08..0F
-- RAlt PrtSc RCtrl
X"FF", X"26", X"FF", X"FF", X"16", X"FF", X"FF", X"FF", -- 10..17
-- LWin
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"08", -- 18..1F (LWIN = $1F = SPACE)
-- RWin
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"08", -- 20..27 (RWIN = $27 = SPACE)
-- Menu
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 28..2F (MENU = $2F = 'M' key)
-- Power
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 30..37
-- Sleep
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 38..3F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 40..47
-- [/]
X"FF", X"FF", X"29", X"FF", X"FF", X"FF", X"FF", X"FF", -- 48..4F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 50..57
-- [Enter] Wake
X"FF", X"FF", X"77", X"FF", X"FF", X"FF", X"FF", X"FF", -- 58..5F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 60..67
-- End Left Home
X"FF", X"47", X"FF", X"48", X"18", X"FF", X"FF", X"FF", -- 68..6F
-- Ins Supr Down Right Up
X"28", X"38", X"68", X"FF", X"78", X"58", X"FF", X"FF", -- 70..77
-- PDown PUp
X"FF", X"FF", X"46", X"FF", X"FF", X"67", X"FF", X"FF", -- 78..7F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 80..87
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 88..8F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 90..97
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 98..9F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A0..A7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A8..AF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B0..B7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B8..BF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C0..C7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C8..CF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D0..D7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D8..DF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E0..E7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E8..EF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0..F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF" -- F8..FF
);
begin
process (clock_i)
begin
if rising_edge(clock_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_wr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_rd_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end RTL;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_s2m_memory_dc.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
-- Design note: Normally, a gray counter is implemented using a binary counter
-- and transfor the output to gray. However, in this design, the number of bit
-- for the gray counters is 4 worst case (C_MULTIBUFFER_DEPTH = 8). In this
-- situation we can use a look-up based approach (LUT4 for each bit). For a
-- gray counter of N bits, gray_inc function should infer a table of 2**N elements.
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
use axis_accelerator_adapter_v2_1_6.iarg_columnized_mem_bank;
entity xd_s2m_memory_dc is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
CONV_DATA_WIDTH : integer;
CONV_ADDR_WIDTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_NONE : integer := 2;
C_EXTRA_SYNCS : integer := 1);
port (
clk : in std_logic;
rst : in std_logic;
conv_addr : in std_logic_vector(CONV_ADDR_WIDTH-1 downto 0);
conv_ce : in std_logic;
conv_we : in std_logic;
conv_last : in std_logic;
conv_rdy : out std_logic;
conv_data : in std_logic_vector(CONV_DATA_WIDTH-1 downto 0);
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
mb_arg_rdy : out std_logic;
mb_arg_done : in std_logic;
status_empty : out std_logic := '0';
status_full : out std_logic := '1';
status_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_s2m_memory_dc is
------------------------------------
function calc_use_columnized_bank return boolean is
variable ret : boolean := false;
begin
if (C_AP_ARG_N_DIM = 2) then
if(C_AP_ARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
if(C_AP_ARG_FORMAT_DIM = 1 and C_AP_ARG_FORMAT_FACTOR > 1) then
ret := true;
end if;
end if;
end if;
return ret;
end function calc_use_columnized_bank;
constant PTR_WIDTH : integer := if_then_else((C_MULTIBUFFER_DEPTH = 1),1,log2(C_MULTIBUFFER_DEPTH));
constant GRAY_WIDTH : integer := calc_gray_width(C_MULTIBUFFER_DEPTH);
constant INIT_RD_GRAY : integer := 0;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := INIT_RD_GRAY-C_MULTIBUFFER_DEPTH+1;
constant USE_COLUMNIZED_BANK : boolean := calc_use_columnized_bank;
signal empty_n : std_logic;
signal ap_rstn : std_logic;
signal rstn : std_logic;
signal mb_arg_rdy_i : std_logic;
signal full_n : std_logic;
-- pragma translate_off
signal empty : std_logic;
signal full : std_logic;
-- pragma translate_on
signal status_empty_i : std_logic;
-- Multibuffer push/pop
signal mb_push : std_logic;
signal m_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal mb_pop : std_logic;
signal mb_push_ok : std_logic;
signal mb_pop_ok : std_logic;
-- Selection for read buffer
signal rd_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal rd_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_pntr_wr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal axis_rd_data_count : std_logic_vector(PTR_WIDTH downto 0);
signal rd_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_gray_wr : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray_wr: std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Gray read counter synchronized with read clk
signal rd_gray_sync : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal rd_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal wr_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal ptr_dist : unsigned(GRAY_WIDTH-1 downto 0);
signal pntr_dist : std_logic_vector(PTR_WIDTH-1 downto 0);
-- Selection for write buffer
signal wr_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal wr_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_pntr_rd : std_logic_vector(PTR_WIDTH-1 downto 0);
signal axis_wr_data_count : std_logic_vector(PTR_WIDTH downto 0);
signal wr_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer is filled is last data beat is written and the multibuffer is
-- not full
mb_push <= full_n and conv_ce and conv_last;
-- Active buffer has been consumed when signal "mb_arg_done" is activated and
-- the multibuffer is not empty.
mb_pop <= empty_n and mb_arg_done;
-- Pointer to write buffer
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_ptr <= (others => '0');
wr_ptr_dec <= (others => '0');
wr_ptr_dec(0) <= '1';
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
if(wr_ptr = C_MULTIBUFFER_DEPTH-1) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
wr_ptr_dec <= wr_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & wr_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD,GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
end if;
end if;
end process;
-- Generation of status full signal
process(clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(clk'event and clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Move to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Selection pointer for read buffer (pop)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
rd_ptr <= (others => '0');
rd_ptr_dec <= (others => '0');
rd_ptr_dec(0) <= '1';
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
if(rd_ptr = C_MULTIBUFFER_DEPTH-1) then
rd_ptr <= (others => '0');
else
rd_ptr <= rd_ptr + 1;
end if;
rd_ptr_dec <= rd_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & rd_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (read) to manage the status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
end if;
end if;
end process;
-- Generation of empty status signal
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
empty_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
mb_pop_ok <= mb_pop and empty_n;
conv_rdy <= full_n;
mb_arg_rdy <= empty_n;
-----------------
-- STATUS INFO --
-----------------
-- Following logic is used to provide status information to software. Among
-- others this information includes:
-- * empty signal
-- * full signal
-- * Number of buffers used
-- All this status information should be provided on the AXI clock domain
-- NUMBER OF USED BUFFERS:
-- this value is calculated based on the distance between the read and write
-- pointers.
-- Synchronization of rd_gray to reduce metastability issues. This will
-- introduce a latency of one clock on rd_clk
process(clk, ap_rst)
begin
if(ap_rst = '1') then
rd_gray_sync <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
rd_gray_sync <= rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_bin <= to_unsigned(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
-- If comparing pointers happens during write, then there will be a one cycle
-- latency to reflect the status of the fifo. To refresh inmediately, during
-- a write we increment the counter.
process(clk, ap_rst)
begin
if(ap_rst = '1') then
ptr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
ptr_dist <= ptr_dist + 1;
else
-- This is also valid when we arrive at the end of counting sequence
-- for wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
process(ptr_dist)
begin
status_used <= (others => '0');
status_used(ptr_dist'range) <= std_logic_vector(ptr_dist);
end process;
-- STATUS FULL:
-- this signal is generated in the AXI clock domain; Hence, status_full
-- is just a simple copy of the internal signal
status_full <= not(full_n);
-- STATUS EMPTY:
-- This signal represents the empty status of the multibiffer from the point
-- of view of the write port (AXI clock domain)
process(clk, ap_rst)
begin
if(ap_rst = '1') then
status_empty_i <= '1';
elsif(clk'event and clk = '1') then
-- If write, we exit the empty condition inmediately
if(mb_push_ok = '1') then
status_empty_i <= '0';
else
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
status_empty_i <= '1';
else
status_empty_i <= '0';
end if;
end if;
end if;
end process;
status_empty <= status_empty_i;
end generate EXISTING;
------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
CONSTANT LOG2DEPTH : integer := log2(C_MULTIBUFFER_DEPTH);
CONSTANT ONE : std_logic_vector(PTR_WIDTH-1 DOWNTO 0)
:= int2lv(1, PTR_WIDTH);
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
ap_rstn <= not(ap_rst);
rstn <= not(rst);
-- pragma translate_on
-- New buffer is filled is last data beat is written and the multibuffer is
-- not full
mb_push <= full_n and conv_ce and conv_last;
-- Active buffer has been consumed when signal "mb_arg_done" is activated and
-- the multibuffer is not empty.
mb_pop <= empty_n and mb_arg_done;
-- Pointer to write buffer
process(clk, rst)
begin
if(rst = '1') then
wr_pntr <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
if(wr_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
wr_pntr <= (others => '0');
else
wr_pntr <= wr_pntr + ONE;
end if;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
rd_pntr <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
if(rd_pntr =int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
rd_pntr <= (others => '0');
else
rd_pntr <= rd_pntr + ONE;
end if;
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD,GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
end if;
end if;
end process;
-- Gray pointers (read) to manage the status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
end if;
end if;
end process;
clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_gray,
RD_PNTR => rd_gray,
WR_PNTR_RD => wr_gray_rd,
RD_PNTR_WR => rd_gray_wr
);
clkx_2: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_gray_ahead,
RD_PNTR => next_rd_gray,
WR_PNTR_RD => wr_gray_ahead_rd,
RD_PNTR_WR => next_rd_gray_wr
);
clkx_3: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => PTR_WIDTH,
C_WR_PNTR_WIDTH => PTR_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_pntr,
RD_PNTR => rd_pntr,
WR_PNTR_RD => wr_pntr_rd,
RD_PNTR_WR => rd_pntr_wr
);
-- Generation of status full signal
process(clk, rst)
begin
if(rst = '1') then
full_n <= '0';
elsif(clk'event and clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray_wr) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Move to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray_wr) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Generation of empty status signal
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
empty_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray_rd) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray_rd) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
mb_pop_ok <= mb_pop and empty_n;
conv_rdy <= full_n;
mb_arg_rdy <= empty_n;
-- AP_IRGRDY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 1,
-- C_VECTOR_WIDTH => 2,
-- C_MTBF_STAGES => C_MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => ap_clk,
-- prmry_resetn => ap_rstn,
-- prmry_in => mb_arg_rdy_i,
-- prmry_vect_in => (others=>'0'),
--
-- scndry_aclk => clk,
-- scndry_resetn => rstn,
-- scndry_out => mb_arg_rdy,
-- scndry_vect_out => open
-- );
MBn : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
pntr_dist <= pntr_dist + 1;
else
-- pntr_dist <= ('0' & wr_pntr) - ( '0' & rd_pntr_wr);
pntr_dist <= ( wr_pntr) - ( rd_pntr_wr);
--pntr_dist <= ( wr_bins) - ( rd_bins);
end if;
end if;
end process;
end generate MBn;
MB1 : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
rd_bins <= rd_gray_wr;
process(clk, rst)
begin
if(rst = '1') then
wr_bins <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_bins <= wr_bins + 1;
end if;
end if;
end process;
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
pntr_dist <= pntr_dist + 1;
else
pntr_dist <= ( wr_bins) - ( rd_bins);
end if;
end if;
end process;
end generate MB1;
process(pntr_dist)
begin
status_used <= (others => '0');
status_used(pntr_dist'range) <= (pntr_dist);
end process;
-- STATUS FULL:
-- this signal is generated in the AXI clock domain; Hence, status_full
-- is just a simple copy of the internal signal
status_full <= not(full_n);
-- STATUS EMPTY:
-- This signal represents the empty status of the multibiffer from the point
-- of view of the write port (AXI clock domain)
process(clk, rst)
begin
if(rst = '1') then
status_empty_i <= '1';
elsif(clk'event and clk = '1') then
-- If write, we exit the empty condition inmediately
if(mb_push_ok = '1') then
status_empty_i <= '0';
else
-- Stay in empty if rd_gray = wr_gray
if(rd_gray_wr = wr_gray) then
status_empty_i <= '1';
else
status_empty_i <= '0';
end if;
end if;
end if;
end process;
status_empty <= status_empty_i;
end generate NEW_INTRO;
LINEAR_BANK_GEN : if not(USE_COLUMNIZED_BANK) generate
-- Efective width for input address bus (conv_addr)
function calc_eff_addr_width return integer is
variable addr_width : integer;
begin
if(CONV_DATA_WIDTH > C_AP_ARG_DATA_WIDTH) then
addr_width := C_AP_ARG_ADDR_WIDTH-log2(CONV_DATA_WIDTH/C_AP_ARG_DATA_WIDTH);
else
addr_width := C_AP_ARG_ADDR_WIDTH+log2(C_AP_ARG_DATA_WIDTH/CONV_DATA_WIDTH);
end if;
return addr_width;
end function calc_eff_addr_width;
constant EFF_ADDR_WIDTH : integer := calc_eff_addr_width;
constant IPORT_ADDR_WIDTH : integer := EFF_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
constant OPORT_ADDR_WIDTH : integer := C_AP_ARG_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
signal iport_addr : std_logic_vector(IPORT_ADDR_WIDTH-1 downto 0);
-- Width of address bus of output port is the addition of number of bits
-- required by input argument plus the required bits to select the
-- appropiate bank (PTR_WIDTH).
signal oport_addr : std_logic_vector(OPORT_ADDR_WIDTH-1 downto 0);
begin
MB1_addr : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
iport_addr <= conv_addr(EFF_ADDR_WIDTH-1 downto 0);
oport_addr <= ap_arg_addr;
end generate MB1_addr;
MBn_addr : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
iport_addr <= std_logic_vector(wr_pntr) & conv_addr(EFF_ADDR_WIDTH-1 downto 0);
oport_addr <= std_logic_vector(rd_pntr) & ap_arg_addr;
end generate MBn_addr;
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 1,
C_IPORT_DWIDTH => CONV_DATA_WIDTH,
C_IPORT_AWIDTH => IPORT_ADDR_WIDTH,
C_OPORT_DWIDTH => C_AP_ARG_DATA_WIDTH,
C_OPORT_AWIDTH => OPORT_ADDR_WIDTH)
port map (
rst => ap_rst,
iport_clk => clk,
iport_ce => conv_ce,
iport_we => '1',
iport_addr => iport_addr,
iport_din => conv_data,
iport_dout => open,
oport_clk => ap_clk,
oport_ce => ap_arg_ce,
oport_we => ap_arg_we,
oport_addr => oport_addr,
oport_din => ap_arg_din,
oport_dout => ap_arg_dout);
end generate LINEAR_BANK_GEN;
COLUMNIZED_BANK_GEN : if (USE_COLUMNIZED_BANK) generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.iarg_columnized_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_BUFFER_WIDTH => PTR_WIDTH,
C_CONV_AWIDTH => CONV_ADDR_WIDTH,
C_CONV_DWIDTH => CONV_DATA_WIDTH,
C_ARG_WIDTH => C_AP_ARG_WIDTH,
C_ARG_AWIDTH => C_AP_ARG_ADDR_WIDTH)
port map (
ap_rst => ap_rst,
clk => clk,
conv_ce => conv_ce,
conv_we => conv_we,
conv_buffer => std_logic_vector(wr_ptr),
conv_addr => conv_addr,
conv_data => conv_data,
ap_clk => ap_clk,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_buffer => std_logic_vector(rd_ptr),
ap_arg_addr => ap_arg_addr,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout);
end generate COLUMNIZED_BANK_GEN;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
entity cached_mblite is
port (
clock : in std_logic;
reset : in std_logic;
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
dmem_o : out dmem_out_type;
dmem_i : in dmem_in_type;
imem_o : out dmem_out_type;
imem_i : in dmem_in_type;
irq_i : in std_logic;
irq_o : out std_logic );
end entity;
architecture structural of cached_mblite is
-- signals from processor to cache
signal cimem_o : imem_out_type;
signal cimem_i : imem_in_type;
signal cdmem_o : dmem_out_type;
signal cdmem_i : dmem_in_type;
BEGIN
core0 : core
port map (
imem_o => cimem_o,
imem_i => cimem_i,
dmem_o => cdmem_o,
dmem_i => cdmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
i_cache: entity work.dm_simple
generic map (
g_data_register => true,
g_mem_direct => true )
port map (
clock => clock,
reset => reset,
dmem_i.adr_o => cimem_o.adr_o,
dmem_i.ena_o => cimem_o.ena_o,
dmem_i.sel_o => "0000",
dmem_i.we_o => '0',
dmem_i.dat_o => (others => '0'),
dmem_o.ena_i => cimem_i.ena_i,
dmem_o.dat_i => cimem_i.dat_i,
mem_o => imem_o,
mem_i => imem_i );
d_cache: entity work.dm_with_invalidate
-- generic map (
-- g_address_swap => X"00010000"
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_i => cdmem_o,
dmem_o => cdmem_i,
mem_o => dmem_o,
mem_i => dmem_i );
-- arb: entity work.dmem_arbiter
-- port map (
-- clock => clock,
-- reset => reset,
-- imem_i => imem_o,
-- imem_o => imem_i,
-- dmem_i => dmem_o,
-- dmem_o => dmem_i,
-- mmem_o => mmem_o,
-- mmem_i => mmem_i );
--
-- process(clock)
-- begin
-- if rising_edge(clock) then
-- if cdmem_i.ena_i='1' and cimem_i.ena_i='1' then
-- stuck <= '0';
-- stuck_cnt <= 0;
-- elsif stuck_cnt = 31 then
-- stuck <= '1';
-- else
-- stuck_cnt <= stuck_cnt + 1;
-- end if;
-- end if;
-- end process;
end architecture;
|
-- Project generated by script.
-- Date: Seg,05/05/2014-11:48:02
-- Author:
-- Comments: Entity Description: unidade_a2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity unidade_a2 is
port (x, y, z, w: in <<type>>; s: out <<type>>);
end unidade_a2;
architecture estrutural of unidade_a2 is
-- Declaration of Components.
component <<COMPONENT_NAME>>
port(<<ports_in>>: in <<type>>; <<ports_out>>: out <<type>>);
end component;
-- Signals declaration.
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;
begin
-- Commands.
-- Component instantiation and port mapping.
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
end estrutural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2202.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02202ent IS
END c07s02b06x00p01n01i02202ent;
ARCHITECTURE c07s02b06x00p01n01i02202arch OF c07s02b06x00p01n01i02202ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x / y; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02202 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02202arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2202.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02202ent IS
END c07s02b06x00p01n01i02202ent;
ARCHITECTURE c07s02b06x00p01n01i02202arch OF c07s02b06x00p01n01i02202ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x / y; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02202 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02202arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2202.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02202ent IS
END c07s02b06x00p01n01i02202ent;
ARCHITECTURE c07s02b06x00p01n01i02202arch OF c07s02b06x00p01n01i02202ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x / y; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02202 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02202arch;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_sfifo_autord;
use axi_sg_v4_1.axi_sg_afifo_autord;
-------------------------------------------------------------------------------
entity axi_sg_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
-- coverage off
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- coverage on
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_sg_v4_1.axi_sg_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture rtl of clk_gen is
constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2);
signal count : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
clk_s <= '0';
elsif rising_edge(clk) then
if count = COUNT_MAX - 1 then
count <= 0;
if clk_s = '1' then
clk_s <= '0';
else
clk_s <= '1';
end if;
else
count <= count + 1;
end if;
end if;
end process;
clk_out <= clk_s;
end architecture;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture rtl of clk_gen is
constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2);
signal count : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
clk_s <= '0';
elsif rising_edge(clk) then
if count = COUNT_MAX - 1 then
count <= 0;
if clk_s = '1' then
clk_s <= '0';
else
clk_s <= '1';
end if;
else
count <= count + 1;
end if;
end if;
end process;
clk_out <= clk_s;
end architecture;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture rtl of clk_gen is
constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2);
signal count : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
clk_s <= '0';
elsif rising_edge(clk) then
if count = COUNT_MAX - 1 then
count <= 0;
if clk_s = '1' then
clk_s <= '0';
else
clk_s <= '1';
end if;
else
count <= count + 1;
end if;
end if;
end process;
clk_out <= clk_s;
end architecture;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture rtl of clk_gen is
constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2);
signal count : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
clk_s <= '0';
elsif rising_edge(clk) then
if count = COUNT_MAX - 1 then
count <= 0;
if clk_s = '1' then
clk_s <= '0';
else
clk_s <= '1';
end if;
else
count <= count + 1;
end if;
end if;
end process;
clk_out <= clk_s;
end architecture;
|
-- Test vectors for the synthesis test for the fixed point math package
-- This test is designed to test fixed_synth and exercise much of the entity.
-- Created for vhdl-200x by David Bishop ([email protected])
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
-- --------------------------------------------------------------------
entity test_fixed_synth is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity test_fixed_synth;
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_pkg.all;
architecture testbench of test_fixed_synth is
procedure report_error (
constant errmes : in string; -- error message
actual : in sfixed; -- data from algorithm
constant expected : in sfixed) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & CR
& "Actual: " & to_string(actual)
& " (" & real'image(to_real(actual)) & ")" & CR
& " /= " & to_string(expected)
& " (" & real'image(to_real(expected)) & ")"
severity error;
return;
end procedure report_error;
-- Device under test. Note that all inputs and outputs are std_logic_vector.
-- This entity can be use both pre and post synthesis.
component fixed_synth is
port (
in1, in2 : in std_logic_vector (15 downto 0); -- inputs
out1 : out std_logic_vector (15 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end component fixed_synth;
constant clock_period : time := 500 ns; -- clock period
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
signal stop_clock : boolean := false; -- stop the clock
signal clk, rst_n : std_ulogic; -- clk and reset
signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
signal in1, in2 : sfixed16; -- inputs
signal out1 : sfixed16; -- output
signal cmd : std_logic_vector (3 downto 0); -- command string
begin -- architecture testbench
-- From fixed point to Std_logic_vector
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
-- Std_logic_vector to fixed point.
out1 <= to_sfixed(out1slv, out1'high, out1'low);
DUT: fixed_synth
port map (
in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
cmd => cmd, -- [in std_logic_vector (2 downto 0)]
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- purpose: clock driver
clkprc: process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
reset_proc: process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
tester: process is
begin -- process tester
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0001"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0010"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0011"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
cmd <= "0100"; -- unsigned add
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0101"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0110"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0100"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0111"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
-- resize
cmd <= "1000";
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-5.25, in2);
wait for clock_period;
in1 <= to_sfixed (21.125, in1);
in2 <= to_sfixed (21.125, in2);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (3, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-5.5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010"; -- abs (mod)
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-42, in1);
wait for clock_period;
cmd <= "1011"; -- mod
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1100"; -- REM
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1101"; -- srl
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-1, in2);
wait for clock_period;
cmd <= "1110"; -- sra
in1 <= to_sfixed (-7.25, in1);
in2 <= to_sfixed (1, in2);
wait for clock_period;
cmd <= "1111"; -- compare
in1 <= to_sfixed (42, in1);
in2 <= to_sfixed (42, in1);
wait for clock_period;
in1 <= to_sfixed (45, in1);
in2 <= to_sfixed (90, in1);
wait for clock_period;
in1 <= to_sfixed (3.125, in1);
in2 <= (others => '0');
wait for clock_period;
in1 <= "0110111110101111";
in2 <= "1111111111111111";
wait for clock_period;
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
in1 <= "0000111000000000";
in2 <= "0000111000000000";
wait for clock_period;
in1 <= (others => '1');
in2 <= (others => '1');
wait for clock_period;
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest: process is
constant fxzero : sfixed16 := (others => '0'); -- zero
variable chks16 : sfixed16; -- variable
variable sm1, sm2 : sfixed7; -- small fixed point
begin -- process checktest
wait for clock_period/2.0;
wait for clock_period;
wait for clock_period;
waitloop: while (out1 = fxzero) loop
wait for clock_period;
end loop waitloop;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
report_error ( "-0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
report_error ( "6.5/0.5 error",
out1,
chks16);
wait for clock_period;
-- resize test
sm1 := out1 (7 downto 1);
sm2 := to_sfixed (5.25, sm2);
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := to_sfixed (-5.25, sm2);
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
sm1 := out1 (7 downto 1);
sm2 := "0101001"; -- wrapped
-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := "0111111"; -- saturate
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
-- to_signed and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_unsigned and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
-- to_integer and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_integer(ufixed) and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
wait for clock_period;
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
wait for clock_period;
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
wait for clock_period;
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
wait for clock_period;
report_error ("abs(-42)", out1, to_sfixed (42, out1));
wait for clock_period;
report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
chks16 := "0000101010000000";
report_error ("5.25 srl -1", out1, chks16);
wait for clock_period;
chks16 := "1111110001100000";
report_error ("-7.25 sra 1", out1, chks16);
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "42=42 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------0001010110";
assert (std_match (out1, chks16))
report "45=90 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------1010101010";
assert (std_match (out1, chks16))
report "3.125=0 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0--1010000101010";
assert (std_match (out1, chks16))
report "pattern1 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0001100000110001";
assert (std_match (out1, chks16))
report "zero = zero " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "1111000000110001";
assert (std_match (out1, chks16))
report "pattern2 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "-1 = -1 " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
|
-- Test vectors for the synthesis test for the fixed point math package
-- This test is designed to test fixed_synth and exercise much of the entity.
-- Created for vhdl-200x by David Bishop ([email protected])
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
-- --------------------------------------------------------------------
entity test_fixed_synth is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity test_fixed_synth;
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_pkg.all;
architecture testbench of test_fixed_synth is
procedure report_error (
constant errmes : in string; -- error message
actual : in sfixed; -- data from algorithm
constant expected : in sfixed) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & CR
& "Actual: " & to_string(actual)
& " (" & real'image(to_real(actual)) & ")" & CR
& " /= " & to_string(expected)
& " (" & real'image(to_real(expected)) & ")"
severity error;
return;
end procedure report_error;
-- Device under test. Note that all inputs and outputs are std_logic_vector.
-- This entity can be use both pre and post synthesis.
component fixed_synth is
port (
in1, in2 : in std_logic_vector (15 downto 0); -- inputs
out1 : out std_logic_vector (15 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end component fixed_synth;
constant clock_period : time := 500 ns; -- clock period
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
signal stop_clock : boolean := false; -- stop the clock
signal clk, rst_n : std_ulogic; -- clk and reset
signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
signal in1, in2 : sfixed16; -- inputs
signal out1 : sfixed16; -- output
signal cmd : std_logic_vector (3 downto 0); -- command string
begin -- architecture testbench
-- From fixed point to Std_logic_vector
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
-- Std_logic_vector to fixed point.
out1 <= to_sfixed(out1slv, out1'high, out1'low);
DUT: fixed_synth
port map (
in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
cmd => cmd, -- [in std_logic_vector (2 downto 0)]
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- purpose: clock driver
clkprc: process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
reset_proc: process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
tester: process is
begin -- process tester
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0001"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0010"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0011"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
cmd <= "0100"; -- unsigned add
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0101"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0110"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0100"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0111"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
-- resize
cmd <= "1000";
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-5.25, in2);
wait for clock_period;
in1 <= to_sfixed (21.125, in1);
in2 <= to_sfixed (21.125, in2);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (3, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-5.5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010"; -- abs (mod)
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-42, in1);
wait for clock_period;
cmd <= "1011"; -- mod
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1100"; -- REM
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1101"; -- srl
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-1, in2);
wait for clock_period;
cmd <= "1110"; -- sra
in1 <= to_sfixed (-7.25, in1);
in2 <= to_sfixed (1, in2);
wait for clock_period;
cmd <= "1111"; -- compare
in1 <= to_sfixed (42, in1);
in2 <= to_sfixed (42, in1);
wait for clock_period;
in1 <= to_sfixed (45, in1);
in2 <= to_sfixed (90, in1);
wait for clock_period;
in1 <= to_sfixed (3.125, in1);
in2 <= (others => '0');
wait for clock_period;
in1 <= "0110111110101111";
in2 <= "1111111111111111";
wait for clock_period;
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
in1 <= "0000111000000000";
in2 <= "0000111000000000";
wait for clock_period;
in1 <= (others => '1');
in2 <= (others => '1');
wait for clock_period;
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest: process is
constant fxzero : sfixed16 := (others => '0'); -- zero
variable chks16 : sfixed16; -- variable
variable sm1, sm2 : sfixed7; -- small fixed point
begin -- process checktest
wait for clock_period/2.0;
wait for clock_period;
wait for clock_period;
waitloop: while (out1 = fxzero) loop
wait for clock_period;
end loop waitloop;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
report_error ( "-0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
report_error ( "6.5/0.5 error",
out1,
chks16);
wait for clock_period;
-- resize test
sm1 := out1 (7 downto 1);
sm2 := to_sfixed (5.25, sm2);
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := to_sfixed (-5.25, sm2);
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
sm1 := out1 (7 downto 1);
sm2 := "0101001"; -- wrapped
-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := "0111111"; -- saturate
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
-- to_signed and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_unsigned and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
-- to_integer and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_integer(ufixed) and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
wait for clock_period;
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
wait for clock_period;
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
wait for clock_period;
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
wait for clock_period;
report_error ("abs(-42)", out1, to_sfixed (42, out1));
wait for clock_period;
report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
chks16 := "0000101010000000";
report_error ("5.25 srl -1", out1, chks16);
wait for clock_period;
chks16 := "1111110001100000";
report_error ("-7.25 sra 1", out1, chks16);
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "42=42 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------0001010110";
assert (std_match (out1, chks16))
report "45=90 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------1010101010";
assert (std_match (out1, chks16))
report "3.125=0 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0--1010000101010";
assert (std_match (out1, chks16))
report "pattern1 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0001100000110001";
assert (std_match (out1, chks16))
report "zero = zero " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "1111000000110001";
assert (std_match (out1, chks16))
report "pattern2 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "-1 = -1 " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
|
library ieee;
use ieee.std_logic_1164.all;
entity pr_axis_buffer is
generic (
DATAWIDTH : integer := 64
);
port (
static_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
static_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_m_axis_data_tready : out std_logic;
static_m_axis_data_tlast : in std_logic;
static_m_axis_data_tvalid : in std_logic;
pr_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
pr_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_m_axis_data_tready : out std_logic;
pr_m_axis_data_tlast : in std_logic;
pr_m_axis_data_tvalid : in std_logic;
static_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
static_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_s_axis_data_tready : in std_logic;
static_s_axis_data_tlast : out std_logic;
static_s_axis_data_tvalid : out std_logic;
pr_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
pr_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_s_axis_data_tready : in std_logic;
pr_s_axis_data_tlast : out std_logic;
pr_s_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end pr_axis_buffer;
architecture rtl of pr_axis_buffer is
component axis_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH;
BUFFER_SIZE : positive := 1
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
component axis_lut_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
signal m_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal m_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal m_axis_data_tlast : STD_LOGIC;
signal m_axis_data_tready : STD_LOGIC;
signal m_axis_data_tvalid : STD_LOGIC;
signal s_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal s_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal s_axis_data_tlast : STD_LOGIC;
signal s_axis_data_tready : STD_LOGIC;
signal s_axis_data_tvalid : STD_LOGIC;
begin
input_buffer: component axis_buffer
generic map (
DATAWIDTH => DATAWIDTH,
BUFFER_SIZE => 1
)
port map(
s_axis_data_tdata => static_m_axis_data_tdata,
s_axis_data_tkeep => static_m_axis_data_tkeep,
s_axis_data_tready => static_m_axis_data_tready,
s_axis_data_tlast => static_m_axis_data_tlast,
s_axis_data_tvalid => static_m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tkeep => m_axis_data_tkeep,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tvalid => m_axis_data_tvalid,
clk => clk
);
input_lut_buffer: component axis_lut_buffer
generic map (
DATAWIDTH => DATAWIDTH
)
port map(
s_axis_data_tdata => m_axis_data_tdata,
s_axis_data_tkeep => m_axis_data_tkeep,
s_axis_data_tready => m_axis_data_tready,
s_axis_data_tlast => m_axis_data_tlast,
s_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => pr_s_axis_data_tdata,
m_axis_data_tkeep => pr_s_axis_data_tkeep,
m_axis_data_tready => pr_s_axis_data_tready,
m_axis_data_tlast => pr_s_axis_data_tlast,
m_axis_data_tvalid => pr_s_axis_data_tvalid,
clk => clk
);
output_buffer: component axis_buffer
generic map (
DATAWIDTH => DATAWIDTH,
BUFFER_SIZE => 1
)
port map(
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tkeep => s_axis_data_tkeep,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
s_axis_data_tvalid => s_axis_data_tvalid,
m_axis_data_tdata => static_s_axis_data_tdata,
m_axis_data_tkeep => static_s_axis_data_tkeep,
m_axis_data_tready => static_s_axis_data_tready,
m_axis_data_tlast => static_s_axis_data_tlast,
m_axis_data_tvalid => static_s_axis_data_tvalid,
clk => clk
);
output_lut_buffer: component axis_lut_buffer
generic map (
DATAWIDTH => DATAWIDTH
)
port map(
s_axis_data_tdata => pr_m_axis_data_tdata,
s_axis_data_tkeep => pr_m_axis_data_tkeep,
s_axis_data_tready => pr_m_axis_data_tready,
s_axis_data_tlast => pr_m_axis_data_tlast,
s_axis_data_tvalid => pr_m_axis_data_tvalid,
m_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tkeep => s_axis_data_tkeep,
m_axis_data_tready => s_axis_data_tready,
m_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tvalid => s_axis_data_tvalid,
clk => clk
);
end architecture rtl; |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
package stratixgx_components is
--
-- stratixgx_lcell
--
COMPONENT stratixgx_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratixgx_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- stratixgx_io
--
COMPONENT stratixgx_io
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratixgx_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- stratixgx_mac_mult
--
COMPONENT stratixgx_mac_mult
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
END COMPONENT;
--
-- stratixgx_mac_out
--
COMPONENT stratixgx_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
END COMPONENT;
--
-- stratixgx_ram_block
--
COMPONENT stratixgx_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratixgx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixgx_pll
--
COMPONENT stratixgx_pll
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratixgx_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
family_name : string := "STRATIXGX";
skip_vco : string := "off";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END COMPONENT;
--
-- stratixgx_dll
--
COMPONENT stratixgx_dll
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratixgx_dll";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END COMPONENT;
--
-- stratixgx_lvds_transmitter
--
COMPONENT stratixgx_lvds_transmitter
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratixgx_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
--
-- stratixgx_jtag
--
COMPONENT stratixgx_jtag
generic (
lpm_type : string := "stratixgx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixgx_crcblock
--
COMPONENT stratixgx_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixgx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixgx_rublock
--
COMPONENT stratixgx_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixgx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratixgx_routing_wire
--
COMPONENT stratixgx_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixgx_lvds_receiver
--
COMPONENT stratixgx_lvds_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
END COMPONENT;
end stratixgx_components;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity present_top is
generic(k: key_enum);
port(plaintext: in std_logic_vector(63 downto 0);
key: in std_logic_vector(key_bits(k)-1 downto 0);
clk: in std_logic;
reset: in std_logic;
ciphertext: out std_logic_vector(63 downto 0)
);
end present_top;
architecture behavioral of present_top is
signal data_state,
data_key_added,
data_substituted,
data_permuted: std_logic_vector(63 downto 0);
signal key_state,
key_updated: std_logic_vector(key_bits(k)-1 downto 0);
signal round_counter: std_logic_vector(4 downto 0);
component sub_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component perm_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component key_schedule
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end component;
begin
SL: sub_layer port map(
data_in => data_key_added,
data_out => data_substituted
);
PL: perm_layer port map(
data_in => data_substituted,
data_out => data_permuted
);
KS: key_schedule generic map(
k => k
) port map(
data_in => key_state,
round_counter => round_counter,
data_out => key_updated
);
data_key_added <= data_state xor key_state(key_bits(k)-1 downto key_bits(k)-64);
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
data_state <= plaintext;
key_state <= key;
round_counter <= "00001";
ciphertext <= (others => '0');
else
data_state <= data_permuted;
key_state <= key_updated;
round_counter <= std_logic_vector(unsigned(round_counter) + 1);
-- when we are "past" the final round, i.e. the 31st round was finished,
-- the round counter addition overflows back to zero. Now set the output
-- signal to the ciphertext.
case round_counter is
when "00000" => ciphertext <= data_key_added;
when others => ciphertext <= (others => '0');
end case;
--if round_counter = "00000" then
-- ciphertext <= data_key_added;
--end if;
end if;
end if;
end process;
end behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Vending_Machine_vlg_check_tst is
port(
D : in vl_logic_vector(1 downto 0);
E : in vl_logic_vector(7 downto 0);
P : in vl_logic_vector(7 downto 0);
sampler_rx : in vl_logic
);
end Vending_Machine_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff05 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
rst : std_logic;
en : std_logic);
end dff05;
architecture behav of dff05 is
begin
process (clk, rst) is
begin
if rst = '1' then
q <= x"00";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
end if;
end if;
end process;
end behav;
|
entity array1 is
end entity;
architecture test of array1 is
impure function func return bit_vector is
begin
return "101";
end function;
begin
p1: process is
begin
assert func = "10";
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIF_MASTER_DPRAM_S_AXIL is
generic (
C_S_AXI_DATA_WIDTH : integer:= 32;
C_S_AXI_ADDR_WIDTH : integer:= 4
);
port (
status_i : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
control_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
length_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_addr_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_addr_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end AXIF_MASTER_DPRAM_S_AXIL;
architecture arch_imp of AXIF_MASTER_DPRAM_S_AXIL is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal aw_en : std_logic;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
control_o <= (others => '0');
length_o <= (others => '0');
rd_addr_o <= (others => '0');
wr_addr_o <= (others => '0');
else
control_o <= (others => '0'); -- to have only a pulse
if (slv_reg_wren = '1') then
case axi_awaddr(ADDR_LSB+1 downto ADDR_LSB) is
when "00" =>
control_o <= S_AXI_WDATA;
when "01" =>
length_o <= S_AXI_WDATA;
when "10" =>
rd_addr_o <= S_AXI_WDATA;
when "11" =>
wr_addr_o <= S_AXI_WDATA;
when others =>
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (status_i, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
begin
-- Address decoding for reading registers
case axi_araddr(ADDR_LSB+1 downto ADDR_LSB) is
when "00" =>
reg_data_out <= status_i;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
end arch_imp;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ethernet bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
byten : out std_logic;
wpn : out std_logic;
-- SSRAM
ssram_ce1n : out std_logic;
ssram_ce2 : out std_logic;
ssram_ce3n : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssaddr : out std_logic_vector(20 downto 2);
ssdata : inout std_logic_vector(31 downto 0);
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adsp_n : out std_ulogic;
ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clkin : in std_logic;
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal ssd, prd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram8 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
end generate;
wpn <= '1'; byten <= '0';
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_adv_n, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adsp_n, gnd(0));
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
port map (ssaddr, memo.address(20 downto 2));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, vcc(0));
ssram_ce1n_pad : outpad generic map (tech => padtech)
port map (ssram_ce1n, gnd(0));
ssram_ce2_pad : outpad generic map (tech => padtech)
port map (ssram_ce2, vcc(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_ce3n, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (ssdata, memo.data, memo.vbdrive, ssd);
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, prd);
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
port map (
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity logic_unit is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
op : in std_logic_vector( 1 downto 0);
r : out std_logic_vector(31 downto 0)
);
end logic_unit;
architecture synth of logic_unit is
begin
process(a, b, op)
begin
case op is
when "00" => r <= a nor b;
when "01" => r <= a and b;
when "10" => r <= a or b;
when "11" => r <= a xor b;
when others =>
end case;
end process;
end synth;
|
architecture RTL of FIFO is
constant c_a : integer;
signal sig_b : std_logic;
shared variable var_1 : integer;
file file1 : integer;
alias alias1 is name;
alias alias1 : subtype_identifier is name;
-- Comment to break up groups
constant c_ab : integer;
signal sig_bc : std_logic;
shared variable var_12 : integer;
file file12 : integer;
constant c_abc : integer;
signal sig_bcd : std_logic;
shared variable var_123 : integer;
file file123 : integer;
-- Comment to break up groups
constant c_abcd : integer;
signal sig_bcde : std_logic;
shared variable var_1234 : integer;
file file1234 : integer;
begin
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_sdram_input_efifo_module is
port(
clk : in vl_logic;
rd : in vl_logic;
reset_n : in vl_logic;
wr : in vl_logic;
wr_data : in vl_logic_vector(61 downto 0);
almost_empty : out vl_logic;
almost_full : out vl_logic;
empty : out vl_logic;
full : out vl_logic;
rd_data : out vl_logic_vector(61 downto 0)
);
end usb_system_sdram_input_efifo_module;
|
-------------------------------------------------------------------------------
-- Entity: fmc_top
-- Author: Sandro Arnold
-------------------------------------------------------------------------------
-- Description: Testatübung ADD
-- FMC Block for Floppy Music Controller.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity gpio is
port(rst : in std_logic;
clk : in std_logic;
-- GPIO bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- GPIO pin signals
gpio_in : in std_logic_vector(DW-1 downto 0);
gpio_out : out std_logic_vector(DW-1 downto 0);
gpio_out_enb : out std_logic_vector(DW-1 downto 0)
);
end gpio;
architecture rtl of gpio is
-- address select signal
signal addr_sel : t_gpio_addr_sel;
-- peripheral registers
signal data_in_reg : std_logic_vector(DW-1 downto 0);
signal data_out_reg : std_logic_vector(DW-1 downto 0);
signal out_enb_reg : std_logic_vector(DW-1 downto 0);
begin
-- output ssignment
gpio_out <= data_out_reg;
gpio_out_enb <= out_enb_reg;
-----------------------------------------------------------------------------
-- Input register
-----------------------------------------------------------------------------
P_in: process(clk)
begin
if rising_edge(clk) then
data_in_reg <= gpio_in;
end if;
end process;
-----------------------------------------------------------------------------
-- Address Decoding (combinationally)
-----------------------------------------------------------------------------
process(bus_in.addr)
begin
case bus_in.addr is
-- Port 1 addresses -----------------------------------------------------
when c_addr_gpio_data_in => addr_sel <= gpio_data_in;
when c_addr_gpio_data_out => addr_sel <= gpio_data_out;
when c_addr_gpio_out_enb => addr_sel <= gpio_enb;
-- unused addresses -----------------------------------------------------
when others => addr_sel <= none;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Access (R and R/W registers)
-----------------------------------------------------------------------------
P_read: process(clk)
begin
if rising_edge(clk) then
-- default assignment
bus_out.data <= (others => '0');
-- use address select signal
case addr_sel is
when gpio_data_in => bus_out.data <= data_in_reg;
when gpio_data_out => bus_out.data <= data_out_reg;
when gpio_enb => bus_out.data <= out_enb_reg;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Access (R/W regsiters only)
-----------------------------------------------------------------------------
P_write: process(clk, rst)
begin
if rst = '1' then
data_out_reg <= (others => '0');
out_enb_reg <= (others => '0'); -- output disabled per default
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
-- use address select signal
case addr_sel is
when gpio_data_out => data_out_reg <= bus_in.data;
when gpio_enb => out_enb_reg <= bus_in.data;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
entity cnt04 is
port (
clk : in std_logic;
rst : in std_logic;
counter : out std_logic_vector (7 downto 0)
);
end cnt04;
architecture behav of cnt04 is
signal s_count : unsigned(7 downto 0); -- := (others => '0');
begin
process(clk, rst)
begin
if rst = '1' then
s_count <= (others => '0');
elsif rising_edge(clk) then
s_count <= s_count + 1;
end if;
end process;
-- connect internal signal to output
counter <= std_logic_vector(s_count + 1);
end behav;
|
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if(inclk0_period > inclk1_period) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCUDA PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cuda_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cuda_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cuda_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cuda_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cuda_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cuda_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cuda_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cuda_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_posedge,
SetupLow => tsetup_d_ena_noedge_posedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
|
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if(inclk0_period > inclk1_period) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCUDA PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cuda_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cuda_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cuda_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cuda_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cuda_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cuda_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cuda_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cuda_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_posedge,
SetupLow => tsetup_d_ena_noedge_posedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa
-- File: ddr2spa.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-, 32- or 64-bit DDR2 memory controller module.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ddrpkg.all;
library techmap;
use techmap.gencomp.all;
entity ddr2spa is
generic (
fabtech : integer := virtex4;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1; -- 1 added read latency cycle
ddelayb0 : integer := 0; -- Data delay value (0 - 63)
ddelayb1 : integer := 0; -- Data delay value (0 - 63)
ddelayb2 : integer := 0; -- Data delay value (0 - 63)
ddelayb3 : integer := 0; -- Data delay value (0 - 63)
ddelayb4 : integer := 0; -- Data delay value (0 - 63)
ddelayb5 : integer := 0; -- Data delay value (0 - 63)
ddelayb6 : integer := 0; -- Data delay value (0 - 63)
ddelayb7 : integer := 0; -- Data delay value (0 - 63)
cbdelayb0 : integer := 0; -- Data delay value (0 - 63)
cbdelayb1 : integer := 0; -- Data delay value (0 - 63)
cbdelayb2 : integer := 0; -- Data delay value (0 - 63)
cbdelayb3 : integer := 0; -- Data delay value (0 - 63)
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0; -- Disable sync registers at CD crossings
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; -- single ended DQS
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_logic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DDR clock
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector(13 downto 0); -- ddr address
ddr_ba : out std_logic_vector(1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector((ddrbits+ftbits)-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic -- Corrected error (for FT)
);
end;
architecture rtl of ddr2spa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
signal sdi : ddrctrl_in_type;
signal sdo : ddrctrl_out_type;
--signal clkread : std_ulogic;
-- Reset scheme:
-- 1. rst_ddr inport is a raw async reset brought in from the outside - goes to PHY/PLL:s
-- 2. lock signal from PHY/PLLs goes out through lock outport to external
-- ahb rstgen and internal ddr reset gen
-- 3. AMBA synchronous reset signal rst_ahb comes back in
-- DDR Clock scheme:
-- 1. clk_ddr (and clkref200) goes into PHY
-- 2. clkddro comes out from PHY and goes out through clkddro port
-- 3. clkddri comes back in and is used to clock DDR-side logic
signal ilock: std_ulogic;
signal ddr_rst: std_logic;
signal ddr_rst_gen: std_logic_vector(3 downto 0);
constant ddr_syncrst: integer := 0;
begin
lock <= ilock;
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst_ahb); -- Reset signal in DDR clock domain
ddrrstproc: process(clkddri, ilock)
begin
if rising_edge(clkddri) then
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
if ddr_syncrst /= 0 and rst_ahb='0' then
ddr_rst_gen <= "0000";
end if;
end if;
if ddr_syncrst=0 and ilock='0' then
ddr_rst_gen <= "0000";
end if;
end process;
nftphy: if true generate
ddr_phy0 : ddr2phy_wrap_cbd
generic map (
tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => 0, clk_mul => clkmul,
clk_div => clkdiv,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, cbdelayb0=> cbdelayb0,
cbdelayb1=> cbdelayb1, cbdelayb2=> cbdelayb2,cbdelayb3=> cbdelayb3,
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
chkbits => ftbits*ft, padbits => ftbits*(1-ft),
ctrl2en => 0, resync => 0, custombits => 8,
nclk => nclk, scantest => scantest )
port map (
rst_ddr, clk_ddr, clkref200, clkddro, clkddri, clkddri, ilock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn,
ddr_ad, ddr_ba, ddr_dq, ddr_odt,
open, open, open, open, open,
sdi, sdo, clkddri, "00000000", open,
ahbsi.testen, ahbsi.scanen, ahbsi.testrst, ahbsi.testoen);
end generate;
ddrc : ddr2spax generic map (memtech => memtech, phytech => fabtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask, ddrbits => ddrbits,
pwron => pwron, MHz => DDR_FREQ, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen, ahbbits => ahbbits,
ft => ft, ddr_syncrst => ddr_syncrst, bigmem => bigmem, raspipe => raspipe, hwidthen => 0, rstdel => rstdel)
port map (ddr_rst, rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo, '0');
ce <= sdo.ce;
end;
|
# Generated by vmake version 2.0
# Define path to each library
LIB_STD = /usr/pack/modelsim-6.0a-ma/modeltech/sunos5/../std
LIB_IEEE = /usr/pack/modelsim-6.0a-ma/modeltech/sunos5/../ieee
LIB_WORK = work
# Define path to each design unit
IEEE-std_logic_1164 = $(LIB_IEEE)/std_logic_1164/_primary.dat
IEEE-numeric_std = $(LIB_IEEE)/numeric_std/_primary.dat
STD-textio = $(LIB_STD)/textio/_primary.dat
IEEE-std_logic_textio = $(LIB_IEEE)/std_logic_textio/_primary.dat
WORK-zunit-simple = $(LIB_WORK)/zunit/simple.dat
WORK-zunit = $(LIB_WORK)/zunit/_primary.dat
WORK-zarchpkg-body = $(LIB_WORK)/zarchpkg/body.dat
WORK-zarchpkg = $(LIB_WORK)/zarchpkg/_primary.dat
WORK-updowncounter-simple = $(LIB_WORK)/updowncounter/simple.dat
WORK-updowncounter = $(LIB_WORK)/updowncounter/_primary.dat
WORK-upcounter-simple = $(LIB_WORK)/upcounter/simple.dat
WORK-upcounter = $(LIB_WORK)/upcounter/_primary.dat
WORK-txt_util-body = $(LIB_WORK)/txt_util/body.dat
WORK-txt_util = $(LIB_WORK)/txt_util/_primary.dat
WORK-tristatebuf-simple = $(LIB_WORK)/tristatebuf/simple.dat
WORK-tristatebuf = $(LIB_WORK)/tristatebuf/_primary.dat
WORK-schedulestoremem-simple = $(LIB_WORK)/schedulestoremem/simple.dat
WORK-schedulestoremem = $(LIB_WORK)/schedulestoremem/_primary.dat
WORK-schedulestore-simple = $(LIB_WORK)/schedulestore/simple.dat
WORK-schedulestore = $(LIB_WORK)/schedulestore/_primary.dat
WORK-schedulectrl-simple = $(LIB_WORK)/schedulectrl/simple.dat
WORK-schedulectrl = $(LIB_WORK)/schedulectrl/_primary.dat
WORK-row-simple = $(LIB_WORK)/row/simple.dat
WORK-row = $(LIB_WORK)/row/_primary.dat
WORK-routel-simple = $(LIB_WORK)/routel/simple.dat
WORK-routel = $(LIB_WORK)/routel/_primary.dat
WORK-rom-behavioral = $(LIB_WORK)/rom/behavioral.dat
WORK-rom = $(LIB_WORK)/rom/_primary.dat
WORK-reg_en-simple = $(LIB_WORK)/reg_en/simple.dat
WORK-reg_en = $(LIB_WORK)/reg_en/_primary.dat
WORK-reg_clr_en-simple = $(LIB_WORK)/reg_clr_en/simple.dat
WORK-reg_clr_en = $(LIB_WORK)/reg_clr_en/_primary.dat
WORK-reg_aclr_en-simple = $(LIB_WORK)/reg_aclr_en/simple.dat
WORK-reg_aclr_en = $(LIB_WORK)/reg_aclr_en/_primary.dat
WORK-pullbus-behav = $(LIB_WORK)/pullbus/behav.dat
WORK-pullbus = $(LIB_WORK)/pullbus/_primary.dat
WORK-pull-behav = $(LIB_WORK)/pull/behav.dat
WORK-pull = $(LIB_WORK)/pull/_primary.dat
WORK-procel-simple = $(LIB_WORK)/procel/simple.dat
WORK-procel = $(LIB_WORK)/procel/_primary.dat
WORK-mux8to1-simple = $(LIB_WORK)/mux8to1/simple.dat
WORK-mux8to1 = $(LIB_WORK)/mux8to1/_primary.dat
WORK-mux4to1-simple = $(LIB_WORK)/mux4to1/simple.dat
WORK-mux4to1 = $(LIB_WORK)/mux4to1/_primary.dat
WORK-mux2to1-simple = $(LIB_WORK)/mux2to1/simple.dat
WORK-mux2to1 = $(LIB_WORK)/mux2to1/_primary.dat
WORK-mux16to1-simple = $(LIB_WORK)/mux16to1/simple.dat
WORK-mux16to1 = $(LIB_WORK)/mux16to1/_primary.dat
WORK-lookuptable4to1-simple = $(LIB_WORK)/lookuptable4to1/simple.dat
WORK-lookuptable4to1 = $(LIB_WORK)/lookuptable4to1/_primary.dat
WORK-ioportctrl-simple = $(LIB_WORK)/ioportctrl/simple.dat
WORK-ioportctrl = $(LIB_WORK)/ioportctrl/_primary.dat
WORK-iop_compare-simple = $(LIB_WORK)/iop_compare/simple.dat
WORK-iop_compare = $(LIB_WORK)/iop_compare/_primary.dat
WORK-gmux-behav = $(LIB_WORK)/gmux/behav.dat
WORK-gmux = $(LIB_WORK)/gmux/_primary.dat
WORK-flipflop_clr-simple = $(LIB_WORK)/flipflop_clr/simple.dat
WORK-flipflop_clr = $(LIB_WORK)/flipflop_clr/_primary.dat
WORK-flipflop-simple = $(LIB_WORK)/flipflop/simple.dat
WORK-flipflop = $(LIB_WORK)/flipflop/_primary.dat
WORK-fifomem-simple = $(LIB_WORK)/fifomem/simple.dat
WORK-fifomem = $(LIB_WORK)/fifomem/_primary.dat
WORK-fifoctrl-simple = $(LIB_WORK)/fifoctrl/simple.dat
WORK-fifoctrl = $(LIB_WORK)/fifoctrl/_primary.dat
WORK-fifo-simple = $(LIB_WORK)/fifo/simple.dat
WORK-fifo = $(LIB_WORK)/fifo/_primary.dat
WORK-engine-simple = $(LIB_WORK)/engine/simple.dat
WORK-engine = $(LIB_WORK)/engine/_primary.dat
WORK-engclearctrl-simple = $(LIB_WORK)/engclearctrl/simple.dat
WORK-engclearctrl = $(LIB_WORK)/engclearctrl/_primary.dat
WORK-decoder-simple = $(LIB_WORK)/decoder/simple.dat
WORK-decoder = $(LIB_WORK)/decoder/_primary.dat
WORK-cycledncntr-simple = $(LIB_WORK)/cycledncntr/simple.dat
WORK-cycledncntr = $(LIB_WORK)/cycledncntr/_primary.dat
WORK-cyclecntctrl-simple = $(LIB_WORK)/cyclecntctrl/simple.dat
WORK-cyclecntctrl = $(LIB_WORK)/cyclecntctrl/_primary.dat
WORK-contextselctrl-simple = $(LIB_WORK)/contextselctrl/simple.dat
WORK-contextselctrl = $(LIB_WORK)/contextselctrl/_primary.dat
WORK-contextregfile-simple = $(LIB_WORK)/contextregfile/simple.dat
WORK-contextregfile = $(LIB_WORK)/contextregfile/_primary.dat
WORK-contextmux-behav = $(LIB_WORK)/contextmux/behav.dat
WORK-contextmux = $(LIB_WORK)/contextmux/_primary.dat
WORK-configpkg-body = $(LIB_WORK)/configpkg/body.dat
WORK-configpkg = $(LIB_WORK)/configpkg/_primary.dat
WORK-configmem-simple = $(LIB_WORK)/configmem/simple.dat
WORK-configmem = $(LIB_WORK)/configmem/_primary.dat
WORK-componentspkg = $(LIB_WORK)/componentspkg/_primary.dat
WORK-cell-simple = $(LIB_WORK)/cell/simple.dat
WORK-cell = $(LIB_WORK)/cell/_primary.dat
WORK-cclkgating-simple = $(LIB_WORK)/cclkgating/simple.dat
WORK-cclkgating = $(LIB_WORK)/cclkgating/_primary.dat
WORK-auxpkg-body = $(LIB_WORK)/auxpkg/body.dat
WORK-auxpkg = $(LIB_WORK)/auxpkg/_primary.dat
WORK-archconfigpkg-body = $(LIB_WORK)/archconfigpkg/body.dat
WORK-archconfigpkg = $(LIB_WORK)/archconfigpkg/_primary.dat
VCOM = vcom
VLOG = vlog
whole_library : $(WORK-zunit-simple) \
$(WORK-zunit) \
$(WORK-zarchpkg-body) \
$(WORK-zarchpkg) \
$(WORK-updowncounter-simple) \
$(WORK-updowncounter) \
$(WORK-upcounter-simple) \
$(WORK-upcounter) \
$(WORK-txt_util-body) \
$(WORK-txt_util) \
$(WORK-tristatebuf-simple) \
$(WORK-tristatebuf) \
$(WORK-schedulestoremem-simple) \
$(WORK-schedulestoremem) \
$(WORK-schedulestore-simple) \
$(WORK-schedulestore) \
$(WORK-schedulectrl-simple) \
$(WORK-schedulectrl) \
$(WORK-row-simple) \
$(WORK-row) \
$(WORK-routel-simple) \
$(WORK-routel) \
$(WORK-rom-behavioral) \
$(WORK-rom) \
$(WORK-reg_en-simple) \
$(WORK-reg_en) \
$(WORK-reg_clr_en-simple) \
$(WORK-reg_clr_en) \
$(WORK-reg_aclr_en-simple) \
$(WORK-reg_aclr_en) \
$(WORK-pullbus-behav) \
$(WORK-pullbus) \
$(WORK-pull-behav) \
$(WORK-pull) \
$(WORK-procel-simple) \
$(WORK-procel) \
$(WORK-mux8to1-simple) \
$(WORK-mux8to1) \
$(WORK-mux4to1-simple) \
$(WORK-mux4to1) \
$(WORK-mux2to1-simple) \
$(WORK-mux2to1) \
$(WORK-mux16to1-simple) \
$(WORK-mux16to1) \
$(WORK-lookuptable4to1-simple) \
$(WORK-lookuptable4to1) \
$(WORK-ioportctrl-simple) \
$(WORK-ioportctrl) \
$(WORK-iop_compare-simple) \
$(WORK-iop_compare) \
$(WORK-gmux-behav) \
$(WORK-gmux) \
$(WORK-flipflop_clr-simple) \
$(WORK-flipflop_clr) \
$(WORK-flipflop-simple) \
$(WORK-flipflop) \
$(WORK-fifomem-simple) \
$(WORK-fifomem) \
$(WORK-fifoctrl-simple) \
$(WORK-fifoctrl) \
$(WORK-fifo-simple) \
$(WORK-fifo) \
$(WORK-engine-simple) \
$(WORK-engine) \
$(WORK-engclearctrl-simple) \
$(WORK-engclearctrl) \
$(WORK-decoder-simple) \
$(WORK-decoder) \
$(WORK-cycledncntr-simple) \
$(WORK-cycledncntr) \
$(WORK-cyclecntctrl-simple) \
$(WORK-cyclecntctrl) \
$(WORK-contextselctrl-simple) \
$(WORK-contextselctrl) \
$(WORK-contextregfile-simple) \
$(WORK-contextregfile) \
$(WORK-contextmux-behav) \
$(WORK-contextmux) \
$(WORK-configpkg-body) \
$(WORK-configpkg) \
$(WORK-configmem-simple) \
$(WORK-configmem) \
$(WORK-componentspkg) \
$(WORK-cell-simple) \
$(WORK-cell) \
$(WORK-cclkgating-simple) \
$(WORK-cclkgating) \
$(WORK-auxpkg-body) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg-body) \
$(WORK-archconfigpkg)
$(WORK-archconfigpkg) \
$(WORK-archconfigpkg-body) : archConfigPkg.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -quiet -93 archConfigPkg.vhd
$(WORK-auxpkg) \
$(WORK-auxpkg-body) : auxPkg.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet auxPkg.vhd
$(WORK-cclkgating) \
$(WORK-cclkgating-simple) : cclkgating.vhd \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet cclkgating.vhd
$(WORK-cell) \
$(WORK-cell-simple) : cell.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet cell.vhd
$(WORK-componentspkg) : componentsPkg.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet componentsPkg.vhd
$(WORK-configmem) \
$(WORK-configmem-simple) : configmem.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-zarchpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet configmem.vhd
$(WORK-configpkg) \
$(WORK-configpkg-body) : configPkg.vhd \
$(WORK-zarchpkg) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-txt_util) \
$(IEEE-std_logic_textio) \
$(STD-textio) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet configPkg.vhd
$(WORK-contextmux) \
$(WORK-contextmux-behav) : contextmux.vhd \
$(WORK-zarchpkg) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-txt_util) \
$(IEEE-std_logic_textio) \
$(STD-textio) \
$(WORK-configpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet contextmux.vhd
$(WORK-contextregfile) \
$(WORK-contextregfile-simple) : contextregfile.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-componentspkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet contextregfile.vhd
$(WORK-contextselctrl) \
$(WORK-contextselctrl-simple) : contextselctrl.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet contextselctrl.vhd
$(WORK-cyclecntctrl) \
$(WORK-cyclecntctrl-simple) : cyclecntctrl.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet cyclecntctrl.vhd
$(WORK-cycledncntr) \
$(WORK-cycledncntr-simple) : cycledncntr.vhd \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet cycledncntr.vhd
$(WORK-decoder) \
$(WORK-decoder-simple) : decoder.vhd \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet decoder.vhd
$(WORK-engclearctrl) \
$(WORK-engclearctrl-simple) : engclearctrl.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet engclearctrl.vhd
$(WORK-engine) \
$(WORK-engine-simple) : engine.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet engine.vhd
$(WORK-fifoctrl) \
$(WORK-fifoctrl-simple) : fifoctrl.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet fifoctrl.vhd
$(WORK-fifo) \
$(WORK-fifo-simple) \
$(WORK-fifomem) \
$(WORK-fifomem-simple) : fifo.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-zarchpkg) \
$(WORK-archconfigpkg) \
$(WORK-componentspkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet fifo.vhd
$(WORK-flipflop) \
$(WORK-flipflop-simple) \
$(WORK-flipflop_clr) \
$(WORK-flipflop_clr-simple) : flipflop.vhd \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet flipflop.vhd
$(WORK-iop_compare) \
$(WORK-iop_compare-simple) \
$(WORK-ioportctrl) \
$(WORK-ioportctrl-simple) \
$(WORK-lookuptable4to1) \
$(WORK-lookuptable4to1-simple) : ioportctrl.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-zarchpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet ioportctrl.vhd
$(WORK-gmux) \
$(WORK-gmux-behav) \
$(WORK-mux16to1) \
$(WORK-mux16to1-simple) \
$(WORK-mux2to1) \
$(WORK-mux2to1-simple) \
$(WORK-mux4to1) \
$(WORK-mux4to1-simple) \
$(WORK-mux8to1) \
$(WORK-mux8to1-simple) : mux.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet mux.vhd
$(WORK-procel) \
$(WORK-procel-simple) : procel.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet procel.vhd
$(WORK-pull) \
$(WORK-pull-behav) \
$(WORK-pullbus) \
$(WORK-pullbus-behav) : pull.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(WORK-componentspkg) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet pull.vhd
$(WORK-reg_aclr_en) \
$(WORK-reg_aclr_en-simple) \
$(WORK-reg_clr_en) \
$(WORK-reg_clr_en-simple) \
$(WORK-reg_en) \
$(WORK-reg_en-simple) : reg.vhd \
$(IEEE-std_logic_1164) \
$(IEEE-numeric_std)
$(VCOM) -lint -quiet -93 -quiet reg.vhd
$(WORK-rom) \
$(WORK-rom-behavioral) : memory.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-zarchpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet memory.vhd
$(WORK-routel) \
$(WORK-routel-simple) : routel.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(WORK-zarchpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet routel.vhd
$(WORK-row) \
$(WORK-row-simple) : row.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(WORK-zarchpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet row.vhd
$(WORK-schedulectrl) \
$(WORK-schedulectrl-simple) : schedulectrl.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet schedulectrl.vhd
$(WORK-schedulestore) \
$(WORK-schedulestore-simple) \
$(WORK-schedulestoremem) \
$(WORK-schedulestoremem-simple) : schedulestore.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-zarchpkg) \
$(WORK-archconfigpkg) \
$(WORK-componentspkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet schedulestore.vhd
$(WORK-tristatebuf) \
$(WORK-tristatebuf-simple) : tristatebuf.vhd \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet tristatebuf.vhd
$(WORK-txt_util) \
$(WORK-txt_util-body) : txt_util.vhd \
$(STD-textio) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet txt_util.vhd
$(WORK-upcounter) \
$(WORK-upcounter-simple) \
$(WORK-updowncounter) \
$(WORK-updowncounter-simple) : counter.vhd \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet counter.vhd
$(WORK-zarchpkg) \
$(WORK-zarchpkg-body) : zarchPkg.vhd \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(WORK-archconfigpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet zarchPkg.vhd
$(WORK-zunit) \
$(WORK-zunit-simple) : zunit.vhd \
$(IEEE-std_logic_textio) \
$(WORK-configpkg) \
$(WORK-componentspkg) \
$(WORK-zarchpkg) \
$(WORK-archconfigpkg) \
$(STD-textio) \
$(WORK-txt_util) \
$(WORK-auxpkg) \
$(IEEE-numeric_std) \
$(IEEE-std_logic_1164)
$(VCOM) -lint -quiet -93 -quiet zunit.vhd
|
------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_array_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_common_math_pkg is
function log2(arg : in natural) return natural;
function log2ceil(arg : in natural) return natural;
function log2ceil(arg : in real) return natural;
function isLog2(arg : in natural) return boolean;
function max( a : in integer;
b : in integer) return integer;
function min( a : in integer;
b : in integer) return integer;
-- choose t if s=true else f
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic;
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector;
function choose( s : in boolean;
t : in integer;
f : in integer) return integer;
function choose( s : in boolean;
t : in string;
f : in string) return string;
function choose( s : in boolean;
t : in real;
f : in real) return real;
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned;
-- count occurence of a value inside an array
function count( a : in t_ainteger;
v : in integer) return integer;
function count( a : in t_abool;
v : in boolean) return integer;
function count( a : in std_logic_vector;
v : in std_logic) return integer;
end psi_common_math_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_common_math_pkg is
-- *** Log2 integer ***
function log2(arg : in natural) return natural is
variable v : natural := arg;
variable r : natural := 0;
begin
while v > 1 loop
v := v/2;
r := r+1;
end loop;
return r;
end function;
-- *** Log2Ceil integer ***
function log2ceil(arg : in natural) return natural is
begin
if arg = 0 then
return 0;
end if;
return log2(arg*2-1);
end function;
-- *** Log2Ceil real ***
function log2ceil(arg : in real) return natural is
variable v : real := arg;
variable r : natural := 0;
begin
while v > 1.0 loop
v := v/2.0;
r := r+1;
end loop;
return r;
end function;
-- *** isLog2 ***
function isLog2(arg : in natural) return boolean is
begin
if log2(arg) = log2ceil(arg) then
return true;
else
return false;
end if;
end function;
-- *** Max ***
function max( a : in integer;
b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- *** Min ***
function min( a : in integer;
b : in integer) return integer is
begin
if a > b then
return b;
else
return a;
end if;
end function;
-- *** Choose (std_logic) ***
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (std_logic_vector) ***
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (integer) ***
function choose( s : in boolean;
t : in integer;
f : in integer) return integer is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (string) ***
function choose( s : in boolean;
t : in string;
f : in string) return string is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (real) ***
function choose( s : in boolean;
t : in real;
f : in real) return real is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (unsigned) ***
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** count (integer) ***
function count( a : in t_ainteger;
v : in integer) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (bool) ***
function count( a : in t_abool;
v : in boolean) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (std_logic) ***
function count( a : in std_logic_vector;
v : in std_logic) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
end psi_common_math_pkg;
|
----------------------------------------------------------------------------------------------------
-- Bi-Phase Decomposition Testbench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.biphase_decomp_pkg.all;
--This module is a test-bench for simulating the bi-phase decomposition module
entity tb_biphase_decomp is
end tb_biphase_decomp;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_biphase_decomp is
signal rst : std_logic;
signal clk : std_logic;
signal count_data : std_logic_vector(15 downto 0);
signal x0 : std_logic_vector(15 downto 0);
signal x1 : std_logic_vector(15 downto 0);
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 30ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--count_process
counter: process(clk, rst)
variable counter : unsigned (15 downto 0) := (others => '0');
begin
if(rst = '1') then
counter := (others => '0');
else
if(rising_edge(clk)) then
counter := counter + 1;
end if;
end if;
count_data <= std_logic_vector(counter);
end process;
--UUT
uut : biphase_decomp
port map( clk => clk,
rst => rst,
x => count_data,
x0 => x0,
x1 => x1);
--Main Process
main: process
begin
rst <= '1';
wait for 50ns;
rst <= '0';
wait;
end process;
end sim;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev41 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev41 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal tmpxx: std_logic_vector(19 downto 0);
signal tmpyy: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDMD2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant STMD : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : std_logic_vector(31 downto 0);
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal dvect : WORD_VECTOR(0 to 7);
signal wout: std_logic_vector(63 downto 0);
signal lcount: std_logic_vector(31 downto 0);
signal scount: std_logic_vector(31 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=LDMD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3=LDMD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX or Opcode3 = STMD) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when ((Opcode4=SYS or Opcode4=STMD) and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2 = LDMD or Opcode2 = STMD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=LDMD or Opcode3 = STMD) else
true when(Opcode4=SYS or Opcode4=RETI or Opcode4 = STMD) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= x"00000000";
lcount <= x"00000000";
scount <= x"00000000";
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM or Opcode2 = LDMD) then
MAR <= x"000" & M2;
tmpxx <= std_logic_vector((unsigned(M2) + 1));
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STMD) then
dvect(0) <= std_logic_vector(unsigned(wva) + unsigned(h0));
dvect(1) <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dvect(2) <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dvect(3) <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dvect(4) <= std_logic_vector(unsigned(wve) + unsigned(h4));
dvect(5) <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dvect(6) <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dvect(7) <= std_logic_vector(unsigned(wvh) + unsigned(h7));
MAR <= x"000" & M2;
MDR_out <= dvect(to_integer(unsigned(scount)))(63 downto 32);
tmpyy <= x"000" & std_logic_vector(unsigned(M2) + 1);
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(wva) + unsigned(h0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(wva) + unsigned(h0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(wvb) + unsigned(h1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(wvb) + unsigned(h1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(wvc) + unsigned(h2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(wvc) + unsigned(h2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(wvd) + unsigned(h3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(wvd) + unsigned(h3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(wve) + unsigned(h4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(wve) + unsigned(h4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(wvf) + unsigned(h5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(wvf) + unsigned(h5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(wvg) + unsigned(h6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(wvg) + unsigned(h6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(wvh) + unsigned(h7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(wvh) + unsigned(h7))(31 downto 0);
elsif (Opcode2 = FIN) then
null;
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX or Opcode2 = LDMD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif(Opcode2=STMD) then
register_file(to_integer(unsigned(RX3))) <= MAR;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDMD) then
mvect(to_integer(unsigned(lcount)))(63 downto 32) <= MDR_in;
MAR <= x"000" & tmpxx;
register_file(to_integer(unsigned(RX3))) <= std_logic_vector(lcount);
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3 = STMD) then
register_file(to_integer(unsigned(RY3))) <= tmpyy;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDMD) then
MDR_in <= MEM_in;
elsif(Opcode3 = STMD) then
MAR <= tmpyy;
MDR_out <= dvect(to_integer(unsigned(scount)))(31 downto 0);
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
mvect(to_integer(unsigned(lcount)))(31 downto 0) <= MDR_in;
elsif (Opcode4 = STMD) then
null;
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
lcount <= std_logic_vector(unsigned(lcount)+1);
elsif (Opcode4 = STMD) then
if (to_integer(unsigned(scount)) = 7) then
scount <= x"00000000";
else
scount <= std_logic_vector(unsigned(scount) + 1);
end if;
end if;
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Slave
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CSlave.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus Slave
--
-- Rev: 3.1
-- rd signal ahead data one clock
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CSlave is
generic(
Bwidth : natural := 16
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector( Bwidth-1 downto 0 );
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector( Bwidth-1 downto 0 );
-- Local Bus
addr : out std_logic_vector( Bwidth-1 downto 0 );
Din : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
Dout : in STD_LOGIC_VECTOR( Bwidth-1 downto 0 ) := (others => '0');
wr : out std_logic;
rd : out std_logic := '0'
--
);
end CSlave;
architecture behave of CSlave is
signal req_i : std_logic := '0';
signal command : std_logic_vector( command_end downto command_start ) := (others => '0');
signal state : natural := 0;
signal tx_i : std_logic_vector( Bwidth-1 downto 0 ) := (others => '0');
begin
req<=req_i;
tx<=tx_i;
FSM:process(clk,rst)
begin
if rst='1' then
state<=state_IDLE;
command<=(others=>'0');
addr<=(others=>'0');
Din<=(others=>'0');
req_i<='0';
wr<='0';
tx_i<=(others=>'0');
elsif rising_edge(clk) then
case state is
when state_IDLE =>
if rx_sop='1' then
command<=rx( command_end downto command_start );
state<=state_ADDR;
end if;
wr<='0';
when state_ADDR =>
addr<=rx;
state<=state_DATA;
when state_DATA =>
if command=command_read then
state<=state_pending;
req_i<='1';
tx_i<=rx;
elsif command=command_write then
wr<='1';
Din<=rx;
state<=state_idle;
else
state<=state_idle;
end if;
when state_pending =>
if en='1' and tx_sop='1' then
req_i<='0';
state<=state_SENDING;
end if;
when state_SENDING =>
tx_i<=Dout;
state<=state_IDLE;
when others =>
state<=state_IDLE;
end case;
end if;
end process;
rd<= '1' when state=state_pending and en='1' and tx_sop='1' else '0';
end behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Position Calculation Core registers
---------------------------------------------------------------------------------------
-- File : wb_pos_calc_regs.vhd
-- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb
-- Created : Thu Jan 16 11:48:43 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pos_calc_wbgen2_pkg.all;
entity wb_pos_calc_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk2x_i : in std_logic;
fs_clk_i : in std_logic;
regs_i : in t_pos_calc_in_registers;
regs_o : out t_pos_calc_out_registers
);
end wb_pos_calc_regs;
architecture syn of wb_pos_calc_regs is
signal pos_calc_ds_tbt_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_tbt_thres_val_swb : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s2 : std_logic ;
signal pos_calc_ds_fofb_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_fofb_thres_val_swb : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s2 : std_logic ;
signal pos_calc_ds_monit_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_monit_thres_val_swb : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s2 : std_logic ;
signal pos_calc_kx_val_int : std_logic_vector(24 downto 0);
signal pos_calc_kx_val_swb : std_logic ;
signal pos_calc_kx_val_swb_delay : std_logic ;
signal pos_calc_kx_val_swb_s0 : std_logic ;
signal pos_calc_kx_val_swb_s1 : std_logic ;
signal pos_calc_kx_val_swb_s2 : std_logic ;
signal pos_calc_ky_val_int : std_logic_vector(24 downto 0);
signal pos_calc_ky_val_swb : std_logic ;
signal pos_calc_ky_val_swb_delay : std_logic ;
signal pos_calc_ky_val_swb_s0 : std_logic ;
signal pos_calc_ky_val_swb_s1 : std_logic ;
signal pos_calc_ky_val_swb_s2 : std_logic ;
signal pos_calc_ksum_val_int : std_logic_vector(24 downto 0);
signal pos_calc_ksum_val_swb : std_logic ;
signal pos_calc_ksum_val_swb_delay : std_logic ;
signal pos_calc_ksum_val_swb_s0 : std_logic ;
signal pos_calc_ksum_val_swb_s1 : std_logic ;
signal pos_calc_ksum_val_swb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_tbt_ch01_lwb : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_tbt_ch23_lwb : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_fofb_ch01_lwb : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_fofb_ch23_lwb : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr1_monit_cic_lwb : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr1_monit_cfir_lwb : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr2_monit_pfir_lwb : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_int : std_logic ;
signal pos_calc_dsp_err_clr_tbt_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_int : std_logic ;
signal pos_calc_dsp_err_clr_fofb_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_int : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_int : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync2 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch0_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch1_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch2_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch3_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch0_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch0_val_swb : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch1_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch1_val_swb : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch2_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch2_val_swb : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch3_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch3_val_swb : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s2 : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_amp_ch0_lwb : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_amp_ch0_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_amp_ch1_lwb : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_amp_ch1_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_amp_ch2_lwb : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_amp_ch2_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_amp_ch3_lwb : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_amp_ch3_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_pos_x_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_pos_x_lwb : std_logic ;
signal pos_calc_dsp_monit_pos_x_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_pos_x_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_pos_x_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_pos_x_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_pos_x_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_pos_y_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_pos_y_lwb : std_logic ;
signal pos_calc_dsp_monit_pos_y_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_pos_y_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_pos_y_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_pos_y_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_pos_y_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_pos_q_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_pos_q_lwb : std_logic ;
signal pos_calc_dsp_monit_pos_q_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_pos_q_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_pos_q_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_pos_q_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_pos_q_lwb_s2 : std_logic ;
signal pos_calc_dsp_monit_pos_sum_int : std_logic_vector(31 downto 0);
signal pos_calc_dsp_monit_pos_sum_lwb : std_logic ;
signal pos_calc_dsp_monit_pos_sum_lwb_delay : std_logic ;
signal pos_calc_dsp_monit_pos_sum_lwb_in_progress : std_logic ;
signal pos_calc_dsp_monit_pos_sum_lwb_s0 : std_logic ;
signal pos_calc_dsp_monit_pos_sum_lwb_s1 : std_logic ;
signal pos_calc_dsp_monit_pos_sum_lwb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pos_calc_ds_tbt_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_tbt_thres_val_swb <= '0';
pos_calc_ds_tbt_thres_val_swb_delay <= '0';
pos_calc_ds_fofb_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_fofb_thres_val_swb <= '0';
pos_calc_ds_fofb_thres_val_swb_delay <= '0';
pos_calc_ds_monit_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_monit_thres_val_swb <= '0';
pos_calc_ds_monit_thres_val_swb_delay <= '0';
pos_calc_kx_val_int <= "0000000000000000000000000";
pos_calc_kx_val_swb <= '0';
pos_calc_kx_val_swb_delay <= '0';
pos_calc_ky_val_int <= "0000000000000000000000000";
pos_calc_ky_val_swb <= '0';
pos_calc_ky_val_swb_delay <= '0';
pos_calc_ksum_val_int <= "0000000000000000000000000";
pos_calc_ksum_val_swb <= '0';
pos_calc_ksum_val_swb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0';
pos_calc_dsp_err_clr_tbt_int <= '0';
pos_calc_dsp_err_clr_tbt_int_delay <= '0';
pos_calc_dsp_err_clr_fofb_int <= '0';
pos_calc_dsp_err_clr_fofb_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part1_int <= '0';
pos_calc_dsp_err_clr_monit_part1_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part2_int <= '0';
pos_calc_dsp_err_clr_monit_part2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch0_int <= '0';
pos_calc_dds_cfg_valid_ch0_int_delay <= '0';
pos_calc_dds_cfg_valid_ch1_int <= '0';
pos_calc_dds_cfg_valid_ch1_int_delay <= '0';
pos_calc_dds_cfg_valid_ch2_int <= '0';
pos_calc_dds_cfg_valid_ch2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch3_int <= '0';
pos_calc_dds_cfg_valid_ch3_int_delay <= '0';
pos_calc_dds_pinc_ch0_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch0_val_swb <= '0';
pos_calc_dds_pinc_ch0_val_swb_delay <= '0';
pos_calc_dds_pinc_ch1_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch1_val_swb <= '0';
pos_calc_dds_pinc_ch1_val_swb_delay <= '0';
pos_calc_dds_pinc_ch2_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch2_val_swb <= '0';
pos_calc_dds_pinc_ch2_val_swb_delay <= '0';
pos_calc_dds_pinc_ch3_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch3_val_swb <= '0';
pos_calc_dds_pinc_ch3_val_swb_delay <= '0';
pos_calc_dds_poff_ch0_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch0_val_swb <= '0';
pos_calc_dds_poff_ch0_val_swb_delay <= '0';
pos_calc_dds_poff_ch1_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch1_val_swb <= '0';
pos_calc_dds_poff_ch1_val_swb_delay <= '0';
pos_calc_dds_poff_ch2_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch2_val_swb <= '0';
pos_calc_dds_poff_ch2_val_swb_delay <= '0';
pos_calc_dds_poff_ch3_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch3_val_swb <= '0';
pos_calc_dds_poff_ch3_val_swb_delay <= '0';
pos_calc_dsp_monit_amp_ch0_lwb <= '0';
pos_calc_dsp_monit_amp_ch0_lwb_delay <= '0';
pos_calc_dsp_monit_amp_ch0_lwb_in_progress <= '0';
pos_calc_dsp_monit_amp_ch1_lwb <= '0';
pos_calc_dsp_monit_amp_ch1_lwb_delay <= '0';
pos_calc_dsp_monit_amp_ch1_lwb_in_progress <= '0';
pos_calc_dsp_monit_amp_ch2_lwb <= '0';
pos_calc_dsp_monit_amp_ch2_lwb_delay <= '0';
pos_calc_dsp_monit_amp_ch2_lwb_in_progress <= '0';
pos_calc_dsp_monit_amp_ch3_lwb <= '0';
pos_calc_dsp_monit_amp_ch3_lwb_delay <= '0';
pos_calc_dsp_monit_amp_ch3_lwb_in_progress <= '0';
pos_calc_dsp_monit_pos_x_lwb <= '0';
pos_calc_dsp_monit_pos_x_lwb_delay <= '0';
pos_calc_dsp_monit_pos_x_lwb_in_progress <= '0';
pos_calc_dsp_monit_pos_y_lwb <= '0';
pos_calc_dsp_monit_pos_y_lwb_delay <= '0';
pos_calc_dsp_monit_pos_y_lwb_in_progress <= '0';
pos_calc_dsp_monit_pos_q_lwb <= '0';
pos_calc_dsp_monit_pos_q_lwb_delay <= '0';
pos_calc_dsp_monit_pos_q_lwb_in_progress <= '0';
pos_calc_dsp_monit_pos_sum_lwb <= '0';
pos_calc_dsp_monit_pos_sum_lwb_delay <= '0';
pos_calc_dsp_monit_pos_sum_lwb_in_progress <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
pos_calc_ds_tbt_thres_val_swb <= pos_calc_ds_tbt_thres_val_swb_delay;
pos_calc_ds_tbt_thres_val_swb_delay <= '0';
pos_calc_ds_fofb_thres_val_swb <= pos_calc_ds_fofb_thres_val_swb_delay;
pos_calc_ds_fofb_thres_val_swb_delay <= '0';
pos_calc_ds_monit_thres_val_swb <= pos_calc_ds_monit_thres_val_swb_delay;
pos_calc_ds_monit_thres_val_swb_delay <= '0';
pos_calc_kx_val_swb <= pos_calc_kx_val_swb_delay;
pos_calc_kx_val_swb_delay <= '0';
pos_calc_ky_val_swb <= pos_calc_ky_val_swb_delay;
pos_calc_ky_val_swb_delay <= '0';
pos_calc_ksum_val_swb <= pos_calc_ksum_val_swb_delay;
pos_calc_ksum_val_swb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb <= pos_calc_dsp_ctnr_tbt_ch01_lwb_delay;
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_tbt_ch01_int;
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_tbt_ch23_lwb <= pos_calc_dsp_ctnr_tbt_ch23_lwb_delay;
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_tbt_ch23_int;
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_fofb_ch01_lwb <= pos_calc_dsp_ctnr_fofb_ch01_lwb_delay;
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_fofb_ch01_int;
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_fofb_ch23_lwb <= pos_calc_dsp_ctnr_fofb_ch23_lwb_delay;
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_fofb_ch23_int;
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr1_monit_cic_lwb <= pos_calc_dsp_ctnr1_monit_cic_lwb_delay;
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr1_monit_cic_int;
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr1_monit_cfir_lwb <= pos_calc_dsp_ctnr1_monit_cfir_lwb_delay;
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr1_monit_cfir_int;
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr2_monit_pfir_lwb <= pos_calc_dsp_ctnr2_monit_pfir_lwb_delay;
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr2_monit_pfir_int;
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr2_monit_fir_01_int;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_err_clr_tbt_int <= pos_calc_dsp_err_clr_tbt_int_delay;
pos_calc_dsp_err_clr_tbt_int_delay <= '0';
pos_calc_dsp_err_clr_fofb_int <= pos_calc_dsp_err_clr_fofb_int_delay;
pos_calc_dsp_err_clr_fofb_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part1_int <= pos_calc_dsp_err_clr_monit_part1_int_delay;
pos_calc_dsp_err_clr_monit_part1_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part2_int <= pos_calc_dsp_err_clr_monit_part2_int_delay;
pos_calc_dsp_err_clr_monit_part2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch0_int <= pos_calc_dds_cfg_valid_ch0_int_delay;
pos_calc_dds_cfg_valid_ch0_int_delay <= '0';
pos_calc_dds_cfg_valid_ch1_int <= pos_calc_dds_cfg_valid_ch1_int_delay;
pos_calc_dds_cfg_valid_ch1_int_delay <= '0';
pos_calc_dds_cfg_valid_ch2_int <= pos_calc_dds_cfg_valid_ch2_int_delay;
pos_calc_dds_cfg_valid_ch2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch3_int <= pos_calc_dds_cfg_valid_ch3_int_delay;
pos_calc_dds_cfg_valid_ch3_int_delay <= '0';
pos_calc_dds_pinc_ch0_val_swb <= pos_calc_dds_pinc_ch0_val_swb_delay;
pos_calc_dds_pinc_ch0_val_swb_delay <= '0';
pos_calc_dds_pinc_ch1_val_swb <= pos_calc_dds_pinc_ch1_val_swb_delay;
pos_calc_dds_pinc_ch1_val_swb_delay <= '0';
pos_calc_dds_pinc_ch2_val_swb <= pos_calc_dds_pinc_ch2_val_swb_delay;
pos_calc_dds_pinc_ch2_val_swb_delay <= '0';
pos_calc_dds_pinc_ch3_val_swb <= pos_calc_dds_pinc_ch3_val_swb_delay;
pos_calc_dds_pinc_ch3_val_swb_delay <= '0';
pos_calc_dds_poff_ch0_val_swb <= pos_calc_dds_poff_ch0_val_swb_delay;
pos_calc_dds_poff_ch0_val_swb_delay <= '0';
pos_calc_dds_poff_ch1_val_swb <= pos_calc_dds_poff_ch1_val_swb_delay;
pos_calc_dds_poff_ch1_val_swb_delay <= '0';
pos_calc_dds_poff_ch2_val_swb <= pos_calc_dds_poff_ch2_val_swb_delay;
pos_calc_dds_poff_ch2_val_swb_delay <= '0';
pos_calc_dds_poff_ch3_val_swb <= pos_calc_dds_poff_ch3_val_swb_delay;
pos_calc_dds_poff_ch3_val_swb_delay <= '0';
pos_calc_dsp_monit_amp_ch0_lwb <= pos_calc_dsp_monit_amp_ch0_lwb_delay;
pos_calc_dsp_monit_amp_ch0_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_amp_ch0_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch0_int;
pos_calc_dsp_monit_amp_ch0_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_amp_ch1_lwb <= pos_calc_dsp_monit_amp_ch1_lwb_delay;
pos_calc_dsp_monit_amp_ch1_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_amp_ch1_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch1_int;
pos_calc_dsp_monit_amp_ch1_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_amp_ch2_lwb <= pos_calc_dsp_monit_amp_ch2_lwb_delay;
pos_calc_dsp_monit_amp_ch2_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_amp_ch2_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch2_int;
pos_calc_dsp_monit_amp_ch2_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_amp_ch3_lwb <= pos_calc_dsp_monit_amp_ch3_lwb_delay;
pos_calc_dsp_monit_amp_ch3_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_amp_ch3_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch3_int;
pos_calc_dsp_monit_amp_ch3_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_pos_x_lwb <= pos_calc_dsp_monit_pos_x_lwb_delay;
pos_calc_dsp_monit_pos_x_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_pos_x_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_x_int;
pos_calc_dsp_monit_pos_x_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_pos_y_lwb <= pos_calc_dsp_monit_pos_y_lwb_delay;
pos_calc_dsp_monit_pos_y_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_pos_y_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_y_int;
pos_calc_dsp_monit_pos_y_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_pos_q_lwb <= pos_calc_dsp_monit_pos_q_lwb_delay;
pos_calc_dsp_monit_pos_q_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_pos_q_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_q_int;
pos_calc_dsp_monit_pos_q_lwb_in_progress <= '0';
end if;
pos_calc_dsp_monit_pos_sum_lwb <= pos_calc_dsp_monit_pos_sum_lwb_delay;
pos_calc_dsp_monit_pos_sum_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_monit_pos_sum_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_sum_int;
pos_calc_dsp_monit_pos_sum_lwb_in_progress <= '0';
end if;
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pos_calc_ds_tbt_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_tbt_thres_val_swb <= '1';
pos_calc_ds_tbt_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_tbt_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_tbt_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pos_calc_ds_fofb_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_fofb_thres_val_swb <= '1';
pos_calc_ds_fofb_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_fofb_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_fofb_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pos_calc_ds_monit_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_monit_thres_val_swb <= '1';
pos_calc_ds_monit_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_monit_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_monit_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pos_calc_kx_val_int <= wrdata_reg(24 downto 0);
pos_calc_kx_val_swb <= '1';
pos_calc_kx_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_kx_val_int;
rddata_reg(31 downto 25) <= regs_i.kx_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pos_calc_ky_val_int <= wrdata_reg(24 downto 0);
pos_calc_ky_val_swb <= '1';
pos_calc_ky_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_ky_val_int;
rddata_reg(31 downto 25) <= regs_i.ky_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pos_calc_ksum_val_int <= wrdata_reg(24 downto 0);
pos_calc_ksum_val_swb <= '1';
pos_calc_ksum_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_ksum_val_int;
rddata_reg(31 downto 25) <= regs_i.ksum_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_tbt_ch01_lwb <= '1';
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '1';
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_tbt_ch23_lwb <= '1';
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '1';
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_fofb_ch01_lwb <= '1';
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '1';
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_fofb_ch23_lwb <= '1';
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '1';
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr1_monit_cic_lwb <= '1';
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '1';
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr1_monit_cfir_lwb <= '1';
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '1';
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr2_monit_pfir_lwb <= '1';
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '1';
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '1';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '1';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pos_calc_dsp_err_clr_tbt_int <= wrdata_reg(0);
pos_calc_dsp_err_clr_tbt_int_delay <= wrdata_reg(0);
pos_calc_dsp_err_clr_fofb_int <= wrdata_reg(1);
pos_calc_dsp_err_clr_fofb_int_delay <= wrdata_reg(1);
pos_calc_dsp_err_clr_monit_part1_int <= wrdata_reg(2);
pos_calc_dsp_err_clr_monit_part1_int_delay <= wrdata_reg(2);
pos_calc_dsp_err_clr_monit_part2_int <= wrdata_reg(3);
pos_calc_dsp_err_clr_monit_part2_int_delay <= wrdata_reg(3);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pos_calc_dds_cfg_valid_ch0_int <= wrdata_reg(0);
pos_calc_dds_cfg_valid_ch0_int_delay <= wrdata_reg(0);
pos_calc_dds_cfg_valid_ch1_int <= wrdata_reg(8);
pos_calc_dds_cfg_valid_ch1_int_delay <= wrdata_reg(8);
pos_calc_dds_cfg_valid_ch2_int <= wrdata_reg(16);
pos_calc_dds_cfg_valid_ch2_int_delay <= wrdata_reg(16);
pos_calc_dds_cfg_valid_ch3_int <= wrdata_reg(24);
pos_calc_dds_cfg_valid_ch3_int_delay <= wrdata_reg(24);
end if;
rddata_reg(0) <= '0';
rddata_reg(7 downto 1) <= regs_i.dds_cfg_reserved_ch0_i;
rddata_reg(8) <= '0';
rddata_reg(15 downto 9) <= regs_i.dds_cfg_reserved_ch1_i;
rddata_reg(16) <= '0';
rddata_reg(23 downto 17) <= regs_i.dds_cfg_reserved_ch2_i;
rddata_reg(24) <= '0';
rddata_reg(31 downto 25) <= regs_i.dds_cfg_reserved_ch3_i;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch0_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch0_val_swb <= '1';
pos_calc_dds_pinc_ch0_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch0_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch0_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch1_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch1_val_swb <= '1';
pos_calc_dds_pinc_ch1_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch1_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch1_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch2_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch2_val_swb <= '1';
pos_calc_dds_pinc_ch2_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch2_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch2_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch3_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch3_val_swb <= '1';
pos_calc_dds_pinc_ch3_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch3_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch3_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch0_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch0_val_swb <= '1';
pos_calc_dds_poff_ch0_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch0_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch0_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch1_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch1_val_swb <= '1';
pos_calc_dds_poff_ch1_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch1_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch1_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch2_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch2_val_swb <= '1';
pos_calc_dds_poff_ch2_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch2_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch2_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch3_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch3_val_swb <= '1';
pos_calc_dds_poff_ch3_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch3_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch3_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_amp_ch0_lwb <= '1';
pos_calc_dsp_monit_amp_ch0_lwb_delay <= '1';
pos_calc_dsp_monit_amp_ch0_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_amp_ch1_lwb <= '1';
pos_calc_dsp_monit_amp_ch1_lwb_delay <= '1';
pos_calc_dsp_monit_amp_ch1_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_amp_ch2_lwb <= '1';
pos_calc_dsp_monit_amp_ch2_lwb_delay <= '1';
pos_calc_dsp_monit_amp_ch2_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_amp_ch3_lwb <= '1';
pos_calc_dsp_monit_amp_ch3_lwb_delay <= '1';
pos_calc_dsp_monit_amp_ch3_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_pos_x_lwb <= '1';
pos_calc_dsp_monit_pos_x_lwb_delay <= '1';
pos_calc_dsp_monit_pos_x_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_pos_y_lwb <= '1';
pos_calc_dsp_monit_pos_y_lwb_delay <= '1';
pos_calc_dsp_monit_pos_y_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11010" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_pos_q_lwb <= '1';
pos_calc_dsp_monit_pos_q_lwb_delay <= '1';
pos_calc_dsp_monit_pos_q_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11011" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_monit_pos_sum_lwb <= '1';
pos_calc_dsp_monit_pos_sum_lwb_delay <= '1';
pos_calc_dsp_monit_pos_sum_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Config divisor threshold TBT
-- asynchronous std_logic_vector register : Config divisor threshold TBT (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_tbt_thres_val_swb_s0 <= '0';
pos_calc_ds_tbt_thres_val_swb_s1 <= '0';
pos_calc_ds_tbt_thres_val_swb_s2 <= '0';
regs_o.ds_tbt_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_tbt_thres_val_swb_s0 <= pos_calc_ds_tbt_thres_val_swb;
pos_calc_ds_tbt_thres_val_swb_s1 <= pos_calc_ds_tbt_thres_val_swb_s0;
pos_calc_ds_tbt_thres_val_swb_s2 <= pos_calc_ds_tbt_thres_val_swb_s1;
if ((pos_calc_ds_tbt_thres_val_swb_s2 = '0') and (pos_calc_ds_tbt_thres_val_swb_s1 = '1')) then
regs_o.ds_tbt_thres_val_o <= pos_calc_ds_tbt_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- Config divisor threshold FOFB
-- asynchronous std_logic_vector register : Config divisor threshold FOFB (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_fofb_thres_val_swb_s0 <= '0';
pos_calc_ds_fofb_thres_val_swb_s1 <= '0';
pos_calc_ds_fofb_thres_val_swb_s2 <= '0';
regs_o.ds_fofb_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_fofb_thres_val_swb_s0 <= pos_calc_ds_fofb_thres_val_swb;
pos_calc_ds_fofb_thres_val_swb_s1 <= pos_calc_ds_fofb_thres_val_swb_s0;
pos_calc_ds_fofb_thres_val_swb_s2 <= pos_calc_ds_fofb_thres_val_swb_s1;
if ((pos_calc_ds_fofb_thres_val_swb_s2 = '0') and (pos_calc_ds_fofb_thres_val_swb_s1 = '1')) then
regs_o.ds_fofb_thres_val_o <= pos_calc_ds_fofb_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- Config Divisor Threshold Monit.
-- asynchronous std_logic_vector register : Config Divisor Threshold Monit. (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_monit_thres_val_swb_s0 <= '0';
pos_calc_ds_monit_thres_val_swb_s1 <= '0';
pos_calc_ds_monit_thres_val_swb_s2 <= '0';
regs_o.ds_monit_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_monit_thres_val_swb_s0 <= pos_calc_ds_monit_thres_val_swb;
pos_calc_ds_monit_thres_val_swb_s1 <= pos_calc_ds_monit_thres_val_swb_s0;
pos_calc_ds_monit_thres_val_swb_s2 <= pos_calc_ds_monit_thres_val_swb_s1;
if ((pos_calc_ds_monit_thres_val_swb_s2 = '0') and (pos_calc_ds_monit_thres_val_swb_s1 = '1')) then
regs_o.ds_monit_thres_val_o <= pos_calc_ds_monit_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (X axis) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (X axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_kx_val_swb_s0 <= '0';
pos_calc_kx_val_swb_s1 <= '0';
pos_calc_kx_val_swb_s2 <= '0';
regs_o.kx_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_kx_val_swb_s0 <= pos_calc_kx_val_swb;
pos_calc_kx_val_swb_s1 <= pos_calc_kx_val_swb_s0;
pos_calc_kx_val_swb_s2 <= pos_calc_kx_val_swb_s1;
if ((pos_calc_kx_val_swb_s2 = '0') and (pos_calc_kx_val_swb_s1 = '1')) then
regs_o.kx_val_o <= pos_calc_kx_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (Y axis) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (Y axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ky_val_swb_s0 <= '0';
pos_calc_ky_val_swb_s1 <= '0';
pos_calc_ky_val_swb_s2 <= '0';
regs_o.ky_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ky_val_swb_s0 <= pos_calc_ky_val_swb;
pos_calc_ky_val_swb_s1 <= pos_calc_ky_val_swb_s0;
pos_calc_ky_val_swb_s2 <= pos_calc_ky_val_swb_s1;
if ((pos_calc_ky_val_swb_s2 = '0') and (pos_calc_ky_val_swb_s1 = '1')) then
regs_o.ky_val_o <= pos_calc_ky_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (Sum) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (Sum) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ksum_val_swb_s0 <= '0';
pos_calc_ksum_val_swb_s1 <= '0';
pos_calc_ksum_val_swb_s2 <= '0';
regs_o.ksum_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ksum_val_swb_s0 <= pos_calc_ksum_val_swb;
pos_calc_ksum_val_swb_s1 <= pos_calc_ksum_val_swb_s0;
pos_calc_ksum_val_swb_s2 <= pos_calc_ksum_val_swb_s1;
if ((pos_calc_ksum_val_swb_s2 = '0') and (pos_calc_ksum_val_swb_s1 = '1')) then
regs_o.ksum_val_o <= pos_calc_ksum_val_int;
end if;
end if;
end process;
-- Reserved
-- TBT incorrect counter for channels 0/1 (multiplexed)
-- asynchronous std_logic_vector register : TBT incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch01_lwb;
pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s0;
pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s1;
if ((pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_tbt_ch01_int <= regs_i.dsp_ctnr_tbt_ch01_i;
end if;
end if;
end process;
-- TBT incorrect counter for channels 2/3 (multiplexed)
-- asynchronous std_logic_vector register : TBT incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch23_lwb;
pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s0;
pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s1;
if ((pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_tbt_ch23_int <= regs_i.dsp_ctnr_tbt_ch23_i;
end if;
end if;
end process;
-- FOFB incorrect counter for channels 0/1 (multiplexed)
-- asynchronous std_logic_vector register : FOFB incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch01_lwb;
pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s0;
pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s1;
if ((pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_fofb_ch01_int <= regs_i.dsp_ctnr_fofb_ch01_i;
end if;
end if;
end process;
-- FOFB incorrect counter for channels 2/3 (multiplexed)
-- asynchronous std_logic_vector register : FOFB incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch23_lwb;
pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s0;
pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s1;
if ((pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_fofb_ch23_int <= regs_i.dsp_ctnr_fofb_ch23_i;
end if;
end if;
end process;
-- Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= '0';
pos_calc_dsp_ctnr1_monit_cic_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cic_lwb;
pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s0;
pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s1;
if ((pos_calc_dsp_ctnr1_monit_cic_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_s2 = '0')) then
pos_calc_dsp_ctnr1_monit_cic_int <= regs_i.dsp_ctnr1_monit_cic_i;
end if;
end if;
end process;
-- Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cfir_lwb;
pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s0;
pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s1;
if ((pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 = '0')) then
pos_calc_dsp_ctnr1_monit_cfir_int <= regs_i.dsp_ctnr1_monit_cfir_i;
end if;
end if;
end process;
-- Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= pos_calc_dsp_ctnr2_monit_pfir_lwb;
pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s0;
pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s1;
if ((pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 = '0')) then
pos_calc_dsp_ctnr2_monit_pfir_int <= regs_i.dsp_ctnr2_monit_pfir_i;
end if;
end if;
end process;
-- Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1;
if ((pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr2_monit_fir_01_int <= regs_i.dsp_ctnr2_monit_fir_01_i;
end if;
end if;
end process;
-- Clear TBT error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_tbt_o <= '0';
pos_calc_dsp_err_clr_tbt_sync0 <= '0';
pos_calc_dsp_err_clr_tbt_sync1 <= '0';
pos_calc_dsp_err_clr_tbt_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_tbt_sync0 <= pos_calc_dsp_err_clr_tbt_int;
pos_calc_dsp_err_clr_tbt_sync1 <= pos_calc_dsp_err_clr_tbt_sync0;
pos_calc_dsp_err_clr_tbt_sync2 <= pos_calc_dsp_err_clr_tbt_sync1;
regs_o.dsp_err_clr_tbt_o <= pos_calc_dsp_err_clr_tbt_sync2 and (not pos_calc_dsp_err_clr_tbt_sync1);
end if;
end process;
-- Clear FOFB error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_fofb_o <= '0';
pos_calc_dsp_err_clr_fofb_sync0 <= '0';
pos_calc_dsp_err_clr_fofb_sync1 <= '0';
pos_calc_dsp_err_clr_fofb_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_fofb_sync0 <= pos_calc_dsp_err_clr_fofb_int;
pos_calc_dsp_err_clr_fofb_sync1 <= pos_calc_dsp_err_clr_fofb_sync0;
pos_calc_dsp_err_clr_fofb_sync2 <= pos_calc_dsp_err_clr_fofb_sync1;
regs_o.dsp_err_clr_fofb_o <= pos_calc_dsp_err_clr_fofb_sync2 and (not pos_calc_dsp_err_clr_fofb_sync1);
end if;
end process;
-- Clear Monit. CIC and CFIR error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_monit_part1_o <= '0';
pos_calc_dsp_err_clr_monit_part1_sync0 <= '0';
pos_calc_dsp_err_clr_monit_part1_sync1 <= '0';
pos_calc_dsp_err_clr_monit_part1_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_monit_part1_sync0 <= pos_calc_dsp_err_clr_monit_part1_int;
pos_calc_dsp_err_clr_monit_part1_sync1 <= pos_calc_dsp_err_clr_monit_part1_sync0;
pos_calc_dsp_err_clr_monit_part1_sync2 <= pos_calc_dsp_err_clr_monit_part1_sync1;
regs_o.dsp_err_clr_monit_part1_o <= pos_calc_dsp_err_clr_monit_part1_sync2 and (not pos_calc_dsp_err_clr_monit_part1_sync1);
end if;
end process;
-- Clear Monit. PFIR and Monit. 0.1 error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_monit_part2_o <= '0';
pos_calc_dsp_err_clr_monit_part2_sync0 <= '0';
pos_calc_dsp_err_clr_monit_part2_sync1 <= '0';
pos_calc_dsp_err_clr_monit_part2_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_monit_part2_sync0 <= pos_calc_dsp_err_clr_monit_part2_int;
pos_calc_dsp_err_clr_monit_part2_sync1 <= pos_calc_dsp_err_clr_monit_part2_sync0;
pos_calc_dsp_err_clr_monit_part2_sync2 <= pos_calc_dsp_err_clr_monit_part2_sync1;
regs_o.dsp_err_clr_monit_part2_o <= pos_calc_dsp_err_clr_monit_part2_sync2 and (not pos_calc_dsp_err_clr_monit_part2_sync1);
end if;
end process;
-- Valid signal for channel 0 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch0_o <= '0';
pos_calc_dds_cfg_valid_ch0_sync0 <= '0';
pos_calc_dds_cfg_valid_ch0_sync1 <= '0';
pos_calc_dds_cfg_valid_ch0_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch0_sync0 <= pos_calc_dds_cfg_valid_ch0_int;
pos_calc_dds_cfg_valid_ch0_sync1 <= pos_calc_dds_cfg_valid_ch0_sync0;
pos_calc_dds_cfg_valid_ch0_sync2 <= pos_calc_dds_cfg_valid_ch0_sync1;
regs_o.dds_cfg_valid_ch0_o <= pos_calc_dds_cfg_valid_ch0_sync2 and (not pos_calc_dds_cfg_valid_ch0_sync1);
end if;
end process;
-- Reserved
-- Valid signal for channel 1 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch1_o <= '0';
pos_calc_dds_cfg_valid_ch1_sync0 <= '0';
pos_calc_dds_cfg_valid_ch1_sync1 <= '0';
pos_calc_dds_cfg_valid_ch1_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch1_sync0 <= pos_calc_dds_cfg_valid_ch1_int;
pos_calc_dds_cfg_valid_ch1_sync1 <= pos_calc_dds_cfg_valid_ch1_sync0;
pos_calc_dds_cfg_valid_ch1_sync2 <= pos_calc_dds_cfg_valid_ch1_sync1;
regs_o.dds_cfg_valid_ch1_o <= pos_calc_dds_cfg_valid_ch1_sync2 and (not pos_calc_dds_cfg_valid_ch1_sync1);
end if;
end process;
-- Reserved
-- Valid signal for channel 2 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch2_o <= '0';
pos_calc_dds_cfg_valid_ch2_sync0 <= '0';
pos_calc_dds_cfg_valid_ch2_sync1 <= '0';
pos_calc_dds_cfg_valid_ch2_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch2_sync0 <= pos_calc_dds_cfg_valid_ch2_int;
pos_calc_dds_cfg_valid_ch2_sync1 <= pos_calc_dds_cfg_valid_ch2_sync0;
pos_calc_dds_cfg_valid_ch2_sync2 <= pos_calc_dds_cfg_valid_ch2_sync1;
regs_o.dds_cfg_valid_ch2_o <= pos_calc_dds_cfg_valid_ch2_sync2 and (not pos_calc_dds_cfg_valid_ch2_sync1);
end if;
end process;
-- Reserved
-- Valid signal for channel 3 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch3_o <= '0';
pos_calc_dds_cfg_valid_ch3_sync0 <= '0';
pos_calc_dds_cfg_valid_ch3_sync1 <= '0';
pos_calc_dds_cfg_valid_ch3_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch3_sync0 <= pos_calc_dds_cfg_valid_ch3_int;
pos_calc_dds_cfg_valid_ch3_sync1 <= pos_calc_dds_cfg_valid_ch3_sync0;
pos_calc_dds_cfg_valid_ch3_sync2 <= pos_calc_dds_cfg_valid_ch3_sync1;
regs_o.dds_cfg_valid_ch3_o <= pos_calc_dds_cfg_valid_ch3_sync2 and (not pos_calc_dds_cfg_valid_ch3_sync1);
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 0
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch0_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch0_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch0_val_swb_s2 <= '0';
regs_o.dds_pinc_ch0_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch0_val_swb_s0 <= pos_calc_dds_pinc_ch0_val_swb;
pos_calc_dds_pinc_ch0_val_swb_s1 <= pos_calc_dds_pinc_ch0_val_swb_s0;
pos_calc_dds_pinc_ch0_val_swb_s2 <= pos_calc_dds_pinc_ch0_val_swb_s1;
if ((pos_calc_dds_pinc_ch0_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch0_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch0_val_o <= pos_calc_dds_pinc_ch0_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 1
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch1_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch1_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch1_val_swb_s2 <= '0';
regs_o.dds_pinc_ch1_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch1_val_swb_s0 <= pos_calc_dds_pinc_ch1_val_swb;
pos_calc_dds_pinc_ch1_val_swb_s1 <= pos_calc_dds_pinc_ch1_val_swb_s0;
pos_calc_dds_pinc_ch1_val_swb_s2 <= pos_calc_dds_pinc_ch1_val_swb_s1;
if ((pos_calc_dds_pinc_ch1_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch1_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch1_val_o <= pos_calc_dds_pinc_ch1_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 2
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch2_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch2_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch2_val_swb_s2 <= '0';
regs_o.dds_pinc_ch2_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch2_val_swb_s0 <= pos_calc_dds_pinc_ch2_val_swb;
pos_calc_dds_pinc_ch2_val_swb_s1 <= pos_calc_dds_pinc_ch2_val_swb_s0;
pos_calc_dds_pinc_ch2_val_swb_s2 <= pos_calc_dds_pinc_ch2_val_swb_s1;
if ((pos_calc_dds_pinc_ch2_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch2_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch2_val_o <= pos_calc_dds_pinc_ch2_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 3
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch3_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch3_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch3_val_swb_s2 <= '0';
regs_o.dds_pinc_ch3_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch3_val_swb_s0 <= pos_calc_dds_pinc_ch3_val_swb;
pos_calc_dds_pinc_ch3_val_swb_s1 <= pos_calc_dds_pinc_ch3_val_swb_s0;
pos_calc_dds_pinc_ch3_val_swb_s2 <= pos_calc_dds_pinc_ch3_val_swb_s1;
if ((pos_calc_dds_pinc_ch3_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch3_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch3_val_o <= pos_calc_dds_pinc_ch3_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 0
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch0_val_swb_s0 <= '0';
pos_calc_dds_poff_ch0_val_swb_s1 <= '0';
pos_calc_dds_poff_ch0_val_swb_s2 <= '0';
regs_o.dds_poff_ch0_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch0_val_swb_s0 <= pos_calc_dds_poff_ch0_val_swb;
pos_calc_dds_poff_ch0_val_swb_s1 <= pos_calc_dds_poff_ch0_val_swb_s0;
pos_calc_dds_poff_ch0_val_swb_s2 <= pos_calc_dds_poff_ch0_val_swb_s1;
if ((pos_calc_dds_poff_ch0_val_swb_s2 = '0') and (pos_calc_dds_poff_ch0_val_swb_s1 = '1')) then
regs_o.dds_poff_ch0_val_o <= pos_calc_dds_poff_ch0_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 1
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch1_val_swb_s0 <= '0';
pos_calc_dds_poff_ch1_val_swb_s1 <= '0';
pos_calc_dds_poff_ch1_val_swb_s2 <= '0';
regs_o.dds_poff_ch1_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch1_val_swb_s0 <= pos_calc_dds_poff_ch1_val_swb;
pos_calc_dds_poff_ch1_val_swb_s1 <= pos_calc_dds_poff_ch1_val_swb_s0;
pos_calc_dds_poff_ch1_val_swb_s2 <= pos_calc_dds_poff_ch1_val_swb_s1;
if ((pos_calc_dds_poff_ch1_val_swb_s2 = '0') and (pos_calc_dds_poff_ch1_val_swb_s1 = '1')) then
regs_o.dds_poff_ch1_val_o <= pos_calc_dds_poff_ch1_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 2
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch2_val_swb_s0 <= '0';
pos_calc_dds_poff_ch2_val_swb_s1 <= '0';
pos_calc_dds_poff_ch2_val_swb_s2 <= '0';
regs_o.dds_poff_ch2_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch2_val_swb_s0 <= pos_calc_dds_poff_ch2_val_swb;
pos_calc_dds_poff_ch2_val_swb_s1 <= pos_calc_dds_poff_ch2_val_swb_s0;
pos_calc_dds_poff_ch2_val_swb_s2 <= pos_calc_dds_poff_ch2_val_swb_s1;
if ((pos_calc_dds_poff_ch2_val_swb_s2 = '0') and (pos_calc_dds_poff_ch2_val_swb_s1 = '1')) then
regs_o.dds_poff_ch2_val_o <= pos_calc_dds_poff_ch2_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 3
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch3_val_swb_s0 <= '0';
pos_calc_dds_poff_ch3_val_swb_s1 <= '0';
pos_calc_dds_poff_ch3_val_swb_s2 <= '0';
regs_o.dds_poff_ch3_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch3_val_swb_s0 <= pos_calc_dds_poff_ch3_val_swb;
pos_calc_dds_poff_ch3_val_swb_s1 <= pos_calc_dds_poff_ch3_val_swb_s0;
pos_calc_dds_poff_ch3_val_swb_s2 <= pos_calc_dds_poff_ch3_val_swb_s1;
if ((pos_calc_dds_poff_ch3_val_swb_s2 = '0') and (pos_calc_dds_poff_ch3_val_swb_s1 = '1')) then
regs_o.dds_poff_ch3_val_o <= pos_calc_dds_poff_ch3_val_int;
end if;
end if;
end process;
-- Reserved
-- Monit. Amplitude Value for channel 0
-- asynchronous std_logic_vector register : Monit. Amplitude Value for channel 0 (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_amp_ch0_lwb_s0 <= '0';
pos_calc_dsp_monit_amp_ch0_lwb_s1 <= '0';
pos_calc_dsp_monit_amp_ch0_lwb_s2 <= '0';
pos_calc_dsp_monit_amp_ch0_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_amp_ch0_lwb_s0 <= pos_calc_dsp_monit_amp_ch0_lwb;
pos_calc_dsp_monit_amp_ch0_lwb_s1 <= pos_calc_dsp_monit_amp_ch0_lwb_s0;
pos_calc_dsp_monit_amp_ch0_lwb_s2 <= pos_calc_dsp_monit_amp_ch0_lwb_s1;
if ((pos_calc_dsp_monit_amp_ch0_lwb_s1 = '1') and (pos_calc_dsp_monit_amp_ch0_lwb_s2 = '0')) then
pos_calc_dsp_monit_amp_ch0_int <= regs_i.dsp_monit_amp_ch0_i;
end if;
end if;
end process;
-- Monit. Amplitude Value for channel 1
-- asynchronous std_logic_vector register : Monit. Amplitude Value for channel 1 (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_amp_ch1_lwb_s0 <= '0';
pos_calc_dsp_monit_amp_ch1_lwb_s1 <= '0';
pos_calc_dsp_monit_amp_ch1_lwb_s2 <= '0';
pos_calc_dsp_monit_amp_ch1_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_amp_ch1_lwb_s0 <= pos_calc_dsp_monit_amp_ch1_lwb;
pos_calc_dsp_monit_amp_ch1_lwb_s1 <= pos_calc_dsp_monit_amp_ch1_lwb_s0;
pos_calc_dsp_monit_amp_ch1_lwb_s2 <= pos_calc_dsp_monit_amp_ch1_lwb_s1;
if ((pos_calc_dsp_monit_amp_ch1_lwb_s1 = '1') and (pos_calc_dsp_monit_amp_ch1_lwb_s2 = '0')) then
pos_calc_dsp_monit_amp_ch1_int <= regs_i.dsp_monit_amp_ch1_i;
end if;
end if;
end process;
-- Monit. Amplitude Value for channel 2
-- asynchronous std_logic_vector register : Monit. Amplitude Value for channel 2 (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_amp_ch2_lwb_s0 <= '0';
pos_calc_dsp_monit_amp_ch2_lwb_s1 <= '0';
pos_calc_dsp_monit_amp_ch2_lwb_s2 <= '0';
pos_calc_dsp_monit_amp_ch2_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_amp_ch2_lwb_s0 <= pos_calc_dsp_monit_amp_ch2_lwb;
pos_calc_dsp_monit_amp_ch2_lwb_s1 <= pos_calc_dsp_monit_amp_ch2_lwb_s0;
pos_calc_dsp_monit_amp_ch2_lwb_s2 <= pos_calc_dsp_monit_amp_ch2_lwb_s1;
if ((pos_calc_dsp_monit_amp_ch2_lwb_s1 = '1') and (pos_calc_dsp_monit_amp_ch2_lwb_s2 = '0')) then
pos_calc_dsp_monit_amp_ch2_int <= regs_i.dsp_monit_amp_ch2_i;
end if;
end if;
end process;
-- Monit. Amplitude Value for channel 3
-- asynchronous std_logic_vector register : Monit. Amplitude Value for channel 3 (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_amp_ch3_lwb_s0 <= '0';
pos_calc_dsp_monit_amp_ch3_lwb_s1 <= '0';
pos_calc_dsp_monit_amp_ch3_lwb_s2 <= '0';
pos_calc_dsp_monit_amp_ch3_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_amp_ch3_lwb_s0 <= pos_calc_dsp_monit_amp_ch3_lwb;
pos_calc_dsp_monit_amp_ch3_lwb_s1 <= pos_calc_dsp_monit_amp_ch3_lwb_s0;
pos_calc_dsp_monit_amp_ch3_lwb_s2 <= pos_calc_dsp_monit_amp_ch3_lwb_s1;
if ((pos_calc_dsp_monit_amp_ch3_lwb_s1 = '1') and (pos_calc_dsp_monit_amp_ch3_lwb_s2 = '0')) then
pos_calc_dsp_monit_amp_ch3_int <= regs_i.dsp_monit_amp_ch3_i;
end if;
end if;
end process;
-- Monit. X Position Value
-- asynchronous std_logic_vector register : Monit. X Position Value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_pos_x_lwb_s0 <= '0';
pos_calc_dsp_monit_pos_x_lwb_s1 <= '0';
pos_calc_dsp_monit_pos_x_lwb_s2 <= '0';
pos_calc_dsp_monit_pos_x_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_pos_x_lwb_s0 <= pos_calc_dsp_monit_pos_x_lwb;
pos_calc_dsp_monit_pos_x_lwb_s1 <= pos_calc_dsp_monit_pos_x_lwb_s0;
pos_calc_dsp_monit_pos_x_lwb_s2 <= pos_calc_dsp_monit_pos_x_lwb_s1;
if ((pos_calc_dsp_monit_pos_x_lwb_s1 = '1') and (pos_calc_dsp_monit_pos_x_lwb_s2 = '0')) then
pos_calc_dsp_monit_pos_x_int <= regs_i.dsp_monit_pos_x_i;
end if;
end if;
end process;
-- Monit. Y Position Value
-- asynchronous std_logic_vector register : Monit. Y Position Value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_pos_y_lwb_s0 <= '0';
pos_calc_dsp_monit_pos_y_lwb_s1 <= '0';
pos_calc_dsp_monit_pos_y_lwb_s2 <= '0';
pos_calc_dsp_monit_pos_y_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_pos_y_lwb_s0 <= pos_calc_dsp_monit_pos_y_lwb;
pos_calc_dsp_monit_pos_y_lwb_s1 <= pos_calc_dsp_monit_pos_y_lwb_s0;
pos_calc_dsp_monit_pos_y_lwb_s2 <= pos_calc_dsp_monit_pos_y_lwb_s1;
if ((pos_calc_dsp_monit_pos_y_lwb_s1 = '1') and (pos_calc_dsp_monit_pos_y_lwb_s2 = '0')) then
pos_calc_dsp_monit_pos_y_int <= regs_i.dsp_monit_pos_y_i;
end if;
end if;
end process;
-- Monit. Q Position Value
-- asynchronous std_logic_vector register : Monit. Q Position Value (type RO/WO, fs_clk_i <-> clk_sys_i)
--process (fs_clk_i, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_pos_q_lwb_s0 <= '0';
pos_calc_dsp_monit_pos_q_lwb_s1 <= '0';
pos_calc_dsp_monit_pos_q_lwb_s2 <= '0';
pos_calc_dsp_monit_pos_q_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_pos_q_lwb_s0 <= pos_calc_dsp_monit_pos_q_lwb;
pos_calc_dsp_monit_pos_q_lwb_s1 <= pos_calc_dsp_monit_pos_q_lwb_s0;
pos_calc_dsp_monit_pos_q_lwb_s2 <= pos_calc_dsp_monit_pos_q_lwb_s1;
if ((pos_calc_dsp_monit_pos_q_lwb_s1 = '1') and (pos_calc_dsp_monit_pos_q_lwb_s2 = '0')) then
pos_calc_dsp_monit_pos_q_int <= regs_i.dsp_monit_pos_q_i;
end if;
end if;
end process;
-- Monit. Sum Position Value
-- asynchronous std_logic_vector register : Monit. Sum Position Value (type RO/WO, fs_clk_i <-> clk_sys_i)
-- process (fs_clk_i, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_monit_pos_sum_lwb_s0 <= '0';
pos_calc_dsp_monit_pos_sum_lwb_s1 <= '0';
pos_calc_dsp_monit_pos_sum_lwb_s2 <= '0';
pos_calc_dsp_monit_pos_sum_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
pos_calc_dsp_monit_pos_sum_lwb_s0 <= pos_calc_dsp_monit_pos_sum_lwb;
pos_calc_dsp_monit_pos_sum_lwb_s1 <= pos_calc_dsp_monit_pos_sum_lwb_s0;
pos_calc_dsp_monit_pos_sum_lwb_s2 <= pos_calc_dsp_monit_pos_sum_lwb_s1;
if ((pos_calc_dsp_monit_pos_sum_lwb_s1 = '1') and (pos_calc_dsp_monit_pos_sum_lwb_s2 = '0')) then
pos_calc_dsp_monit_pos_sum_int <= regs_i.dsp_monit_pos_sum_i;
end if;
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jqxZHtK4DF7FN7MnfoXwOPg9JHLh/xYyJVOcuANxf+9aDyU8tiAbMKMcksWZAVyMCFpdey/nqjYh
/OPH2/fu1w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UnYTLPVVIcWXQW1hyG6ahQ9XFDPUnW9paO39lozGP0YcMX2Akp9RmjSXxuuMoNtsYVEji+RX7LT9
fyJE5drW3mhND1U//SSeQPkA1iFNx/SNNNsaaYmEDR6VmNMnSj9t92JKXW1hyiEDPBNA/QlewL8b
bH0qgcHPQyfMmur17XI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Xwupj/KUD7H+XEyDC8LyeIlyRqBAReFJWy/CtZ3tay8VXbADL67XAbdVX9f8lgWei9aJTVA6WPjB
QdoY1hMd0pJlPyi91Jx2aYKq1i1ql8EHPkCPMNEk3lxt1jEWF0E6okotqWgbXT2guJeZQYa7K/FU
KOLWfkMqCt4xgBsgWWp8iEDEbKhbjcxIJQZVHkXNXLnNzn3L6XdYflHQoyw+Y00DxjzBznSNlUNU
RJF64E/g8M6k9agDzwf8qw1Df6mRpWMlVbVfvuR+N/7L2UYD5fr1jvoMaXYJwvC8Z5smi1KkFFj7
0/aZ2e8Ru+i5P71MYkSPPF1YmFm0gtQR9RrOcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lx9rlWxQN/kYEKka9UUdwsMbC2WjMyihMvnlGYopOjXfWByEeTbWfmCjFd7eVwgdVEeb61pxTBon
c3RsGtVgfclQ85Z1/A3qtMAH8UiXrkxFQd+SMjhFeCnfMUG7XFVvU/32OFX0kryJwzNykkSWWKSr
mfdgzRylz8ar3Q4OwbM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
olHkIijGKXhyAkPsQhczvzeTBQSoEYvYO3tgbaqFjnpXLmKMF+Q4pm7TtOgamWjUMmH8gm+tQv7L
zupyfd3704yvTBMeUc2cZIQWBLcCui4M1DTfGlE2CTN87Pw8402EGEPuY6iwmRhphTUZjawBSl6d
hZW1EomSdBx1q4GR9xNlk5Dho66UL1RywwPzxyyu7nr/2NwcEuL6t00UrX+TujdJXK1MRUWqooYh
+ly4V5Sq+5i3qoOPMd/NmGUyDTnWViZBo4XhLxmNXg348RPgZ/U5/RYEspxfdTi3YKcC7PyQfqxM
Y/gHvkdYBcQ+nlqezDIuhO+9G8tzuAnG4VQn/w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15520)
`protect data_block
7j0ddWUK6vS/0f5k/gL8CW6k8ZyX/3ChOfrvOaEvCo3+h+oVu7d4pSx4O2pw3z9cYS4+YtuIqYoR
JgpruPJyJww0YVdcjEMYqRPqXPyEzVT2nT3D2zKqFrYEwg5PgwluCjZBEeFI7U1c5FN0VZCQ9MH0
3dSOMO43FIlcjddFYs9yDCA1sI79KYr0t4RDUdaeqBumbkzbsIjFje+LpuXS62La4rpX8++ycrJn
car5qyIBLeMNX8zm5aa6pqmFT9AQ1sKLYU35hcmqe7SwcWKZvn5H2bENgUDVBU1rQPR4OmusuRDu
Yc07+4uuERdyBTZ12wy5vr70tdfI+EgwTrz9E6DYa7g0U/nFHuA8m8oRoZe8FVkQCKOnLLr0Jb73
QjaQ256EPw5qyZlSixUqDt3/eSYJbyUgPtcijvLxW6GvNFmP1YXj878WX5mRwUfq3BJcd0P44maS
fQouV58/bN9OqFWmsQCxq8QAkfLOPr1W2Ls3L3sJ4skrKdPjFHHZ4goaRSZ616rvSB8IgjlOJPxX
geo7W8SJbf+6SXxCP8spCZYSxwFMbgATi+WJYpGUHY1J56lpXg8z43CNstZrzWu0/mTCTApf3VAv
28swUAHQw8MK4MWAQCy7Y7i6VachlTGsBfdI+8xnAHzVhdMEPYm6DpKAGsKKz6TqpRw1pfAxILX/
JywMicqzVW45DPZfWcYI5LOwbv6IqYpwv3A+b4oD4nTYTwGiVhEsyBAwsRJxJBxDD07wU/aGmNA6
0CmkORg29dMD8daU1rgHPgqQV4H455+ABoRQIp4Sugrxi7HWJhXA35Z6nXmWfNLjZM5IL9UKMe4N
+Nj1tTm+F2BwIv2WLX17bQKCgjz6ZkmtsxdccAlywHUSPlUJ2IUMyiq0je+/EstBfI33pk7w5VdB
rv1gsxHoJXjsA+bHgCae+kh5pGuvBFmQRYIMNZmuePJNpFyFqgPz55IpAfC9hQiDs4FXW2F4+Vq/
KHWpEGejjgnYER1+SDuy3gN3nEK9n4BR1s4N8QWZPzkcRodXlRKWwIeG60BNVWB8JO3UFVwtYbk0
uypciLcRJMGrdO5e65l6IHW56OyHwVUXTbJRY7vFBJezRIS8HmxYhSfkDwuH6xmafJXB0CMQ61Ux
Ro53b0lkp00TuaQq+e90Bs6yU6jB4g2PyKxTRwOWPLEwTguNT1OouXp9fuKZn19pZc0jTr85JhgK
ELm3wjerSkKEPBVLfB72iA3JSuLNpOw+fPmg/1zprdbvL/uR/9ZKbnQMQ/Hmq2hdpXfS6TeNmzJt
+CtroP6yKwdV+j8YvYWc5X2MGlPd749d3KNhngrjbhloIxypNicSWasxptfDoHp8zw5nOjw8XS2Q
zzVjM/dWcsZTDBiFqWy1TyTVW62FhnzkZRbiOYCKabWxgPCBbcEzcXjMCV4P0NJBnhohBw+PmQVW
WF6+YNh4CCv0cGXAbuGJ320gAD60+AxkbsXEFZsaNfuU3md4osa8t3bDfFslc6on5h/3uAshhgSB
5Gaa52sWasB2T33oiAasnVXlqNNBS97qosSTisJv1gJpR1gaiY3gYWOp02rDDqnQIlSvW2oCVWxC
OWfW4pAd/yDnGKiYunSpawpEhHylvHPjdgXxIvzslnkbC2ZYDodZVP68PeWUk4QqbwrcPWldxCD7
xbeefnY4ELrEZCu4CAfTsDgOAs9WiX/SjcSOd8t9FNk0a6oVgN6SvprWs/0qIsBgR3otHoNGDUFw
HiuTLIeAzrFfYZ61PW+MZbNAgdg5ZIqK5PZskL36nQpmQf4O7ScnsDA16aSmpTbSKejN9A7naUVE
1dG266Xznt57ObuIv0xADHJdSCEjhK2pDH7VJGxJr2bs1RNbFuGoP3tci+dfCcnmK7pdxugt9j4J
BwHkdgdUhPVtu0DKpFtf1+/LX+HTKKketTmFfiDrtN9cjsg5n6JeHC255NTClHsBoeOouwQZzkJS
7msX/mJ9EISHnJx0rtTOXrJ1y+p4SRr8RehS9CLJTW1WVrmph/ExH3skBMtzlxCDOqSIuTiY+7YD
B8p+vhUQ5j4+9uWRIleDcDG2HqMhNQiIB95bPNx1yISTEzzdHLbo+XWpHJzu0z4qF7POsQsnD1S9
iSbfRkFUXdFCEXEfiukeri4gFoRXqUfIBDKNn4ba7CKAhCNIO8bPcJSV1tbNMYgjLLHOIphryL4n
rvNTDYCvdu7OrZo+Ia5xdwWyrXHG4/b/dTEyMwFI969QUlT43kn32A7SOfXUYq4FIqPqcrWznQsP
C8z5YTa+ALM73wrEPmBUBknvap5TeSOHLlNpuJ+GfO642D7dKyta7Ghv7AxTXYzLFnJLhPAScUGf
q3b0tloPe85HSrdQ1ANgLrr0SE0zpTm7hXIrbrsEcvr4vYVouEGcGB6rBpdmM/QNJDgIXdcWI/DB
Gt1G/pTw2YlQxuF2tD9JjanKoNLfkaYjsoYoz8WkE8iwZU1vhSPMPDUWTCb6R5zIr9EGKBp/OTHp
q+X1Sg08gfsLH78m1aZ5tyvCQyL5kKONDbTPkrRvU168wFH55x0Uz83pTjjVpbDv6DVcVn2Ly0GT
K7Hv73gefhsHIX2o5qe8grZ1o4LabTrc9tqUgj3hosexijyojbvJyMwQTUO4Gj3BFmfkSxbbeMIB
x2jYdu4PSb4/QtpvgION9vXY01Abf/jfwql31Vwqae38dTpuJ/nluO3yAxthrf9F5rXVuuTglsGh
vLBVDda96xaZ8I4ui2UQN/s7RYIM4VCfTUrx5JYBfDrXjQ7yw46lLNrgfVkgBLQvj40nhHkTzAz/
Z98Nel0ICntxlUbjQrD+ZwT/y+jf3DuL8XyQ3D3lY6MAb4eA34OlTnDy+AxxlgERCjlA1PxjlLzB
b0MleDaSvHF16RYfiWk/vHKtplQ6UCqbuGi76rJM4vIte4myppQfZ7ckALBIFp1ek3dMpPz7wXqi
zXtGpamGuut1Ay1E3p+W2OSwvMX6t+r7lDetJiusQRPFwPYq+NmFXn4IMwWXGErcth0EyOIUXyOC
6c4ZCLGTM87XR5QhFh+6E36hLFvdSU+wNTuROmSmu1fEEyRFcSo3WLxWY4RF8qkzsv13Jc6ZaXcL
6froXO+miJVagvg1tvNwhSlEXMW8yt76lbVcmxQ2EREtjV+oTNUQiyP4SPAm5lOLsWh7gbFLfRfl
QgvzwBsjkjxJPGGqfzH561jfNYdjpyzCDPjpnSI6mbkD8Dp46UPQbZAGils1zUpHUKYYX5aXnyIY
abCBpei1NQiC0E+smKdRgSpJUZZjoJXV6iqvvCbnZ+ZZ1LqZvJasTNUashy19ERYNV2hhzrqOO8E
pxbHbwJMcF58UoM94mtw+pWa42HuiiGk8hQgk2DYTV2xrYyJNE1ZdvgOTxhlj19sCtc1fxkOZkNf
GpXUIGtvM62C+bbT2LPRw5WJE68di79OPvRnfRr2ZBG0skcMdXNKWlbOIv0s+SZ2vMxKLZlmhw5B
Fss0HX3NsjRCUwR0Cd0PSMKTXjWeWQWYbXnhaLAhw3FHa3jE11a0tIk7an/eJW01CUR3Kx/svYEU
ppiTpqW7x3Td4LIi2i/HO1TwBTeM4VXzg8KKkyG/T9zfgfnFLKr+IOSuDrugJcLsf3C4zRX+/MpP
mDlVmaRR8rFhdBTnM10xKtPWgtTicANhF9bL4ASr0VGIM7zng0MPfgiudCvBJn8s1y0+sccs0fRG
FYa1Rvow3aYpWnbcR+9uDGRqERbak7dVziOffPRRB5b+NV0Qb1cyDqpz8Umly8svRhYSeetVrGkb
mYb4ykuo37kWx3du0UhLstgg6elvB5rnYMFKAApE9Cfrzzvascqa8OTAm2wyLljZgART/zvPVqHh
advmVESloVvjLxhC/9jsYFJ475xI3PN94YUS1UB90zL+sRyAvhKIyoKiTjJgNdULoxqYmL/MVsrM
hymiTHxJ8S2ZO9V7FstIm//AOffBnGTXdtRTcy6g/hthAKw4D4/Jg9zR0V9egjdP7jkrthsMdmso
1eu1gV/kuTxdlDgUU4xavRs1V5UyPLabWjli1Y0n6TuBPT1ygUyksZ5ffYaXBrHYkpVfnjqQonzA
S8reO+JJI08DdJvgy1qzpJbmAJz0q6nlnha+C4WcdTx21k9L2pN6iBABOAQYsNoAQYYMvxPqihfx
tArb//2YQKmOZrw7UsGJT8xDXe6IvoRetHaffxT1QT1uh/DPzYjjDhJD4ILo0OicK9AGgZD++SRQ
wy9jssTBveFvEHprK38BT/Tsj4oKMjDx1mLFoP5r3/O4KUswmdQ8URdyJhdZI0snHhu/eEV6V+Bq
qvyHRgDtbinHzFuDY8pYAdZz7+5QFELygNaDBtE2zumCBqDu+UCW2w2jTMxMPJ1RTgfvfaTd1uT8
A9RpNtWl//VpKo/ytzQiBv2924Wj94tAYUMNFIi7xUV08ybys7fqQM3miHs3BWOr2Ca0aWrE2EwE
d5DNQkRr5W7EQlqwvbot73ef2ROwVLI8OU7xwWrpvSRFGXzVB0FRuIrT0SwDSl6hEJV3dFyfginS
slOtgphzOv7p/3DX2gtLY8odE4wHdzcQJp+hXk1P1gDOyU5tW5vY4p3igf2UPAoXmgEsZ965DMCq
zMEs+od/Zuop9g4osBnML0bibSP7A+qSVErhLupfGiieRrDk3XTNDIIHLA5wLEJUWDtbELRm4Nmj
swautmQKa/D2EIujMhj6HS97igUFNyQ6vGRdKrKa09tGD9HfcAjxjzoZlhG7RL7cM5yGhWuYCNl8
N/mt73NiXBuPGmLgZ/47TVdqCiEUNyZzhihCywwAM8wX1Fz9gdTUL+PE9hentYKjDb5f3jljwVqf
Y+T1evltO87D7PMh0ZlXay9Gnk6fY9C2q364my/9J5GC0VBSRVjl1ji0c3Xw3rgKMmg0RPb5rGYF
DLNu7htmJXhxywfuN5cFhUzU9TomRxCjY6JO7iSPbcIl3re2IL+GeFnGvPcD+CCQAJEAahmO8WQD
Pti8l+dg7C8ZU31aZtMCfoDjKpwep8mWMD5Yrnm0kbJ+JIx3eSTtlS622pv1NmvO3Pl/KN21SiQq
6NaR4FJudcjEYw0u6dy0HRRMRakwt+S7bgsqm8rHtNm4Nr3BCNNU4h2Wiyf83nndiqpt5RosLYef
H7TYmRswMDfBLR7RNFSrgSm0k9jYFCGF9Vwyj2UVGvmMd+vCFnhaUHZrcnZjJa3RLG/u6v+y2ptL
QZRNvbryyv/d9eRZqq1Ch1xyT2VlEKkD/gQ3MxzvZQTUIR+wXiLVWEMAUTAa4iF0qZcvBB4WVfay
tlSawtxvGEIohKofn8yTevFu9Vg3xjd3k6FW9Mwt5Yvm4uFgSNuw/TR1P75bE4ZXv65ZfcCg2Hmk
TN5Y7KtaAALF8FLffw6vEUnddjM8LKVClhZZC+IlJ+mAEagGrXSVgrTEnykDuYIb1yDOLt0TfQSv
R1FoBkASZv9VGIKrqdXeJDjYi9kOQN8L3Fhxr4up3qF7INDUHBJ7ymVNt6aU4l5VxixBn16l8dkq
7619SKOyS4MOMyGwFYoNwf4grnNur8p3vdb5spXWeAZHpxfICjLJIAV8QkTNSeWWqC+03gcgwJDm
MgwpM5pvtWuCiOK/6rlVLV5OgdEyqubn9BoO3xGFEVG8Tv/igmR3FGlliBtwjm5EVQkNYvjY3gDK
xQM3kvV0OPy3XNQeRtMAzpzHb+PGy5cTIdIIjvmqjwih6Lq6msPpv0ldhFqYv7Zg/x/7257PgovU
rsQUAMee4yrZOPXjTqCffFZCotTguu/N67f3k6naiqAzmHIoKJ/V/7f1HJ9iAp36NAWNULcdb0dX
WUaWILMsWlqNJt/+ZUOmxQmseyYtpbFI4nde1lbNIFA3nMvNPBDbZ/MMTuLW1m8TRxyoPJu5Xy21
HpeS6LkstLP/kaX5Fu4/N4ysnSYHI4khYPKtpurnnX9cfhva9KmH5WexoCroZfZ1jibGjRyXKzxB
57sdDhykSu1HnOC7Akj/5TWxi0QbifcDJjfX2UWULs5YZxnw87pvM7VARNbAkboZkM5zAwFLwSCA
ujotU5RI56K3UQxsm56gLg5q65yQI0+sj1OOSVIcj3RspOlzyeiF06/zLHPXKW378IGQxRUoDref
DsG1AZ/7mpVh1pA77PjBtx7OdPsbUZaJ8Bf5GNuhEQF5JXvv0YrWk96TzWJ02jGlksVIx0DKLtGq
iD/TzodMndjovGY9EERfgrErS0H+lcnrkmdNTSagtGvxDXxYdUHQtQ5tDMNdQQgr0jVFkja+KJUH
rwPGX0Kf8BlUnCVJUIGd2rK1oKUV1c25yGQAG0KAoyT+Y5jkkw6Jc0MenwDyOo9ypDA2MuBvCyal
dh92f1MbK+wQ5q0H6AnG+8ZLZYsxCCSF9EHmHimOjQIceJKUrmgpxE2pGbR+SbnAlQ/UG2V6BdQo
4Tw8PuDawMu563fdMXJDNJSevt4K2BJx4JhaVs4wcw/8U5j8f/h2H015oNG1uN+faDV19l83qg2q
srpYZHhL36M9trwh6/CqXiUkjqLbBmZRLCpzSuIj7nuWw3yuaupKua8ytjF1JXaF9d5Pn2iFpN21
MgCwP9cX3VKaSxuyvcweSIXt3/wmmpy3Bd8nSFq1tu3Zsme9FALhIEtBWrZSg+cFU2erULmQt55K
Q3+5EIPOUaR4TkbCgzdWv9GkFyQ7IDyTPMfNUQDhk9VTFwJwnH9eo9zWkk+1aPHFdzcydA0mWv3/
GMjV5RLflUmlaA4Bev8niI5u+vO9v9PpPHV26ZF2JlsEMxQFUFMlrt/zbPpO8v5y9OrP9p3krK0U
PF54VgQaW3OgTCFEdk+4L7W6RgATZNcc1Th/5mih2V23i48+iW0SIvkfzziKmRSG9BVbm4EUkp0Y
wfdK/PPSuPEGNPlJy6V5jYcgXP8G2fF3SAxsIuSSOYAPJDF/fE2w/ffU/yES9RcX8s7NNZlZO9kP
9eZcuc78j8JNvyRMgCHz8c4Q4a2+1RJD8z6Z/Q5SJQibwVqsGaSm4CgZHsemKpGuQWzsYFB5K/2j
Fi+kjzHoK/K5lNL+DxcXug9NA6E5QZOdnBR5NSV8g1kA25drirZLbFWP2xvlyxePXmXI/OGpVNsD
rahlb9a3ijBhgVAFvjVoqU4zz1Fx3YJ+5F4pFiJLfrWmaywVXtqN7ovQFeNscDHXfWf6YS/if1L4
1xpMhBA4aKqQnecOQOX4P3NiiAGxbqveZybKaAw5q0FKoK5XNPVI0omXBqzon/1SjAdxC4ESnK5p
jgkQ8Ps6Q5lpueFnGaElMwZDROtlzw2bzDS6R4XorF+/JNWu7CXyUu8g0HuGiu2nHQjfPKvuzU5p
ef4HbVEgju2UntS18AropaQser6w+6pQp57svp16zEKFYvDbS0VNtErea3R42vNt2z9F2K3Vfvh0
seJPlA3aJG1AsSZYG2IyJjuRxBrKZuvXX1c1T1fXf8htWQnpPo/13eXLCOuwkoJZlvWhOo8wqqkS
+x3eb8djH13o1t084MoLT5aflf8NxckeEtUKfG+Vkym/vJQJ55OYWNeZG3sOJbuel9odc8UchWSB
+xprv+HGKknTSqMdPZi3hEqc/hL99/zsfWpSkTrgzEFSkJgHGC0WBILMzobCrtSLdAc3Hr7125BX
QkYHzoOPO5Hh7RefYmjLn1FcWd+3wgqnUj0Zro6vPBwHmzzdP55f09c6v8oNvfxhOXgNAgqFJ7W/
I6ZrSJIzXDN+4oSE/wGvGluVXTlfBL4c2eJE5HWnjBybCBru+8CcGqG6xJik95kXxCnyea/xDyBl
fnFPbOyQ7mM9lA9tE5FtGl/MiLbQCZy2ravz28MfiFvLLfJTa8kdsZqSqjfZOxVR8xfl9ic1JRDc
uaKBTSCUx8OPrteXSrTlxeilwkpUi4WSzDrkGnYifROnRuUbv1cLa2YOsWPfsKLRpnlIAaPg4r3P
p7wMZRLNirGXSj0/mqak+VXJw1fyTiX1Gs1vvypMNj1bCEIw5k8MNeMqRZTkOCdqrBhV0DqbH/sG
LF0ZziCESV5l1ynV9dnmN1OTSwnlAhhMxoGJfhVijd1GwgErs+hwWBDjfu6ur1wDRQSePvzUfIBo
6d/jwnzhZb+JxvHncqIWO0HuBk9a2/tyqzB5iXaUUwf7KhLVuwA+76+fh+fx+lDltPswizb4bx6p
rJOmPzhIaM6QjkQ8/us78pVRvVbyo0Ed1+EJ0N7voZM2igzNAl6i9cCQql/1G3yTLByHd0z5im59
yDD9B+u8//s1obhFCNkDvR+xxwG+KYEpPi0kDflh9w7fWteMfMfl9A3EXcuz0czJJGlKkLGydeo6
ajk8IJKk3tk7n91fwohA4TNFUcUqfuwEcbrUI8Fvw9tZ8px/ZRb885BnH901/RxhvX2CZp96pvBS
8f57jtNnFC8xewiaUQFWhJJT/oJHI8SSCLC/WcFWlKjF9BIhU8qFOkemZHonl9+eYuf5AMURnUB3
8oIU4GBcg/Hq8e0wH5lYSASMreAbyKEOAuQQeSdvT46xsi1tHDMTowmd2SoFs3GtCJHFspRgB/dJ
SOewSFVILZzjT/VJUycdw6vlhNA2Rjcj9AFFIQ72dPoHp7CG++8T/8pN00VtKPyDeG4f3HargCuf
9fjAyeqVE1DlE070pS4WlmePulu9yFWh/cyridNSqJAoqdJco1khPVZsERv4+QIqDrsz56qS1HVq
Lg0BmoOnCpfyxHBGZcC+iDuofHwxFwv+iLKMR8fcsvwRVLp+q7MxzUB3VG55FxXwntaJFDlL6d04
Rm6/O1uKqHCcFn3q5AX3ANePmg7EUDDZNJd4aUNJKy2Cfra8mWlkyL6WTSQTny+4aHcbdZoNU0bK
krFW0VWK2LhyMgAQkj+fA//zbhhRZm181SsbGmcxXY3NMbnWdiOC4G1fkpLvaQk/o3E+JvpvCEse
5V5qtEWu4+7L/e5qQkur6pgTB8rbS0mCZdKvzKdETLFEQT35y61/0b/HOBJ2O1a/6FUSIgcI7+Ov
AQ1CaGBOxd+RHUdwDJe3IzSSROT/LWPQugvkcbBimMkzxYH5PDm17EqSHlw7AkIigsx39WH/KCBq
vBdP7U35lk55geZJka83PPnoMVv+FWhJcDe+mjVVeWFaXVcVyQ3u1qgqAgvmKcDoUV6C+rwIYqGN
iah1dESKPEaBwP2616ouFAfl1LXikqpFvFsIGQtw7/PMgXacdH5+jeWOj/Edj0WLaJcbhzu29GuO
cPAtFs6FRgsX6iETOKkPw9YchrPir3Ow1FriTDWDw5iq02Voc4eIllcqW0AVH94Ww7XO5NezK7KS
AUZ4YKluSpdLCZktWXTqR+/iwEmyyYg5RjIAAV9rWpmEeR1fGrlO7SDLNVlX/1waO51LYQSwHuFr
gBjLBpOQYDsqqvx3H/nD77KbNSGD4pxjM7ZeWgJj8MVP8wQPyG4D40t/YjhtyPfZNzjaTFtYWl3Z
JlNrv1+8x2axhDaRTZVEsmtg3inCWhQjHjuGnSv19q+NUkXsYVNxb1jYPObCNIGOeiQ/6ULqbQrH
V5DKlhV8zP/vDwTL3xnapjaZhCKxJ2Z/W3RPFRghMfbh83BMzi+NCWANTt2JUMi01bCgqR+qyhPk
vI+cAHJ5qZbSJBem+bCA+K20dLfL7jKf6V1UKnqmkFJyhErcsLJM8sUTcd2GWE0FpXGd0INeYAbm
ZtaSSTyn4Zvcw/EO/nO5bpczoSRKpa8fUq0RXJGiCsk20P4w7ZZWsT8Fy6BgBS9JO/3UdglK5Kum
/+1zxSAHo9JHVgoEr0KKYFcZOFK84+yuKJuGLC8kme2ClC2vrq7TJR8rtKlxS7Tx+KJsjZyN8tKJ
ox01moIHQeT0rWc+uf0MY5LK6EAsfY7InoymujYljBn1Lzr+8SxS9u5/KSjSI/iAwAIeQOB1a53B
qN4gPFDbQo/I1iRlDaarTcZWk/qEr2jn2Fg6ooM6V03moigUG+rehJDJQHSkLeAKkb6B8h2YWN86
UzTHtFcJQ8fpBpHTk12cnZH9frD/e1bhFo34YkSFGGlP7K28lDmBiaqVkA+llaUjJ1v3NUZCclQl
o99BWyrkb/fu7OEzRfB6kPZd5/oeWRmgUbGwY70bBE9Nx2mPoUSejI3K/m308EvR94f4bS15HXgQ
T/q8q2LgF2ksHFWvErqFydQILK54LgiDbERxTgLfvjsUZOsZQT3mKnsg5IrOCuq8e2BckoxfDqxH
dZvaCMTSVnxd9DNFlZKl+KAJOv3fk/Hn+lEJEgHKDQhLthheQ3TqRAPfU7Zd+mVSVqeHWlfEjNOG
aaFwa0SGwnYAge8SceZRczoQPq2c1fNSA3toAwJox8FfQyhX2sH5nXvjsuCHmvskUWx8DjXvSS4U
/dtKFpd1o4HgiMho13SEYO/453HtYAR3ci123GURiS9MZJQidnwxHTznMSqWc4z40vktsVYGGU+i
IQc2trNILvG2S/k4OKvGOk3dCFXSiLHCusQHWteSMn39d7b+idRW6ZaoLz8ZDPqg2mBddCJslLL3
K66L8X0eroZpcruew6/PaI5jii0WoqBufHUAAJe8FZdsyCaPCK23x+TqVfy9gFbOW6KCWX9g/tek
HahRnwhf04hLCWPFvCbdgEiIJwa453Nj0KMcC0Xw98jK17DrUpWMsG68VM6+6dZXJ0Q9uhLYHr/W
tcmO7LM0sZNY4hZ5ZHH9LXJnMjvLZHcSmpVoy+2lSXNvtlh9BEkYnj3u4rt/jBCErNltzFZYtOkY
BKGby4exajgcKE2uwOZEhQ1fGdJLamf5mqGsneomO/uPw5Gam7z2CIjYVuuOHyDxVrmi+muX0fyq
FxTdSbyN3T0XANNrRZXdataLGQr6uD4jogn066Ogo2DB2WWbUlt0lS2yik4/xjmBHg48a87nbDWJ
yb4+rDlFArx/Z4KO5OiMAsW003PdGHD4ubFfU5CXGPQY5NmnrwZAEcjNSHXwWJGBNkJCi0xx6RXu
nHqMDIc5FgrBII9V5amwCJLTopg3cS5dmgdhCeCfHlX0IEay8SOrHz+f7iM26golYkS77IxnzNnZ
M7nIB80ffn8jpK/Yr0E5jzS9Y+5LraY1QPCNktu3CahPWKR4HBvLfGktMS2vqSfm3IyxOTB5nPn7
+j17f9dicebwkZUEpydkI7zCi/qCFNf3L9Px7IITYc01IPNZbX1bOu6hozKwdvGVr4ujIRihke4k
CQ8sj1yCh7XvQy8N9LRigtBtUaTdNng4vT36oTRSTjh7hF5GkIjSJIiRVOrMJESN5y0V3qPZcggA
ssZTN0Cnv1EK+9hnEasdbi5uhPLN5C8p87YNu/vuntPpbb23jCGdMEPykgStAyZ+OXbNjS3yoANm
P4DxAFOo+52K8Qa372B7adKm0DX+M4vLyEFiMFMY1Z6eqgUoiml6iSjMNH0tv84a5m6SpyTPG0wA
SllNl3nqd0o3uR9ZyiR5VFtP0qiI5HXmEzoMmc++mCkziz2ofuTbeouL70et8UN0WmWW6DVSnJmo
X67fMQOK3aGsjdU61jeOSXmEJaX7cjYADWRw/HoL/uLuY/L3eUGzclOXcYiIyjyHVHAiyJkJVT+r
2QPv0AtaYvUzvgyyfJL+mgIxgdWLpmEpopmyemeV8JNeCnp9mSuP6p2NSXmtAOjmCcvOAJNgNx2b
lzrUzTQfVh9/mL+NnGZoWJYieUZggECE6rlKTsuZikMprCF3/R2zLHzd2jsQsn73anoyK2fTu/EX
SEpTqn1LrR0UM7pnowTYxpX+qStVqLiaHDAJt8Mv/tJYwRjy2/qaAfh37A+MyBCHTdYbXRM4mbXg
phh5iY8KpPzzL9guRyAsfi+pJdhINk2ugEZmiGowwDkFPir83WrK1ZaxND2JdJBYqboN6tFjTIJd
azirvG2BAGMDPTs2Y2gAJyOq5pus2O8w9aypcGCiCtVWbqUR1uiU6oyrZc2D6RsJuHP1iNTVii6K
SuBEnpxeXu0K64jpdWttbbo5XLQKapF+tLqeZ9RrpwfHrUCETROhh4r7VUcr5dOESQ22kJ3gq/iZ
R++Nt7yvUf5xmIvgebl6taxeojC9YJSkN4vlPfDPw2y51+vfFqcf9Bv5OEVLsIGcOZjWUxU5IRMp
816KZCjQiUc1VPIUIIHHgxUX6MbNmWPowm3tEPcftyfqsIbXzmkB7XABOdjgxUpMFfLVr8kr2tsI
rAcGWWph7qcHlNwfSR1w+jBNRmPzvArrWXGHQzkSZQp6s7f13HCELIIiHppcMnGCQ/nIa6bZhZSC
jpm0oyRUe8YtXYU3vjTi6oo5JW6ddwSn+9Uj2TRYUTPdXlC/gSk0LnU9TISSCTZDvfDJAyjICIzm
/ZQRpC2hv9LcKIGyHxJp0m6vJTb2jFAK2grLjrIaob+Rhpc49pSdhm3oa6SnC6m+b4cnh/5u5rLl
HzCQsm0TYbIs0LxYLmZAGpzvDuGjroc6kepT3g/xzWnd6hIT3lpjPQYjn5pgJH1Pr2Fk00ypAdJ9
52+8JmvqQPWHGXlhky96678Uk/LffIXIUIFc0hGLGFQvaVBLuT7G/u+pltAsN9I85SeREuV6knjq
QdMfFdCRpJXVsmaRON41/TxaUs6m9owyRdedJ47+DtBHosEc67RWpFJXloCNsen88xd8giOZhmyg
swG+NlEHB54I3BpM942nHBUaXegKc03nXW/+XVN0ajNrNVQ1dg+YOWu0PaDmT4edc6JheEGgNCfq
PzGkIZOal+Hpl9yg99woUCqYrmH5IMamc6JCcxW9MYF+IQIx4SAxMMeb9wgwJF4modaHRuDWbnGZ
kZ+2eQN98FV3lfLg/joBi1AuD95yKsIv6gx1RicHLYIWxigrjGtyUDyyg8ekMpZayokrhyIBSibf
fj8v8Zx+kN/8rigEfb0hjw16uftPrdDIar0Q2GA1lJIhgbcSfC4hwkaOyI4uVvgfftuvkf+v6uWb
yxhsaWhdCVaByj5nUdcCSf2v+XKWbrAQyEyvz8+ZFUCxlFexCSf44q2Ayqbhs3q3VLs/C+Af8+V9
6K2pL4L7FunygO+PJ8QZLhkWuhFb4M5hp3gME8bcxHfdkLEiqTEDuH0CN/ftkssfsMaCJUK+wBn8
h8nY9QjFCZTuZgnX/Qs9CIRaX0L6REPLlNoEuNwzR4RyUwplwjPC62PdZ7apRi3tMn/qNE66b8qK
z7BrchdCJUkA9NfgvJVgZl3GFiVd5e/fpUiFrpC7b7H98fO7sOqlIDRI66MpJhtNiD394vqxUst0
a5Mvo1sdkoqNjXvygYHfs6JAEYxx3h9Ar3skC/Cs8eqn9zJruUf3W/3qzZQPlqSPverLMen6lz5h
QSYDNLy4NO9HcQCRkTn6MH4WDQSXcjQr79qtwpXlH6M6vIp63ObtXkS2fMRfFU/N/6uLu0mO6S+G
Bk9RAj+it5qijTrzCLKCuutNpdUIKMxj4aHSJz/DeWrcaG9g3s98Q84o1F2rIY1jiUkKGasZtMlK
Co9Yc2ITWNedqLY3+7Jj8JOaksqR1dG4QT/22QWgrL7TjMUdpabLP1VIrxgZLlbmE5R4aTcfXXTF
X5dzBhZ6XnJ9Un3MYrGM3TmBl4BPbvoMegSqlp2rctQMIzTqiSeVNIr5osgujiU2Nk/E7YBJgaxY
U9xftWHXjlPFX+pWLv2l1NQSrfN61FmYwIq9jkr06e/Tf63/pbA5H9NV4k4NLwwrNd80JJ+rgemp
iwF/UbMhX4gxslKQiwfayvPjEtn6XFLuBibq7DOwOe8CsoJj2IGcj7dOg2LKSy/+/1XkmOtxQR8r
0Dv/277H8bcAjQ7PeeNRsayx26AKn4m5QyB8G2ToW56Jm3Zy/PGliufgUDbrQsx+2Qb4y2424bgu
BDGKos2DQDmqwcG4qEAENncFiiVxdXeTd8nx55Z+6CwF3ECLtc3pIiOcOikNUw1DzrZ05Oelqm1Z
TJm/vPpQabdnpHF3H0/dAxZfESso0EibQEMX7gLBDj383J6MA+4TOAZiJ7G83YZTyDqiD53u1XWX
9rqBLAO6aasd+p9eGnEGVSVkBMeYIqEz7ogBmS/+LKx+BOC8R6wm9s4A+aqbMlnTBsER2HLkbYqu
Gd7GPIT6oRgGv94e0F7e9raxt7k4H3Ro10ec9AsjHadQBDjc9KI0UcRMUriWfRWB0FimH6UMAPAf
75AE5xOIyQNMhUvEXrVqKE1Fo7hdCtGBZYJEsPKdNQoBZlqBWbZC8Qhwcaii2lVrQKVJi7+2N17d
2dhcav6hzq0Aj4dP0V4D+j5I1OkbNan1xtWsKTgVDY8J0R76BqEuLAmqvKzs6Nd3UJ/MPDL/KDVA
fOJLHPdP9JvMqCpPzhDo2OZX9Vl3YuS2vfccwDA1iBv5H+kDfa6+VjiVzhV1xGaP+hOB+IA6OrlK
E8uTYw8njGbxGpOxxP0hLOib2gLePRoUzkLGRZdZeTD1EoYq1NGZoASGn2i53AEwXs5hSooLnao1
ZuJGznzeK9MUIvb0b7z83JuXdQp3N8VAh7TA7GwO61skklTNopOcvLLyqVbbW92KHCFdvRoQYbdc
y5/8i/TWimO38hgR/OCOP7ad2sMCB7B/H0pDyXdcPN0bWKem7UsJ8hNFkDYuMqHNgsrdgKjGWUVE
/9NyQLZFPCpra6zzb1+lFvglOAA0g2foV1gv2w8a8tHRCO8MHBZHiPXCyrkF8vguXLm9pQRYF01i
m7J5rgor+B+rPguGFEef4UUyqF2pl+Ff+pKw0JqGqhxUmHk4WBu05ukgF/iZRXcuGKBbEz4x0K/P
a0Khq4Gr0uld6TU2OgV6Bx9YvRZi3dw7rhsz0mibFZjgRc/5/9waElYUeUbbetvX4GevYGCjtCFq
zhkI6bDrp56zaoSd0ZrEBZ/Ed+y1O+0DeJn0hs3GU4T7eEWeO9Z7i4XqAKvSVhEQCFrSooA421mr
4qKyEdDvATQkHXzRXLyKuGZoXThEgz/n2Xe5HVGPjFxv6Lqe1AHIXZPqMocURwiDNagi6M7HtFE8
sa/KVJ1LrU3DY/mJhbw8cfaF1x271C6pTSCsRSWl7JTia8jVoh8G87VBU+VyUE0FX9CSsSGW4Ioj
iRuylqqOXnFR6ejHTCg/KF+Kl1oUN2EkOIgq3vCaVtuvlzNzm8DMe/9rot2hf4ou5BMqYfsINJDR
94j7cR99nEV1MfBfPB3UGFmMKb5mxMo8Pctvcd4XFbTPjiUFWIdgkjcfr1EMX1+V8bLzEdQJGFJL
4qyXAUn6cLqI7QEoYhdszHcMTGskmWvX7wMqUdz5lyrLNnitq6N38EDATK4XutakAedK3GE+bSNg
Q7BjuAPD+BB+c/AHllIgyAtBjRXkK8u2j+ImLmK9uWEki2+EJjvC/IIOxvVtXGLGov12DpbL78Gl
mfKGb7IuwgqNgRJ8UZgvQ11FoKPLt3BzcPAaKujv38+yogQ9gTVMYgAqbvPc9aUm0Ri9v1TYPng3
FFAj/5OhRU23Yt4Pk0d6Jx+lV4VvooPd15wsdUwWm2QFK1CuvMhIfIkkY80WkoD+v3/va+urHMVf
u683V7iO2Wzg4EAtavwuwlLfjDSz2zlsIEuu7KxNcVsCxVjeLYzw605GvP/ngwzl947h93v6FFRU
Y9mEcm6jLUfoXrO/KszllaoExY3wTJznt2Mg9X5ldZ6cCRfc9rX5N0Oeh9HE2mMBurKvCIuK65eu
DQQl/LOYzFSHgFOQrTmAiphnLaw/yXYxz3z8h4Sfhyhu90PomSqKeimGs5ZB3jUH4++aOca7iHK5
Dv5lqS0O/vqBYmnqA/dkCliOYJ0/G6rG259rO4xV9vp/zPhw0ohr6AgTordsnyUjUkepUYXur78t
Gd3NiLCtzYlqp0Rs8UBdtBw2fQnxl2lZFnYA5bev6of4FDZFxLa7whLSLAIqAPhTZYVkq7PiSNHv
BGebYbsUiD8Y+KNJU2KJDKOwZrqmv4U9GoCDlmg7ufQOCSAcgIDlIygbzIxvUpnRMByP7X/vfLR8
/Qj6Rxxo5qaEmnUMaQob5l4ZKwDWIa7V5Dku72JeSC0UBwYpRlK57id0f1AsiWD8Y1WlQ7V4EzBp
cX13wlMsD8inecE6hofAs8258ieS41+YeLL5PuJ0dQERiaDzB1G/heTwwP7bq5mf2gOT5mkIxRo5
22dXrnt+oOxlmhH8F7I3nOPwhujzB6ur2fMCKK0VtKk4BxZ4gwfs0E1w60On4JT2tD0MB276hvqE
akWgBs5siKaPlDbZ6cYwyYOVWmL0D6tmYKCdrj0+YmvjXF5edKlFL7c7TtF/jNBHvZtz1s2wF0MO
Qdd5ijct14dd028RmDj3/Ka57W0PluRTaKxIAtJwohPK4sKjLuX2t5rn79eAOsXdBlbqHIjWAA5N
4FGbDgLzkvP/VGWuEX4zWr6Pu9WW/ndNl14xtp5L45M5UxAVVIwjt+Mrdxl29I7DWL1gf6ApndGF
LCyBAYQxQd4hH9j+mwiUs75TnkuQE3CqAwRWpJmx30f2WLyNNIDwrGYYrwaOzFjoyCe0HZv5/7ah
hjQc12fM/heRbYTkyEC9MoOK3PZYjnl3a8wZ+Yid1MOClvpsFr6LL+mx29stySfLC0CJHre+4zee
e7BVqpszWvp00/9jJ/UeCLy0tPRlP+9O/E/CUlySuY4GpQ1jm7nTl6JA8JOObFfsUO05BhXqqJng
wHYnn+egyNdLF3h0oMdFBBgfKx3if5+TyPmRpAQwyypTFOXtS73/WXhnS/IogHLkJrn7r7xO7Zzv
avh3vd3uvvl8Uxq7BSCp60ZfOROKQAoM8ldz8RQW1GhhsM7UOsze6zsClk2BwHvO49w5ShHL+MHh
mSP3VSGo/eGOiF9wle+R51pzJtaiKVuEQN9Up1idToegd9YOtDSIMwjoQYPQ9B79fqKAkAL251Rx
dO98L1RAJmZ+Ax8KqxExUx+XWs3Yp/bh9V/EMoC84F92FVo99n+vFPFyVO2yrIuhHE1hlob59AEE
dD2jVzCfyoABSUnLd8MASINZyMo/VLttfICsVRGYL+ewB0zFdwlGdVH3Bw/JH3xkzjvg3X6EYf5m
H3wQMpzOshzwdfvfBtvtZneYwoE9yxSD1NEk3HSUhqfQfxraR4gBhWvjGSU4hGbHqtQcVd7I670k
SjqiwMFfZoK4vtgPUCWjzQQFFQ8M7w6DU1JP/XmxwQDQ/VcHhHEAkHEGsl+RG2oeZDIYv4x+zKwP
HAf1tS2/lkOl7dWTrN+HjvJlMsdj+VMkdGbLB4FUt7t0XaPOErLrzDJhmanrPCgIXmYeCXlQQ+RB
CvngPhypfQaP9w2N6PKIETmlCfPcxZdb7b/BEuvtOIeKV4APz331Srd8w68qDyNOfRgjjUcq5mK+
rnOJozurbHEMJoI8lLLN+PqVDnV34E/85FobGDuYDPums1EwlezyM7aSenfANPmz/Px9uQSQVI+d
/G3DGjnULNK/hvHJs12Gd81mqOhMOnavnEwOW1fJGhlIcrJY9gN4p1gs5wLPJ8jwH5aRHEAwZtCb
Mmd8Pp7KIFUdfIIyVC62NMPtQ/BMPjNO2XgJY53HXxvw8JNRR88eTC9aGo5YuTdsyX7emLfUS/TP
NPhjznF9mg6nvYOYu5qawqY4NE8Smr/f6ouzrOkVg2yKaYSmULJnO9BuJtrf1BWE+EIEQVLFybRh
+l7cilfHa22X5N0HBq2o5HQzTLSzFI/hX5Y+FYb3qoLB4k3nQJdV/bGMyiBoTbDRv3K/Q1dupHJs
5uOZUetINkDvpHZQ7hjOf5BeOnGw8ekfzeD5w8P8sKp34de0xw1fvI1LvUfz/p7giWCcOwIVpiu3
bMlBPBAMK4U0Qa2S4QUqafO2Fi3f7acihMabA0njMp7IAjchfhL1nQkbW1r+hDyIC9CxkQglKDur
4D1bDk2G7BuDyqK7c38Qkg1cNrtmj+BXdCGG9Q0L5xZ7MxOISPV34QCPSIfJjiEo178uTya8QPw4
OwPTAdyPAEZRQkbH3nwK4eFcKvVrzMv8/nK/IJ4XEDXzf2DYWD9kkAUBi2s6hpgk7V7pvilRFiNr
Z8GyN+fho63mEtfanA7zVSWzvVBPOY/Q/9MSxkXJF8r/Aq4GDVEf6jLATSb530lmNubTa/hHlJsh
NdvUC5Z45XHXqwd5wckRqdKPUf8N39m4TRFm/PfK3vgdUWyQoYqqaLQ5+1XAZqkzjO0iCoiHQU1V
6OaUUn70J6qV2FfPkLAyuMgAerejS9w/EUnHMAidsbKEZ9bKyGQnqikEhlRKuMrfsKXUNujZz8PC
2V0+rOxTeM1euu2Q0xmipQjJ454przuYTdhim0KCKsQITw//EuPgx5Dl7q0i6BqQ7Amnhy20jdUy
FxP34NpIUf04L+qEy4h50rM4Q0Zg+wacdubYegZLB4/fHXhKKLkKth7W21h7lqk9s8sMuUi/PF+a
cZneO8T/MHNGyaXRbXn6shlYrLyLCkLU6Ju8RuWtGk9KOB4xICuN9QYgQRtdNC20UPXEwr45QMXc
W4nQYCYL3s5GgE1UcQ0RwWsBOTz5gDjpbl65CsVB2RJI/b+6fifps8KpYfoexq7yLxcbRqswfY3S
yxTydB7zNsS0Yt30I0CL6Pv/fvJn5L1eNdahUXnIFFe6RCwGnYmskGbBpVyxVhmS+qid8xrfC6UP
N1BLKD2Onf6zmnUhCHq1z5fjiESvKdOLOucqVmRr3rpq2+0RufuXkuwl7K2+lpEEeyUQgx3u86qq
fPKyKN0qFO2meEBvh/fxCfddjz3QVngc1ohHdFxriQQftFOURyt53Ad7luyoHjQmF2YW1+t6pskq
jxSFSG+CmtB/vaZzVW1ubx9Pu4LY/mv+JLklwYDhRQZW+95sZ7fa0h+W4nzyShL3hK24fSbP310x
zLtxPjqmWWP2/sKR7FjOulbw9hqffPGBB1xE9IDCvsymnxg2bQl0TD7/ZdNaJjylKClZAtLj28Ct
JNk94vBVxwqgJNsV+ntYTI72r6UaprXWe6XSgVv8bzxRamRPIshhMOgWDO9CXJUN4aEIUws5Hb2V
1XKQeIfGVg/JqLdmKPRCrICCaohLSylv1dNvhWMEBR+8y+nfPu55YuDdngmiLphrqGlrhw+U8oYr
rU0iztyB1mfQTnfwvW05MNkgKq1NxBDh4IBS+G52l8MPkdn6OvxxsiDZV0COty6g6LkwXxdJV1xV
Rbd/Vws6wALWBZI9yHUx2HcOdxSj6RawEkW6153UFWXzuEzDz1KGETXFRqOprPdIjAGTmSkM1ynU
1DJdnVydrvz731yX+s2VHlBA7r4DL8VbOOThT0dF/C6A0vzblmBfXqJ3qMeuZL6bYstbqtyHe0jh
ZgwiQrq1n2NlOv/VEO8fkZZ3bP2LRdweGtHQJaxXPa0X0H1X3zit7n1dgByp8q4zxJz7qC1yIijd
CzAPr03x2ubmi8PrkAhitCPeO9iFuuDXD63Mzx1S+O3L9DEjN0OgDz25VwLsM7SKyH1thyQxgCTE
6rixV4nyqsDojDBrwz0t8FnsBA5QkuS7R5Ro97tn/C/k7vzJXopu+eM04rRmDGO3gTJvWu7XBkgw
OIyVZrRTEPd7csulSjO3Uc9I9BcbKwjOpEgiiDwn/vUOJE2/XeMWy28Cmu9TCU8s9yXd3ohqVYOz
/LLpYRJDoed34z5EAZQnq5yr9wkv5lW/OPFGij3jzJ1eX6gebdzItUOaSBvUl66IKrXCacQUqj6v
AdSVXIoZuJEgQMrOHEVaEEUK8VPTJfSv1BEkMBoCF4EtIjgoeVrs7EAnhnimlbrWUA6vwI+CtcD2
9mn0mR4i0xNNBYV1EmGmAaU270jF1dUlNMqV0jjQP2xnVlViNZUv8NzgeGPwAjmuEjAqHgZZolii
qRtLcu1Iw1xedy1yqYKgXMvAkmijUUoN3kPtpwwnnpnRD5SwX6sSOcumoYVNoA1tlIFMCsTJluPk
nUwnUccmvC36I+hhTliFkUF0lb9f+ENzN8N4IjHxOo0e27OsbC0b27aAhcXD9dBBeRc5hdF5UC0j
NRamISzkvVUNrH8cpQwEeFqcRqHnFm7u5woFQvEh9nBjuVrvxs8wazTZ1SRNq80XYAQ1kTX56wXc
D6Yd99Yzbqhe1g720n7iXQncd3hq6Ffl+gsDm6YXofExfqDCpeEbzxyuZ/uoKwk0Zo0pB4hf51MU
TTQK1mB6oTVkHlvoEzYfWHt7Jctkw72IXi3SFvlOVELB45HySOmi6G4YGREcgayQPZYvr2VERPRv
VksXixJIHNiSb7NgHf33Ur/VboZR+hfHoF54b7Y+Qth4QJDKmXnUI9B7+pAeZRpVLviY1Al/tURW
ce64wzRasL/8FA+N+nzGsmhQ3X17gnCIDg2v6+N3VvZMvKcNQ+Bl3d9oPKKnTRCkFmjt4ht1ph6Z
MeVs5VTLo9ZGIg/7Xc1O1OqpW350EB8CZyWjxgujmrhfc431HoqnrID8WXoJ3++b+Lh2vmS1MBG7
204gcR7oSvXAtfGxvwKQupm+6ZJrHf2p3KTHYrKJUvWGlZnpjOeqvkKbRdKq4Ldbk5qjMLfRf20p
X7azrifxPIMl5pYD6wWQDzxvad4ZbJHfuyvLcb4+qfiywUXU2hnUvUeFwIogw6uWHNUQQ0J7QJSQ
8P3obmmVJJGI4PPh3RkxuQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jqxZHtK4DF7FN7MnfoXwOPg9JHLh/xYyJVOcuANxf+9aDyU8tiAbMKMcksWZAVyMCFpdey/nqjYh
/OPH2/fu1w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UnYTLPVVIcWXQW1hyG6ahQ9XFDPUnW9paO39lozGP0YcMX2Akp9RmjSXxuuMoNtsYVEji+RX7LT9
fyJE5drW3mhND1U//SSeQPkA1iFNx/SNNNsaaYmEDR6VmNMnSj9t92JKXW1hyiEDPBNA/QlewL8b
bH0qgcHPQyfMmur17XI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Xwupj/KUD7H+XEyDC8LyeIlyRqBAReFJWy/CtZ3tay8VXbADL67XAbdVX9f8lgWei9aJTVA6WPjB
QdoY1hMd0pJlPyi91Jx2aYKq1i1ql8EHPkCPMNEk3lxt1jEWF0E6okotqWgbXT2guJeZQYa7K/FU
KOLWfkMqCt4xgBsgWWp8iEDEbKhbjcxIJQZVHkXNXLnNzn3L6XdYflHQoyw+Y00DxjzBznSNlUNU
RJF64E/g8M6k9agDzwf8qw1Df6mRpWMlVbVfvuR+N/7L2UYD5fr1jvoMaXYJwvC8Z5smi1KkFFj7
0/aZ2e8Ru+i5P71MYkSPPF1YmFm0gtQR9RrOcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lx9rlWxQN/kYEKka9UUdwsMbC2WjMyihMvnlGYopOjXfWByEeTbWfmCjFd7eVwgdVEeb61pxTBon
c3RsGtVgfclQ85Z1/A3qtMAH8UiXrkxFQd+SMjhFeCnfMUG7XFVvU/32OFX0kryJwzNykkSWWKSr
mfdgzRylz8ar3Q4OwbM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
olHkIijGKXhyAkPsQhczvzeTBQSoEYvYO3tgbaqFjnpXLmKMF+Q4pm7TtOgamWjUMmH8gm+tQv7L
zupyfd3704yvTBMeUc2cZIQWBLcCui4M1DTfGlE2CTN87Pw8402EGEPuY6iwmRhphTUZjawBSl6d
hZW1EomSdBx1q4GR9xNlk5Dho66UL1RywwPzxyyu7nr/2NwcEuL6t00UrX+TujdJXK1MRUWqooYh
+ly4V5Sq+5i3qoOPMd/NmGUyDTnWViZBo4XhLxmNXg348RPgZ/U5/RYEspxfdTi3YKcC7PyQfqxM
Y/gHvkdYBcQ+nlqezDIuhO+9G8tzuAnG4VQn/w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15520)
`protect data_block
7j0ddWUK6vS/0f5k/gL8CW6k8ZyX/3ChOfrvOaEvCo3+h+oVu7d4pSx4O2pw3z9cYS4+YtuIqYoR
JgpruPJyJww0YVdcjEMYqRPqXPyEzVT2nT3D2zKqFrYEwg5PgwluCjZBEeFI7U1c5FN0VZCQ9MH0
3dSOMO43FIlcjddFYs9yDCA1sI79KYr0t4RDUdaeqBumbkzbsIjFje+LpuXS62La4rpX8++ycrJn
car5qyIBLeMNX8zm5aa6pqmFT9AQ1sKLYU35hcmqe7SwcWKZvn5H2bENgUDVBU1rQPR4OmusuRDu
Yc07+4uuERdyBTZ12wy5vr70tdfI+EgwTrz9E6DYa7g0U/nFHuA8m8oRoZe8FVkQCKOnLLr0Jb73
QjaQ256EPw5qyZlSixUqDt3/eSYJbyUgPtcijvLxW6GvNFmP1YXj878WX5mRwUfq3BJcd0P44maS
fQouV58/bN9OqFWmsQCxq8QAkfLOPr1W2Ls3L3sJ4skrKdPjFHHZ4goaRSZ616rvSB8IgjlOJPxX
geo7W8SJbf+6SXxCP8spCZYSxwFMbgATi+WJYpGUHY1J56lpXg8z43CNstZrzWu0/mTCTApf3VAv
28swUAHQw8MK4MWAQCy7Y7i6VachlTGsBfdI+8xnAHzVhdMEPYm6DpKAGsKKz6TqpRw1pfAxILX/
JywMicqzVW45DPZfWcYI5LOwbv6IqYpwv3A+b4oD4nTYTwGiVhEsyBAwsRJxJBxDD07wU/aGmNA6
0CmkORg29dMD8daU1rgHPgqQV4H455+ABoRQIp4Sugrxi7HWJhXA35Z6nXmWfNLjZM5IL9UKMe4N
+Nj1tTm+F2BwIv2WLX17bQKCgjz6ZkmtsxdccAlywHUSPlUJ2IUMyiq0je+/EstBfI33pk7w5VdB
rv1gsxHoJXjsA+bHgCae+kh5pGuvBFmQRYIMNZmuePJNpFyFqgPz55IpAfC9hQiDs4FXW2F4+Vq/
KHWpEGejjgnYER1+SDuy3gN3nEK9n4BR1s4N8QWZPzkcRodXlRKWwIeG60BNVWB8JO3UFVwtYbk0
uypciLcRJMGrdO5e65l6IHW56OyHwVUXTbJRY7vFBJezRIS8HmxYhSfkDwuH6xmafJXB0CMQ61Ux
Ro53b0lkp00TuaQq+e90Bs6yU6jB4g2PyKxTRwOWPLEwTguNT1OouXp9fuKZn19pZc0jTr85JhgK
ELm3wjerSkKEPBVLfB72iA3JSuLNpOw+fPmg/1zprdbvL/uR/9ZKbnQMQ/Hmq2hdpXfS6TeNmzJt
+CtroP6yKwdV+j8YvYWc5X2MGlPd749d3KNhngrjbhloIxypNicSWasxptfDoHp8zw5nOjw8XS2Q
zzVjM/dWcsZTDBiFqWy1TyTVW62FhnzkZRbiOYCKabWxgPCBbcEzcXjMCV4P0NJBnhohBw+PmQVW
WF6+YNh4CCv0cGXAbuGJ320gAD60+AxkbsXEFZsaNfuU3md4osa8t3bDfFslc6on5h/3uAshhgSB
5Gaa52sWasB2T33oiAasnVXlqNNBS97qosSTisJv1gJpR1gaiY3gYWOp02rDDqnQIlSvW2oCVWxC
OWfW4pAd/yDnGKiYunSpawpEhHylvHPjdgXxIvzslnkbC2ZYDodZVP68PeWUk4QqbwrcPWldxCD7
xbeefnY4ELrEZCu4CAfTsDgOAs9WiX/SjcSOd8t9FNk0a6oVgN6SvprWs/0qIsBgR3otHoNGDUFw
HiuTLIeAzrFfYZ61PW+MZbNAgdg5ZIqK5PZskL36nQpmQf4O7ScnsDA16aSmpTbSKejN9A7naUVE
1dG266Xznt57ObuIv0xADHJdSCEjhK2pDH7VJGxJr2bs1RNbFuGoP3tci+dfCcnmK7pdxugt9j4J
BwHkdgdUhPVtu0DKpFtf1+/LX+HTKKketTmFfiDrtN9cjsg5n6JeHC255NTClHsBoeOouwQZzkJS
7msX/mJ9EISHnJx0rtTOXrJ1y+p4SRr8RehS9CLJTW1WVrmph/ExH3skBMtzlxCDOqSIuTiY+7YD
B8p+vhUQ5j4+9uWRIleDcDG2HqMhNQiIB95bPNx1yISTEzzdHLbo+XWpHJzu0z4qF7POsQsnD1S9
iSbfRkFUXdFCEXEfiukeri4gFoRXqUfIBDKNn4ba7CKAhCNIO8bPcJSV1tbNMYgjLLHOIphryL4n
rvNTDYCvdu7OrZo+Ia5xdwWyrXHG4/b/dTEyMwFI969QUlT43kn32A7SOfXUYq4FIqPqcrWznQsP
C8z5YTa+ALM73wrEPmBUBknvap5TeSOHLlNpuJ+GfO642D7dKyta7Ghv7AxTXYzLFnJLhPAScUGf
q3b0tloPe85HSrdQ1ANgLrr0SE0zpTm7hXIrbrsEcvr4vYVouEGcGB6rBpdmM/QNJDgIXdcWI/DB
Gt1G/pTw2YlQxuF2tD9JjanKoNLfkaYjsoYoz8WkE8iwZU1vhSPMPDUWTCb6R5zIr9EGKBp/OTHp
q+X1Sg08gfsLH78m1aZ5tyvCQyL5kKONDbTPkrRvU168wFH55x0Uz83pTjjVpbDv6DVcVn2Ly0GT
K7Hv73gefhsHIX2o5qe8grZ1o4LabTrc9tqUgj3hosexijyojbvJyMwQTUO4Gj3BFmfkSxbbeMIB
x2jYdu4PSb4/QtpvgION9vXY01Abf/jfwql31Vwqae38dTpuJ/nluO3yAxthrf9F5rXVuuTglsGh
vLBVDda96xaZ8I4ui2UQN/s7RYIM4VCfTUrx5JYBfDrXjQ7yw46lLNrgfVkgBLQvj40nhHkTzAz/
Z98Nel0ICntxlUbjQrD+ZwT/y+jf3DuL8XyQ3D3lY6MAb4eA34OlTnDy+AxxlgERCjlA1PxjlLzB
b0MleDaSvHF16RYfiWk/vHKtplQ6UCqbuGi76rJM4vIte4myppQfZ7ckALBIFp1ek3dMpPz7wXqi
zXtGpamGuut1Ay1E3p+W2OSwvMX6t+r7lDetJiusQRPFwPYq+NmFXn4IMwWXGErcth0EyOIUXyOC
6c4ZCLGTM87XR5QhFh+6E36hLFvdSU+wNTuROmSmu1fEEyRFcSo3WLxWY4RF8qkzsv13Jc6ZaXcL
6froXO+miJVagvg1tvNwhSlEXMW8yt76lbVcmxQ2EREtjV+oTNUQiyP4SPAm5lOLsWh7gbFLfRfl
QgvzwBsjkjxJPGGqfzH561jfNYdjpyzCDPjpnSI6mbkD8Dp46UPQbZAGils1zUpHUKYYX5aXnyIY
abCBpei1NQiC0E+smKdRgSpJUZZjoJXV6iqvvCbnZ+ZZ1LqZvJasTNUashy19ERYNV2hhzrqOO8E
pxbHbwJMcF58UoM94mtw+pWa42HuiiGk8hQgk2DYTV2xrYyJNE1ZdvgOTxhlj19sCtc1fxkOZkNf
GpXUIGtvM62C+bbT2LPRw5WJE68di79OPvRnfRr2ZBG0skcMdXNKWlbOIv0s+SZ2vMxKLZlmhw5B
Fss0HX3NsjRCUwR0Cd0PSMKTXjWeWQWYbXnhaLAhw3FHa3jE11a0tIk7an/eJW01CUR3Kx/svYEU
ppiTpqW7x3Td4LIi2i/HO1TwBTeM4VXzg8KKkyG/T9zfgfnFLKr+IOSuDrugJcLsf3C4zRX+/MpP
mDlVmaRR8rFhdBTnM10xKtPWgtTicANhF9bL4ASr0VGIM7zng0MPfgiudCvBJn8s1y0+sccs0fRG
FYa1Rvow3aYpWnbcR+9uDGRqERbak7dVziOffPRRB5b+NV0Qb1cyDqpz8Umly8svRhYSeetVrGkb
mYb4ykuo37kWx3du0UhLstgg6elvB5rnYMFKAApE9Cfrzzvascqa8OTAm2wyLljZgART/zvPVqHh
advmVESloVvjLxhC/9jsYFJ475xI3PN94YUS1UB90zL+sRyAvhKIyoKiTjJgNdULoxqYmL/MVsrM
hymiTHxJ8S2ZO9V7FstIm//AOffBnGTXdtRTcy6g/hthAKw4D4/Jg9zR0V9egjdP7jkrthsMdmso
1eu1gV/kuTxdlDgUU4xavRs1V5UyPLabWjli1Y0n6TuBPT1ygUyksZ5ffYaXBrHYkpVfnjqQonzA
S8reO+JJI08DdJvgy1qzpJbmAJz0q6nlnha+C4WcdTx21k9L2pN6iBABOAQYsNoAQYYMvxPqihfx
tArb//2YQKmOZrw7UsGJT8xDXe6IvoRetHaffxT1QT1uh/DPzYjjDhJD4ILo0OicK9AGgZD++SRQ
wy9jssTBveFvEHprK38BT/Tsj4oKMjDx1mLFoP5r3/O4KUswmdQ8URdyJhdZI0snHhu/eEV6V+Bq
qvyHRgDtbinHzFuDY8pYAdZz7+5QFELygNaDBtE2zumCBqDu+UCW2w2jTMxMPJ1RTgfvfaTd1uT8
A9RpNtWl//VpKo/ytzQiBv2924Wj94tAYUMNFIi7xUV08ybys7fqQM3miHs3BWOr2Ca0aWrE2EwE
d5DNQkRr5W7EQlqwvbot73ef2ROwVLI8OU7xwWrpvSRFGXzVB0FRuIrT0SwDSl6hEJV3dFyfginS
slOtgphzOv7p/3DX2gtLY8odE4wHdzcQJp+hXk1P1gDOyU5tW5vY4p3igf2UPAoXmgEsZ965DMCq
zMEs+od/Zuop9g4osBnML0bibSP7A+qSVErhLupfGiieRrDk3XTNDIIHLA5wLEJUWDtbELRm4Nmj
swautmQKa/D2EIujMhj6HS97igUFNyQ6vGRdKrKa09tGD9HfcAjxjzoZlhG7RL7cM5yGhWuYCNl8
N/mt73NiXBuPGmLgZ/47TVdqCiEUNyZzhihCywwAM8wX1Fz9gdTUL+PE9hentYKjDb5f3jljwVqf
Y+T1evltO87D7PMh0ZlXay9Gnk6fY9C2q364my/9J5GC0VBSRVjl1ji0c3Xw3rgKMmg0RPb5rGYF
DLNu7htmJXhxywfuN5cFhUzU9TomRxCjY6JO7iSPbcIl3re2IL+GeFnGvPcD+CCQAJEAahmO8WQD
Pti8l+dg7C8ZU31aZtMCfoDjKpwep8mWMD5Yrnm0kbJ+JIx3eSTtlS622pv1NmvO3Pl/KN21SiQq
6NaR4FJudcjEYw0u6dy0HRRMRakwt+S7bgsqm8rHtNm4Nr3BCNNU4h2Wiyf83nndiqpt5RosLYef
H7TYmRswMDfBLR7RNFSrgSm0k9jYFCGF9Vwyj2UVGvmMd+vCFnhaUHZrcnZjJa3RLG/u6v+y2ptL
QZRNvbryyv/d9eRZqq1Ch1xyT2VlEKkD/gQ3MxzvZQTUIR+wXiLVWEMAUTAa4iF0qZcvBB4WVfay
tlSawtxvGEIohKofn8yTevFu9Vg3xjd3k6FW9Mwt5Yvm4uFgSNuw/TR1P75bE4ZXv65ZfcCg2Hmk
TN5Y7KtaAALF8FLffw6vEUnddjM8LKVClhZZC+IlJ+mAEagGrXSVgrTEnykDuYIb1yDOLt0TfQSv
R1FoBkASZv9VGIKrqdXeJDjYi9kOQN8L3Fhxr4up3qF7INDUHBJ7ymVNt6aU4l5VxixBn16l8dkq
7619SKOyS4MOMyGwFYoNwf4grnNur8p3vdb5spXWeAZHpxfICjLJIAV8QkTNSeWWqC+03gcgwJDm
MgwpM5pvtWuCiOK/6rlVLV5OgdEyqubn9BoO3xGFEVG8Tv/igmR3FGlliBtwjm5EVQkNYvjY3gDK
xQM3kvV0OPy3XNQeRtMAzpzHb+PGy5cTIdIIjvmqjwih6Lq6msPpv0ldhFqYv7Zg/x/7257PgovU
rsQUAMee4yrZOPXjTqCffFZCotTguu/N67f3k6naiqAzmHIoKJ/V/7f1HJ9iAp36NAWNULcdb0dX
WUaWILMsWlqNJt/+ZUOmxQmseyYtpbFI4nde1lbNIFA3nMvNPBDbZ/MMTuLW1m8TRxyoPJu5Xy21
HpeS6LkstLP/kaX5Fu4/N4ysnSYHI4khYPKtpurnnX9cfhva9KmH5WexoCroZfZ1jibGjRyXKzxB
57sdDhykSu1HnOC7Akj/5TWxi0QbifcDJjfX2UWULs5YZxnw87pvM7VARNbAkboZkM5zAwFLwSCA
ujotU5RI56K3UQxsm56gLg5q65yQI0+sj1OOSVIcj3RspOlzyeiF06/zLHPXKW378IGQxRUoDref
DsG1AZ/7mpVh1pA77PjBtx7OdPsbUZaJ8Bf5GNuhEQF5JXvv0YrWk96TzWJ02jGlksVIx0DKLtGq
iD/TzodMndjovGY9EERfgrErS0H+lcnrkmdNTSagtGvxDXxYdUHQtQ5tDMNdQQgr0jVFkja+KJUH
rwPGX0Kf8BlUnCVJUIGd2rK1oKUV1c25yGQAG0KAoyT+Y5jkkw6Jc0MenwDyOo9ypDA2MuBvCyal
dh92f1MbK+wQ5q0H6AnG+8ZLZYsxCCSF9EHmHimOjQIceJKUrmgpxE2pGbR+SbnAlQ/UG2V6BdQo
4Tw8PuDawMu563fdMXJDNJSevt4K2BJx4JhaVs4wcw/8U5j8f/h2H015oNG1uN+faDV19l83qg2q
srpYZHhL36M9trwh6/CqXiUkjqLbBmZRLCpzSuIj7nuWw3yuaupKua8ytjF1JXaF9d5Pn2iFpN21
MgCwP9cX3VKaSxuyvcweSIXt3/wmmpy3Bd8nSFq1tu3Zsme9FALhIEtBWrZSg+cFU2erULmQt55K
Q3+5EIPOUaR4TkbCgzdWv9GkFyQ7IDyTPMfNUQDhk9VTFwJwnH9eo9zWkk+1aPHFdzcydA0mWv3/
GMjV5RLflUmlaA4Bev8niI5u+vO9v9PpPHV26ZF2JlsEMxQFUFMlrt/zbPpO8v5y9OrP9p3krK0U
PF54VgQaW3OgTCFEdk+4L7W6RgATZNcc1Th/5mih2V23i48+iW0SIvkfzziKmRSG9BVbm4EUkp0Y
wfdK/PPSuPEGNPlJy6V5jYcgXP8G2fF3SAxsIuSSOYAPJDF/fE2w/ffU/yES9RcX8s7NNZlZO9kP
9eZcuc78j8JNvyRMgCHz8c4Q4a2+1RJD8z6Z/Q5SJQibwVqsGaSm4CgZHsemKpGuQWzsYFB5K/2j
Fi+kjzHoK/K5lNL+DxcXug9NA6E5QZOdnBR5NSV8g1kA25drirZLbFWP2xvlyxePXmXI/OGpVNsD
rahlb9a3ijBhgVAFvjVoqU4zz1Fx3YJ+5F4pFiJLfrWmaywVXtqN7ovQFeNscDHXfWf6YS/if1L4
1xpMhBA4aKqQnecOQOX4P3NiiAGxbqveZybKaAw5q0FKoK5XNPVI0omXBqzon/1SjAdxC4ESnK5p
jgkQ8Ps6Q5lpueFnGaElMwZDROtlzw2bzDS6R4XorF+/JNWu7CXyUu8g0HuGiu2nHQjfPKvuzU5p
ef4HbVEgju2UntS18AropaQser6w+6pQp57svp16zEKFYvDbS0VNtErea3R42vNt2z9F2K3Vfvh0
seJPlA3aJG1AsSZYG2IyJjuRxBrKZuvXX1c1T1fXf8htWQnpPo/13eXLCOuwkoJZlvWhOo8wqqkS
+x3eb8djH13o1t084MoLT5aflf8NxckeEtUKfG+Vkym/vJQJ55OYWNeZG3sOJbuel9odc8UchWSB
+xprv+HGKknTSqMdPZi3hEqc/hL99/zsfWpSkTrgzEFSkJgHGC0WBILMzobCrtSLdAc3Hr7125BX
QkYHzoOPO5Hh7RefYmjLn1FcWd+3wgqnUj0Zro6vPBwHmzzdP55f09c6v8oNvfxhOXgNAgqFJ7W/
I6ZrSJIzXDN+4oSE/wGvGluVXTlfBL4c2eJE5HWnjBybCBru+8CcGqG6xJik95kXxCnyea/xDyBl
fnFPbOyQ7mM9lA9tE5FtGl/MiLbQCZy2ravz28MfiFvLLfJTa8kdsZqSqjfZOxVR8xfl9ic1JRDc
uaKBTSCUx8OPrteXSrTlxeilwkpUi4WSzDrkGnYifROnRuUbv1cLa2YOsWPfsKLRpnlIAaPg4r3P
p7wMZRLNirGXSj0/mqak+VXJw1fyTiX1Gs1vvypMNj1bCEIw5k8MNeMqRZTkOCdqrBhV0DqbH/sG
LF0ZziCESV5l1ynV9dnmN1OTSwnlAhhMxoGJfhVijd1GwgErs+hwWBDjfu6ur1wDRQSePvzUfIBo
6d/jwnzhZb+JxvHncqIWO0HuBk9a2/tyqzB5iXaUUwf7KhLVuwA+76+fh+fx+lDltPswizb4bx6p
rJOmPzhIaM6QjkQ8/us78pVRvVbyo0Ed1+EJ0N7voZM2igzNAl6i9cCQql/1G3yTLByHd0z5im59
yDD9B+u8//s1obhFCNkDvR+xxwG+KYEpPi0kDflh9w7fWteMfMfl9A3EXcuz0czJJGlKkLGydeo6
ajk8IJKk3tk7n91fwohA4TNFUcUqfuwEcbrUI8Fvw9tZ8px/ZRb885BnH901/RxhvX2CZp96pvBS
8f57jtNnFC8xewiaUQFWhJJT/oJHI8SSCLC/WcFWlKjF9BIhU8qFOkemZHonl9+eYuf5AMURnUB3
8oIU4GBcg/Hq8e0wH5lYSASMreAbyKEOAuQQeSdvT46xsi1tHDMTowmd2SoFs3GtCJHFspRgB/dJ
SOewSFVILZzjT/VJUycdw6vlhNA2Rjcj9AFFIQ72dPoHp7CG++8T/8pN00VtKPyDeG4f3HargCuf
9fjAyeqVE1DlE070pS4WlmePulu9yFWh/cyridNSqJAoqdJco1khPVZsERv4+QIqDrsz56qS1HVq
Lg0BmoOnCpfyxHBGZcC+iDuofHwxFwv+iLKMR8fcsvwRVLp+q7MxzUB3VG55FxXwntaJFDlL6d04
Rm6/O1uKqHCcFn3q5AX3ANePmg7EUDDZNJd4aUNJKy2Cfra8mWlkyL6WTSQTny+4aHcbdZoNU0bK
krFW0VWK2LhyMgAQkj+fA//zbhhRZm181SsbGmcxXY3NMbnWdiOC4G1fkpLvaQk/o3E+JvpvCEse
5V5qtEWu4+7L/e5qQkur6pgTB8rbS0mCZdKvzKdETLFEQT35y61/0b/HOBJ2O1a/6FUSIgcI7+Ov
AQ1CaGBOxd+RHUdwDJe3IzSSROT/LWPQugvkcbBimMkzxYH5PDm17EqSHlw7AkIigsx39WH/KCBq
vBdP7U35lk55geZJka83PPnoMVv+FWhJcDe+mjVVeWFaXVcVyQ3u1qgqAgvmKcDoUV6C+rwIYqGN
iah1dESKPEaBwP2616ouFAfl1LXikqpFvFsIGQtw7/PMgXacdH5+jeWOj/Edj0WLaJcbhzu29GuO
cPAtFs6FRgsX6iETOKkPw9YchrPir3Ow1FriTDWDw5iq02Voc4eIllcqW0AVH94Ww7XO5NezK7KS
AUZ4YKluSpdLCZktWXTqR+/iwEmyyYg5RjIAAV9rWpmEeR1fGrlO7SDLNVlX/1waO51LYQSwHuFr
gBjLBpOQYDsqqvx3H/nD77KbNSGD4pxjM7ZeWgJj8MVP8wQPyG4D40t/YjhtyPfZNzjaTFtYWl3Z
JlNrv1+8x2axhDaRTZVEsmtg3inCWhQjHjuGnSv19q+NUkXsYVNxb1jYPObCNIGOeiQ/6ULqbQrH
V5DKlhV8zP/vDwTL3xnapjaZhCKxJ2Z/W3RPFRghMfbh83BMzi+NCWANTt2JUMi01bCgqR+qyhPk
vI+cAHJ5qZbSJBem+bCA+K20dLfL7jKf6V1UKnqmkFJyhErcsLJM8sUTcd2GWE0FpXGd0INeYAbm
ZtaSSTyn4Zvcw/EO/nO5bpczoSRKpa8fUq0RXJGiCsk20P4w7ZZWsT8Fy6BgBS9JO/3UdglK5Kum
/+1zxSAHo9JHVgoEr0KKYFcZOFK84+yuKJuGLC8kme2ClC2vrq7TJR8rtKlxS7Tx+KJsjZyN8tKJ
ox01moIHQeT0rWc+uf0MY5LK6EAsfY7InoymujYljBn1Lzr+8SxS9u5/KSjSI/iAwAIeQOB1a53B
qN4gPFDbQo/I1iRlDaarTcZWk/qEr2jn2Fg6ooM6V03moigUG+rehJDJQHSkLeAKkb6B8h2YWN86
UzTHtFcJQ8fpBpHTk12cnZH9frD/e1bhFo34YkSFGGlP7K28lDmBiaqVkA+llaUjJ1v3NUZCclQl
o99BWyrkb/fu7OEzRfB6kPZd5/oeWRmgUbGwY70bBE9Nx2mPoUSejI3K/m308EvR94f4bS15HXgQ
T/q8q2LgF2ksHFWvErqFydQILK54LgiDbERxTgLfvjsUZOsZQT3mKnsg5IrOCuq8e2BckoxfDqxH
dZvaCMTSVnxd9DNFlZKl+KAJOv3fk/Hn+lEJEgHKDQhLthheQ3TqRAPfU7Zd+mVSVqeHWlfEjNOG
aaFwa0SGwnYAge8SceZRczoQPq2c1fNSA3toAwJox8FfQyhX2sH5nXvjsuCHmvskUWx8DjXvSS4U
/dtKFpd1o4HgiMho13SEYO/453HtYAR3ci123GURiS9MZJQidnwxHTznMSqWc4z40vktsVYGGU+i
IQc2trNILvG2S/k4OKvGOk3dCFXSiLHCusQHWteSMn39d7b+idRW6ZaoLz8ZDPqg2mBddCJslLL3
K66L8X0eroZpcruew6/PaI5jii0WoqBufHUAAJe8FZdsyCaPCK23x+TqVfy9gFbOW6KCWX9g/tek
HahRnwhf04hLCWPFvCbdgEiIJwa453Nj0KMcC0Xw98jK17DrUpWMsG68VM6+6dZXJ0Q9uhLYHr/W
tcmO7LM0sZNY4hZ5ZHH9LXJnMjvLZHcSmpVoy+2lSXNvtlh9BEkYnj3u4rt/jBCErNltzFZYtOkY
BKGby4exajgcKE2uwOZEhQ1fGdJLamf5mqGsneomO/uPw5Gam7z2CIjYVuuOHyDxVrmi+muX0fyq
FxTdSbyN3T0XANNrRZXdataLGQr6uD4jogn066Ogo2DB2WWbUlt0lS2yik4/xjmBHg48a87nbDWJ
yb4+rDlFArx/Z4KO5OiMAsW003PdGHD4ubFfU5CXGPQY5NmnrwZAEcjNSHXwWJGBNkJCi0xx6RXu
nHqMDIc5FgrBII9V5amwCJLTopg3cS5dmgdhCeCfHlX0IEay8SOrHz+f7iM26golYkS77IxnzNnZ
M7nIB80ffn8jpK/Yr0E5jzS9Y+5LraY1QPCNktu3CahPWKR4HBvLfGktMS2vqSfm3IyxOTB5nPn7
+j17f9dicebwkZUEpydkI7zCi/qCFNf3L9Px7IITYc01IPNZbX1bOu6hozKwdvGVr4ujIRihke4k
CQ8sj1yCh7XvQy8N9LRigtBtUaTdNng4vT36oTRSTjh7hF5GkIjSJIiRVOrMJESN5y0V3qPZcggA
ssZTN0Cnv1EK+9hnEasdbi5uhPLN5C8p87YNu/vuntPpbb23jCGdMEPykgStAyZ+OXbNjS3yoANm
P4DxAFOo+52K8Qa372B7adKm0DX+M4vLyEFiMFMY1Z6eqgUoiml6iSjMNH0tv84a5m6SpyTPG0wA
SllNl3nqd0o3uR9ZyiR5VFtP0qiI5HXmEzoMmc++mCkziz2ofuTbeouL70et8UN0WmWW6DVSnJmo
X67fMQOK3aGsjdU61jeOSXmEJaX7cjYADWRw/HoL/uLuY/L3eUGzclOXcYiIyjyHVHAiyJkJVT+r
2QPv0AtaYvUzvgyyfJL+mgIxgdWLpmEpopmyemeV8JNeCnp9mSuP6p2NSXmtAOjmCcvOAJNgNx2b
lzrUzTQfVh9/mL+NnGZoWJYieUZggECE6rlKTsuZikMprCF3/R2zLHzd2jsQsn73anoyK2fTu/EX
SEpTqn1LrR0UM7pnowTYxpX+qStVqLiaHDAJt8Mv/tJYwRjy2/qaAfh37A+MyBCHTdYbXRM4mbXg
phh5iY8KpPzzL9guRyAsfi+pJdhINk2ugEZmiGowwDkFPir83WrK1ZaxND2JdJBYqboN6tFjTIJd
azirvG2BAGMDPTs2Y2gAJyOq5pus2O8w9aypcGCiCtVWbqUR1uiU6oyrZc2D6RsJuHP1iNTVii6K
SuBEnpxeXu0K64jpdWttbbo5XLQKapF+tLqeZ9RrpwfHrUCETROhh4r7VUcr5dOESQ22kJ3gq/iZ
R++Nt7yvUf5xmIvgebl6taxeojC9YJSkN4vlPfDPw2y51+vfFqcf9Bv5OEVLsIGcOZjWUxU5IRMp
816KZCjQiUc1VPIUIIHHgxUX6MbNmWPowm3tEPcftyfqsIbXzmkB7XABOdjgxUpMFfLVr8kr2tsI
rAcGWWph7qcHlNwfSR1w+jBNRmPzvArrWXGHQzkSZQp6s7f13HCELIIiHppcMnGCQ/nIa6bZhZSC
jpm0oyRUe8YtXYU3vjTi6oo5JW6ddwSn+9Uj2TRYUTPdXlC/gSk0LnU9TISSCTZDvfDJAyjICIzm
/ZQRpC2hv9LcKIGyHxJp0m6vJTb2jFAK2grLjrIaob+Rhpc49pSdhm3oa6SnC6m+b4cnh/5u5rLl
HzCQsm0TYbIs0LxYLmZAGpzvDuGjroc6kepT3g/xzWnd6hIT3lpjPQYjn5pgJH1Pr2Fk00ypAdJ9
52+8JmvqQPWHGXlhky96678Uk/LffIXIUIFc0hGLGFQvaVBLuT7G/u+pltAsN9I85SeREuV6knjq
QdMfFdCRpJXVsmaRON41/TxaUs6m9owyRdedJ47+DtBHosEc67RWpFJXloCNsen88xd8giOZhmyg
swG+NlEHB54I3BpM942nHBUaXegKc03nXW/+XVN0ajNrNVQ1dg+YOWu0PaDmT4edc6JheEGgNCfq
PzGkIZOal+Hpl9yg99woUCqYrmH5IMamc6JCcxW9MYF+IQIx4SAxMMeb9wgwJF4modaHRuDWbnGZ
kZ+2eQN98FV3lfLg/joBi1AuD95yKsIv6gx1RicHLYIWxigrjGtyUDyyg8ekMpZayokrhyIBSibf
fj8v8Zx+kN/8rigEfb0hjw16uftPrdDIar0Q2GA1lJIhgbcSfC4hwkaOyI4uVvgfftuvkf+v6uWb
yxhsaWhdCVaByj5nUdcCSf2v+XKWbrAQyEyvz8+ZFUCxlFexCSf44q2Ayqbhs3q3VLs/C+Af8+V9
6K2pL4L7FunygO+PJ8QZLhkWuhFb4M5hp3gME8bcxHfdkLEiqTEDuH0CN/ftkssfsMaCJUK+wBn8
h8nY9QjFCZTuZgnX/Qs9CIRaX0L6REPLlNoEuNwzR4RyUwplwjPC62PdZ7apRi3tMn/qNE66b8qK
z7BrchdCJUkA9NfgvJVgZl3GFiVd5e/fpUiFrpC7b7H98fO7sOqlIDRI66MpJhtNiD394vqxUst0
a5Mvo1sdkoqNjXvygYHfs6JAEYxx3h9Ar3skC/Cs8eqn9zJruUf3W/3qzZQPlqSPverLMen6lz5h
QSYDNLy4NO9HcQCRkTn6MH4WDQSXcjQr79qtwpXlH6M6vIp63ObtXkS2fMRfFU/N/6uLu0mO6S+G
Bk9RAj+it5qijTrzCLKCuutNpdUIKMxj4aHSJz/DeWrcaG9g3s98Q84o1F2rIY1jiUkKGasZtMlK
Co9Yc2ITWNedqLY3+7Jj8JOaksqR1dG4QT/22QWgrL7TjMUdpabLP1VIrxgZLlbmE5R4aTcfXXTF
X5dzBhZ6XnJ9Un3MYrGM3TmBl4BPbvoMegSqlp2rctQMIzTqiSeVNIr5osgujiU2Nk/E7YBJgaxY
U9xftWHXjlPFX+pWLv2l1NQSrfN61FmYwIq9jkr06e/Tf63/pbA5H9NV4k4NLwwrNd80JJ+rgemp
iwF/UbMhX4gxslKQiwfayvPjEtn6XFLuBibq7DOwOe8CsoJj2IGcj7dOg2LKSy/+/1XkmOtxQR8r
0Dv/277H8bcAjQ7PeeNRsayx26AKn4m5QyB8G2ToW56Jm3Zy/PGliufgUDbrQsx+2Qb4y2424bgu
BDGKos2DQDmqwcG4qEAENncFiiVxdXeTd8nx55Z+6CwF3ECLtc3pIiOcOikNUw1DzrZ05Oelqm1Z
TJm/vPpQabdnpHF3H0/dAxZfESso0EibQEMX7gLBDj383J6MA+4TOAZiJ7G83YZTyDqiD53u1XWX
9rqBLAO6aasd+p9eGnEGVSVkBMeYIqEz7ogBmS/+LKx+BOC8R6wm9s4A+aqbMlnTBsER2HLkbYqu
Gd7GPIT6oRgGv94e0F7e9raxt7k4H3Ro10ec9AsjHadQBDjc9KI0UcRMUriWfRWB0FimH6UMAPAf
75AE5xOIyQNMhUvEXrVqKE1Fo7hdCtGBZYJEsPKdNQoBZlqBWbZC8Qhwcaii2lVrQKVJi7+2N17d
2dhcav6hzq0Aj4dP0V4D+j5I1OkbNan1xtWsKTgVDY8J0R76BqEuLAmqvKzs6Nd3UJ/MPDL/KDVA
fOJLHPdP9JvMqCpPzhDo2OZX9Vl3YuS2vfccwDA1iBv5H+kDfa6+VjiVzhV1xGaP+hOB+IA6OrlK
E8uTYw8njGbxGpOxxP0hLOib2gLePRoUzkLGRZdZeTD1EoYq1NGZoASGn2i53AEwXs5hSooLnao1
ZuJGznzeK9MUIvb0b7z83JuXdQp3N8VAh7TA7GwO61skklTNopOcvLLyqVbbW92KHCFdvRoQYbdc
y5/8i/TWimO38hgR/OCOP7ad2sMCB7B/H0pDyXdcPN0bWKem7UsJ8hNFkDYuMqHNgsrdgKjGWUVE
/9NyQLZFPCpra6zzb1+lFvglOAA0g2foV1gv2w8a8tHRCO8MHBZHiPXCyrkF8vguXLm9pQRYF01i
m7J5rgor+B+rPguGFEef4UUyqF2pl+Ff+pKw0JqGqhxUmHk4WBu05ukgF/iZRXcuGKBbEz4x0K/P
a0Khq4Gr0uld6TU2OgV6Bx9YvRZi3dw7rhsz0mibFZjgRc/5/9waElYUeUbbetvX4GevYGCjtCFq
zhkI6bDrp56zaoSd0ZrEBZ/Ed+y1O+0DeJn0hs3GU4T7eEWeO9Z7i4XqAKvSVhEQCFrSooA421mr
4qKyEdDvATQkHXzRXLyKuGZoXThEgz/n2Xe5HVGPjFxv6Lqe1AHIXZPqMocURwiDNagi6M7HtFE8
sa/KVJ1LrU3DY/mJhbw8cfaF1x271C6pTSCsRSWl7JTia8jVoh8G87VBU+VyUE0FX9CSsSGW4Ioj
iRuylqqOXnFR6ejHTCg/KF+Kl1oUN2EkOIgq3vCaVtuvlzNzm8DMe/9rot2hf4ou5BMqYfsINJDR
94j7cR99nEV1MfBfPB3UGFmMKb5mxMo8Pctvcd4XFbTPjiUFWIdgkjcfr1EMX1+V8bLzEdQJGFJL
4qyXAUn6cLqI7QEoYhdszHcMTGskmWvX7wMqUdz5lyrLNnitq6N38EDATK4XutakAedK3GE+bSNg
Q7BjuAPD+BB+c/AHllIgyAtBjRXkK8u2j+ImLmK9uWEki2+EJjvC/IIOxvVtXGLGov12DpbL78Gl
mfKGb7IuwgqNgRJ8UZgvQ11FoKPLt3BzcPAaKujv38+yogQ9gTVMYgAqbvPc9aUm0Ri9v1TYPng3
FFAj/5OhRU23Yt4Pk0d6Jx+lV4VvooPd15wsdUwWm2QFK1CuvMhIfIkkY80WkoD+v3/va+urHMVf
u683V7iO2Wzg4EAtavwuwlLfjDSz2zlsIEuu7KxNcVsCxVjeLYzw605GvP/ngwzl947h93v6FFRU
Y9mEcm6jLUfoXrO/KszllaoExY3wTJznt2Mg9X5ldZ6cCRfc9rX5N0Oeh9HE2mMBurKvCIuK65eu
DQQl/LOYzFSHgFOQrTmAiphnLaw/yXYxz3z8h4Sfhyhu90PomSqKeimGs5ZB3jUH4++aOca7iHK5
Dv5lqS0O/vqBYmnqA/dkCliOYJ0/G6rG259rO4xV9vp/zPhw0ohr6AgTordsnyUjUkepUYXur78t
Gd3NiLCtzYlqp0Rs8UBdtBw2fQnxl2lZFnYA5bev6of4FDZFxLa7whLSLAIqAPhTZYVkq7PiSNHv
BGebYbsUiD8Y+KNJU2KJDKOwZrqmv4U9GoCDlmg7ufQOCSAcgIDlIygbzIxvUpnRMByP7X/vfLR8
/Qj6Rxxo5qaEmnUMaQob5l4ZKwDWIa7V5Dku72JeSC0UBwYpRlK57id0f1AsiWD8Y1WlQ7V4EzBp
cX13wlMsD8inecE6hofAs8258ieS41+YeLL5PuJ0dQERiaDzB1G/heTwwP7bq5mf2gOT5mkIxRo5
22dXrnt+oOxlmhH8F7I3nOPwhujzB6ur2fMCKK0VtKk4BxZ4gwfs0E1w60On4JT2tD0MB276hvqE
akWgBs5siKaPlDbZ6cYwyYOVWmL0D6tmYKCdrj0+YmvjXF5edKlFL7c7TtF/jNBHvZtz1s2wF0MO
Qdd5ijct14dd028RmDj3/Ka57W0PluRTaKxIAtJwohPK4sKjLuX2t5rn79eAOsXdBlbqHIjWAA5N
4FGbDgLzkvP/VGWuEX4zWr6Pu9WW/ndNl14xtp5L45M5UxAVVIwjt+Mrdxl29I7DWL1gf6ApndGF
LCyBAYQxQd4hH9j+mwiUs75TnkuQE3CqAwRWpJmx30f2WLyNNIDwrGYYrwaOzFjoyCe0HZv5/7ah
hjQc12fM/heRbYTkyEC9MoOK3PZYjnl3a8wZ+Yid1MOClvpsFr6LL+mx29stySfLC0CJHre+4zee
e7BVqpszWvp00/9jJ/UeCLy0tPRlP+9O/E/CUlySuY4GpQ1jm7nTl6JA8JOObFfsUO05BhXqqJng
wHYnn+egyNdLF3h0oMdFBBgfKx3if5+TyPmRpAQwyypTFOXtS73/WXhnS/IogHLkJrn7r7xO7Zzv
avh3vd3uvvl8Uxq7BSCp60ZfOROKQAoM8ldz8RQW1GhhsM7UOsze6zsClk2BwHvO49w5ShHL+MHh
mSP3VSGo/eGOiF9wle+R51pzJtaiKVuEQN9Up1idToegd9YOtDSIMwjoQYPQ9B79fqKAkAL251Rx
dO98L1RAJmZ+Ax8KqxExUx+XWs3Yp/bh9V/EMoC84F92FVo99n+vFPFyVO2yrIuhHE1hlob59AEE
dD2jVzCfyoABSUnLd8MASINZyMo/VLttfICsVRGYL+ewB0zFdwlGdVH3Bw/JH3xkzjvg3X6EYf5m
H3wQMpzOshzwdfvfBtvtZneYwoE9yxSD1NEk3HSUhqfQfxraR4gBhWvjGSU4hGbHqtQcVd7I670k
SjqiwMFfZoK4vtgPUCWjzQQFFQ8M7w6DU1JP/XmxwQDQ/VcHhHEAkHEGsl+RG2oeZDIYv4x+zKwP
HAf1tS2/lkOl7dWTrN+HjvJlMsdj+VMkdGbLB4FUt7t0XaPOErLrzDJhmanrPCgIXmYeCXlQQ+RB
CvngPhypfQaP9w2N6PKIETmlCfPcxZdb7b/BEuvtOIeKV4APz331Srd8w68qDyNOfRgjjUcq5mK+
rnOJozurbHEMJoI8lLLN+PqVDnV34E/85FobGDuYDPums1EwlezyM7aSenfANPmz/Px9uQSQVI+d
/G3DGjnULNK/hvHJs12Gd81mqOhMOnavnEwOW1fJGhlIcrJY9gN4p1gs5wLPJ8jwH5aRHEAwZtCb
Mmd8Pp7KIFUdfIIyVC62NMPtQ/BMPjNO2XgJY53HXxvw8JNRR88eTC9aGo5YuTdsyX7emLfUS/TP
NPhjznF9mg6nvYOYu5qawqY4NE8Smr/f6ouzrOkVg2yKaYSmULJnO9BuJtrf1BWE+EIEQVLFybRh
+l7cilfHa22X5N0HBq2o5HQzTLSzFI/hX5Y+FYb3qoLB4k3nQJdV/bGMyiBoTbDRv3K/Q1dupHJs
5uOZUetINkDvpHZQ7hjOf5BeOnGw8ekfzeD5w8P8sKp34de0xw1fvI1LvUfz/p7giWCcOwIVpiu3
bMlBPBAMK4U0Qa2S4QUqafO2Fi3f7acihMabA0njMp7IAjchfhL1nQkbW1r+hDyIC9CxkQglKDur
4D1bDk2G7BuDyqK7c38Qkg1cNrtmj+BXdCGG9Q0L5xZ7MxOISPV34QCPSIfJjiEo178uTya8QPw4
OwPTAdyPAEZRQkbH3nwK4eFcKvVrzMv8/nK/IJ4XEDXzf2DYWD9kkAUBi2s6hpgk7V7pvilRFiNr
Z8GyN+fho63mEtfanA7zVSWzvVBPOY/Q/9MSxkXJF8r/Aq4GDVEf6jLATSb530lmNubTa/hHlJsh
NdvUC5Z45XHXqwd5wckRqdKPUf8N39m4TRFm/PfK3vgdUWyQoYqqaLQ5+1XAZqkzjO0iCoiHQU1V
6OaUUn70J6qV2FfPkLAyuMgAerejS9w/EUnHMAidsbKEZ9bKyGQnqikEhlRKuMrfsKXUNujZz8PC
2V0+rOxTeM1euu2Q0xmipQjJ454przuYTdhim0KCKsQITw//EuPgx5Dl7q0i6BqQ7Amnhy20jdUy
FxP34NpIUf04L+qEy4h50rM4Q0Zg+wacdubYegZLB4/fHXhKKLkKth7W21h7lqk9s8sMuUi/PF+a
cZneO8T/MHNGyaXRbXn6shlYrLyLCkLU6Ju8RuWtGk9KOB4xICuN9QYgQRtdNC20UPXEwr45QMXc
W4nQYCYL3s5GgE1UcQ0RwWsBOTz5gDjpbl65CsVB2RJI/b+6fifps8KpYfoexq7yLxcbRqswfY3S
yxTydB7zNsS0Yt30I0CL6Pv/fvJn5L1eNdahUXnIFFe6RCwGnYmskGbBpVyxVhmS+qid8xrfC6UP
N1BLKD2Onf6zmnUhCHq1z5fjiESvKdOLOucqVmRr3rpq2+0RufuXkuwl7K2+lpEEeyUQgx3u86qq
fPKyKN0qFO2meEBvh/fxCfddjz3QVngc1ohHdFxriQQftFOURyt53Ad7luyoHjQmF2YW1+t6pskq
jxSFSG+CmtB/vaZzVW1ubx9Pu4LY/mv+JLklwYDhRQZW+95sZ7fa0h+W4nzyShL3hK24fSbP310x
zLtxPjqmWWP2/sKR7FjOulbw9hqffPGBB1xE9IDCvsymnxg2bQl0TD7/ZdNaJjylKClZAtLj28Ct
JNk94vBVxwqgJNsV+ntYTI72r6UaprXWe6XSgVv8bzxRamRPIshhMOgWDO9CXJUN4aEIUws5Hb2V
1XKQeIfGVg/JqLdmKPRCrICCaohLSylv1dNvhWMEBR+8y+nfPu55YuDdngmiLphrqGlrhw+U8oYr
rU0iztyB1mfQTnfwvW05MNkgKq1NxBDh4IBS+G52l8MPkdn6OvxxsiDZV0COty6g6LkwXxdJV1xV
Rbd/Vws6wALWBZI9yHUx2HcOdxSj6RawEkW6153UFWXzuEzDz1KGETXFRqOprPdIjAGTmSkM1ynU
1DJdnVydrvz731yX+s2VHlBA7r4DL8VbOOThT0dF/C6A0vzblmBfXqJ3qMeuZL6bYstbqtyHe0jh
ZgwiQrq1n2NlOv/VEO8fkZZ3bP2LRdweGtHQJaxXPa0X0H1X3zit7n1dgByp8q4zxJz7qC1yIijd
CzAPr03x2ubmi8PrkAhitCPeO9iFuuDXD63Mzx1S+O3L9DEjN0OgDz25VwLsM7SKyH1thyQxgCTE
6rixV4nyqsDojDBrwz0t8FnsBA5QkuS7R5Ro97tn/C/k7vzJXopu+eM04rRmDGO3gTJvWu7XBkgw
OIyVZrRTEPd7csulSjO3Uc9I9BcbKwjOpEgiiDwn/vUOJE2/XeMWy28Cmu9TCU8s9yXd3ohqVYOz
/LLpYRJDoed34z5EAZQnq5yr9wkv5lW/OPFGij3jzJ1eX6gebdzItUOaSBvUl66IKrXCacQUqj6v
AdSVXIoZuJEgQMrOHEVaEEUK8VPTJfSv1BEkMBoCF4EtIjgoeVrs7EAnhnimlbrWUA6vwI+CtcD2
9mn0mR4i0xNNBYV1EmGmAaU270jF1dUlNMqV0jjQP2xnVlViNZUv8NzgeGPwAjmuEjAqHgZZolii
qRtLcu1Iw1xedy1yqYKgXMvAkmijUUoN3kPtpwwnnpnRD5SwX6sSOcumoYVNoA1tlIFMCsTJluPk
nUwnUccmvC36I+hhTliFkUF0lb9f+ENzN8N4IjHxOo0e27OsbC0b27aAhcXD9dBBeRc5hdF5UC0j
NRamISzkvVUNrH8cpQwEeFqcRqHnFm7u5woFQvEh9nBjuVrvxs8wazTZ1SRNq80XYAQ1kTX56wXc
D6Yd99Yzbqhe1g720n7iXQncd3hq6Ffl+gsDm6YXofExfqDCpeEbzxyuZ/uoKwk0Zo0pB4hf51MU
TTQK1mB6oTVkHlvoEzYfWHt7Jctkw72IXi3SFvlOVELB45HySOmi6G4YGREcgayQPZYvr2VERPRv
VksXixJIHNiSb7NgHf33Ur/VboZR+hfHoF54b7Y+Qth4QJDKmXnUI9B7+pAeZRpVLviY1Al/tURW
ce64wzRasL/8FA+N+nzGsmhQ3X17gnCIDg2v6+N3VvZMvKcNQ+Bl3d9oPKKnTRCkFmjt4ht1ph6Z
MeVs5VTLo9ZGIg/7Xc1O1OqpW350EB8CZyWjxgujmrhfc431HoqnrID8WXoJ3++b+Lh2vmS1MBG7
204gcR7oSvXAtfGxvwKQupm+6ZJrHf2p3KTHYrKJUvWGlZnpjOeqvkKbRdKq4Ldbk5qjMLfRf20p
X7azrifxPIMl5pYD6wWQDzxvad4ZbJHfuyvLcb4+qfiywUXU2hnUvUeFwIogw6uWHNUQQ0J7QJSQ
8P3obmmVJJGI4PPh3RkxuQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jqxZHtK4DF7FN7MnfoXwOPg9JHLh/xYyJVOcuANxf+9aDyU8tiAbMKMcksWZAVyMCFpdey/nqjYh
/OPH2/fu1w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UnYTLPVVIcWXQW1hyG6ahQ9XFDPUnW9paO39lozGP0YcMX2Akp9RmjSXxuuMoNtsYVEji+RX7LT9
fyJE5drW3mhND1U//SSeQPkA1iFNx/SNNNsaaYmEDR6VmNMnSj9t92JKXW1hyiEDPBNA/QlewL8b
bH0qgcHPQyfMmur17XI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Xwupj/KUD7H+XEyDC8LyeIlyRqBAReFJWy/CtZ3tay8VXbADL67XAbdVX9f8lgWei9aJTVA6WPjB
QdoY1hMd0pJlPyi91Jx2aYKq1i1ql8EHPkCPMNEk3lxt1jEWF0E6okotqWgbXT2guJeZQYa7K/FU
KOLWfkMqCt4xgBsgWWp8iEDEbKhbjcxIJQZVHkXNXLnNzn3L6XdYflHQoyw+Y00DxjzBznSNlUNU
RJF64E/g8M6k9agDzwf8qw1Df6mRpWMlVbVfvuR+N/7L2UYD5fr1jvoMaXYJwvC8Z5smi1KkFFj7
0/aZ2e8Ru+i5P71MYkSPPF1YmFm0gtQR9RrOcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lx9rlWxQN/kYEKka9UUdwsMbC2WjMyihMvnlGYopOjXfWByEeTbWfmCjFd7eVwgdVEeb61pxTBon
c3RsGtVgfclQ85Z1/A3qtMAH8UiXrkxFQd+SMjhFeCnfMUG7XFVvU/32OFX0kryJwzNykkSWWKSr
mfdgzRylz8ar3Q4OwbM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
olHkIijGKXhyAkPsQhczvzeTBQSoEYvYO3tgbaqFjnpXLmKMF+Q4pm7TtOgamWjUMmH8gm+tQv7L
zupyfd3704yvTBMeUc2cZIQWBLcCui4M1DTfGlE2CTN87Pw8402EGEPuY6iwmRhphTUZjawBSl6d
hZW1EomSdBx1q4GR9xNlk5Dho66UL1RywwPzxyyu7nr/2NwcEuL6t00UrX+TujdJXK1MRUWqooYh
+ly4V5Sq+5i3qoOPMd/NmGUyDTnWViZBo4XhLxmNXg348RPgZ/U5/RYEspxfdTi3YKcC7PyQfqxM
Y/gHvkdYBcQ+nlqezDIuhO+9G8tzuAnG4VQn/w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15520)
`protect data_block
7j0ddWUK6vS/0f5k/gL8CW6k8ZyX/3ChOfrvOaEvCo3+h+oVu7d4pSx4O2pw3z9cYS4+YtuIqYoR
JgpruPJyJww0YVdcjEMYqRPqXPyEzVT2nT3D2zKqFrYEwg5PgwluCjZBEeFI7U1c5FN0VZCQ9MH0
3dSOMO43FIlcjddFYs9yDCA1sI79KYr0t4RDUdaeqBumbkzbsIjFje+LpuXS62La4rpX8++ycrJn
car5qyIBLeMNX8zm5aa6pqmFT9AQ1sKLYU35hcmqe7SwcWKZvn5H2bENgUDVBU1rQPR4OmusuRDu
Yc07+4uuERdyBTZ12wy5vr70tdfI+EgwTrz9E6DYa7g0U/nFHuA8m8oRoZe8FVkQCKOnLLr0Jb73
QjaQ256EPw5qyZlSixUqDt3/eSYJbyUgPtcijvLxW6GvNFmP1YXj878WX5mRwUfq3BJcd0P44maS
fQouV58/bN9OqFWmsQCxq8QAkfLOPr1W2Ls3L3sJ4skrKdPjFHHZ4goaRSZ616rvSB8IgjlOJPxX
geo7W8SJbf+6SXxCP8spCZYSxwFMbgATi+WJYpGUHY1J56lpXg8z43CNstZrzWu0/mTCTApf3VAv
28swUAHQw8MK4MWAQCy7Y7i6VachlTGsBfdI+8xnAHzVhdMEPYm6DpKAGsKKz6TqpRw1pfAxILX/
JywMicqzVW45DPZfWcYI5LOwbv6IqYpwv3A+b4oD4nTYTwGiVhEsyBAwsRJxJBxDD07wU/aGmNA6
0CmkORg29dMD8daU1rgHPgqQV4H455+ABoRQIp4Sugrxi7HWJhXA35Z6nXmWfNLjZM5IL9UKMe4N
+Nj1tTm+F2BwIv2WLX17bQKCgjz6ZkmtsxdccAlywHUSPlUJ2IUMyiq0je+/EstBfI33pk7w5VdB
rv1gsxHoJXjsA+bHgCae+kh5pGuvBFmQRYIMNZmuePJNpFyFqgPz55IpAfC9hQiDs4FXW2F4+Vq/
KHWpEGejjgnYER1+SDuy3gN3nEK9n4BR1s4N8QWZPzkcRodXlRKWwIeG60BNVWB8JO3UFVwtYbk0
uypciLcRJMGrdO5e65l6IHW56OyHwVUXTbJRY7vFBJezRIS8HmxYhSfkDwuH6xmafJXB0CMQ61Ux
Ro53b0lkp00TuaQq+e90Bs6yU6jB4g2PyKxTRwOWPLEwTguNT1OouXp9fuKZn19pZc0jTr85JhgK
ELm3wjerSkKEPBVLfB72iA3JSuLNpOw+fPmg/1zprdbvL/uR/9ZKbnQMQ/Hmq2hdpXfS6TeNmzJt
+CtroP6yKwdV+j8YvYWc5X2MGlPd749d3KNhngrjbhloIxypNicSWasxptfDoHp8zw5nOjw8XS2Q
zzVjM/dWcsZTDBiFqWy1TyTVW62FhnzkZRbiOYCKabWxgPCBbcEzcXjMCV4P0NJBnhohBw+PmQVW
WF6+YNh4CCv0cGXAbuGJ320gAD60+AxkbsXEFZsaNfuU3md4osa8t3bDfFslc6on5h/3uAshhgSB
5Gaa52sWasB2T33oiAasnVXlqNNBS97qosSTisJv1gJpR1gaiY3gYWOp02rDDqnQIlSvW2oCVWxC
OWfW4pAd/yDnGKiYunSpawpEhHylvHPjdgXxIvzslnkbC2ZYDodZVP68PeWUk4QqbwrcPWldxCD7
xbeefnY4ELrEZCu4CAfTsDgOAs9WiX/SjcSOd8t9FNk0a6oVgN6SvprWs/0qIsBgR3otHoNGDUFw
HiuTLIeAzrFfYZ61PW+MZbNAgdg5ZIqK5PZskL36nQpmQf4O7ScnsDA16aSmpTbSKejN9A7naUVE
1dG266Xznt57ObuIv0xADHJdSCEjhK2pDH7VJGxJr2bs1RNbFuGoP3tci+dfCcnmK7pdxugt9j4J
BwHkdgdUhPVtu0DKpFtf1+/LX+HTKKketTmFfiDrtN9cjsg5n6JeHC255NTClHsBoeOouwQZzkJS
7msX/mJ9EISHnJx0rtTOXrJ1y+p4SRr8RehS9CLJTW1WVrmph/ExH3skBMtzlxCDOqSIuTiY+7YD
B8p+vhUQ5j4+9uWRIleDcDG2HqMhNQiIB95bPNx1yISTEzzdHLbo+XWpHJzu0z4qF7POsQsnD1S9
iSbfRkFUXdFCEXEfiukeri4gFoRXqUfIBDKNn4ba7CKAhCNIO8bPcJSV1tbNMYgjLLHOIphryL4n
rvNTDYCvdu7OrZo+Ia5xdwWyrXHG4/b/dTEyMwFI969QUlT43kn32A7SOfXUYq4FIqPqcrWznQsP
C8z5YTa+ALM73wrEPmBUBknvap5TeSOHLlNpuJ+GfO642D7dKyta7Ghv7AxTXYzLFnJLhPAScUGf
q3b0tloPe85HSrdQ1ANgLrr0SE0zpTm7hXIrbrsEcvr4vYVouEGcGB6rBpdmM/QNJDgIXdcWI/DB
Gt1G/pTw2YlQxuF2tD9JjanKoNLfkaYjsoYoz8WkE8iwZU1vhSPMPDUWTCb6R5zIr9EGKBp/OTHp
q+X1Sg08gfsLH78m1aZ5tyvCQyL5kKONDbTPkrRvU168wFH55x0Uz83pTjjVpbDv6DVcVn2Ly0GT
K7Hv73gefhsHIX2o5qe8grZ1o4LabTrc9tqUgj3hosexijyojbvJyMwQTUO4Gj3BFmfkSxbbeMIB
x2jYdu4PSb4/QtpvgION9vXY01Abf/jfwql31Vwqae38dTpuJ/nluO3yAxthrf9F5rXVuuTglsGh
vLBVDda96xaZ8I4ui2UQN/s7RYIM4VCfTUrx5JYBfDrXjQ7yw46lLNrgfVkgBLQvj40nhHkTzAz/
Z98Nel0ICntxlUbjQrD+ZwT/y+jf3DuL8XyQ3D3lY6MAb4eA34OlTnDy+AxxlgERCjlA1PxjlLzB
b0MleDaSvHF16RYfiWk/vHKtplQ6UCqbuGi76rJM4vIte4myppQfZ7ckALBIFp1ek3dMpPz7wXqi
zXtGpamGuut1Ay1E3p+W2OSwvMX6t+r7lDetJiusQRPFwPYq+NmFXn4IMwWXGErcth0EyOIUXyOC
6c4ZCLGTM87XR5QhFh+6E36hLFvdSU+wNTuROmSmu1fEEyRFcSo3WLxWY4RF8qkzsv13Jc6ZaXcL
6froXO+miJVagvg1tvNwhSlEXMW8yt76lbVcmxQ2EREtjV+oTNUQiyP4SPAm5lOLsWh7gbFLfRfl
QgvzwBsjkjxJPGGqfzH561jfNYdjpyzCDPjpnSI6mbkD8Dp46UPQbZAGils1zUpHUKYYX5aXnyIY
abCBpei1NQiC0E+smKdRgSpJUZZjoJXV6iqvvCbnZ+ZZ1LqZvJasTNUashy19ERYNV2hhzrqOO8E
pxbHbwJMcF58UoM94mtw+pWa42HuiiGk8hQgk2DYTV2xrYyJNE1ZdvgOTxhlj19sCtc1fxkOZkNf
GpXUIGtvM62C+bbT2LPRw5WJE68di79OPvRnfRr2ZBG0skcMdXNKWlbOIv0s+SZ2vMxKLZlmhw5B
Fss0HX3NsjRCUwR0Cd0PSMKTXjWeWQWYbXnhaLAhw3FHa3jE11a0tIk7an/eJW01CUR3Kx/svYEU
ppiTpqW7x3Td4LIi2i/HO1TwBTeM4VXzg8KKkyG/T9zfgfnFLKr+IOSuDrugJcLsf3C4zRX+/MpP
mDlVmaRR8rFhdBTnM10xKtPWgtTicANhF9bL4ASr0VGIM7zng0MPfgiudCvBJn8s1y0+sccs0fRG
FYa1Rvow3aYpWnbcR+9uDGRqERbak7dVziOffPRRB5b+NV0Qb1cyDqpz8Umly8svRhYSeetVrGkb
mYb4ykuo37kWx3du0UhLstgg6elvB5rnYMFKAApE9Cfrzzvascqa8OTAm2wyLljZgART/zvPVqHh
advmVESloVvjLxhC/9jsYFJ475xI3PN94YUS1UB90zL+sRyAvhKIyoKiTjJgNdULoxqYmL/MVsrM
hymiTHxJ8S2ZO9V7FstIm//AOffBnGTXdtRTcy6g/hthAKw4D4/Jg9zR0V9egjdP7jkrthsMdmso
1eu1gV/kuTxdlDgUU4xavRs1V5UyPLabWjli1Y0n6TuBPT1ygUyksZ5ffYaXBrHYkpVfnjqQonzA
S8reO+JJI08DdJvgy1qzpJbmAJz0q6nlnha+C4WcdTx21k9L2pN6iBABOAQYsNoAQYYMvxPqihfx
tArb//2YQKmOZrw7UsGJT8xDXe6IvoRetHaffxT1QT1uh/DPzYjjDhJD4ILo0OicK9AGgZD++SRQ
wy9jssTBveFvEHprK38BT/Tsj4oKMjDx1mLFoP5r3/O4KUswmdQ8URdyJhdZI0snHhu/eEV6V+Bq
qvyHRgDtbinHzFuDY8pYAdZz7+5QFELygNaDBtE2zumCBqDu+UCW2w2jTMxMPJ1RTgfvfaTd1uT8
A9RpNtWl//VpKo/ytzQiBv2924Wj94tAYUMNFIi7xUV08ybys7fqQM3miHs3BWOr2Ca0aWrE2EwE
d5DNQkRr5W7EQlqwvbot73ef2ROwVLI8OU7xwWrpvSRFGXzVB0FRuIrT0SwDSl6hEJV3dFyfginS
slOtgphzOv7p/3DX2gtLY8odE4wHdzcQJp+hXk1P1gDOyU5tW5vY4p3igf2UPAoXmgEsZ965DMCq
zMEs+od/Zuop9g4osBnML0bibSP7A+qSVErhLupfGiieRrDk3XTNDIIHLA5wLEJUWDtbELRm4Nmj
swautmQKa/D2EIujMhj6HS97igUFNyQ6vGRdKrKa09tGD9HfcAjxjzoZlhG7RL7cM5yGhWuYCNl8
N/mt73NiXBuPGmLgZ/47TVdqCiEUNyZzhihCywwAM8wX1Fz9gdTUL+PE9hentYKjDb5f3jljwVqf
Y+T1evltO87D7PMh0ZlXay9Gnk6fY9C2q364my/9J5GC0VBSRVjl1ji0c3Xw3rgKMmg0RPb5rGYF
DLNu7htmJXhxywfuN5cFhUzU9TomRxCjY6JO7iSPbcIl3re2IL+GeFnGvPcD+CCQAJEAahmO8WQD
Pti8l+dg7C8ZU31aZtMCfoDjKpwep8mWMD5Yrnm0kbJ+JIx3eSTtlS622pv1NmvO3Pl/KN21SiQq
6NaR4FJudcjEYw0u6dy0HRRMRakwt+S7bgsqm8rHtNm4Nr3BCNNU4h2Wiyf83nndiqpt5RosLYef
H7TYmRswMDfBLR7RNFSrgSm0k9jYFCGF9Vwyj2UVGvmMd+vCFnhaUHZrcnZjJa3RLG/u6v+y2ptL
QZRNvbryyv/d9eRZqq1Ch1xyT2VlEKkD/gQ3MxzvZQTUIR+wXiLVWEMAUTAa4iF0qZcvBB4WVfay
tlSawtxvGEIohKofn8yTevFu9Vg3xjd3k6FW9Mwt5Yvm4uFgSNuw/TR1P75bE4ZXv65ZfcCg2Hmk
TN5Y7KtaAALF8FLffw6vEUnddjM8LKVClhZZC+IlJ+mAEagGrXSVgrTEnykDuYIb1yDOLt0TfQSv
R1FoBkASZv9VGIKrqdXeJDjYi9kOQN8L3Fhxr4up3qF7INDUHBJ7ymVNt6aU4l5VxixBn16l8dkq
7619SKOyS4MOMyGwFYoNwf4grnNur8p3vdb5spXWeAZHpxfICjLJIAV8QkTNSeWWqC+03gcgwJDm
MgwpM5pvtWuCiOK/6rlVLV5OgdEyqubn9BoO3xGFEVG8Tv/igmR3FGlliBtwjm5EVQkNYvjY3gDK
xQM3kvV0OPy3XNQeRtMAzpzHb+PGy5cTIdIIjvmqjwih6Lq6msPpv0ldhFqYv7Zg/x/7257PgovU
rsQUAMee4yrZOPXjTqCffFZCotTguu/N67f3k6naiqAzmHIoKJ/V/7f1HJ9iAp36NAWNULcdb0dX
WUaWILMsWlqNJt/+ZUOmxQmseyYtpbFI4nde1lbNIFA3nMvNPBDbZ/MMTuLW1m8TRxyoPJu5Xy21
HpeS6LkstLP/kaX5Fu4/N4ysnSYHI4khYPKtpurnnX9cfhva9KmH5WexoCroZfZ1jibGjRyXKzxB
57sdDhykSu1HnOC7Akj/5TWxi0QbifcDJjfX2UWULs5YZxnw87pvM7VARNbAkboZkM5zAwFLwSCA
ujotU5RI56K3UQxsm56gLg5q65yQI0+sj1OOSVIcj3RspOlzyeiF06/zLHPXKW378IGQxRUoDref
DsG1AZ/7mpVh1pA77PjBtx7OdPsbUZaJ8Bf5GNuhEQF5JXvv0YrWk96TzWJ02jGlksVIx0DKLtGq
iD/TzodMndjovGY9EERfgrErS0H+lcnrkmdNTSagtGvxDXxYdUHQtQ5tDMNdQQgr0jVFkja+KJUH
rwPGX0Kf8BlUnCVJUIGd2rK1oKUV1c25yGQAG0KAoyT+Y5jkkw6Jc0MenwDyOo9ypDA2MuBvCyal
dh92f1MbK+wQ5q0H6AnG+8ZLZYsxCCSF9EHmHimOjQIceJKUrmgpxE2pGbR+SbnAlQ/UG2V6BdQo
4Tw8PuDawMu563fdMXJDNJSevt4K2BJx4JhaVs4wcw/8U5j8f/h2H015oNG1uN+faDV19l83qg2q
srpYZHhL36M9trwh6/CqXiUkjqLbBmZRLCpzSuIj7nuWw3yuaupKua8ytjF1JXaF9d5Pn2iFpN21
MgCwP9cX3VKaSxuyvcweSIXt3/wmmpy3Bd8nSFq1tu3Zsme9FALhIEtBWrZSg+cFU2erULmQt55K
Q3+5EIPOUaR4TkbCgzdWv9GkFyQ7IDyTPMfNUQDhk9VTFwJwnH9eo9zWkk+1aPHFdzcydA0mWv3/
GMjV5RLflUmlaA4Bev8niI5u+vO9v9PpPHV26ZF2JlsEMxQFUFMlrt/zbPpO8v5y9OrP9p3krK0U
PF54VgQaW3OgTCFEdk+4L7W6RgATZNcc1Th/5mih2V23i48+iW0SIvkfzziKmRSG9BVbm4EUkp0Y
wfdK/PPSuPEGNPlJy6V5jYcgXP8G2fF3SAxsIuSSOYAPJDF/fE2w/ffU/yES9RcX8s7NNZlZO9kP
9eZcuc78j8JNvyRMgCHz8c4Q4a2+1RJD8z6Z/Q5SJQibwVqsGaSm4CgZHsemKpGuQWzsYFB5K/2j
Fi+kjzHoK/K5lNL+DxcXug9NA6E5QZOdnBR5NSV8g1kA25drirZLbFWP2xvlyxePXmXI/OGpVNsD
rahlb9a3ijBhgVAFvjVoqU4zz1Fx3YJ+5F4pFiJLfrWmaywVXtqN7ovQFeNscDHXfWf6YS/if1L4
1xpMhBA4aKqQnecOQOX4P3NiiAGxbqveZybKaAw5q0FKoK5XNPVI0omXBqzon/1SjAdxC4ESnK5p
jgkQ8Ps6Q5lpueFnGaElMwZDROtlzw2bzDS6R4XorF+/JNWu7CXyUu8g0HuGiu2nHQjfPKvuzU5p
ef4HbVEgju2UntS18AropaQser6w+6pQp57svp16zEKFYvDbS0VNtErea3R42vNt2z9F2K3Vfvh0
seJPlA3aJG1AsSZYG2IyJjuRxBrKZuvXX1c1T1fXf8htWQnpPo/13eXLCOuwkoJZlvWhOo8wqqkS
+x3eb8djH13o1t084MoLT5aflf8NxckeEtUKfG+Vkym/vJQJ55OYWNeZG3sOJbuel9odc8UchWSB
+xprv+HGKknTSqMdPZi3hEqc/hL99/zsfWpSkTrgzEFSkJgHGC0WBILMzobCrtSLdAc3Hr7125BX
QkYHzoOPO5Hh7RefYmjLn1FcWd+3wgqnUj0Zro6vPBwHmzzdP55f09c6v8oNvfxhOXgNAgqFJ7W/
I6ZrSJIzXDN+4oSE/wGvGluVXTlfBL4c2eJE5HWnjBybCBru+8CcGqG6xJik95kXxCnyea/xDyBl
fnFPbOyQ7mM9lA9tE5FtGl/MiLbQCZy2ravz28MfiFvLLfJTa8kdsZqSqjfZOxVR8xfl9ic1JRDc
uaKBTSCUx8OPrteXSrTlxeilwkpUi4WSzDrkGnYifROnRuUbv1cLa2YOsWPfsKLRpnlIAaPg4r3P
p7wMZRLNirGXSj0/mqak+VXJw1fyTiX1Gs1vvypMNj1bCEIw5k8MNeMqRZTkOCdqrBhV0DqbH/sG
LF0ZziCESV5l1ynV9dnmN1OTSwnlAhhMxoGJfhVijd1GwgErs+hwWBDjfu6ur1wDRQSePvzUfIBo
6d/jwnzhZb+JxvHncqIWO0HuBk9a2/tyqzB5iXaUUwf7KhLVuwA+76+fh+fx+lDltPswizb4bx6p
rJOmPzhIaM6QjkQ8/us78pVRvVbyo0Ed1+EJ0N7voZM2igzNAl6i9cCQql/1G3yTLByHd0z5im59
yDD9B+u8//s1obhFCNkDvR+xxwG+KYEpPi0kDflh9w7fWteMfMfl9A3EXcuz0czJJGlKkLGydeo6
ajk8IJKk3tk7n91fwohA4TNFUcUqfuwEcbrUI8Fvw9tZ8px/ZRb885BnH901/RxhvX2CZp96pvBS
8f57jtNnFC8xewiaUQFWhJJT/oJHI8SSCLC/WcFWlKjF9BIhU8qFOkemZHonl9+eYuf5AMURnUB3
8oIU4GBcg/Hq8e0wH5lYSASMreAbyKEOAuQQeSdvT46xsi1tHDMTowmd2SoFs3GtCJHFspRgB/dJ
SOewSFVILZzjT/VJUycdw6vlhNA2Rjcj9AFFIQ72dPoHp7CG++8T/8pN00VtKPyDeG4f3HargCuf
9fjAyeqVE1DlE070pS4WlmePulu9yFWh/cyridNSqJAoqdJco1khPVZsERv4+QIqDrsz56qS1HVq
Lg0BmoOnCpfyxHBGZcC+iDuofHwxFwv+iLKMR8fcsvwRVLp+q7MxzUB3VG55FxXwntaJFDlL6d04
Rm6/O1uKqHCcFn3q5AX3ANePmg7EUDDZNJd4aUNJKy2Cfra8mWlkyL6WTSQTny+4aHcbdZoNU0bK
krFW0VWK2LhyMgAQkj+fA//zbhhRZm181SsbGmcxXY3NMbnWdiOC4G1fkpLvaQk/o3E+JvpvCEse
5V5qtEWu4+7L/e5qQkur6pgTB8rbS0mCZdKvzKdETLFEQT35y61/0b/HOBJ2O1a/6FUSIgcI7+Ov
AQ1CaGBOxd+RHUdwDJe3IzSSROT/LWPQugvkcbBimMkzxYH5PDm17EqSHlw7AkIigsx39WH/KCBq
vBdP7U35lk55geZJka83PPnoMVv+FWhJcDe+mjVVeWFaXVcVyQ3u1qgqAgvmKcDoUV6C+rwIYqGN
iah1dESKPEaBwP2616ouFAfl1LXikqpFvFsIGQtw7/PMgXacdH5+jeWOj/Edj0WLaJcbhzu29GuO
cPAtFs6FRgsX6iETOKkPw9YchrPir3Ow1FriTDWDw5iq02Voc4eIllcqW0AVH94Ww7XO5NezK7KS
AUZ4YKluSpdLCZktWXTqR+/iwEmyyYg5RjIAAV9rWpmEeR1fGrlO7SDLNVlX/1waO51LYQSwHuFr
gBjLBpOQYDsqqvx3H/nD77KbNSGD4pxjM7ZeWgJj8MVP8wQPyG4D40t/YjhtyPfZNzjaTFtYWl3Z
JlNrv1+8x2axhDaRTZVEsmtg3inCWhQjHjuGnSv19q+NUkXsYVNxb1jYPObCNIGOeiQ/6ULqbQrH
V5DKlhV8zP/vDwTL3xnapjaZhCKxJ2Z/W3RPFRghMfbh83BMzi+NCWANTt2JUMi01bCgqR+qyhPk
vI+cAHJ5qZbSJBem+bCA+K20dLfL7jKf6V1UKnqmkFJyhErcsLJM8sUTcd2GWE0FpXGd0INeYAbm
ZtaSSTyn4Zvcw/EO/nO5bpczoSRKpa8fUq0RXJGiCsk20P4w7ZZWsT8Fy6BgBS9JO/3UdglK5Kum
/+1zxSAHo9JHVgoEr0KKYFcZOFK84+yuKJuGLC8kme2ClC2vrq7TJR8rtKlxS7Tx+KJsjZyN8tKJ
ox01moIHQeT0rWc+uf0MY5LK6EAsfY7InoymujYljBn1Lzr+8SxS9u5/KSjSI/iAwAIeQOB1a53B
qN4gPFDbQo/I1iRlDaarTcZWk/qEr2jn2Fg6ooM6V03moigUG+rehJDJQHSkLeAKkb6B8h2YWN86
UzTHtFcJQ8fpBpHTk12cnZH9frD/e1bhFo34YkSFGGlP7K28lDmBiaqVkA+llaUjJ1v3NUZCclQl
o99BWyrkb/fu7OEzRfB6kPZd5/oeWRmgUbGwY70bBE9Nx2mPoUSejI3K/m308EvR94f4bS15HXgQ
T/q8q2LgF2ksHFWvErqFydQILK54LgiDbERxTgLfvjsUZOsZQT3mKnsg5IrOCuq8e2BckoxfDqxH
dZvaCMTSVnxd9DNFlZKl+KAJOv3fk/Hn+lEJEgHKDQhLthheQ3TqRAPfU7Zd+mVSVqeHWlfEjNOG
aaFwa0SGwnYAge8SceZRczoQPq2c1fNSA3toAwJox8FfQyhX2sH5nXvjsuCHmvskUWx8DjXvSS4U
/dtKFpd1o4HgiMho13SEYO/453HtYAR3ci123GURiS9MZJQidnwxHTznMSqWc4z40vktsVYGGU+i
IQc2trNILvG2S/k4OKvGOk3dCFXSiLHCusQHWteSMn39d7b+idRW6ZaoLz8ZDPqg2mBddCJslLL3
K66L8X0eroZpcruew6/PaI5jii0WoqBufHUAAJe8FZdsyCaPCK23x+TqVfy9gFbOW6KCWX9g/tek
HahRnwhf04hLCWPFvCbdgEiIJwa453Nj0KMcC0Xw98jK17DrUpWMsG68VM6+6dZXJ0Q9uhLYHr/W
tcmO7LM0sZNY4hZ5ZHH9LXJnMjvLZHcSmpVoy+2lSXNvtlh9BEkYnj3u4rt/jBCErNltzFZYtOkY
BKGby4exajgcKE2uwOZEhQ1fGdJLamf5mqGsneomO/uPw5Gam7z2CIjYVuuOHyDxVrmi+muX0fyq
FxTdSbyN3T0XANNrRZXdataLGQr6uD4jogn066Ogo2DB2WWbUlt0lS2yik4/xjmBHg48a87nbDWJ
yb4+rDlFArx/Z4KO5OiMAsW003PdGHD4ubFfU5CXGPQY5NmnrwZAEcjNSHXwWJGBNkJCi0xx6RXu
nHqMDIc5FgrBII9V5amwCJLTopg3cS5dmgdhCeCfHlX0IEay8SOrHz+f7iM26golYkS77IxnzNnZ
M7nIB80ffn8jpK/Yr0E5jzS9Y+5LraY1QPCNktu3CahPWKR4HBvLfGktMS2vqSfm3IyxOTB5nPn7
+j17f9dicebwkZUEpydkI7zCi/qCFNf3L9Px7IITYc01IPNZbX1bOu6hozKwdvGVr4ujIRihke4k
CQ8sj1yCh7XvQy8N9LRigtBtUaTdNng4vT36oTRSTjh7hF5GkIjSJIiRVOrMJESN5y0V3qPZcggA
ssZTN0Cnv1EK+9hnEasdbi5uhPLN5C8p87YNu/vuntPpbb23jCGdMEPykgStAyZ+OXbNjS3yoANm
P4DxAFOo+52K8Qa372B7adKm0DX+M4vLyEFiMFMY1Z6eqgUoiml6iSjMNH0tv84a5m6SpyTPG0wA
SllNl3nqd0o3uR9ZyiR5VFtP0qiI5HXmEzoMmc++mCkziz2ofuTbeouL70et8UN0WmWW6DVSnJmo
X67fMQOK3aGsjdU61jeOSXmEJaX7cjYADWRw/HoL/uLuY/L3eUGzclOXcYiIyjyHVHAiyJkJVT+r
2QPv0AtaYvUzvgyyfJL+mgIxgdWLpmEpopmyemeV8JNeCnp9mSuP6p2NSXmtAOjmCcvOAJNgNx2b
lzrUzTQfVh9/mL+NnGZoWJYieUZggECE6rlKTsuZikMprCF3/R2zLHzd2jsQsn73anoyK2fTu/EX
SEpTqn1LrR0UM7pnowTYxpX+qStVqLiaHDAJt8Mv/tJYwRjy2/qaAfh37A+MyBCHTdYbXRM4mbXg
phh5iY8KpPzzL9guRyAsfi+pJdhINk2ugEZmiGowwDkFPir83WrK1ZaxND2JdJBYqboN6tFjTIJd
azirvG2BAGMDPTs2Y2gAJyOq5pus2O8w9aypcGCiCtVWbqUR1uiU6oyrZc2D6RsJuHP1iNTVii6K
SuBEnpxeXu0K64jpdWttbbo5XLQKapF+tLqeZ9RrpwfHrUCETROhh4r7VUcr5dOESQ22kJ3gq/iZ
R++Nt7yvUf5xmIvgebl6taxeojC9YJSkN4vlPfDPw2y51+vfFqcf9Bv5OEVLsIGcOZjWUxU5IRMp
816KZCjQiUc1VPIUIIHHgxUX6MbNmWPowm3tEPcftyfqsIbXzmkB7XABOdjgxUpMFfLVr8kr2tsI
rAcGWWph7qcHlNwfSR1w+jBNRmPzvArrWXGHQzkSZQp6s7f13HCELIIiHppcMnGCQ/nIa6bZhZSC
jpm0oyRUe8YtXYU3vjTi6oo5JW6ddwSn+9Uj2TRYUTPdXlC/gSk0LnU9TISSCTZDvfDJAyjICIzm
/ZQRpC2hv9LcKIGyHxJp0m6vJTb2jFAK2grLjrIaob+Rhpc49pSdhm3oa6SnC6m+b4cnh/5u5rLl
HzCQsm0TYbIs0LxYLmZAGpzvDuGjroc6kepT3g/xzWnd6hIT3lpjPQYjn5pgJH1Pr2Fk00ypAdJ9
52+8JmvqQPWHGXlhky96678Uk/LffIXIUIFc0hGLGFQvaVBLuT7G/u+pltAsN9I85SeREuV6knjq
QdMfFdCRpJXVsmaRON41/TxaUs6m9owyRdedJ47+DtBHosEc67RWpFJXloCNsen88xd8giOZhmyg
swG+NlEHB54I3BpM942nHBUaXegKc03nXW/+XVN0ajNrNVQ1dg+YOWu0PaDmT4edc6JheEGgNCfq
PzGkIZOal+Hpl9yg99woUCqYrmH5IMamc6JCcxW9MYF+IQIx4SAxMMeb9wgwJF4modaHRuDWbnGZ
kZ+2eQN98FV3lfLg/joBi1AuD95yKsIv6gx1RicHLYIWxigrjGtyUDyyg8ekMpZayokrhyIBSibf
fj8v8Zx+kN/8rigEfb0hjw16uftPrdDIar0Q2GA1lJIhgbcSfC4hwkaOyI4uVvgfftuvkf+v6uWb
yxhsaWhdCVaByj5nUdcCSf2v+XKWbrAQyEyvz8+ZFUCxlFexCSf44q2Ayqbhs3q3VLs/C+Af8+V9
6K2pL4L7FunygO+PJ8QZLhkWuhFb4M5hp3gME8bcxHfdkLEiqTEDuH0CN/ftkssfsMaCJUK+wBn8
h8nY9QjFCZTuZgnX/Qs9CIRaX0L6REPLlNoEuNwzR4RyUwplwjPC62PdZ7apRi3tMn/qNE66b8qK
z7BrchdCJUkA9NfgvJVgZl3GFiVd5e/fpUiFrpC7b7H98fO7sOqlIDRI66MpJhtNiD394vqxUst0
a5Mvo1sdkoqNjXvygYHfs6JAEYxx3h9Ar3skC/Cs8eqn9zJruUf3W/3qzZQPlqSPverLMen6lz5h
QSYDNLy4NO9HcQCRkTn6MH4WDQSXcjQr79qtwpXlH6M6vIp63ObtXkS2fMRfFU/N/6uLu0mO6S+G
Bk9RAj+it5qijTrzCLKCuutNpdUIKMxj4aHSJz/DeWrcaG9g3s98Q84o1F2rIY1jiUkKGasZtMlK
Co9Yc2ITWNedqLY3+7Jj8JOaksqR1dG4QT/22QWgrL7TjMUdpabLP1VIrxgZLlbmE5R4aTcfXXTF
X5dzBhZ6XnJ9Un3MYrGM3TmBl4BPbvoMegSqlp2rctQMIzTqiSeVNIr5osgujiU2Nk/E7YBJgaxY
U9xftWHXjlPFX+pWLv2l1NQSrfN61FmYwIq9jkr06e/Tf63/pbA5H9NV4k4NLwwrNd80JJ+rgemp
iwF/UbMhX4gxslKQiwfayvPjEtn6XFLuBibq7DOwOe8CsoJj2IGcj7dOg2LKSy/+/1XkmOtxQR8r
0Dv/277H8bcAjQ7PeeNRsayx26AKn4m5QyB8G2ToW56Jm3Zy/PGliufgUDbrQsx+2Qb4y2424bgu
BDGKos2DQDmqwcG4qEAENncFiiVxdXeTd8nx55Z+6CwF3ECLtc3pIiOcOikNUw1DzrZ05Oelqm1Z
TJm/vPpQabdnpHF3H0/dAxZfESso0EibQEMX7gLBDj383J6MA+4TOAZiJ7G83YZTyDqiD53u1XWX
9rqBLAO6aasd+p9eGnEGVSVkBMeYIqEz7ogBmS/+LKx+BOC8R6wm9s4A+aqbMlnTBsER2HLkbYqu
Gd7GPIT6oRgGv94e0F7e9raxt7k4H3Ro10ec9AsjHadQBDjc9KI0UcRMUriWfRWB0FimH6UMAPAf
75AE5xOIyQNMhUvEXrVqKE1Fo7hdCtGBZYJEsPKdNQoBZlqBWbZC8Qhwcaii2lVrQKVJi7+2N17d
2dhcav6hzq0Aj4dP0V4D+j5I1OkbNan1xtWsKTgVDY8J0R76BqEuLAmqvKzs6Nd3UJ/MPDL/KDVA
fOJLHPdP9JvMqCpPzhDo2OZX9Vl3YuS2vfccwDA1iBv5H+kDfa6+VjiVzhV1xGaP+hOB+IA6OrlK
E8uTYw8njGbxGpOxxP0hLOib2gLePRoUzkLGRZdZeTD1EoYq1NGZoASGn2i53AEwXs5hSooLnao1
ZuJGznzeK9MUIvb0b7z83JuXdQp3N8VAh7TA7GwO61skklTNopOcvLLyqVbbW92KHCFdvRoQYbdc
y5/8i/TWimO38hgR/OCOP7ad2sMCB7B/H0pDyXdcPN0bWKem7UsJ8hNFkDYuMqHNgsrdgKjGWUVE
/9NyQLZFPCpra6zzb1+lFvglOAA0g2foV1gv2w8a8tHRCO8MHBZHiPXCyrkF8vguXLm9pQRYF01i
m7J5rgor+B+rPguGFEef4UUyqF2pl+Ff+pKw0JqGqhxUmHk4WBu05ukgF/iZRXcuGKBbEz4x0K/P
a0Khq4Gr0uld6TU2OgV6Bx9YvRZi3dw7rhsz0mibFZjgRc/5/9waElYUeUbbetvX4GevYGCjtCFq
zhkI6bDrp56zaoSd0ZrEBZ/Ed+y1O+0DeJn0hs3GU4T7eEWeO9Z7i4XqAKvSVhEQCFrSooA421mr
4qKyEdDvATQkHXzRXLyKuGZoXThEgz/n2Xe5HVGPjFxv6Lqe1AHIXZPqMocURwiDNagi6M7HtFE8
sa/KVJ1LrU3DY/mJhbw8cfaF1x271C6pTSCsRSWl7JTia8jVoh8G87VBU+VyUE0FX9CSsSGW4Ioj
iRuylqqOXnFR6ejHTCg/KF+Kl1oUN2EkOIgq3vCaVtuvlzNzm8DMe/9rot2hf4ou5BMqYfsINJDR
94j7cR99nEV1MfBfPB3UGFmMKb5mxMo8Pctvcd4XFbTPjiUFWIdgkjcfr1EMX1+V8bLzEdQJGFJL
4qyXAUn6cLqI7QEoYhdszHcMTGskmWvX7wMqUdz5lyrLNnitq6N38EDATK4XutakAedK3GE+bSNg
Q7BjuAPD+BB+c/AHllIgyAtBjRXkK8u2j+ImLmK9uWEki2+EJjvC/IIOxvVtXGLGov12DpbL78Gl
mfKGb7IuwgqNgRJ8UZgvQ11FoKPLt3BzcPAaKujv38+yogQ9gTVMYgAqbvPc9aUm0Ri9v1TYPng3
FFAj/5OhRU23Yt4Pk0d6Jx+lV4VvooPd15wsdUwWm2QFK1CuvMhIfIkkY80WkoD+v3/va+urHMVf
u683V7iO2Wzg4EAtavwuwlLfjDSz2zlsIEuu7KxNcVsCxVjeLYzw605GvP/ngwzl947h93v6FFRU
Y9mEcm6jLUfoXrO/KszllaoExY3wTJznt2Mg9X5ldZ6cCRfc9rX5N0Oeh9HE2mMBurKvCIuK65eu
DQQl/LOYzFSHgFOQrTmAiphnLaw/yXYxz3z8h4Sfhyhu90PomSqKeimGs5ZB3jUH4++aOca7iHK5
Dv5lqS0O/vqBYmnqA/dkCliOYJ0/G6rG259rO4xV9vp/zPhw0ohr6AgTordsnyUjUkepUYXur78t
Gd3NiLCtzYlqp0Rs8UBdtBw2fQnxl2lZFnYA5bev6of4FDZFxLa7whLSLAIqAPhTZYVkq7PiSNHv
BGebYbsUiD8Y+KNJU2KJDKOwZrqmv4U9GoCDlmg7ufQOCSAcgIDlIygbzIxvUpnRMByP7X/vfLR8
/Qj6Rxxo5qaEmnUMaQob5l4ZKwDWIa7V5Dku72JeSC0UBwYpRlK57id0f1AsiWD8Y1WlQ7V4EzBp
cX13wlMsD8inecE6hofAs8258ieS41+YeLL5PuJ0dQERiaDzB1G/heTwwP7bq5mf2gOT5mkIxRo5
22dXrnt+oOxlmhH8F7I3nOPwhujzB6ur2fMCKK0VtKk4BxZ4gwfs0E1w60On4JT2tD0MB276hvqE
akWgBs5siKaPlDbZ6cYwyYOVWmL0D6tmYKCdrj0+YmvjXF5edKlFL7c7TtF/jNBHvZtz1s2wF0MO
Qdd5ijct14dd028RmDj3/Ka57W0PluRTaKxIAtJwohPK4sKjLuX2t5rn79eAOsXdBlbqHIjWAA5N
4FGbDgLzkvP/VGWuEX4zWr6Pu9WW/ndNl14xtp5L45M5UxAVVIwjt+Mrdxl29I7DWL1gf6ApndGF
LCyBAYQxQd4hH9j+mwiUs75TnkuQE3CqAwRWpJmx30f2WLyNNIDwrGYYrwaOzFjoyCe0HZv5/7ah
hjQc12fM/heRbYTkyEC9MoOK3PZYjnl3a8wZ+Yid1MOClvpsFr6LL+mx29stySfLC0CJHre+4zee
e7BVqpszWvp00/9jJ/UeCLy0tPRlP+9O/E/CUlySuY4GpQ1jm7nTl6JA8JOObFfsUO05BhXqqJng
wHYnn+egyNdLF3h0oMdFBBgfKx3if5+TyPmRpAQwyypTFOXtS73/WXhnS/IogHLkJrn7r7xO7Zzv
avh3vd3uvvl8Uxq7BSCp60ZfOROKQAoM8ldz8RQW1GhhsM7UOsze6zsClk2BwHvO49w5ShHL+MHh
mSP3VSGo/eGOiF9wle+R51pzJtaiKVuEQN9Up1idToegd9YOtDSIMwjoQYPQ9B79fqKAkAL251Rx
dO98L1RAJmZ+Ax8KqxExUx+XWs3Yp/bh9V/EMoC84F92FVo99n+vFPFyVO2yrIuhHE1hlob59AEE
dD2jVzCfyoABSUnLd8MASINZyMo/VLttfICsVRGYL+ewB0zFdwlGdVH3Bw/JH3xkzjvg3X6EYf5m
H3wQMpzOshzwdfvfBtvtZneYwoE9yxSD1NEk3HSUhqfQfxraR4gBhWvjGSU4hGbHqtQcVd7I670k
SjqiwMFfZoK4vtgPUCWjzQQFFQ8M7w6DU1JP/XmxwQDQ/VcHhHEAkHEGsl+RG2oeZDIYv4x+zKwP
HAf1tS2/lkOl7dWTrN+HjvJlMsdj+VMkdGbLB4FUt7t0XaPOErLrzDJhmanrPCgIXmYeCXlQQ+RB
CvngPhypfQaP9w2N6PKIETmlCfPcxZdb7b/BEuvtOIeKV4APz331Srd8w68qDyNOfRgjjUcq5mK+
rnOJozurbHEMJoI8lLLN+PqVDnV34E/85FobGDuYDPums1EwlezyM7aSenfANPmz/Px9uQSQVI+d
/G3DGjnULNK/hvHJs12Gd81mqOhMOnavnEwOW1fJGhlIcrJY9gN4p1gs5wLPJ8jwH5aRHEAwZtCb
Mmd8Pp7KIFUdfIIyVC62NMPtQ/BMPjNO2XgJY53HXxvw8JNRR88eTC9aGo5YuTdsyX7emLfUS/TP
NPhjznF9mg6nvYOYu5qawqY4NE8Smr/f6ouzrOkVg2yKaYSmULJnO9BuJtrf1BWE+EIEQVLFybRh
+l7cilfHa22X5N0HBq2o5HQzTLSzFI/hX5Y+FYb3qoLB4k3nQJdV/bGMyiBoTbDRv3K/Q1dupHJs
5uOZUetINkDvpHZQ7hjOf5BeOnGw8ekfzeD5w8P8sKp34de0xw1fvI1LvUfz/p7giWCcOwIVpiu3
bMlBPBAMK4U0Qa2S4QUqafO2Fi3f7acihMabA0njMp7IAjchfhL1nQkbW1r+hDyIC9CxkQglKDur
4D1bDk2G7BuDyqK7c38Qkg1cNrtmj+BXdCGG9Q0L5xZ7MxOISPV34QCPSIfJjiEo178uTya8QPw4
OwPTAdyPAEZRQkbH3nwK4eFcKvVrzMv8/nK/IJ4XEDXzf2DYWD9kkAUBi2s6hpgk7V7pvilRFiNr
Z8GyN+fho63mEtfanA7zVSWzvVBPOY/Q/9MSxkXJF8r/Aq4GDVEf6jLATSb530lmNubTa/hHlJsh
NdvUC5Z45XHXqwd5wckRqdKPUf8N39m4TRFm/PfK3vgdUWyQoYqqaLQ5+1XAZqkzjO0iCoiHQU1V
6OaUUn70J6qV2FfPkLAyuMgAerejS9w/EUnHMAidsbKEZ9bKyGQnqikEhlRKuMrfsKXUNujZz8PC
2V0+rOxTeM1euu2Q0xmipQjJ454przuYTdhim0KCKsQITw//EuPgx5Dl7q0i6BqQ7Amnhy20jdUy
FxP34NpIUf04L+qEy4h50rM4Q0Zg+wacdubYegZLB4/fHXhKKLkKth7W21h7lqk9s8sMuUi/PF+a
cZneO8T/MHNGyaXRbXn6shlYrLyLCkLU6Ju8RuWtGk9KOB4xICuN9QYgQRtdNC20UPXEwr45QMXc
W4nQYCYL3s5GgE1UcQ0RwWsBOTz5gDjpbl65CsVB2RJI/b+6fifps8KpYfoexq7yLxcbRqswfY3S
yxTydB7zNsS0Yt30I0CL6Pv/fvJn5L1eNdahUXnIFFe6RCwGnYmskGbBpVyxVhmS+qid8xrfC6UP
N1BLKD2Onf6zmnUhCHq1z5fjiESvKdOLOucqVmRr3rpq2+0RufuXkuwl7K2+lpEEeyUQgx3u86qq
fPKyKN0qFO2meEBvh/fxCfddjz3QVngc1ohHdFxriQQftFOURyt53Ad7luyoHjQmF2YW1+t6pskq
jxSFSG+CmtB/vaZzVW1ubx9Pu4LY/mv+JLklwYDhRQZW+95sZ7fa0h+W4nzyShL3hK24fSbP310x
zLtxPjqmWWP2/sKR7FjOulbw9hqffPGBB1xE9IDCvsymnxg2bQl0TD7/ZdNaJjylKClZAtLj28Ct
JNk94vBVxwqgJNsV+ntYTI72r6UaprXWe6XSgVv8bzxRamRPIshhMOgWDO9CXJUN4aEIUws5Hb2V
1XKQeIfGVg/JqLdmKPRCrICCaohLSylv1dNvhWMEBR+8y+nfPu55YuDdngmiLphrqGlrhw+U8oYr
rU0iztyB1mfQTnfwvW05MNkgKq1NxBDh4IBS+G52l8MPkdn6OvxxsiDZV0COty6g6LkwXxdJV1xV
Rbd/Vws6wALWBZI9yHUx2HcOdxSj6RawEkW6153UFWXzuEzDz1KGETXFRqOprPdIjAGTmSkM1ynU
1DJdnVydrvz731yX+s2VHlBA7r4DL8VbOOThT0dF/C6A0vzblmBfXqJ3qMeuZL6bYstbqtyHe0jh
ZgwiQrq1n2NlOv/VEO8fkZZ3bP2LRdweGtHQJaxXPa0X0H1X3zit7n1dgByp8q4zxJz7qC1yIijd
CzAPr03x2ubmi8PrkAhitCPeO9iFuuDXD63Mzx1S+O3L9DEjN0OgDz25VwLsM7SKyH1thyQxgCTE
6rixV4nyqsDojDBrwz0t8FnsBA5QkuS7R5Ro97tn/C/k7vzJXopu+eM04rRmDGO3gTJvWu7XBkgw
OIyVZrRTEPd7csulSjO3Uc9I9BcbKwjOpEgiiDwn/vUOJE2/XeMWy28Cmu9TCU8s9yXd3ohqVYOz
/LLpYRJDoed34z5EAZQnq5yr9wkv5lW/OPFGij3jzJ1eX6gebdzItUOaSBvUl66IKrXCacQUqj6v
AdSVXIoZuJEgQMrOHEVaEEUK8VPTJfSv1BEkMBoCF4EtIjgoeVrs7EAnhnimlbrWUA6vwI+CtcD2
9mn0mR4i0xNNBYV1EmGmAaU270jF1dUlNMqV0jjQP2xnVlViNZUv8NzgeGPwAjmuEjAqHgZZolii
qRtLcu1Iw1xedy1yqYKgXMvAkmijUUoN3kPtpwwnnpnRD5SwX6sSOcumoYVNoA1tlIFMCsTJluPk
nUwnUccmvC36I+hhTliFkUF0lb9f+ENzN8N4IjHxOo0e27OsbC0b27aAhcXD9dBBeRc5hdF5UC0j
NRamISzkvVUNrH8cpQwEeFqcRqHnFm7u5woFQvEh9nBjuVrvxs8wazTZ1SRNq80XYAQ1kTX56wXc
D6Yd99Yzbqhe1g720n7iXQncd3hq6Ffl+gsDm6YXofExfqDCpeEbzxyuZ/uoKwk0Zo0pB4hf51MU
TTQK1mB6oTVkHlvoEzYfWHt7Jctkw72IXi3SFvlOVELB45HySOmi6G4YGREcgayQPZYvr2VERPRv
VksXixJIHNiSb7NgHf33Ur/VboZR+hfHoF54b7Y+Qth4QJDKmXnUI9B7+pAeZRpVLviY1Al/tURW
ce64wzRasL/8FA+N+nzGsmhQ3X17gnCIDg2v6+N3VvZMvKcNQ+Bl3d9oPKKnTRCkFmjt4ht1ph6Z
MeVs5VTLo9ZGIg/7Xc1O1OqpW350EB8CZyWjxgujmrhfc431HoqnrID8WXoJ3++b+Lh2vmS1MBG7
204gcR7oSvXAtfGxvwKQupm+6ZJrHf2p3KTHYrKJUvWGlZnpjOeqvkKbRdKq4Ldbk5qjMLfRf20p
X7azrifxPIMl5pYD6wWQDzxvad4ZbJHfuyvLcb4+qfiywUXU2hnUvUeFwIogw6uWHNUQQ0J7QJSQ
8P3obmmVJJGI4PPh3RkxuQ==
`protect end_protected
|
-- -------------------------------------------------------------
--
-- Generated Configuration for padframe
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: padframe-struct-conf-c.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: padframe-struct-conf-c.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration padframe_struct_conf / padframe
--
configuration padframe_struct_conf of padframe is
for struct
-- Generated Configuration
for i_pads_en : pads_eastnord
use configuration work.pads_eastnord_struct_conf;
end for;
for i_pads_es : pads_eastsouth
use configuration work.pads_eastsouth_struct_conf;
end for;
for i_pads_ne : pads_nordeast
use configuration work.pads_nordeast_struct_conf;
end for;
for i_pads_nw : pads_nordwest
use configuration work.pads_nordwest_struct_conf;
end for;
for i_pads_se : pads_southeast
use configuration work.pads_southeast_struct_conf;
end for;
for i_pads_sw : pads_southwest
use configuration work.pads_southwest_struct_conf;
end for;
for i_pads_wn : pads_westnord
use configuration work.pads_westnord_struct_conf;
end for;
for i_pads_ws : pads_westsouth
use configuration work.pads_westsouth_struct_conf;
end for;
end for;
end padframe_struct_conf;
--
-- End of Generated Configuration padframe_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 45
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FSM16_control is
port(
RST : in std_logic;
CLK : in std_logic;
START : in std_logic;
EOT : in std_logic;
RDY : out std_logic;
SEL : out std_logic;
STR : out std_logic
);
end FSM16_control;
architecture simple of FSM16_control is
signal Qp,Qn : std_logic_vector(2 downto 0);
begin
combinacional: process(EOT,START,Qp)
begin
case Qp is
when "000"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "001";
end if;
SEL <= '0';
STR <= '0';
RDY <= '1';
when "001"=>
Qn <= "010";
SEL <= '0';
STR <= '1';
RDY <= '0';
when "010"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "011";
end if;
SEL <= '0';
STR <= '0';
RDY <= '0';
when "011"=>
Qn <= "100";
SEL <= '1';
STR <= '0';
RDY <= '0';
when "100"=>
Qn <= "101";
SEL <= '1';
STR <= '1';
RDY <= '0';
when "101"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "110";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when "110"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "000";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when others=>
Qn <= "000";
SEL <= '0';
STR <= '0';
RDY <= '1';
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>"000");
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process secuencial;
end simple;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FSM16_control is
port(
RST : in std_logic;
CLK : in std_logic;
START : in std_logic;
EOT : in std_logic;
RDY : out std_logic;
SEL : out std_logic;
STR : out std_logic
);
end FSM16_control;
architecture simple of FSM16_control is
signal Qp,Qn : std_logic_vector(2 downto 0);
begin
combinacional: process(EOT,START,Qp)
begin
case Qp is
when "000"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "001";
end if;
SEL <= '0';
STR <= '0';
RDY <= '1';
when "001"=>
Qn <= "010";
SEL <= '0';
STR <= '1';
RDY <= '0';
when "010"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "011";
end if;
SEL <= '0';
STR <= '0';
RDY <= '0';
when "011"=>
Qn <= "100";
SEL <= '1';
STR <= '0';
RDY <= '0';
when "100"=>
Qn <= "101";
SEL <= '1';
STR <= '1';
RDY <= '0';
when "101"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "110";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when "110"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "000";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when others=>
Qn <= "000";
SEL <= '0';
STR <= '0';
RDY <= '1';
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>"000");
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process secuencial;
end simple;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Design unit : Simple UART (transmitter) --
-------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY uarttx IS
PORT(
clk : IN std_logic;
enable : IN std_logic; -- 1 x bit_rate Transmit clock enable
resetn : IN std_logic;
dbus : IN std_logic_vector (7 DOWNTO 0); -- input to txshift register
tdre : OUT std_logic;
wrn : IN std_logic;
tx : OUT std_logic
);
-- Declarations
END uarttx ;
architecture rtl of uarttx is
signal txshift_s : std_logic_vector(9 downto 0); -- Transmit Shift Register
signal txreg_s : std_logic_vector(7 downto 0); -- Transmit Holding Register
signal bitcount_s : std_logic_vector(3 downto 0); -- 9 to 0 bit counter
signal tsrl_s : std_logic; -- latch Data (txclk strobe)
signal tdre_s : std_logic; -- Transmit Data Register Empty
signal shift_s : std_logic; -- Shift transmit register signal
TYPE STATE_TYPE IS (Sstart,Slatch,Swait,Sshift);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE ;
SIGNAL next_state : STATE_TYPE ;
-- architecture declarations
type state_type2 is (s0,s1,s2);
-- declare current and next state signals
signal current_state2: state_type2 ;
signal next_state2 : state_type2 ;
begin
-------------------------------------------------------------------------------
-- Transmit Hold Register
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
txreg_s <= (others => '1');
elsif (rising_edge(clk)) then
if wrn='0' then
txreg_s <= dbus;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Shift out every enable pulse.
-------------------------------------------------------------------------------
process (resetn,clk)
begin
if resetn='0' then
txshift_s <= (others => '1'); -- init to all '1' (including start bit)
elsif (rising_edge(clk)) then
if tsrl_s='1' then
txshift_s <= '1'&txreg_s&'0'; -- latch data
elsif shift_s='1' then
txshift_s <= '1' & txshift_s(9 downto 1);-- shift right
end if;
end if;
end process;
tx <= txshift_s(0); -- transmit pin
-------------------------------------------------------------------------------
-- FSM1, control shift & tsrl_s signals
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state <= sstart;
bitcount_s <= "0000";
elsif (clk'event and clk = '1') then
current_state <= next_state;
case current_state is
when slatch =>
bitcount_s<="0000";
when sshift =>
bitcount_s<=bitcount_s+'1';
when others =>
null;
end case;
end if;
end process;
process (bitcount_s,current_state,tdre_s,enable)
begin
shift_s <= '0';
tsrl_s <= '0';
case current_state is
when sstart =>
if (tdre_s='0' and enable='1') then
next_state <= slatch;
else
next_state <= sstart;
end if;
when slatch =>
tsrl_s<='1';
next_state <= swait;
when swait =>
if (enable='1') then
next_state <= sshift;
elsif (bitcount_s="1001") then
next_state <= sstart;
else
next_state <= swait;
end if;
when sshift =>
shift_s<='1';
next_state <= swait;
when others =>
next_state <= sstart;
end case;
end process;
-------------------------------------------------------------------------------
-- FSM2, wait rising_edge(wrn) then assert tdre_s=0 until trsl=1
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state2 <= s0;
elsif (rising_edge(clk)) then
current_state2 <= next_state2;
end if;
end process;
process (current_state2,tsrl_s,wrn)
begin
case current_state2 is
when s0 =>
tdre_s <='1';
if (wrn='0') then next_state2 <= s1;
else next_state2 <= s0;
end if;
when s1 =>
tdre_s <='1';
if (wrn='1') then next_state2 <= s2;
else next_state2 <= s1;
end if;
when s2 =>
tdre_s <='0';
if (tsrl_s='1') then next_state2 <= s0;
else next_state2 <= s2;
end if;
when others =>
tdre_s <= '1';
next_state2 <= s0;
end case;
end process;
tdre <= tdre_s;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_8_stub.vhdl
-- Design : mul8_8
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[7:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:26:29 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic;
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.ac97_if_pkg.all;
architecture imp of standalone is
signal new_sample : std_logic;
signal left_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal leds_i : std_logic_vector(3 downto 0);
signal clkin_cntr : unsigned(26 downto 0) := (others => '0');
signal ac97clk_cntr : unsigned(26 downto 0) := (others => '0');
signal debug_i : std_logic_vector(3 downto 0);
signal reset_i : std_logic;
signal ac97reset_n_i,sync_i,sdata_out_i : std_logic;
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
-- CODEC signals (synchronized to AC97Clk)
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component ac97_if;
begin
reset_i <= not Reset_n;
delay_PROCESS : process (ClkIn) is
begin
if ClkIn'event and ClkIn='1' and new_sample = '1' then
left_channel_1 <= left_channel_0;
right_channel_1 <= right_channel_0;
left_channel_2 <= left_channel_1;
right_channel_2 <= right_channel_1;
end if;
end process;
LED <= not debug_i;
ac97_if_I : ac97_if
port map (
ClkIn => ClkIn,
Reset => Reset_i,
PCM_Playback_Left => left_channel_2,
PCM_Playback_Right => right_channel_2,
PCM_Playback_Accept => new_sample,
PCM_Record_Left => left_channel_0,
PCM_Record_Right => right_channel_0,
PCM_Record_Valid => open,
Debug => debug_i,
AC97Reset_n => AC97Reset_n_i,
AC97Clk => AC97Clk,
Sync => sync_i,
SData_Out => SData_Out_i,
SData_In => SData_in
);
AC97Reset_n <= AC97Reset_n_i;
Sync <= sync_i;
SData_Out <= SData_Out_i;
DEBUG(0) <= AC97Clk;
DEBUG(1) <= AC97Reset_n_i;
DEBUG(2) <= Sync_i;
DEBUG(3) <= SData_Out_i;
DEBUG(4) <= SData_In;
end architecture imp;
|
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:26:29 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic;
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.ac97_if_pkg.all;
architecture imp of standalone is
signal new_sample : std_logic;
signal left_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal leds_i : std_logic_vector(3 downto 0);
signal clkin_cntr : unsigned(26 downto 0) := (others => '0');
signal ac97clk_cntr : unsigned(26 downto 0) := (others => '0');
signal debug_i : std_logic_vector(3 downto 0);
signal reset_i : std_logic;
signal ac97reset_n_i,sync_i,sdata_out_i : std_logic;
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
-- CODEC signals (synchronized to AC97Clk)
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component ac97_if;
begin
reset_i <= not Reset_n;
delay_PROCESS : process (ClkIn) is
begin
if ClkIn'event and ClkIn='1' and new_sample = '1' then
left_channel_1 <= left_channel_0;
right_channel_1 <= right_channel_0;
left_channel_2 <= left_channel_1;
right_channel_2 <= right_channel_1;
end if;
end process;
LED <= not debug_i;
ac97_if_I : ac97_if
port map (
ClkIn => ClkIn,
Reset => Reset_i,
PCM_Playback_Left => left_channel_2,
PCM_Playback_Right => right_channel_2,
PCM_Playback_Accept => new_sample,
PCM_Record_Left => left_channel_0,
PCM_Record_Right => right_channel_0,
PCM_Record_Valid => open,
Debug => debug_i,
AC97Reset_n => AC97Reset_n_i,
AC97Clk => AC97Clk,
Sync => sync_i,
SData_Out => SData_Out_i,
SData_In => SData_in
);
AC97Reset_n <= AC97Reset_n_i;
Sync <= sync_i;
SData_Out <= SData_Out_i;
DEBUG(0) <= AC97Clk;
DEBUG(1) <= AC97Reset_n_i;
DEBUG(2) <= Sync_i;
DEBUG(3) <= SData_Out_i;
DEBUG(4) <= SData_In;
end architecture imp;
|
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:26:29 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic;
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.ac97_if_pkg.all;
architecture imp of standalone is
signal new_sample : std_logic;
signal left_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal leds_i : std_logic_vector(3 downto 0);
signal clkin_cntr : unsigned(26 downto 0) := (others => '0');
signal ac97clk_cntr : unsigned(26 downto 0) := (others => '0');
signal debug_i : std_logic_vector(3 downto 0);
signal reset_i : std_logic;
signal ac97reset_n_i,sync_i,sdata_out_i : std_logic;
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
-- CODEC signals (synchronized to AC97Clk)
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component ac97_if;
begin
reset_i <= not Reset_n;
delay_PROCESS : process (ClkIn) is
begin
if ClkIn'event and ClkIn='1' and new_sample = '1' then
left_channel_1 <= left_channel_0;
right_channel_1 <= right_channel_0;
left_channel_2 <= left_channel_1;
right_channel_2 <= right_channel_1;
end if;
end process;
LED <= not debug_i;
ac97_if_I : ac97_if
port map (
ClkIn => ClkIn,
Reset => Reset_i,
PCM_Playback_Left => left_channel_2,
PCM_Playback_Right => right_channel_2,
PCM_Playback_Accept => new_sample,
PCM_Record_Left => left_channel_0,
PCM_Record_Right => right_channel_0,
PCM_Record_Valid => open,
Debug => debug_i,
AC97Reset_n => AC97Reset_n_i,
AC97Clk => AC97Clk,
Sync => sync_i,
SData_Out => SData_Out_i,
SData_In => SData_in
);
AC97Reset_n <= AC97Reset_n_i;
Sync <= sync_i;
SData_Out <= SData_Out_i;
DEBUG(0) <= AC97Clk;
DEBUG(1) <= AC97Reset_n_i;
DEBUG(2) <= Sync_i;
DEBUG(3) <= SData_Out_i;
DEBUG(4) <= SData_In;
end architecture imp;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_tb IS
END ENTITY;
ARCHITECTURE rgbfifo_arch OF rgbfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from rgbfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of rgbfifo_synth
rgbfifo_synth_inst:rgbfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 13
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_tb IS
END ENTITY;
ARCHITECTURE rgbfifo_arch OF rgbfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from rgbfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of rgbfifo_synth
rgbfifo_synth_inst:rgbfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 13
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_tb IS
END ENTITY;
ARCHITECTURE rgbfifo_arch OF rgbfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from rgbfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of rgbfifo_synth
rgbfifo_synth_inst:rgbfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 13
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.06.2017 14:18:44
-- Design Name: VMM ODDR Wrapper
-- Module Name: vmm_oddr_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484 and xc7a100t
-- Tool Versions: Vivado 2017.2
-- Description: Wrapper that contains the ODDR instantiations necessary for VMM
-- clock forwarding.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VComponents.all;
entity vmm_oddr_wrapper is
Port(
-------------------------------------------------------
ckdt_bufg : in std_logic;
ckdt_enable_vec : in std_logic_vector(8 downto 1);
ckdt_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckbc_bufg : in std_logic;
ckbc_enable : in std_logic;
ckbc_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
cktp_bufg : in std_logic;
cktp_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckart_bufg : in std_logic;
ckart_toBuf_vec : out std_logic_vector(9 downto 1)
-------------------------------------------------------
);
end vmm_oddr_wrapper;
architecture RTL of vmm_oddr_wrapper is
signal ckdt_inhibit : std_logic_vector(8 downto 1) := (others => '0');
signal ckbc_inhibit : std_logic := '0';
begin
----------------------------
--------- CKDT/ODDR --------
----------------------------
ODDR_CKDT_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(1),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(2),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(3),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(4),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(5),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(6),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(7),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(8),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKBC/ODDR --------
----------------------------
ODDR_CKBC_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(1),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(2),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(3),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(4),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(5),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(6),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(7),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(8),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKTP/ODDR --------
----------------------------
ODDR_CKTP_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(1),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(2),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(3),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(4),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(5),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(6),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(7),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(8),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKART/ODDR -------
----------------------------
ODDR_CKART_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(1),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(2),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(3),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(4),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(5),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(6),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(7),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(8),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_9: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(9),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ckdt_inhibit(1) <= not ckdt_enable_vec(1);
ckdt_inhibit(2) <= not ckdt_enable_vec(2);
ckdt_inhibit(3) <= not ckdt_enable_vec(3);
ckdt_inhibit(4) <= not ckdt_enable_vec(4);
ckdt_inhibit(5) <= not ckdt_enable_vec(5);
ckdt_inhibit(6) <= not ckdt_enable_vec(6);
ckdt_inhibit(7) <= not ckdt_enable_vec(7);
ckdt_inhibit(8) <= not ckdt_enable_vec(8);
ckbc_inhibit <= not ckbc_enable;
end RTL; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
h9n9zuV5lMts7E8xcOwd5OEmBQQTWDUfOd1CCpJtcRNKaLNoUwHfGMhoPZ3WDIQ/m/MGtplKUoFx
i0ug5BLY2g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZAtlDW7Tx/YNYYE2jawvMMCW40921zRgvYomlY8wcRlNVBEsxE3apQL4IIwUk/r0NSl3FJUcJhGx
bQnpoTAX9Ea3Clu4koloRBtU2UrIb0exCd/DMK0iUTANkETqlKdRXQmfp4uhLE/Mwb1kY3UYzJ49
sjSxoyKm731gwTjgRUs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
zmahq0NBzWzSfB1lvTCKBHtcaT5fN4U5k3LSzpiyaronk8xbbzR0dP9ew/cCp7rP2xsweaYMIJwx
4tmNaS7SVhNupTu5LCXNmztcum/6LIM82sP+XQm5E7P0stmksBmyeSbapkfjB3tOjixv1ipZ9lRT
2jAX4EzvQPFwL1SCK/TmWrKTBIMU3eqF/utXUKRyj7DjUJ0x1aH9jKDC27lR7DlDP2SBEkOmgqcY
fTCK/5N/0X3p0e5mIiq2SvHWuPYbZ7BMT//QkpjRJU3GGQzTUnWlASUM6m7MfRJi+M+OFHeWmIB1
L8QJdkXfxFeLLQrNhvUzOnNIZLmBjvdfQ87R5A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WsmxTCG8DN8fztPhtVEIEPIJmz2GzQ5Wdg9bSDQl1VF3JlYnfBA+IyOkDekq95uPzD6xo0LmAdhN
45mP3q7RIMlQDqqjev5Ze2rMOTLhI8TWgOLrSla7VmvhnhO8tYwKCxVJUylQ4E7/oh8VrC7Nw3ew
p2dO5WqGm3u7Xcft7oU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
npmiJ2K+H/l4V7AAYSTOYU/3uFzD/iDh8KDcJ+ujzbpP1wELTkvl517j+UF8hq8Wy9Jlc7X49HWY
t4VpDPll3CSI+Ftj1wtWAwLuDCoHBFLyHJPwcRoy6IeCNPyfibFC6V2Uo5iXcC4P779DwMxlxxky
0XNIlA5nWPpVtuz85emt2UvJ1pAyXLeevu9blapiJGoIha8GQrB8wyqkPvvKT9MI6pSyZ1GtGhUX
fUxqKljAZGqWzTtg2PAxwy0F19VQSW/vc/hbOa+wNtsrL69a4qy8LeaRMY2No8kIjF5gTCchKrZ6
GxMPIk/mE4d4hLlcMFX5ZGeyNa0b/a8KsPdd3A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
oOvEnJ/GqdI/mBAktuImzUEao7fJyx2acDaKqLRNaxqMfuEg0PFVjg4IPVvWkNQXn4wEaq01cfJ0
dykKujaQ943VfNYnxtBaq7tSOPbfT3cm2hOm4vONVfKfNDg2uWW1rtrYZmHa9JK1qx33EI/v8TLt
zjabOEP49gM99I8a5F7hsWisbSXjJ4jEDc2Ic+VfjtTjwKXZhkmPGFd8Q0WQa8CRNxxSjITveso1
5opJKiUzUESVmOL1vxfj7lkIcNmvOndKKWS3CvL5MsfRSZZWb4/JPTKCuhheFTxajgWZ/xiNehO4
JyDkWW335v3Ycu6Z7mHC4uPzBJL17zW1ce7zGsuVcyFCAzSg/Xsuq5g6T77ZkTo/jfeBbtVvnyV5
0nQim3L5U6B2/OXkPFPclas7oo5pHeoOWx4dgq+p+5B3KkAXnb/ydE5nYSpu9jt1v5VcG7S391Dh
6HyTbIXma1lAWOnmycEdxoQ13Aekc+YcxJ/KQlX0JQNE0R9Jx+ElcmyCAhxP+wBT7KFmxRlbaSXy
k+IaTcwm1cIUTQOqCKg05ELIBOpKfTsa9ZYFG6I/M+ktpcVrzbwErpfzVGhCGc6Qzfln+nWdnymt
4Xn7K+efHnyOKHuNIqeZjJUZEi7NVYFKGdZCz2T6YtiQ3chmQB2pCOpoSrYgtFLbAYy5q4jfhHEM
8wknAMRATQqLwDK+g55EYamIVomMzE/C6M+Fc1Tu4G7SfQcW0ovIdNsYEFd2whiqlPw8oerXbxDT
0otiW3S5Q5YiidZNkROuOshX8JrxX8eAWP/HNiYgU8bf6nOmjESDtz/NebC/D5/ejbuJ8tnATTFi
vGW43Pr7lNaAgTVeVucxTI/JtuBz8hxcX3RCddI67DKOMR9RY2CIjFgid1z7RA6ETpdPQkB2lFKq
yYB3GaMhNXr8ryC11xgsE9xdkZd2ziQ2xnxGM02+Sji4BkZIewXf2OZVt7JbweoZBAlxH5HUNdkB
UFSdt9Je0Xa4dX0umh8yLSZC4ash7XyBu4vr/+O8RbmwIiczUW2uzlzrRDOAQenpaQ8Ydt9OPZbM
8Uhq/QErtedF0zDjJNxz0Jdpz8sBSHmx8HSaTQXjThmlQQkaDy2jSpu8Oeh+twAsBtBpFJD9gnh2
hA8UeMiV/nqniCIbpNztZcsJATA003/mePLQzU2xNs1JHQ5beKRSLTWQa/3hswNL7oKTWHtJXvyc
HTA6ax4/lbdnLRqE1gr/WjkCnY+HZhWvUlhQkv9O6lq9Ku6THkBP3qO04kX58T0H5u/Zvfea/5bP
ICJ21L12jfAwb/dbFI//fMJsPUa9Yxhcx8ClwLTXapMnzuqgKJsv0x5T/P5ERa4tTiC4dRfaihA3
pnLLiGbuLJF9+1+kpqcwZ4JH4iMuuuX+PYFvtnPI6b5Gv3o2HnhTpHEofoko60Az02bXlzdcn34O
7mmuOAwCT5gfza9pvoD+QnEgA82AM/ZEHIDA9NPlr9nipk75y3skHQkXx4F45EDbQXSMN0XN4G7p
CvBobcUoFCFQkL6GGDCSvz0ezHwrj75QdMZ5pLTPtn2MUklXDGuS/VHl/fpQ6/4PH1IkLKgmQ87K
0N9cQM9SIyVFRDMw7HbjmhI+FbDyqKHSTNxLzVfuX81bvc4Op+gRZUg6iQYHYjuFLKx9RoOz/jZ7
nNRIwN6FDaH1gbhvDILmRHpjGmi1QiJOHQcU/cVQEDe3/nZwAGRZlLCeH50mQegkkoS/2rD7xDxP
Ji5+CsrJNdVQ93e8eBHwZTgBwOc4xSJe7o5iilamnXry81OvuiunaeawYyTv20mDgN8+ZDmugOYH
R0IKRLALek7I9BqhbI4aIPwm47zSZzF26GtTRUmF1kEfIaTkFADEIYNOuNyD/4Rj8YfiktAw+arN
dsLD1dKVlRTAho6lKZwVLGp8mcluvWJ4AryOfJ6T82XbGWe/QSZNxLwKhYgYP1pDPW18kVHjdu18
NLq/TngSvoFWwxmexXXhSkCi7UlrC4Vqid15U9mJsQu7dgrAcArSB8D7T8Xc9sqbZs833Y31GsLc
7IgtVvQ1A8JzPSXpO1fuOhY60nwg9M/3KKkOEmGaedehH8aUA4eB0qGpmrz5OY39RR0imzCtNte4
ku5rIMeATGA2UbGqgZviQsFW0uJ5Xdl6fyJIlG76G9XwClIw2I+HYt9PnRTEqYpJfUCIGAzQ3p7b
8YA306ysBvHNEyIlCf6082AJnVVwrdAjdNW8o+YQn/JUawh5AfGsdUPPB60+yCACnpRC1YGLWAir
m6TMPg5l7QKTx/O4Bx7UoBr55L3QJMSJOm86hTl60zGE7UPkjHN92KOQmxYRldExMCAIG26tzZ86
AopIJWRGj2+0GUzJ648y5p1eotUygxrK+M0nXfQffWCX4h0vG4pmZ4K445BlzEFZ/j/DjK5iwcDV
h2ZhWNSXXVG3CNJX1aGna2vHqTnKbhCc0g0a9WqCr2z6QlNpT7axOoiYh0+ZSYGs26J0+8buG1sq
eHHA1Vs8JZ1cPDM3eM1oYHN0OO3ISKKEwH4UE8fNqwgIwqgOHkpaK6E0qm4SxgdmwVhRkNNkUKeG
WUgHIvEagwDWqUC5erlHAVC+8TwczhmJj8kI/SXCHeR40q3tsI8MfYfeJWMBHB1biON2oDaLyUmY
2ZOVZ7OeNot6LU1JO+NWBiNVu10wwO11yH08cRySslMc5koktZBwiUf9jAMq/xJxyYJUpdoJdJci
DoBnTpLX4K5qUmKZ1mPx7sIWhyVDlMVG750vsQZ4PJzjFP0ubi9ycaxW0ucVvTgSqw5Zqjdse0+C
Hjrp2WHLC5k8tGe32jF4mjezTd2LnUmYpLd++l6W0F/+0JJtdlCozR0sKZfsBHEND9al6RH+TCpb
hFCzDhZb5s93ubDmq9bLc0B70KvIuW3woHLzKlAzcvcCp0S6YQWQRE6BL5vApebKJwlsrY8LrlaD
YobN87XShGLVb65SEJbzJ4m97nJjZQKi3QMhJk04Lv5ZL3KSVydQgzKqi+NVdmHSZuUxiaFj5vIx
QFQ+tJviyumV7/fjVF0DPficxkdPvKhY5/vt4oBsT1oj4VQ8caAzihxriqafX/lQC0gYT9TQ8Rhb
gFzL31Hp8thM5RBPuVXEe9lBmnECmUeO7TOCgZj/0Ya9NKP9GH2LsMSQwrhxMmdjy5s6PtTQhElx
+2u6Gyrejzd70TGuxN9+SkKqHiUp66m7/lSyucJYm4zQ/uPD5H2L99tPqeQLbIXm4yK7q0qT95bw
klKI4pAVCTGRhtxEaZZLg6WRXTto/o3reo3KjW1xMcAgKwXjiOJm2zmVuw52Of+mjAQ8q7mhCcX9
xVRlQeoBAtrIy9M8R3iILsHJfvlNQqdVokeLnTsEyGtFcWsdnfqeeDUERI3vjKVuk7nhFv/4NLTB
KJ1WIzfZ1TqXm7VK+WynzzV8U2mBsebakjE4bFdOiR/eWto6rOEWHUnjddz8hvgQteYhkt4kQue/
EtEEsdVMzNKaPdUuVzM6DYpsKjczV4QQTI8/vxAZ1Gda0pDIDFe++Ga6y2vLn7rRT78hRGQ2i1Mf
2uuWljrxhTARlBsEioVFoK7LwqpezWLw7ICaawKEwRamQFPftQaXkW+jOGAVVY2a3r8d/fnwBHRs
RptIGic1qFXNDxe7NvgJIFev7OELHnLUc18x9R2Hm28S8VwCXdpkGcn71gkvmoDbesyWL4DyJguR
NLNWjedBQEzTyd4MUpFXrHW2iexH5wd2qrkY3I72MiyNNDpydmGcahUmrCRoNRxmEGAzoqJcG0X+
myQKqAASz2JQQCRbp0o08/g3M79nUkC39MNQ5JWB4dCslihPNbz3shGBhTbP2mBtptZgSqvQ0tm+
3S7WGMme75surxuoLPKh3zbpYV2rw/nUA7bkkh/R0dApbXbRR6KNfzXVe5NdS+vyg5er0tZo5bq/
HymENQdJal7OhTuS9dRlwoGLuCEagiW6PiRWKCsuYRKrj2ISjiamCWcdMU5/etlZIqPdMJ9rjn8L
uxWlWIACq/dJ2VDUHoGT44TC9JxZHXrnDa4l003eYSM3ZbN2VQ6vZnQ6+MftjwaiUePWW2iEQ8+S
APlSUgt77wO/RcUQL7qBE6t2iAw2fTL3N5Fi11qqUZJyMHx4i4ufbbHVk0epElJfACwjF9IyWJHd
uSs/c1oM65KO/oVMoo78K/SI9Vya8bSGpYfT4NdIVMfH+T/Fg8lAY423/35rsAUT9MYr9C/p5yyz
SL2R8pn4Ol2O0SXC8cRUrfZMbj9PhxpnNNG7VYU8kG9BoSM+lYK966vLWy1fxMKFahVZaS4ZEAIe
wTUZJoLHyuKYNFYATNA0rh8qe24DuDgrmfcMLjZeTunRNWYCB9EW58NMLUyayg0ME2oh7wwiEsDa
SFYSrgID5DjnFiQMZfi5bhCWh5ttBhpILA1UHF0SjyvEilD1163DnoUC9cMGswrA0Vrj1mKWGJ6i
TMc7kK5XBZLzoc4V0k61/gSxZKZmNCG1VTweFaYmgb6LeRuBEJIDSeJC3HJ+GBWdOIho4JdVjRon
Mjem3cwj3QVjo9532EdBQwCqgXuhPdZ9vLVNyMT4+Wwg+PB0huTLoObpZvqpsacShO4ukPTo+fng
ZKpOoNWvEU+VB5OD+gj9Uqw1wX5FbHEUUq0AKH8c4ShTNNHQEN70CFdjoS6EO6DUI/Yl+m004GIq
MRfgup4gImqdpiw+ivoodtPt9pe5bqDuwXUusoyj9U9+iNn15yz7NnF2b+WWK1XLOjNlpal5Vfns
+dmG8S2SqnQZQG/ecq+OQHh2dnanlhuexMKHjy9CpDrYqYeJpep+DPjITEASosQAWQoAVrNEXtB+
+0sJMORm3LvxxR83+XF0mBGAUqIdlKoDgtkyfJOZNfIaskkdSOF4A7mEVyekH4QtbytvwPbwXWKk
LxG8TrFPh8YMZNCKlZv4V+yR6jfoNc/RKPgpsnScEwpOKun4FirjN+3U5nkvpSvY1hGWqMrsKBRE
sOcW4pq6ao5vycHZ5MOPTjwdQEwtPHiMa0ld5iW4TzjQlaty3Ta84brnTjYSOE29nZtF1WaCYIEb
rp+5ehfOGKkw7OjNVEw1SVw2rCqG64v1p0et3cwvGTtteF7LHeL//3eCRm0f78YKKuIx5sV3wOgB
L3pkxe4QNzXOGg0a0X4gUppt4/PPDIjKHg5KpRrdF5NbNIesiRv1uWSkWOPrtJs4RD4+qcPPlWsB
lQ/do/k2h8xyFnLQ3HMl5Pu2ZghcLvMs2jCsR4Lq1d8jKJn6vorOaPPXpvSZQQG1dzekwAIJPv1D
Ae3ml5E83i6tuiGnzMeBKeZMSriGBkyTsUoJtHnM4r5wq4gCr/63jW4eHE0ZDdRA9XtY4SUayo0C
SKjtOnI8DFIOqgqkW2OlZF6Qpo4aA/7mc5CjReh34IxHOay49NBivRnS8D2lDrDv60evVqi9m0Az
sCNBy9UsIPDouDwmdW9azFeKuWxO0uczlp0bOzJsjn53xKmryyyHjL9ANc+IA26ud0f00RPaWf+L
XNJ8xvSx+241WOkTsm8AEwqIORS5UZfQsmnBMfwUmW5C7LjWmDxShizvUeHNN+kV72iWhdxHhdSp
hohDdClXcTXAa4s8VYcuURR0Wq7v1avORB+ADDV2grkTZ98OOztQ5hAoMlx2jImBoahTtDgHiVNX
8P+vGmZi5JS2hhIY0St2vY3MAjk3vQyYyl9CRBCT2+I59A3t2y3e/04OPtuN+Ds1PrvqU94o4Evj
sik1rPrSUIAEJ4hbfhwfNX10KXQoE7BsNBJXjLpuMYvMxA8aQHXdhAn/pU0VpsywBVclwBGdXZCp
nhm23wco1uKx2vviuqxR1gTu3AS3SzP8vE3jcIENH7FnSUHUuVYNZEru2YPKFSYZ5BQCQdMyua1H
s0RBFTeb7GZQlh1Ni2vjaOfv2MaFXKi0mZAHRoFkAp0vxxlB5FhOXpTZlyj/NBVQScyLJ2cKK+ZP
+Ysq+hLIKJafWSUAt8c1oMtsTdBvlYe6gJF9+DcyGVdQ6A8pIB353zTghiDkWNwkaZhG6n4oCkWE
mKVa4NRINkmS63bZy/LHwtuPqQ+InAia3hUKgqIHFuq6z+fiy0J77E74urYh4spHUBzNWpPDB/YN
ZGM9LPJKpJ6dhyloHtEgXD+wm6sX1POkpvvyqnM9p9CxYaFmEjilPM7BdiUNBBWFn3SW0caWkWQP
H2oCbRjnTQ1R/F90Efy84Z1zsAUhZxOtd7qlYH9aBEuZp+qZeGitzcV5G2CG3FDBZ+Ibmk/DGiNW
79iF+coXVU8IW+N4lOoZN0U+LTpguYmg6UTsXsjPU6i7kI7qMAmrH6Kxxo4Pbiu6crl4IHl3qugU
3Od51347rQ6SnLt1PTNeVau1LB6oO2YgSRUp4c0kID1CiHlBnSLW+J2p+67WwB0YVcpJxwd35WjU
fxLvgtkjmUo0c2E3yICLMgJdtc5PzW4VdryXu7gz2O0uqoje3VJSyub64Lkn3YDBRkJ+BsGSITjx
0jplK7L69ZcVP/kkc5a1gFaeXlW+bXWGEBMI0wljfd7h/o5Ztz2KKjSIXzd85LVDT648K5526MTV
gdj+cfVwql/CwUZxkKpRlofR8un3B+gIThmHABcnlih85cVQYtEgROjEn6grKQrOZOoDPZZX1At/
Ds0X3YJYHVCVDzWIx9wTrqdMpme0QbxzcmvW0LwoAbJ0wcF7egf1tVF2WyWzPVlDHsD/sqIM7Rf9
rLhY23CFA/e120Wed9+LKLGaVIoGkQ0lB9U1iKAwDni7mb7lVDidQCFy6eX1k6F7cN6kZOPuYyy/
wl7zVoXjtjUmNAfxPKGgy1/ZXsvb43T5XvRUFzM/3qRpZf7iFNJG69MrnCU0RBkFqEYVwWb+rn3I
dtp8lmcDQRu1+/FxRqhMzWjd+3nbpP8166kvFO6cU9Hhej4uCEskz5xsTA6hRYOu+AZZYo1v7OHP
oKCpeUzq6TOcOdR+qHIW7YecNC8LQD3BUbY/FYdSbBT6Yuog8p5tzrECHGEd7+NqSuQwvJfHqlNd
eWgy/o8NUYgxAIFmaMfWdtMS1aLXMhW14o4CI8ghvi7acM58ZTOk89MEXmgVPdFpJbp/HQ/3uDoY
b9bfzFN6drzZvQ984GQSByNq8Zn6S9JuaNmIyvTL40SEL9D/ytvMVA8F2ZL2jCQuG1R8ukhoOqnl
QphQaiQeocalDIOt0I+6sHBK1or+nV49lbi14TQY++bquwEfW7qZPQ019uBvbjde/CLPf02WvMVS
+oxoQNQ3zv4S/wFhLbIEWbrePShZ0VLHTKmkFtTbuvcIaQLTHqF1oix/1xI6e1+CmPxQEmqAV1W+
aDtKICNrZCJMcIgGxNWhXdd+8u29nobOsFtAXzspqaLfGWadnVUE87gpWKPVoRBCC02eYNaUj++I
RtUS3Qtp2OjnQ5fEb2pNJ9E1iOhVCCyUDEiYQjOrgBefn1zPD6fZRYfIho+fgk64axrWCewiZhVM
ZsaR6kNvFospo4T0AufeVyzz2AhSTDyapDGgst2PCuGd1VnT2WYSYW7DbWx/snA7Fmo8HxUgg+H6
pthaOeVZ+nTRPUcv7ca/3gvKymwCNP+awemiKiZ4t+ZXyjeDctT0h+mmlcT/JPFLu9V//FhWKI+r
kwKRniPufZxRrP9ylwg+NqK2dbna1w0CKrJJG+FHXssRg/UVQyQwcS4G6G2XT6syfBs6u77ybEZI
yLT3aqeSK8DDdqjDo3M2dy6hEd1LdjKSw3jy4bAN4p7vc88aXquHg/W5zu1NG075KsL8za8nj7lw
GfqsGnSFgUBVZltMDj4+gsjEykwF6mdyKorWHo1U71qBvCuR0CJwJr74VlrXDJlXcNGOgjmbTwqa
gWJhLbVfEZ5E2bLGWqtVbNezWZGuJzCFk4gyFcoq/MiIWtUVu4ezm6IV2TBDSS1vweSWoySHZxuO
7Lu8iSlCULBrckTXL/MEh1U7wJD9diTqb1p6/LuZsvXlmVgXS0ckdmmR6M3lqu2jETITuahgQ5hz
UwA1w29zUtnTI2zz7S5imY88ayteApKkN0oAsMBwEXJLe1W4eB5j62moNFs5Px3TkhIDru2Kn+dv
jCkoo2nbo8J6MxNwblnddyu0IFxaPzbnRBXVd4JreR/HR7BqJw8X8WeweEVK6fLPW8oYYylcGvGO
2ChR+kIG+wwvDduDiw13qjaK2cAtXZQPEqiI1+ZUl1ut0jPh4D0ShxqiGg242UY3gpRJbPbiz3I9
AZK6jsC0S2AI8sKtl8OZnQ6YE98QRGLk5pW71CZBT//5L6JSNKbjQzSeiGmpx9+xN8goEZnvpLnw
MHfE1L7BZuFM77PR3YygOMJxPTZ3u/oqz4XULraoz/aCzH0nMgHFg/VV5YcoHN3772+1XQhAGpk/
ZkMaz9e9wiPriQVxTaNCEdMsgX6rYRPeIp/Fwz3Z56pQzTw0nlFmEbvKRqKiGN/Tjz6+ov8QHo0U
ZL91OkKEcBperXv5Z14WlkUo+LICQJIXvcLrH9ytizAgV9bkHVZewCMk0kk1GQEVu/iqbG71IHQu
M4Ysav5/PZ1EUY2GcI7luz54EhvXhxPSfntkD+GLZfuwuhEWaJJwqDm90N/+RNPuF/KGpJV8p0EE
tcnC1PfS+0SurJMpNgNAB3JY8O1TuI0CYrMPIkY+4IVOBEc3NtCcHOmeOjpIPXmgFdpk5DVV2MyY
gkqlPfpMwC2W0pFmQC+HGbMOpyYkUJ16HtSUSBrpBQwZssl0oTxGv4sh46pPLPY5LlH1knRPfLbr
WfICyIvMRrut9SKFfdGbzCxqpkMurWQG2AuXjE4Ly8XyUHVauhdxNVSx2uGLDVCW0eOjZHgVQZk2
5L0F1BA3ZlheGmO6O7xn6kaht6Gxmty/heB6f2TplsWIzQJ1sJ99e63DJZ85GDK8bgkZL6AGyUmy
HWNkRY11Zjw3i6H/kfZQQ7BkJsIr+OVVdCLmUIMzysBkyfMgSqOd30D+ps+D7cZFpe84S8Sk/hbk
tT1WrB/StZV0BIoo/4uyz/FFmfATBB3fpLDXcARqcbPRugE2OqOZV0FNtcGeao5z4MsTc9EusMob
Hl24ftk3A44rdwK1l78hJMhQz61ezGqIaxyh9BX7VLqN7G25E2HCMIdFLCSK9DPaHqdUhvd2B+mu
53jaxSZ2b2lldIW+RorQmhLsaPU8/MX1+LAulDjRxk4R17l84rVjhQxLLXTiSC9+2dJL3VDVzHeB
V0djUtGfqProI+0SQBG7H6DuGz2vkadPexoteYC+LuVtzuyi9n6YN3kva9bqSdWJD81Ycu/3jNeO
0cQMZ+H8/MVuTy0/dS8YWtD0dgFX2lYGNDWTqA7TCJpUwPTZaBFf2djYsSdaw9xCMJK6nihHSRbS
2gDruxkiGtDY13BAqZ1XH3i/P89QUYSkzmKSfVxPNT7FypmQb8hHUDCMV+CTma++RUtdUyU/PpC/
svAsRb8kl5mwg5Uw5JaGcQnqas0QnpDKD3gM6h6GdnJ6YXdO/Vhmf5617+xW/BY8IHioSiC9+MCx
Ymp0X3MB7Qv8BZs1oA5zCdB6Vc67ZA13TiRYx68iTjshnpH6NyssA760UCTwDP+8fWD+ntYze4w9
UgcsFa0S8NLDhDzG0DCzk7cusxLITLUrl1YpFVTUG4p1Un/EV/EBY2jzB7qBsxS8MFC98vpk//fB
cs55BuM8boyTaDpzC3j8cAW96e3on53MEpVtCXBXuqbRENN2ajRDBndo1143Zg9UsA8SAtzdIIHD
VlRQpcaXWaHm9OSwXD0VSN7HG4F8lpy/CNVvCGPFIht5aH1LYjw7Bj6+0rlC0h2cDa22f0hPdyIw
GrV/rZmmW7c9ilCwMoKzAbEWQEnyIQxEFEpYz4cFN6BV+8CA3iZ17x6GLWcv0i5zW+6Xridk93w3
Oh/t9b2vRUaVE338vvPf3wqRSzsOyANWBuJEJ47LTSQTVJh7dqeHaEZmPekaIS+OtoJULZBukT6H
SKnj+3SPrVEDJZEql1sghPB4c46qNPOJQvyh3GQJVOrjD+TaDD8A+loqOkudQPS83stmZuqDSIjl
v+iFmNgWyQYK6Djz6/fGVcQZAVMWfVe7XMt2koD29tHfxSQT3oTF2Aw348Y2oC2SY2rLy1Cza1eY
OTi/eYTbeMtM/hq5ucqNfOE5nADvL4SjAEr0WgM+fBKT5TGUjL87Wgw6DQS48UKlDUV6LWnVj/GH
Y03Fq+rEWyRd/ys8SfR61RIaX995b9RX5DezYTaKP7YRk125yekIDSLT6MNE3MRzelwu/Wd2UGZr
BE4MQKVuSlfs67Jy3ixijvZ2GXlIzHecAeYjh7yEdiEryO6cTyRLPabKivtyzba3yOJu1myqcdKV
B1E42v2Ehz72/fe34/5BzDET54GZr9yOhRFHJCWL+LCT5ViYTSyyrYZmFtCvdTVEo2d8RvRJqVi8
g/2eCDG4rSUboBE5BoPqkm85BvTgCFgGJB/aguxzp1mZzC1W+x6hAfL0cuIL2KsXh+s2x/ULo9mW
l79nn7YNRuWfOIHOwjjYIYrFV7cjVptg4T1kK3g7nuuEcCRvEUivkIiuns2w6NZq4lGrc3XZEwv8
ZxTZ/Qy+NXMA/FgR2COWKDEuvAutTUpWkAo5EBpmMENkPL9p8YyZtAGU4BZUd2WXimIk2DlsGP1g
AFX0Lnt0/YiFfJlm6+IpKnwG6Lv48bVjD8s8OnYQLRm8Vhdn2UFHeZZdKCYxmKVEvbE4PDWqH059
KDENkT+yzerIund+DHfmE4BSQLy7PRDG2o8ywu0GynxL2if89EBPHC47MAvAMQnItPWJ+steMIE3
mHNAOPaJsTbucJMFLRGLmxVvncL+dSv47otxdi7IOZlz88DjOlM2tbbVAEYpOEQvNDw15w79RW4s
12/Pn96Wd+vJvippM9VBaURMKTWtZUOPiRqMBLxuTzBg13UbnJ3na3R0hyo07l+O+eA9T37OImcM
Pp0BS8aUmjoNVjFg1rUaCLUocvtOcVvhvOm3oY4d2Acu6sB/jZIdFslHuMmbBveLo9lHq/hg+2VS
6fHlGMlfy/j8TROEjWxwpvU7xB+f72M55/0re+DqngAeVPj6f+utmI53YsAfMOFfCONGakG4HJG2
WH7AknRwGNeEHGcPeFz2UfU4BOG4dFAqODrIJMsQRDroR0NvvXLB+s/I8UNBxK7Ruqz+ATpMibyF
B2aKEum1MtxmGwPuPVJivXWjkOjDbGzR7kz4yeW7VWMSp/C7efsv1N6wUpq2H4uPWcQrIayWk4nW
2U8Oo7F+dUMqiUDolc7W2Bc7kJBHFE2PGhgKO/416/BWWuo1tQeL4ZcKLFn4qX+50GRFTNTiNsM9
YvodwmEsT4u1BiWj8SPafwxkDclNmx4F5KlTgQu17BdBzWjS1kV4XJhb87Q7+n+aCuu+d+MdBPG5
hIdXwuAWArUPwolJC0J6FW/ZPKyvrrtCejlXV8+/bINhhvNI3w9ODkS19djHcysms9nbTXL+8tvG
4iWJtKRurSDbFwFd4YDEheyEfN8qz+uBEPwqPIzlFavOHugijjwiULwnhr5jlgqelvVD2CsKsn+h
O2biBWIlcugODe0Jxjv/M2d0+yKQO5XznHXn8Pca/aWnmQqxsLmzvAA9TgAfk+QiWLyVoG2+2Pe2
zYh2m855jiRnjCFUYqUilSLq/70LQ5157T8W+q/R5CffQp1qJ7ZM9PYObapqiJ4Gpq0AhdmPCPQg
Hik+WsQsWTA7Q8PkXjFLOevK1p8fMo+0GUQrqb/daVT/4buqwkg+kGDcJ9W5jQPLsDa6H5qE/+Ca
W9bTb6wlVpO62Xfdg0mqm7xBiDiBVZ81VmhYfeNEF8Go7C4N5YORHHpu3KyrOzQFVh3My0lPSTBy
OCmlFsrDTJzIacLT2mIWCkWSUsrEKo3FomjSC/MDamukkxfo7JZ0ThJ0N15C0EGATfLNKqGPJGTF
m9xKHl1s+pXRbVgdKhDpF3s3sJqiJqIky8tuPp56hE8pG0clEHIQwm9fE9Yzbj5RbI+jrA/Mfb19
jeqsMpvG5boLDjMVCN/fQ4t0iyr9aK/F/yeewTI/RsunvYSjSbCiLi++MDkeMtTCr1bfNzvzFDPh
Os7ZPy/bqeWKYYrhBT/S/xQCMJLiIiLEXhNFGHtv5wU8eiC2pHdbi6AoXRzyYWVFHkQ3nE0IeWB5
Q45nz5GAWhDS05cg7OAIEtESzTa+8VGLN97dXg2QJMv/cQ22Elm2Sx4XfqnlkM0sxF+Cm6h/nGDr
aXEdasDB80n0tEpmskhjBVvZgE9zXsJJwkoCZ9QUdoBtk5TDiFhemjwzcUZATFNeQbFcXZTdG1bi
WIdSTuX/qSgCidJvv7hBPMNCFttAtHjjTIe1k3c2D0zzzRsXcLXIJMDyRH+tpyvZh/NAXIQqm8bX
48g0G6iMt0lQkYBs90BJgIdgLkRW5Ciua4qrcbgwSvOw8beDwyUtbT4yUpT1ks3EIcEm/v4poD/T
Bu7gNs7pNAcvS4y2gAIqmCeBOCzD2VMrIRoUT7/flzbN93crPs7mRAU3k+DEhHScmIMOLtTaytxJ
COQmpoCC9rbu3OJ9PrVjfBe0Wkv72er0topLjok2VpHgwloTQbV21ghjXE+ki24WP/9IPdwk+fOt
4U3cLZGtTlTu4L5oOe2S/ekfmQqigE5wD+YawYkpDm8Fci2AwYpqC893xaJ+LNclRunkhAvXrDsv
fUF50Tk5O5gR4cp8v/VbdYYJP3uMYONeuBA+VFEVe7NVSER+/uBw7j6UnrJfdItASGhmJ8VNpUVM
Ufr3Z4TPFkhxKoE0P70pW53f4MBVIxTmbQ5sMwYVbdv5KGSIbSwwGjPt6l84yTHrPndwA2EHTpM1
7HWZ8QJtiFY364omzkrIoYGihPj5u/Oy9wbYzdgBF6W2cxKsNDQaEGZzC5TmocGn5xLVn2+3E3u8
BwIxKgKeVaedfxb1X16lQDWJaoPgh8ONMwtXvrGr/2we8pbGQKasWiXNHO1V71CkYCbUhsWzNvaN
ChOpG85ws67XPHNZKYYs1GqlmRHDu2TCHxwD2pr+cpqBs19IpiB56ZFw6b5Ou1fQvrEOmY4U62DE
YHdS+6TF4Xv3wfp+eryV0V9KDbl7PJxwMVMh6ySOYGJZzG23DV+YAaY5y4EzJXJlRX7NYdScGcaV
DUoeD/U+JRZvHHPlHiIzo2JfwPO09uW0J+gxEGk9BuFnn+Ve3+jleWBAPtIAo0UZkDGOWlDsLQKH
b1Kb2LZI0xVxt0GnJGtPuZawOTdt9Vg4PXm2bjeXdFqqbbSyy7ZAg43JCNhjxiRc0UVgpSefSyaj
5LerS3x6OZC+xLc3EOKyY1Z582k7psNJ+AanJk03/B8mL3LW3/c9XHceUXbJRfaGr1hH7Ge9s0q4
Xs5xnhXdk7eIE1wiovWcY3K6+sThTPomLDzHW76rYR+GqCi6VQyiblEwBCyBZrJM0TAj1EA1lTZd
031+NyYun9dz6WwZM4N/ZZCTgpuXW7Od6yHr7kpKQLtgBEfDcrJ2ty7FDbeo/La2X6FJfeNDdki3
Aj6pKAttsyJuV9wWtJsP7LqK/+jBJHolnXZiXrf8Hdw4w6TqQZ3v+JOEcCXvGaIYqwb/uHdYgkLz
PiGRz2wDWn/99pI/ZnyvI+UUqtGTTrMk5E91IU+5MkcK3AFbCoqgY8oag+04hsBSmWVK+YMsNFd2
qQRHCKCMdySyXXB0bVsqXa13luZFTnGP6QDyLLZj/yrP+CXD8R5ze2uk4cRdv3qLNFOviDPyjsbL
RxmNl8qhkRTq9oHZZCiGhDzbiFx9FIgA4IHbBK8dPyl8lUEoqF2wZVfVMNFLe3AiupWyUm0+CHII
g7SGDzUN2a5fk8z2WD0nb5mQqY3XRSNj5cwaVFOgvxCmUlQW73iKOC/VRzcX/uPVl2MocicHnOyJ
B+PQQDH5pJTBdidvwbGJwZJhsXho2a2QU9I/xi1NRAsqZAI/D3TJe8g2Ivy/Yhzt1SmPm9EAAWrO
rXoINM+bPLeVe0aFfefJaJZdTqXOkVcOEQBe5oT02Z6n0iah8NNJ695nb5OUZZ5/YvDZRKxs2EUZ
Nc1q73ccpxq/b7Lx9gEPck9PQLI3pAt0yPIvFse1E9ibGaHbpcWohlj86kUQZy0CplNfPkOVTZrM
2dcQkvsGuoU0oO1N5XWTURTIg3qSDwQAYHBT6XeXHw6us7y/byow1F0M4nOFOc1q9AF4C3b4GKZs
wmdC635Ppowh3+plnleR+By9vPFimoU2lJOZBLnZ/jvWL16CI2DZRzvGHl3QmVtCFDeN6A/reEKk
ntjG+Sw13cIVhPwrznAfRke1jiW8Jb0L6lBSAguT2TnYFYCKS+U6si+1JLcfAfUwZf8BSV+ewFLu
hm3J6kETglUZ8YJC93RIqIT2rx2YiA1Kwa2odhv6c94aVHIDlPaC4Jtg1X3tn1IVA2cv9kSO5Uo5
04vAKMNayD3whd0ews3GFt89HTOL9c4Y3EMm09LtKYis09Fo+CM0cxBlEciRqb6GkiccsFLSsgzm
a/XUhlQOL+9yhGDECAiJMLBbTkKEix0kD3Ry7fYMbO5eIu0cLf+Ib6n6aaMuPZqiEUubHvvAK3JL
dQHNcmpS0295tjqo7RLMMEmeW6TvyrvUHO82K9b1fiCL8xFzifkrFp6fDLS4T0jf3KkLkkI9TpoE
DzLeoECtSFUJ7MgqqZhzFHIRfbyXu9jXDwek1sw9M6UCCg9wpRypK2yVPiuqO5aAkeV8gpliv7ET
VYk4Zp4UmEvt5s4BMEcXP2H4MAPzUDbawWedNKDtvnUc7jjY7S6U9CaOhLbjNcBz2Z4+CZfR9DJp
Wa08m0BTsx3tuJ2ncpPXGirSkHf1vfnaPNMMMF4jnU3xNZJ+hO/kBhV6nAHpqEYa1seG1+tcShQw
aOskJc1R6tSUFnp8iUgAWHLh7tCX3kzTWF0BPZgE8MEkIluezfXejNo7aD7PigFpjGF8by9VXH0K
PfYUEnFcgWYY7f61RurOIrVccFhcw5TrnOFr5gGnwq879RKgK1/NEnWE5qeqz+TpABuAz0jQvcXz
IlKYIAboZLW2Aiy0LxffY06Q414Q6DXXrtqsZ8uci7FEcTBHWmVuVgeYlr8HBDZd0AFdfuhqXHfU
kzdIoeU2+hXOFezWWRWzLXxubZMEXiNbsrxryBgPfkXpxkt1qONTdW37ez4XP9s+ahTEcd5I3CHz
Z/bQRnpvn0kR8kmYnGDBiBppoUACJGtk7PgeFzBZeFkX39+vEZZ+5wTKD2F09jfDaeVzTTiMYajA
1zGBUGrg5k6TmSkafcj857lajy+blpKR4Laly+r98TOu58uSP99C7VJgWcb3VcNVPivsYft5Dfcy
A+nL1BruGXxlcoNv8PyrkuY4rvFQYYOegvpe6sjDJjUm42xG1NyahIlBhIiMcnPDZ1xO9lLjVSDc
+y5eEC5d2/CMzn3qD+BpptQgR9rFsXzxapYCJUWRqNE0ME8gy+T4IElf2oBioynKU0afucX0TYcF
IAW+ajqbSnWB7CF/JRnFK6pZ6ofLVqFf7FsWQFuxLQIn4hl0yGcOZ8AQoJS4PBaBnLWnoSX3B8dY
8suH2kICa7BfvSm7iyucUpsWPKS1HQ2IZXw1T/3hQIj5fIwQUrKlnpqD+zOd/QFBrw/rzCySkgmE
sP/LQwHPw9OtJWI4b0IAz7DVwxb6+lUybaOAE0+8Ha4K7zUEcGzco12LOootZp41TF2IiFQJnktT
MqnXABhiwxBeWzYwNN8AvYfMMzw1UQJj3QOE8hK1iFQ=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
h9n9zuV5lMts7E8xcOwd5OEmBQQTWDUfOd1CCpJtcRNKaLNoUwHfGMhoPZ3WDIQ/m/MGtplKUoFx
i0ug5BLY2g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZAtlDW7Tx/YNYYE2jawvMMCW40921zRgvYomlY8wcRlNVBEsxE3apQL4IIwUk/r0NSl3FJUcJhGx
bQnpoTAX9Ea3Clu4koloRBtU2UrIb0exCd/DMK0iUTANkETqlKdRXQmfp4uhLE/Mwb1kY3UYzJ49
sjSxoyKm731gwTjgRUs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
zmahq0NBzWzSfB1lvTCKBHtcaT5fN4U5k3LSzpiyaronk8xbbzR0dP9ew/cCp7rP2xsweaYMIJwx
4tmNaS7SVhNupTu5LCXNmztcum/6LIM82sP+XQm5E7P0stmksBmyeSbapkfjB3tOjixv1ipZ9lRT
2jAX4EzvQPFwL1SCK/TmWrKTBIMU3eqF/utXUKRyj7DjUJ0x1aH9jKDC27lR7DlDP2SBEkOmgqcY
fTCK/5N/0X3p0e5mIiq2SvHWuPYbZ7BMT//QkpjRJU3GGQzTUnWlASUM6m7MfRJi+M+OFHeWmIB1
L8QJdkXfxFeLLQrNhvUzOnNIZLmBjvdfQ87R5A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WsmxTCG8DN8fztPhtVEIEPIJmz2GzQ5Wdg9bSDQl1VF3JlYnfBA+IyOkDekq95uPzD6xo0LmAdhN
45mP3q7RIMlQDqqjev5Ze2rMOTLhI8TWgOLrSla7VmvhnhO8tYwKCxVJUylQ4E7/oh8VrC7Nw3ew
p2dO5WqGm3u7Xcft7oU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
npmiJ2K+H/l4V7AAYSTOYU/3uFzD/iDh8KDcJ+ujzbpP1wELTkvl517j+UF8hq8Wy9Jlc7X49HWY
t4VpDPll3CSI+Ftj1wtWAwLuDCoHBFLyHJPwcRoy6IeCNPyfibFC6V2Uo5iXcC4P779DwMxlxxky
0XNIlA5nWPpVtuz85emt2UvJ1pAyXLeevu9blapiJGoIha8GQrB8wyqkPvvKT9MI6pSyZ1GtGhUX
fUxqKljAZGqWzTtg2PAxwy0F19VQSW/vc/hbOa+wNtsrL69a4qy8LeaRMY2No8kIjF5gTCchKrZ6
GxMPIk/mE4d4hLlcMFX5ZGeyNa0b/a8KsPdd3A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
oOvEnJ/GqdI/mBAktuImzUEao7fJyx2acDaKqLRNaxqMfuEg0PFVjg4IPVvWkNQXn4wEaq01cfJ0
dykKujaQ943VfNYnxtBaq7tSOPbfT3cm2hOm4vONVfKfNDg2uWW1rtrYZmHa9JK1qx33EI/v8TLt
zjabOEP49gM99I8a5F7hsWisbSXjJ4jEDc2Ic+VfjtTjwKXZhkmPGFd8Q0WQa8CRNxxSjITveso1
5opJKiUzUESVmOL1vxfj7lkIcNmvOndKKWS3CvL5MsfRSZZWb4/JPTKCuhheFTxajgWZ/xiNehO4
JyDkWW335v3Ycu6Z7mHC4uPzBJL17zW1ce7zGsuVcyFCAzSg/Xsuq5g6T77ZkTo/jfeBbtVvnyV5
0nQim3L5U6B2/OXkPFPclas7oo5pHeoOWx4dgq+p+5B3KkAXnb/ydE5nYSpu9jt1v5VcG7S391Dh
6HyTbIXma1lAWOnmycEdxoQ13Aekc+YcxJ/KQlX0JQNE0R9Jx+ElcmyCAhxP+wBT7KFmxRlbaSXy
k+IaTcwm1cIUTQOqCKg05ELIBOpKfTsa9ZYFG6I/M+ktpcVrzbwErpfzVGhCGc6Qzfln+nWdnymt
4Xn7K+efHnyOKHuNIqeZjJUZEi7NVYFKGdZCz2T6YtiQ3chmQB2pCOpoSrYgtFLbAYy5q4jfhHEM
8wknAMRATQqLwDK+g55EYamIVomMzE/C6M+Fc1Tu4G7SfQcW0ovIdNsYEFd2whiqlPw8oerXbxDT
0otiW3S5Q5YiidZNkROuOshX8JrxX8eAWP/HNiYgU8bf6nOmjESDtz/NebC/D5/ejbuJ8tnATTFi
vGW43Pr7lNaAgTVeVucxTI/JtuBz8hxcX3RCddI67DKOMR9RY2CIjFgid1z7RA6ETpdPQkB2lFKq
yYB3GaMhNXr8ryC11xgsE9xdkZd2ziQ2xnxGM02+Sji4BkZIewXf2OZVt7JbweoZBAlxH5HUNdkB
UFSdt9Je0Xa4dX0umh8yLSZC4ash7XyBu4vr/+O8RbmwIiczUW2uzlzrRDOAQenpaQ8Ydt9OPZbM
8Uhq/QErtedF0zDjJNxz0Jdpz8sBSHmx8HSaTQXjThmlQQkaDy2jSpu8Oeh+twAsBtBpFJD9gnh2
hA8UeMiV/nqniCIbpNztZcsJATA003/mePLQzU2xNs1JHQ5beKRSLTWQa/3hswNL7oKTWHtJXvyc
HTA6ax4/lbdnLRqE1gr/WjkCnY+HZhWvUlhQkv9O6lq9Ku6THkBP3qO04kX58T0H5u/Zvfea/5bP
ICJ21L12jfAwb/dbFI//fMJsPUa9Yxhcx8ClwLTXapMnzuqgKJsv0x5T/P5ERa4tTiC4dRfaihA3
pnLLiGbuLJF9+1+kpqcwZ4JH4iMuuuX+PYFvtnPI6b5Gv3o2HnhTpHEofoko60Az02bXlzdcn34O
7mmuOAwCT5gfza9pvoD+QnEgA82AM/ZEHIDA9NPlr9nipk75y3skHQkXx4F45EDbQXSMN0XN4G7p
CvBobcUoFCFQkL6GGDCSvz0ezHwrj75QdMZ5pLTPtn2MUklXDGuS/VHl/fpQ6/4PH1IkLKgmQ87K
0N9cQM9SIyVFRDMw7HbjmhI+FbDyqKHSTNxLzVfuX81bvc4Op+gRZUg6iQYHYjuFLKx9RoOz/jZ7
nNRIwN6FDaH1gbhvDILmRHpjGmi1QiJOHQcU/cVQEDe3/nZwAGRZlLCeH50mQegkkoS/2rD7xDxP
Ji5+CsrJNdVQ93e8eBHwZTgBwOc4xSJe7o5iilamnXry81OvuiunaeawYyTv20mDgN8+ZDmugOYH
R0IKRLALek7I9BqhbI4aIPwm47zSZzF26GtTRUmF1kEfIaTkFADEIYNOuNyD/4Rj8YfiktAw+arN
dsLD1dKVlRTAho6lKZwVLGp8mcluvWJ4AryOfJ6T82XbGWe/QSZNxLwKhYgYP1pDPW18kVHjdu18
NLq/TngSvoFWwxmexXXhSkCi7UlrC4Vqid15U9mJsQu7dgrAcArSB8D7T8Xc9sqbZs833Y31GsLc
7IgtVvQ1A8JzPSXpO1fuOhY60nwg9M/3KKkOEmGaedehH8aUA4eB0qGpmrz5OY39RR0imzCtNte4
ku5rIMeATGA2UbGqgZviQsFW0uJ5Xdl6fyJIlG76G9XwClIw2I+HYt9PnRTEqYpJfUCIGAzQ3p7b
8YA306ysBvHNEyIlCf6082AJnVVwrdAjdNW8o+YQn/JUawh5AfGsdUPPB60+yCACnpRC1YGLWAir
m6TMPg5l7QKTx/O4Bx7UoBr55L3QJMSJOm86hTl60zGE7UPkjHN92KOQmxYRldExMCAIG26tzZ86
AopIJWRGj2+0GUzJ648y5p1eotUygxrK+M0nXfQffWCX4h0vG4pmZ4K445BlzEFZ/j/DjK5iwcDV
h2ZhWNSXXVG3CNJX1aGna2vHqTnKbhCc0g0a9WqCr2z6QlNpT7axOoiYh0+ZSYGs26J0+8buG1sq
eHHA1Vs8JZ1cPDM3eM1oYHN0OO3ISKKEwH4UE8fNqwgIwqgOHkpaK6E0qm4SxgdmwVhRkNNkUKeG
WUgHIvEagwDWqUC5erlHAVC+8TwczhmJj8kI/SXCHeR40q3tsI8MfYfeJWMBHB1biON2oDaLyUmY
2ZOVZ7OeNot6LU1JO+NWBiNVu10wwO11yH08cRySslMc5koktZBwiUf9jAMq/xJxyYJUpdoJdJci
DoBnTpLX4K5qUmKZ1mPx7sIWhyVDlMVG750vsQZ4PJzjFP0ubi9ycaxW0ucVvTgSqw5Zqjdse0+C
Hjrp2WHLC5k8tGe32jF4mjezTd2LnUmYpLd++l6W0F/+0JJtdlCozR0sKZfsBHEND9al6RH+TCpb
hFCzDhZb5s93ubDmq9bLc0B70KvIuW3woHLzKlAzcvcCp0S6YQWQRE6BL5vApebKJwlsrY8LrlaD
YobN87XShGLVb65SEJbzJ4m97nJjZQKi3QMhJk04Lv5ZL3KSVydQgzKqi+NVdmHSZuUxiaFj5vIx
QFQ+tJviyumV7/fjVF0DPficxkdPvKhY5/vt4oBsT1oj4VQ8caAzihxriqafX/lQC0gYT9TQ8Rhb
gFzL31Hp8thM5RBPuVXEe9lBmnECmUeO7TOCgZj/0Ya9NKP9GH2LsMSQwrhxMmdjy5s6PtTQhElx
+2u6Gyrejzd70TGuxN9+SkKqHiUp66m7/lSyucJYm4zQ/uPD5H2L99tPqeQLbIXm4yK7q0qT95bw
klKI4pAVCTGRhtxEaZZLg6WRXTto/o3reo3KjW1xMcAgKwXjiOJm2zmVuw52Of+mjAQ8q7mhCcX9
xVRlQeoBAtrIy9M8R3iILsHJfvlNQqdVokeLnTsEyGtFcWsdnfqeeDUERI3vjKVuk7nhFv/4NLTB
KJ1WIzfZ1TqXm7VK+WynzzV8U2mBsebakjE4bFdOiR/eWto6rOEWHUnjddz8hvgQteYhkt4kQue/
EtEEsdVMzNKaPdUuVzM6DYpsKjczV4QQTI8/vxAZ1Gda0pDIDFe++Ga6y2vLn7rRT78hRGQ2i1Mf
2uuWljrxhTARlBsEioVFoK7LwqpezWLw7ICaawKEwRamQFPftQaXkW+jOGAVVY2a3r8d/fnwBHRs
RptIGic1qFXNDxe7NvgJIFev7OELHnLUc18x9R2Hm28S8VwCXdpkGcn71gkvmoDbesyWL4DyJguR
NLNWjedBQEzTyd4MUpFXrHW2iexH5wd2qrkY3I72MiyNNDpydmGcahUmrCRoNRxmEGAzoqJcG0X+
myQKqAASz2JQQCRbp0o08/g3M79nUkC39MNQ5JWB4dCslihPNbz3shGBhTbP2mBtptZgSqvQ0tm+
3S7WGMme75surxuoLPKh3zbpYV2rw/nUA7bkkh/R0dApbXbRR6KNfzXVe5NdS+vyg5er0tZo5bq/
HymENQdJal7OhTuS9dRlwoGLuCEagiW6PiRWKCsuYRKrj2ISjiamCWcdMU5/etlZIqPdMJ9rjn8L
uxWlWIACq/dJ2VDUHoGT44TC9JxZHXrnDa4l003eYSM3ZbN2VQ6vZnQ6+MftjwaiUePWW2iEQ8+S
APlSUgt77wO/RcUQL7qBE6t2iAw2fTL3N5Fi11qqUZJyMHx4i4ufbbHVk0epElJfACwjF9IyWJHd
uSs/c1oM65KO/oVMoo78K/SI9Vya8bSGpYfT4NdIVMfH+T/Fg8lAY423/35rsAUT9MYr9C/p5yyz
SL2R8pn4Ol2O0SXC8cRUrfZMbj9PhxpnNNG7VYU8kG9BoSM+lYK966vLWy1fxMKFahVZaS4ZEAIe
wTUZJoLHyuKYNFYATNA0rh8qe24DuDgrmfcMLjZeTunRNWYCB9EW58NMLUyayg0ME2oh7wwiEsDa
SFYSrgID5DjnFiQMZfi5bhCWh5ttBhpILA1UHF0SjyvEilD1163DnoUC9cMGswrA0Vrj1mKWGJ6i
TMc7kK5XBZLzoc4V0k61/gSxZKZmNCG1VTweFaYmgb6LeRuBEJIDSeJC3HJ+GBWdOIho4JdVjRon
Mjem3cwj3QVjo9532EdBQwCqgXuhPdZ9vLVNyMT4+Wwg+PB0huTLoObpZvqpsacShO4ukPTo+fng
ZKpOoNWvEU+VB5OD+gj9Uqw1wX5FbHEUUq0AKH8c4ShTNNHQEN70CFdjoS6EO6DUI/Yl+m004GIq
MRfgup4gImqdpiw+ivoodtPt9pe5bqDuwXUusoyj9U9+iNn15yz7NnF2b+WWK1XLOjNlpal5Vfns
+dmG8S2SqnQZQG/ecq+OQHh2dnanlhuexMKHjy9CpDrYqYeJpep+DPjITEASosQAWQoAVrNEXtB+
+0sJMORm3LvxxR83+XF0mBGAUqIdlKoDgtkyfJOZNfIaskkdSOF4A7mEVyekH4QtbytvwPbwXWKk
LxG8TrFPh8YMZNCKlZv4V+yR6jfoNc/RKPgpsnScEwpOKun4FirjN+3U5nkvpSvY1hGWqMrsKBRE
sOcW4pq6ao5vycHZ5MOPTjwdQEwtPHiMa0ld5iW4TzjQlaty3Ta84brnTjYSOE29nZtF1WaCYIEb
rp+5ehfOGKkw7OjNVEw1SVw2rCqG64v1p0et3cwvGTtteF7LHeL//3eCRm0f78YKKuIx5sV3wOgB
L3pkxe4QNzXOGg0a0X4gUppt4/PPDIjKHg5KpRrdF5NbNIesiRv1uWSkWOPrtJs4RD4+qcPPlWsB
lQ/do/k2h8xyFnLQ3HMl5Pu2ZghcLvMs2jCsR4Lq1d8jKJn6vorOaPPXpvSZQQG1dzekwAIJPv1D
Ae3ml5E83i6tuiGnzMeBKeZMSriGBkyTsUoJtHnM4r5wq4gCr/63jW4eHE0ZDdRA9XtY4SUayo0C
SKjtOnI8DFIOqgqkW2OlZF6Qpo4aA/7mc5CjReh34IxHOay49NBivRnS8D2lDrDv60evVqi9m0Az
sCNBy9UsIPDouDwmdW9azFeKuWxO0uczlp0bOzJsjn53xKmryyyHjL9ANc+IA26ud0f00RPaWf+L
XNJ8xvSx+241WOkTsm8AEwqIORS5UZfQsmnBMfwUmW5C7LjWmDxShizvUeHNN+kV72iWhdxHhdSp
hohDdClXcTXAa4s8VYcuURR0Wq7v1avORB+ADDV2grkTZ98OOztQ5hAoMlx2jImBoahTtDgHiVNX
8P+vGmZi5JS2hhIY0St2vY3MAjk3vQyYyl9CRBCT2+I59A3t2y3e/04OPtuN+Ds1PrvqU94o4Evj
sik1rPrSUIAEJ4hbfhwfNX10KXQoE7BsNBJXjLpuMYvMxA8aQHXdhAn/pU0VpsywBVclwBGdXZCp
nhm23wco1uKx2vviuqxR1gTu3AS3SzP8vE3jcIENH7FnSUHUuVYNZEru2YPKFSYZ5BQCQdMyua1H
s0RBFTeb7GZQlh1Ni2vjaOfv2MaFXKi0mZAHRoFkAp0vxxlB5FhOXpTZlyj/NBVQScyLJ2cKK+ZP
+Ysq+hLIKJafWSUAt8c1oMtsTdBvlYe6gJF9+DcyGVdQ6A8pIB353zTghiDkWNwkaZhG6n4oCkWE
mKVa4NRINkmS63bZy/LHwtuPqQ+InAia3hUKgqIHFuq6z+fiy0J77E74urYh4spHUBzNWpPDB/YN
ZGM9LPJKpJ6dhyloHtEgXD+wm6sX1POkpvvyqnM9p9CxYaFmEjilPM7BdiUNBBWFn3SW0caWkWQP
H2oCbRjnTQ1R/F90Efy84Z1zsAUhZxOtd7qlYH9aBEuZp+qZeGitzcV5G2CG3FDBZ+Ibmk/DGiNW
79iF+coXVU8IW+N4lOoZN0U+LTpguYmg6UTsXsjPU6i7kI7qMAmrH6Kxxo4Pbiu6crl4IHl3qugU
3Od51347rQ6SnLt1PTNeVau1LB6oO2YgSRUp4c0kID1CiHlBnSLW+J2p+67WwB0YVcpJxwd35WjU
fxLvgtkjmUo0c2E3yICLMgJdtc5PzW4VdryXu7gz2O0uqoje3VJSyub64Lkn3YDBRkJ+BsGSITjx
0jplK7L69ZcVP/kkc5a1gFaeXlW+bXWGEBMI0wljfd7h/o5Ztz2KKjSIXzd85LVDT648K5526MTV
gdj+cfVwql/CwUZxkKpRlofR8un3B+gIThmHABcnlih85cVQYtEgROjEn6grKQrOZOoDPZZX1At/
Ds0X3YJYHVCVDzWIx9wTrqdMpme0QbxzcmvW0LwoAbJ0wcF7egf1tVF2WyWzPVlDHsD/sqIM7Rf9
rLhY23CFA/e120Wed9+LKLGaVIoGkQ0lB9U1iKAwDni7mb7lVDidQCFy6eX1k6F7cN6kZOPuYyy/
wl7zVoXjtjUmNAfxPKGgy1/ZXsvb43T5XvRUFzM/3qRpZf7iFNJG69MrnCU0RBkFqEYVwWb+rn3I
dtp8lmcDQRu1+/FxRqhMzWjd+3nbpP8166kvFO6cU9Hhej4uCEskz5xsTA6hRYOu+AZZYo1v7OHP
oKCpeUzq6TOcOdR+qHIW7YecNC8LQD3BUbY/FYdSbBT6Yuog8p5tzrECHGEd7+NqSuQwvJfHqlNd
eWgy/o8NUYgxAIFmaMfWdtMS1aLXMhW14o4CI8ghvi7acM58ZTOk89MEXmgVPdFpJbp/HQ/3uDoY
b9bfzFN6drzZvQ984GQSByNq8Zn6S9JuaNmIyvTL40SEL9D/ytvMVA8F2ZL2jCQuG1R8ukhoOqnl
QphQaiQeocalDIOt0I+6sHBK1or+nV49lbi14TQY++bquwEfW7qZPQ019uBvbjde/CLPf02WvMVS
+oxoQNQ3zv4S/wFhLbIEWbrePShZ0VLHTKmkFtTbuvcIaQLTHqF1oix/1xI6e1+CmPxQEmqAV1W+
aDtKICNrZCJMcIgGxNWhXdd+8u29nobOsFtAXzspqaLfGWadnVUE87gpWKPVoRBCC02eYNaUj++I
RtUS3Qtp2OjnQ5fEb2pNJ9E1iOhVCCyUDEiYQjOrgBefn1zPD6fZRYfIho+fgk64axrWCewiZhVM
ZsaR6kNvFospo4T0AufeVyzz2AhSTDyapDGgst2PCuGd1VnT2WYSYW7DbWx/snA7Fmo8HxUgg+H6
pthaOeVZ+nTRPUcv7ca/3gvKymwCNP+awemiKiZ4t+ZXyjeDctT0h+mmlcT/JPFLu9V//FhWKI+r
kwKRniPufZxRrP9ylwg+NqK2dbna1w0CKrJJG+FHXssRg/UVQyQwcS4G6G2XT6syfBs6u77ybEZI
yLT3aqeSK8DDdqjDo3M2dy6hEd1LdjKSw3jy4bAN4p7vc88aXquHg/W5zu1NG075KsL8za8nj7lw
GfqsGnSFgUBVZltMDj4+gsjEykwF6mdyKorWHo1U71qBvCuR0CJwJr74VlrXDJlXcNGOgjmbTwqa
gWJhLbVfEZ5E2bLGWqtVbNezWZGuJzCFk4gyFcoq/MiIWtUVu4ezm6IV2TBDSS1vweSWoySHZxuO
7Lu8iSlCULBrckTXL/MEh1U7wJD9diTqb1p6/LuZsvXlmVgXS0ckdmmR6M3lqu2jETITuahgQ5hz
UwA1w29zUtnTI2zz7S5imY88ayteApKkN0oAsMBwEXJLe1W4eB5j62moNFs5Px3TkhIDru2Kn+dv
jCkoo2nbo8J6MxNwblnddyu0IFxaPzbnRBXVd4JreR/HR7BqJw8X8WeweEVK6fLPW8oYYylcGvGO
2ChR+kIG+wwvDduDiw13qjaK2cAtXZQPEqiI1+ZUl1ut0jPh4D0ShxqiGg242UY3gpRJbPbiz3I9
AZK6jsC0S2AI8sKtl8OZnQ6YE98QRGLk5pW71CZBT//5L6JSNKbjQzSeiGmpx9+xN8goEZnvpLnw
MHfE1L7BZuFM77PR3YygOMJxPTZ3u/oqz4XULraoz/aCzH0nMgHFg/VV5YcoHN3772+1XQhAGpk/
ZkMaz9e9wiPriQVxTaNCEdMsgX6rYRPeIp/Fwz3Z56pQzTw0nlFmEbvKRqKiGN/Tjz6+ov8QHo0U
ZL91OkKEcBperXv5Z14WlkUo+LICQJIXvcLrH9ytizAgV9bkHVZewCMk0kk1GQEVu/iqbG71IHQu
M4Ysav5/PZ1EUY2GcI7luz54EhvXhxPSfntkD+GLZfuwuhEWaJJwqDm90N/+RNPuF/KGpJV8p0EE
tcnC1PfS+0SurJMpNgNAB3JY8O1TuI0CYrMPIkY+4IVOBEc3NtCcHOmeOjpIPXmgFdpk5DVV2MyY
gkqlPfpMwC2W0pFmQC+HGbMOpyYkUJ16HtSUSBrpBQwZssl0oTxGv4sh46pPLPY5LlH1knRPfLbr
WfICyIvMRrut9SKFfdGbzCxqpkMurWQG2AuXjE4Ly8XyUHVauhdxNVSx2uGLDVCW0eOjZHgVQZk2
5L0F1BA3ZlheGmO6O7xn6kaht6Gxmty/heB6f2TplsWIzQJ1sJ99e63DJZ85GDK8bgkZL6AGyUmy
HWNkRY11Zjw3i6H/kfZQQ7BkJsIr+OVVdCLmUIMzysBkyfMgSqOd30D+ps+D7cZFpe84S8Sk/hbk
tT1WrB/StZV0BIoo/4uyz/FFmfATBB3fpLDXcARqcbPRugE2OqOZV0FNtcGeao5z4MsTc9EusMob
Hl24ftk3A44rdwK1l78hJMhQz61ezGqIaxyh9BX7VLqN7G25E2HCMIdFLCSK9DPaHqdUhvd2B+mu
53jaxSZ2b2lldIW+RorQmhLsaPU8/MX1+LAulDjRxk4R17l84rVjhQxLLXTiSC9+2dJL3VDVzHeB
V0djUtGfqProI+0SQBG7H6DuGz2vkadPexoteYC+LuVtzuyi9n6YN3kva9bqSdWJD81Ycu/3jNeO
0cQMZ+H8/MVuTy0/dS8YWtD0dgFX2lYGNDWTqA7TCJpUwPTZaBFf2djYsSdaw9xCMJK6nihHSRbS
2gDruxkiGtDY13BAqZ1XH3i/P89QUYSkzmKSfVxPNT7FypmQb8hHUDCMV+CTma++RUtdUyU/PpC/
svAsRb8kl5mwg5Uw5JaGcQnqas0QnpDKD3gM6h6GdnJ6YXdO/Vhmf5617+xW/BY8IHioSiC9+MCx
Ymp0X3MB7Qv8BZs1oA5zCdB6Vc67ZA13TiRYx68iTjshnpH6NyssA760UCTwDP+8fWD+ntYze4w9
UgcsFa0S8NLDhDzG0DCzk7cusxLITLUrl1YpFVTUG4p1Un/EV/EBY2jzB7qBsxS8MFC98vpk//fB
cs55BuM8boyTaDpzC3j8cAW96e3on53MEpVtCXBXuqbRENN2ajRDBndo1143Zg9UsA8SAtzdIIHD
VlRQpcaXWaHm9OSwXD0VSN7HG4F8lpy/CNVvCGPFIht5aH1LYjw7Bj6+0rlC0h2cDa22f0hPdyIw
GrV/rZmmW7c9ilCwMoKzAbEWQEnyIQxEFEpYz4cFN6BV+8CA3iZ17x6GLWcv0i5zW+6Xridk93w3
Oh/t9b2vRUaVE338vvPf3wqRSzsOyANWBuJEJ47LTSQTVJh7dqeHaEZmPekaIS+OtoJULZBukT6H
SKnj+3SPrVEDJZEql1sghPB4c46qNPOJQvyh3GQJVOrjD+TaDD8A+loqOkudQPS83stmZuqDSIjl
v+iFmNgWyQYK6Djz6/fGVcQZAVMWfVe7XMt2koD29tHfxSQT3oTF2Aw348Y2oC2SY2rLy1Cza1eY
OTi/eYTbeMtM/hq5ucqNfOE5nADvL4SjAEr0WgM+fBKT5TGUjL87Wgw6DQS48UKlDUV6LWnVj/GH
Y03Fq+rEWyRd/ys8SfR61RIaX995b9RX5DezYTaKP7YRk125yekIDSLT6MNE3MRzelwu/Wd2UGZr
BE4MQKVuSlfs67Jy3ixijvZ2GXlIzHecAeYjh7yEdiEryO6cTyRLPabKivtyzba3yOJu1myqcdKV
B1E42v2Ehz72/fe34/5BzDET54GZr9yOhRFHJCWL+LCT5ViYTSyyrYZmFtCvdTVEo2d8RvRJqVi8
g/2eCDG4rSUboBE5BoPqkm85BvTgCFgGJB/aguxzp1mZzC1W+x6hAfL0cuIL2KsXh+s2x/ULo9mW
l79nn7YNRuWfOIHOwjjYIYrFV7cjVptg4T1kK3g7nuuEcCRvEUivkIiuns2w6NZq4lGrc3XZEwv8
ZxTZ/Qy+NXMA/FgR2COWKDEuvAutTUpWkAo5EBpmMENkPL9p8YyZtAGU4BZUd2WXimIk2DlsGP1g
AFX0Lnt0/YiFfJlm6+IpKnwG6Lv48bVjD8s8OnYQLRm8Vhdn2UFHeZZdKCYxmKVEvbE4PDWqH059
KDENkT+yzerIund+DHfmE4BSQLy7PRDG2o8ywu0GynxL2if89EBPHC47MAvAMQnItPWJ+steMIE3
mHNAOPaJsTbucJMFLRGLmxVvncL+dSv47otxdi7IOZlz88DjOlM2tbbVAEYpOEQvNDw15w79RW4s
12/Pn96Wd+vJvippM9VBaURMKTWtZUOPiRqMBLxuTzBg13UbnJ3na3R0hyo07l+O+eA9T37OImcM
Pp0BS8aUmjoNVjFg1rUaCLUocvtOcVvhvOm3oY4d2Acu6sB/jZIdFslHuMmbBveLo9lHq/hg+2VS
6fHlGMlfy/j8TROEjWxwpvU7xB+f72M55/0re+DqngAeVPj6f+utmI53YsAfMOFfCONGakG4HJG2
WH7AknRwGNeEHGcPeFz2UfU4BOG4dFAqODrIJMsQRDroR0NvvXLB+s/I8UNBxK7Ruqz+ATpMibyF
B2aKEum1MtxmGwPuPVJivXWjkOjDbGzR7kz4yeW7VWMSp/C7efsv1N6wUpq2H4uPWcQrIayWk4nW
2U8Oo7F+dUMqiUDolc7W2Bc7kJBHFE2PGhgKO/416/BWWuo1tQeL4ZcKLFn4qX+50GRFTNTiNsM9
YvodwmEsT4u1BiWj8SPafwxkDclNmx4F5KlTgQu17BdBzWjS1kV4XJhb87Q7+n+aCuu+d+MdBPG5
hIdXwuAWArUPwolJC0J6FW/ZPKyvrrtCejlXV8+/bINhhvNI3w9ODkS19djHcysms9nbTXL+8tvG
4iWJtKRurSDbFwFd4YDEheyEfN8qz+uBEPwqPIzlFavOHugijjwiULwnhr5jlgqelvVD2CsKsn+h
O2biBWIlcugODe0Jxjv/M2d0+yKQO5XznHXn8Pca/aWnmQqxsLmzvAA9TgAfk+QiWLyVoG2+2Pe2
zYh2m855jiRnjCFUYqUilSLq/70LQ5157T8W+q/R5CffQp1qJ7ZM9PYObapqiJ4Gpq0AhdmPCPQg
Hik+WsQsWTA7Q8PkXjFLOevK1p8fMo+0GUQrqb/daVT/4buqwkg+kGDcJ9W5jQPLsDa6H5qE/+Ca
W9bTb6wlVpO62Xfdg0mqm7xBiDiBVZ81VmhYfeNEF8Go7C4N5YORHHpu3KyrOzQFVh3My0lPSTBy
OCmlFsrDTJzIacLT2mIWCkWSUsrEKo3FomjSC/MDamukkxfo7JZ0ThJ0N15C0EGATfLNKqGPJGTF
m9xKHl1s+pXRbVgdKhDpF3s3sJqiJqIky8tuPp56hE8pG0clEHIQwm9fE9Yzbj5RbI+jrA/Mfb19
jeqsMpvG5boLDjMVCN/fQ4t0iyr9aK/F/yeewTI/RsunvYSjSbCiLi++MDkeMtTCr1bfNzvzFDPh
Os7ZPy/bqeWKYYrhBT/S/xQCMJLiIiLEXhNFGHtv5wU8eiC2pHdbi6AoXRzyYWVFHkQ3nE0IeWB5
Q45nz5GAWhDS05cg7OAIEtESzTa+8VGLN97dXg2QJMv/cQ22Elm2Sx4XfqnlkM0sxF+Cm6h/nGDr
aXEdasDB80n0tEpmskhjBVvZgE9zXsJJwkoCZ9QUdoBtk5TDiFhemjwzcUZATFNeQbFcXZTdG1bi
WIdSTuX/qSgCidJvv7hBPMNCFttAtHjjTIe1k3c2D0zzzRsXcLXIJMDyRH+tpyvZh/NAXIQqm8bX
48g0G6iMt0lQkYBs90BJgIdgLkRW5Ciua4qrcbgwSvOw8beDwyUtbT4yUpT1ks3EIcEm/v4poD/T
Bu7gNs7pNAcvS4y2gAIqmCeBOCzD2VMrIRoUT7/flzbN93crPs7mRAU3k+DEhHScmIMOLtTaytxJ
COQmpoCC9rbu3OJ9PrVjfBe0Wkv72er0topLjok2VpHgwloTQbV21ghjXE+ki24WP/9IPdwk+fOt
4U3cLZGtTlTu4L5oOe2S/ekfmQqigE5wD+YawYkpDm8Fci2AwYpqC893xaJ+LNclRunkhAvXrDsv
fUF50Tk5O5gR4cp8v/VbdYYJP3uMYONeuBA+VFEVe7NVSER+/uBw7j6UnrJfdItASGhmJ8VNpUVM
Ufr3Z4TPFkhxKoE0P70pW53f4MBVIxTmbQ5sMwYVbdv5KGSIbSwwGjPt6l84yTHrPndwA2EHTpM1
7HWZ8QJtiFY364omzkrIoYGihPj5u/Oy9wbYzdgBF6W2cxKsNDQaEGZzC5TmocGn5xLVn2+3E3u8
BwIxKgKeVaedfxb1X16lQDWJaoPgh8ONMwtXvrGr/2we8pbGQKasWiXNHO1V71CkYCbUhsWzNvaN
ChOpG85ws67XPHNZKYYs1GqlmRHDu2TCHxwD2pr+cpqBs19IpiB56ZFw6b5Ou1fQvrEOmY4U62DE
YHdS+6TF4Xv3wfp+eryV0V9KDbl7PJxwMVMh6ySOYGJZzG23DV+YAaY5y4EzJXJlRX7NYdScGcaV
DUoeD/U+JRZvHHPlHiIzo2JfwPO09uW0J+gxEGk9BuFnn+Ve3+jleWBAPtIAo0UZkDGOWlDsLQKH
b1Kb2LZI0xVxt0GnJGtPuZawOTdt9Vg4PXm2bjeXdFqqbbSyy7ZAg43JCNhjxiRc0UVgpSefSyaj
5LerS3x6OZC+xLc3EOKyY1Z582k7psNJ+AanJk03/B8mL3LW3/c9XHceUXbJRfaGr1hH7Ge9s0q4
Xs5xnhXdk7eIE1wiovWcY3K6+sThTPomLDzHW76rYR+GqCi6VQyiblEwBCyBZrJM0TAj1EA1lTZd
031+NyYun9dz6WwZM4N/ZZCTgpuXW7Od6yHr7kpKQLtgBEfDcrJ2ty7FDbeo/La2X6FJfeNDdki3
Aj6pKAttsyJuV9wWtJsP7LqK/+jBJHolnXZiXrf8Hdw4w6TqQZ3v+JOEcCXvGaIYqwb/uHdYgkLz
PiGRz2wDWn/99pI/ZnyvI+UUqtGTTrMk5E91IU+5MkcK3AFbCoqgY8oag+04hsBSmWVK+YMsNFd2
qQRHCKCMdySyXXB0bVsqXa13luZFTnGP6QDyLLZj/yrP+CXD8R5ze2uk4cRdv3qLNFOviDPyjsbL
RxmNl8qhkRTq9oHZZCiGhDzbiFx9FIgA4IHbBK8dPyl8lUEoqF2wZVfVMNFLe3AiupWyUm0+CHII
g7SGDzUN2a5fk8z2WD0nb5mQqY3XRSNj5cwaVFOgvxCmUlQW73iKOC/VRzcX/uPVl2MocicHnOyJ
B+PQQDH5pJTBdidvwbGJwZJhsXho2a2QU9I/xi1NRAsqZAI/D3TJe8g2Ivy/Yhzt1SmPm9EAAWrO
rXoINM+bPLeVe0aFfefJaJZdTqXOkVcOEQBe5oT02Z6n0iah8NNJ695nb5OUZZ5/YvDZRKxs2EUZ
Nc1q73ccpxq/b7Lx9gEPck9PQLI3pAt0yPIvFse1E9ibGaHbpcWohlj86kUQZy0CplNfPkOVTZrM
2dcQkvsGuoU0oO1N5XWTURTIg3qSDwQAYHBT6XeXHw6us7y/byow1F0M4nOFOc1q9AF4C3b4GKZs
wmdC635Ppowh3+plnleR+By9vPFimoU2lJOZBLnZ/jvWL16CI2DZRzvGHl3QmVtCFDeN6A/reEKk
ntjG+Sw13cIVhPwrznAfRke1jiW8Jb0L6lBSAguT2TnYFYCKS+U6si+1JLcfAfUwZf8BSV+ewFLu
hm3J6kETglUZ8YJC93RIqIT2rx2YiA1Kwa2odhv6c94aVHIDlPaC4Jtg1X3tn1IVA2cv9kSO5Uo5
04vAKMNayD3whd0ews3GFt89HTOL9c4Y3EMm09LtKYis09Fo+CM0cxBlEciRqb6GkiccsFLSsgzm
a/XUhlQOL+9yhGDECAiJMLBbTkKEix0kD3Ry7fYMbO5eIu0cLf+Ib6n6aaMuPZqiEUubHvvAK3JL
dQHNcmpS0295tjqo7RLMMEmeW6TvyrvUHO82K9b1fiCL8xFzifkrFp6fDLS4T0jf3KkLkkI9TpoE
DzLeoECtSFUJ7MgqqZhzFHIRfbyXu9jXDwek1sw9M6UCCg9wpRypK2yVPiuqO5aAkeV8gpliv7ET
VYk4Zp4UmEvt5s4BMEcXP2H4MAPzUDbawWedNKDtvnUc7jjY7S6U9CaOhLbjNcBz2Z4+CZfR9DJp
Wa08m0BTsx3tuJ2ncpPXGirSkHf1vfnaPNMMMF4jnU3xNZJ+hO/kBhV6nAHpqEYa1seG1+tcShQw
aOskJc1R6tSUFnp8iUgAWHLh7tCX3kzTWF0BPZgE8MEkIluezfXejNo7aD7PigFpjGF8by9VXH0K
PfYUEnFcgWYY7f61RurOIrVccFhcw5TrnOFr5gGnwq879RKgK1/NEnWE5qeqz+TpABuAz0jQvcXz
IlKYIAboZLW2Aiy0LxffY06Q414Q6DXXrtqsZ8uci7FEcTBHWmVuVgeYlr8HBDZd0AFdfuhqXHfU
kzdIoeU2+hXOFezWWRWzLXxubZMEXiNbsrxryBgPfkXpxkt1qONTdW37ez4XP9s+ahTEcd5I3CHz
Z/bQRnpvn0kR8kmYnGDBiBppoUACJGtk7PgeFzBZeFkX39+vEZZ+5wTKD2F09jfDaeVzTTiMYajA
1zGBUGrg5k6TmSkafcj857lajy+blpKR4Laly+r98TOu58uSP99C7VJgWcb3VcNVPivsYft5Dfcy
A+nL1BruGXxlcoNv8PyrkuY4rvFQYYOegvpe6sjDJjUm42xG1NyahIlBhIiMcnPDZ1xO9lLjVSDc
+y5eEC5d2/CMzn3qD+BpptQgR9rFsXzxapYCJUWRqNE0ME8gy+T4IElf2oBioynKU0afucX0TYcF
IAW+ajqbSnWB7CF/JRnFK6pZ6ofLVqFf7FsWQFuxLQIn4hl0yGcOZ8AQoJS4PBaBnLWnoSX3B8dY
8suH2kICa7BfvSm7iyucUpsWPKS1HQ2IZXw1T/3hQIj5fIwQUrKlnpqD+zOd/QFBrw/rzCySkgmE
sP/LQwHPw9OtJWI4b0IAz7DVwxb6+lUybaOAE0+8Ha4K7zUEcGzco12LOootZp41TF2IiFQJnktT
MqnXABhiwxBeWzYwNN8AvYfMMzw1UQJj3QOE8hK1iFQ=
`protect end_protected
|
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_multiplier is
end;
architecture test_multiplier of test_multiplier is
component c_multiplier
generic(width : INTEGER
);
port(Input1, Input2 : in std_logic_vector((width - 1) downto 0);
Output : out std_logic_vector((2*width - 2) downto 0));
end component;
for all : c_multiplier use entity WORK.c_multiplier(behavior);
signal Input1, Input2 : std_logic_vector(3 downto 0);
signal Output : std_logic_vector(6 downto 0);
file S_IN : TEXT is out "c_multiplier_beh.out";
begin
multiplier_1 : c_multiplier
generic map(4)
port map(Input1, Input2, Output);
test_process : process
begin
Input1 <= "1010";
Input2 <= "0001";
wait for 50 ns;
Input1 <= "0101";
Input2 <= "0011";
wait for 50 ns;
Input1 <= "0110";
Input2 <= "0100";
wait for 50 ns;
Input1 <= "0000";
Input2 <= "1000";
wait for 50 ns;
Input1 <= "0000";
Input2 <= "0000";
wait for 50 ns;
Input1 <= "0101";
Input2 <= "0111";
wait for 50 ns;
Input1 <= "1111";
Input2 <= "1111";
wait for 50 ns;
Input1 <= "1001";
Input2 <= "0010";
wait for 50 ns;
Input1 <= "1110";
Input2 <= "0010";
wait for 50 ns;
wait;
end process test_process;
end test_multiplier;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_MEMCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 2;
C_CLKOUT1_DIVIDE : integer := 2;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 4;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
U_BUFG_CLK1 : BUFG
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in
);
process (clk0_bufg, sys_rst)
begin
if (clk0_bufg'event and clk0_bufg = '1') then
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
rst_tmp <= sys_rst or not(powerup_pll_locked);
async_rst <= rst_tmp;
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity mwe_tb is
end mwe_tb;
architecture testbench of mwe_tb is
component mwe_entity is
port(
input : in std_logic;
output: out std_logic
);
end component;
signal i,o : std_logic;
begin
dut:mwe_entity
port map(input => i,output => o);
process
begin
for t in 0 to 10 loop
i <= '1';
wait for 5 ns;
assert o = '1' severity failure;
i <= '0';
wait for 5 ns;
assert o = '0' severity failure;
end loop;
wait;
end process;
end testbench;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_async_fifo_double_flipflop is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_DATA : in vl_logic_vector;
oOUT_DATA : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end mist1032sa_async_fifo_double_flipflop;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.cpu_pkg.all;
entity cachearray is
Port (
CLK : in STD_LOGIC;
-- bus interface
RW : in STD_LOGIC;
RD_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
WR_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
-- inputs
Vin : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
TAGin : in STD_LOGIC_VECTOR (19 downto 0);
-- outputs
Vout : out STD_LOGIC;
Dout : out STD_LOGIC_VECTOR (31 downto 0);
TAGout : out STD_LOGIC_VECTOR (19 downto 0)
);
end entity;
architecture Behavioral of cachearray is
type cache_v_t is array (0 to 1023) of std_logic;
type cache_data_t is array (0 to 1023) of std_logic_vector(31 downto 0);
type cache_tag_t is array (0 to 1023) of std_logic_vector(19 downto 0);
signal cache_arr_v : cache_v_t := (others => '0');
signal cache_arr_data : cache_data_t;
signal cache_arr_tag : cache_tag_t;
attribute ram_style: string;
attribute ram_style of cache_arr_v : signal is "block";
attribute ram_style of cache_arr_data : signal is "block";
attribute ram_style of cache_arr_tag : signal is "block";
begin
process (CLK)
begin
if ( CLK = '0' and CLK'event ) then
if (RW = '1') then
cache_arr_v(conv_integer(WR_ADDR)) <= Vin;
cache_arr_data(conv_integer(WR_ADDR)) <= Din;
cache_arr_tag(conv_integer(WR_ADDR)) <= TAGin;
else
Vout <= cache_arr_v(conv_integer(RD_ADDR));
Dout <= cache_arr_data(conv_integer(RD_ADDR));
TAGout <= cache_arr_tag(conv_integer(RD_ADDR));
end if;
end if;
end process;
end Behavioral;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
signal data_concat_tlast, tlast_new : std_logic;
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
|
entity tb_cnt04 is
end tb_cnt04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt04 is
signal clk : std_logic;
signal rst : std_logic;
signal counter : std_logic_vector (7 downto 0);
begin
dut: entity work.cnt04
port map (clk => clk, rst => rst, counter => counter);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert counter = x"01" severity failure;
rst <= '0';
pulse;
assert counter = x"02" severity failure;
pulse;
assert counter = x"03" severity failure;
wait;
end process;
end behav;
|
entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
|
entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
|
entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
|
entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
|
entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- digit subtypes incl. error value (-1)
subtype T_DIGIT_BIN is INTEGER range -1 to 1;
subtype T_DIGIT_OCT is INTEGER range -1 to 7;
subtype T_DIGIT_DEC is INTEGER range -1 to 9;
subtype T_DIGIT_HEX is INTEGER range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- digit subtypes incl. error value (-1)
subtype T_DIGIT_BIN is INTEGER range -1 to 1;
subtype T_DIGIT_OCT is INTEGER range -1 to 7;
subtype T_DIGIT_DEC is INTEGER range -1 to 9;
subtype T_DIGIT_HEX is INTEGER range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use WORK.alu_types.all;
-- This entity has A in input and implements a behavioural
-- representation of the table for RADIX-4 booth's algorithm.
-- As you can see this is not a standard multiplexer, altough
-- we left this name for simplicity.
-- The even multiplication ( left shift ) of A is performed in parallel by using OFFSET.
entity MUX3B is
generic (
N: integer := adderBits;
OFFSET: integer := 0 -- It's the offset for the depth of shift left of A
);
port (
A : in std_logic_vector(N-1 downto 0);
CTRL : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(N-1 downto 0);
Cin : out std_logic -- It's used for implement the 2's complement.It goes at the input of the RCA blocks.
);
end MUX3B;
architecture behavioral of MUX3B is
begin
MUX: process(A,CTRL)
variable tempA, tempS: unsigned(N-1 downto 0);
begin
-- Implement the table
case(CTRL) is
when "000" | "111" =>
Y <= (others=>'0');
Cin <= '0';
-- + A
when "001" | "010" =>
tempA := unsigned(A);
tempS := tempA sll OFFSET;
Y <= std_logic_vector(temps);
Cin <= '0';
-- +2A
when "011" =>
tempA := unsigned(A); -- i.e: OFFSET = 2 => Y = 8*A
tempS := tempA sll (OFFSET + 1); -- Shift left +1
Y <= std_logic_vector(tempS);
Cin <= '0';
-- -A
when "101" | "110" =>
tempA := unsigned(A);
tempS := tempA sll OFFSET;
Y <= not std_logic_vector(tempS); -- Negate now
Cin <= '1'; -- Add 1 in the adder to
-- implement the 2's complement
-- -2A
when "100" =>
tempA := unsigned(A);
tempS := tempA sll (OFFSET + 1); -- Shift left +1
Y <= not std_logic_vector(tempS); -- Negate now
Cin <= '1'; -- Add 1 in the adder to
-- implement the 2's complement
when others =>
null;
end case;
end process;
end behavioral;
|
----------------------------------------------------------------------
-- brdRstClk (for Maker Board)
----------------------------------------------------------------------
-- (c) 2019 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- Sync up o_rst_n to fit to rising edge of o_clk.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end brdRstClk;
----------------------------------------------------------------------
architecture rtl of brdRstClk is
component SYSRESET
port( DEVRST_N : in std_logic;
POWER_ON_RESET_N : out std_logic );
end component;
signal s_tgl, s_dly_n, s_rst_n : std_logic;
begin
SYSRESET_0 : SYSRESET
port map(
DEVRST_N => i_rst_n,
POWER_ON_RESET_N => s_rst_n );
process(i_clk, s_rst_n)
begin
if s_rst_n = '0' then
s_dly_n <= '0';
s_tgl <= '0';
o_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_tgl <= not s_tgl;
o_rst_n <= s_dly_n;
end if;
end process;
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
o_clk <= i_clk; -- 50MHz, direct
--o_clk <= s_tgl; -- 25MHz, divided
end rtl;
----------------------------------------------------------------------
|
-------------------------------------------------------
-- Design Name : ram_sp_ar_aw
-- File Name : ram_sp_ar_aw.vhd
-- Function : Asynchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_sp_ar_aw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 15
);
port (
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Input
data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-directional
cs :in std_logic; -- Chip Select
we :in std_logic; -- Write Enable/Read Enable
oe :in std_logic -- Output Enable
);
end entity;
architecture rtl of ram_sp_ar_aw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------
-- Tri-State Buffer control
data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
-- Memory Write Block
MEM_WRITE:
process (address, data, cs, we) begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;
-- Memory Read Block
MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-e.vhd,v 1.3 2005/11/30 14:04:00 wig Exp $
-- $Date: 2005/11/30 14:04:00 $
-- $Log: ent_ab-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:00 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ab
--
entity ent_ab is
-- Generics:
-- No Generated Generics for Entity ent_ab
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic; -- Use internally test1
port_ab_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0) -- Create internal signal name
-- End of Generated Port for Entity ent_ab
);
end ent_ab;
--
-- End of Generated Entity ent_ab
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.in for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library UniSim;
use UniSim.vComponents.all;
entity ddrio_in_xilinx is
generic (
BITS : POSITIVE;
INIT_VALUE_HIGH : BIT_VECTOR := "1";
INIT_VALUE_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_in_xilinx is
begin
gen : for i in 0 to WIDTH - 1 generate
iff : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT_Q1 => INIT_VALUE_HIGH(i),
INIT_Q2 => INIT_VALUE_LOW(i),
SRTYPE => "SYNC"
)
port map (
C => Clock,
CE => ClockEnable,
D => Pad(i),
Q1 => DataIn_high(i),
Q2 => DataIn_low(i),
R => '0',
S => '0'
);
end generate;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.in for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library UniSim;
use UniSim.vComponents.all;
entity ddrio_in_xilinx is
generic (
BITS : POSITIVE;
INIT_VALUE_HIGH : BIT_VECTOR := "1";
INIT_VALUE_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_in_xilinx is
begin
gen : for i in 0 to WIDTH - 1 generate
iff : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT_Q1 => INIT_VALUE_HIGH(i),
INIT_Q2 => INIT_VALUE_LOW(i),
SRTYPE => "SYNC"
)
port map (
C => Clock,
CE => ClockEnable,
D => Pad(i),
Q1 => DataIn_high(i),
Q2 => DataIn_low(i),
R => '0',
S => '0'
);
end generate;
end architecture;
|
constant SensorFSMLength : integer := 1180;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "0011000101100000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000000000001010000000000001000000000000000011000101000000010000001000000010001000010100000000000010000000100100011001000000000001000000001000100010000001000000010000000010010001110000010000000110000000100010001100000000010001100000001001001000000000000100100000000010001001000001000000001000000000100100100100010000000010100000000010101000000000000010001010000001001100000011000000001000101000000100100100010100000000100011100000000101100001000000100000001110000000010001100111000010000001000000000001011000001000000010000100000000000100011010000000001000010010000000010110000001001000000001001000000001000110100100100000001111100000000000000000000000000000111110000000000000000000000000000000001111100000000000000000000000000000000011111000000000000000000000000000000000111110000000000000000000000000000000001111100000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000111110000000000000000000000000000000000000000011111000000000000000000000000000000000000000001111100000000000000000000000000000000000000000";
|
-- bit_manipulation.vhdl - miscellaneous bit manipulation functions
-- Copyright (C) 2001, 2002 Michael Riepe <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id: bit_manipulation.vhdl,v 1.10 2002/07/05 21:36:57 michael Exp $
-- url : http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/common/bit_manipulation.vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package Bit_Manipulation is
-- reverse bits in a vector
function bit_reverse (A : in signed) return signed;
function bit_reverse (A : in unsigned) return unsigned;
function bit_reverse (A : in std_logic_vector) return std_logic_vector;
-- extract 1 bit of N, starting at offset O
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector;
-- duplicate all bits in a vector
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- duplicate vector
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- AND cascade
function cascade_and (A : in std_logic_vector) return std_logic_vector;
-- OR cascade
function cascade_or (A : in std_logic_vector) return std_logic_vector;
-- n:1 AND
function reduce_and (A : in std_logic_vector) return std_logic;
-- n:1 XOR
function reduce_xor (A : in std_logic_vector) return std_logic;
-- n:1 OR
function reduce_or (A : in std_logic_vector) return std_logic;
-- left shift w/ carry-in
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- left shift w/o carry-in
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic left shift
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right shift w/ carry-in
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- right shift w/o carry-in
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic right shift
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- left rotate
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right rotate
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned;
-- function bitbit_and(A : in signed; B : in signed) return signed;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector;
end Bit_Manipulation;
package body Bit_Manipulation is
function bit_reverse (A : in signed) return signed is
begin
return signed(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in unsigned) return unsigned is
begin
return unsigned(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, yy : std_logic_vector(L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in aa'range loop
yy(i) := aa(L - 1 - i);
end loop;
return yy;
end bit_reverse;
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector is
constant L : natural := A'length;
constant L2 : natural := (L - O + N - 1) / N;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L2-1 downto 0);
begin
--pragma synthesis_off
assert L > O;
--pragma synthesis_on
for i in L2-1 downto 0 loop
yy(i) := aa(N*i+O);
end loop;
return yy;
end bit_extract;
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i/N);
end loop;
return yy;
end bit_duplicate;
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i rem L);
end loop;
return yy;
end vector_duplicate;
function cascade_and (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) and aa(k1) and aa(k2) and aa(k3);
when 2 =>
bb(j) := aa(j) and aa(k1) and aa(k2);
when 1 =>
bb(j) := aa(j) and aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_and;
function cascade_or (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) or aa(k1) or aa(k2) or aa(k3);
when 2 =>
bb(j) := aa(j) or aa(k1) or aa(k2);
when 1 =>
bb(j) := aa(j) or aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_or;
function reduce_and (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) and aa(4*i+1) and aa(4*i+2) and aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) and aa(4*k+1) and aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) and aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_and;
function reduce_xor (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 31 loop -- should be enough
exit when len = 1;
k := len / 2;
for i in 0 to k-1 loop
aa(i) := aa(2*i+0) xor aa(2*i+1);
end loop;
case len mod 2 is
when 1 => aa(k) := aa(2*k+0);
when others => null;
end case;
len := (len + 1) / 2;
end loop;
return aa(0);
end reduce_xor;
function reduce_or (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) or aa(4*i+1) or aa(4*i+2) or aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) or aa(4*k+1) or aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) or aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_or;
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-1 downto N) := aa(L-N-1 downto 0);
end if;
return yy;
end lshift;
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, '0');
end lshift;
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, A(A'right));
end lshifta;
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-N-1 downto 0) := aa(L-1 downto N);
end if;
return yy;
end rshift;
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, '0');
end rshift;
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, A(A'left));
end rshifta;
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + L - N) rem L);
end loop;
return yy;
end lrotate;
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + N) rem L);
end loop;
return yy;
end rrotate;
-- function bitbit_and(A : in signed; B : in signed) return signed is
-- begin
-- return signed(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned is
-- begin
-- return unsigned(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and bb(i);
end loop;
return yy;
end bitbit_and;
function bitbit_or(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) or bb(i);
end loop;
return yy;
end bitbit_or;
end Bit_Manipulation;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please
|
-- bit_manipulation.vhdl - miscellaneous bit manipulation functions
-- Copyright (C) 2001, 2002 Michael Riepe <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id: bit_manipulation.vhdl,v 1.10 2002/07/05 21:36:57 michael Exp $
-- url : http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/common/bit_manipulation.vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package Bit_Manipulation is
-- reverse bits in a vector
function bit_reverse (A : in signed) return signed;
function bit_reverse (A : in unsigned) return unsigned;
function bit_reverse (A : in std_logic_vector) return std_logic_vector;
-- extract 1 bit of N, starting at offset O
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector;
-- duplicate all bits in a vector
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- duplicate vector
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- AND cascade
function cascade_and (A : in std_logic_vector) return std_logic_vector;
-- OR cascade
function cascade_or (A : in std_logic_vector) return std_logic_vector;
-- n:1 AND
function reduce_and (A : in std_logic_vector) return std_logic;
-- n:1 XOR
function reduce_xor (A : in std_logic_vector) return std_logic;
-- n:1 OR
function reduce_or (A : in std_logic_vector) return std_logic;
-- left shift w/ carry-in
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- left shift w/o carry-in
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic left shift
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right shift w/ carry-in
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- right shift w/o carry-in
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic right shift
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- left rotate
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right rotate
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned;
-- function bitbit_and(A : in signed; B : in signed) return signed;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector;
end Bit_Manipulation;
package body Bit_Manipulation is
function bit_reverse (A : in signed) return signed is
begin
return signed(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in unsigned) return unsigned is
begin
return unsigned(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, yy : std_logic_vector(L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in aa'range loop
yy(i) := aa(L - 1 - i);
end loop;
return yy;
end bit_reverse;
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector is
constant L : natural := A'length;
constant L2 : natural := (L - O + N - 1) / N;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L2-1 downto 0);
begin
--pragma synthesis_off
assert L > O;
--pragma synthesis_on
for i in L2-1 downto 0 loop
yy(i) := aa(N*i+O);
end loop;
return yy;
end bit_extract;
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i/N);
end loop;
return yy;
end bit_duplicate;
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i rem L);
end loop;
return yy;
end vector_duplicate;
function cascade_and (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) and aa(k1) and aa(k2) and aa(k3);
when 2 =>
bb(j) := aa(j) and aa(k1) and aa(k2);
when 1 =>
bb(j) := aa(j) and aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_and;
function cascade_or (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) or aa(k1) or aa(k2) or aa(k3);
when 2 =>
bb(j) := aa(j) or aa(k1) or aa(k2);
when 1 =>
bb(j) := aa(j) or aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_or;
function reduce_and (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) and aa(4*i+1) and aa(4*i+2) and aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) and aa(4*k+1) and aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) and aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_and;
function reduce_xor (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 31 loop -- should be enough
exit when len = 1;
k := len / 2;
for i in 0 to k-1 loop
aa(i) := aa(2*i+0) xor aa(2*i+1);
end loop;
case len mod 2 is
when 1 => aa(k) := aa(2*k+0);
when others => null;
end case;
len := (len + 1) / 2;
end loop;
return aa(0);
end reduce_xor;
function reduce_or (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) or aa(4*i+1) or aa(4*i+2) or aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) or aa(4*k+1) or aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) or aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_or;
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-1 downto N) := aa(L-N-1 downto 0);
end if;
return yy;
end lshift;
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, '0');
end lshift;
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, A(A'right));
end lshifta;
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-N-1 downto 0) := aa(L-1 downto N);
end if;
return yy;
end rshift;
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, '0');
end rshift;
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, A(A'left));
end rshifta;
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + L - N) rem L);
end loop;
return yy;
end lrotate;
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + N) rem L);
end loop;
return yy;
end rrotate;
-- function bitbit_and(A : in signed; B : in signed) return signed is
-- begin
-- return signed(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned is
-- begin
-- return unsigned(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and bb(i);
end loop;
return yy;
end bitbit_and;
function bitbit_or(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) or bb(i);
end loop;
return yy;
end bitbit_or;
end Bit_Manipulation;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 38,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 7,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_ANGLE_WIDTH => 16,
C_PHASE_INCREMENT => 3,
C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 1,
C_S_PHASE_TDATA_WIDTH => 40,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 40,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => s_axis_phase_tvalid,
s_axis_phase_tdata => s_axis_phase_tdata,
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END dds_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 38,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 7,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_ANGLE_WIDTH => 16,
C_PHASE_INCREMENT => 3,
C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 1,
C_S_PHASE_TDATA_WIDTH => 40,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 40,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => s_axis_phase_tvalid,
s_axis_phase_tdata => s_axis_phase_tdata,
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END dds_arch;
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