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--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc6.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00006ent IS
END c04s01b00x00p08n01i00006ent;
ARCHITECTURE c04s01b00x00p08n01i00006arch OF c04s01b00x00p08n01i00006ent IS
BEGIN
TESTING: PROCESS
type REAL1 is range 1.0 to 1.0;
type REAL2 is range 1.0 to 1.0;
variable V3: REAL1;
variable V4: REAL2;
BEGIN
if V3 = V4 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST:c04s01b00x00p08n01i00006 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00006arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc6.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00006ent IS
END c04s01b00x00p08n01i00006ent;
ARCHITECTURE c04s01b00x00p08n01i00006arch OF c04s01b00x00p08n01i00006ent IS
BEGIN
TESTING: PROCESS
type REAL1 is range 1.0 to 1.0;
type REAL2 is range 1.0 to 1.0;
variable V3: REAL1;
variable V4: REAL2;
BEGIN
if V3 = V4 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST:c04s01b00x00p08n01i00006 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00006arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc6.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00006ent IS
END c04s01b00x00p08n01i00006ent;
ARCHITECTURE c04s01b00x00p08n01i00006arch OF c04s01b00x00p08n01i00006ent IS
BEGIN
TESTING: PROCESS
type REAL1 is range 1.0 to 1.0;
type REAL2 is range 1.0 to 1.0;
variable V3: REAL1;
variable V4: REAL2;
BEGIN
if V3 = V4 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST:c04s01b00x00p08n01i00006 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00006arch;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
--Date : Thu Mar 02 22:09:48 2017
--Host : Tho running 64-bit Service Pack 1 (build 7601)
--Command : generate_target wasca_toplevel_wrapper.bd
--Design : wasca_toplevel_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity wasca_toplevel_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_irq_dir : out STD_LOGIC;
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_wait : inout STD_LOGIC;
abus_wait_dir : out STD_LOGIC;
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 )
);
end wasca_toplevel_wrapper;
architecture STRUCTURE of wasca_toplevel_wrapper is
component wasca_toplevel is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
abus_wait : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq_dir : out STD_LOGIC;
abus_wait_dir : out STD_LOGIC
);
end component wasca_toplevel;
begin
wasca_toplevel_i: component wasca_toplevel
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
abus_address(25 downto 0) => abus_address(25 downto 0),
abus_chipselect(2 downto 0) => abus_chipselect(2 downto 0),
abus_data_dir => abus_data_dir,
abus_irq(0) => abus_irq(0),
abus_irq_dir => abus_irq_dir,
abus_read => abus_read,
abus_reset => abus_reset,
abus_wait => abus_wait,
abus_wait_dir => abus_wait_dir,
abus_write(1 downto 0) => abus_write(1 downto 0),
data_to_and_from_pins(15 downto 0) => data_to_and_from_pins(15 downto 0)
);
end STRUCTURE;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
--Date : Thu Mar 02 22:09:48 2017
--Host : Tho running 64-bit Service Pack 1 (build 7601)
--Command : generate_target wasca_toplevel_wrapper.bd
--Design : wasca_toplevel_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity wasca_toplevel_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_irq_dir : out STD_LOGIC;
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_wait : inout STD_LOGIC;
abus_wait_dir : out STD_LOGIC;
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 )
);
end wasca_toplevel_wrapper;
architecture STRUCTURE of wasca_toplevel_wrapper is
component wasca_toplevel is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
abus_wait : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq_dir : out STD_LOGIC;
abus_wait_dir : out STD_LOGIC
);
end component wasca_toplevel;
begin
wasca_toplevel_i: component wasca_toplevel
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
abus_address(25 downto 0) => abus_address(25 downto 0),
abus_chipselect(2 downto 0) => abus_chipselect(2 downto 0),
abus_data_dir => abus_data_dir,
abus_irq(0) => abus_irq(0),
abus_irq_dir => abus_irq_dir,
abus_read => abus_read,
abus_reset => abus_reset,
abus_wait => abus_wait,
abus_wait_dir => abus_wait_dir,
abus_write(1 downto 0) => abus_write(1 downto 0),
data_to_and_from_pins(15 downto 0) => data_to_and_from_pins(15 downto 0)
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer is
port(
sign1_in : in std_logic;
sign2_in : in std_logic;
sign_out : out std_logic
);
end;
architecture sign_computer_arq of sign_computer is
begin
process(sign1_in, sign2_in)
begin
sign_out <= sign1_in xor sign2_in;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
library osvvm;
use osvvm.NamePkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.AlertLogPkg.all ;
use osvvm.RandomPkg.all ;
use osvvm.CoveragePkg.all ;
use osvvm.MemoryPkg.all ;
entity osvvm_fsm_coverage is
end entity osvvm_fsm_coverage;
architecture sim of osvvm_fsm_coverage is
type t_fsm_state is (IDLE, ADDR, DATA);
signal s_fsm_state : t_fsm_state;
signal s_clk : std_logic := '0';
signal s_reset_n : std_logic := '0';
shared variable sv_cover : CovPType;
procedure fsm_covadd_states (name : in string;
prev : in t_fsm_state;
curr : in t_fsm_state;
covdb : inout CovPType) is
begin
covdb.AddCross(name,
GenBin(t_fsm_state'pos(prev)),
GenBin(t_fsm_state'pos(curr)));
wait;
end procedure fsm_covadd_states;
procedure fsm_covadd_illegal (name : in string;
covdb : inout CovPType) is
begin
covdb.AddCross(ALL_ILLEGAL, ALL_ILLEGAL);
wait;
end procedure fsm_covadd_illegal;
procedure fsm_covcollect (signal reset : in std_logic;
signal clk : in std_logic;
signal state : in t_fsm_state;
covdb : inout CovPType) is
variable v_state : t_fsm_state := t_fsm_state'left;
begin
wait until reset = '1' and rising_edge(clk);
loop
v_state := state;
wait until rising_edge(s_clk);
covdb.ICover((t_fsm_state'pos(v_state), t_fsm_state'pos(state)));
end loop;
end procedure fsm_covcollect;
begin
s_clk <= not(s_clk) after 5 ns;
s_reset_n <= '1' after 20 ns;
FsmP : process (s_reset_n, s_clk) is
begin
if (s_reset_n = '0') then
s_fsm_state <= IDLE;
elsif (rising_edge(s_clk)) then
case s_fsm_state is
when IDLE => s_fsm_state <= ADDR;
when ADDR => s_fsm_state <= DATA;
when DATA => s_fsm_state <= IDLE;
when others =>
null;
end case;
end if;
end process FsmP;
fsm_covadd_states ("IDLE->ADDR", IDLE, ADDR, sv_cover);
fsm_covadd_states ("ADDR->DATA", ADDR, DATA, sv_cover);
fsm_covadd_states ("DATA->IDLE", DATA, IDLE, sv_cover);
fsm_covadd_illegal ("ILLEGAL", sv_cover);
fsm_covcollect (s_reset_n, s_clk, s_fsm_state, sv_cover);
FinishP : process is
begin
wait until s_clk'active;
if (sv_cover.IsCovered) then
Log("FSM full covered :)", ALWAYS);
sv_cover.SetName("FSM state coverage report");
sv_cover.WriteBin;
stop(0);
end if;
end process FinishP;
-- psl default clock is rising_edge(s_clk);
-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n)
-- report "FSM error: IDLE should be followed by ADDR state";
-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n);
-- report "FSM error: ADDR should be followed by DATA state";
-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n);
-- report "FSM error: DATA should be followed by IDLE state";
end architecture sim;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45904)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45904)
`protect data_block
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`protect end_protected
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:50:58 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_stub.vhdl
-- Design : ip_design_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[191:0],m_axi_awprot[17:0],m_axi_awvalid[5:0],m_axi_awready[5:0],m_axi_wdata[191:0],m_axi_wstrb[23:0],m_axi_wvalid[5:0],m_axi_wready[5:0],m_axi_bresp[11:0],m_axi_bvalid[5:0],m_axi_bready[5:0],m_axi_araddr[191:0],m_axi_arprot[17:0],m_axi_arvalid[5:0],m_axi_arready[5:0],m_axi_rdata[191:0],m_axi_rresp[11:0],m_axi_rvalid[5:0],m_axi_rready[5:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3";
begin
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_POST_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--High-Speed D-PHY clock RX PHY for MIPI CSI-2 Rx core
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
-- This receives the input clock and produces both real and complement DDR bit
-- clocks and an SDR (i.e. in/4) byte clock for the SERDES and other downstream devices
entity csi_rx_hs_clk_phy is
generic (
series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6
term_en : boolean := true
);
port (
dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --D-PHY clock input; 1 is P, 0 is N
reset : in STD_LOGIC; --reset input for BUFR
ddr_bit_clock : out STD_LOGIC; --DDR bit clock (i.e. input clock buffered) out
ddr_bit_clock_b : out STD_LOGIC; --Inverted DDR bit clock out
byte_clock : out STD_LOGIC --SDR byte clock (i.e. input clock / 4) out
);
end csi_rx_hs_clk_phy;
architecture Behavioral of csi_rx_hs_clk_phy is
signal bit_clock_int_pre : std_logic;
signal bit_clock_int : std_logic;
signal bit_clock_b_int : std_logic;
signal byte_clock_int : std_logic;
begin
iclkdbuf : IBUFDS
generic map (
DIFF_TERM => term_en,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT"
)
port map(
O => bit_clock_int_pre,
I => dphy_clk(1),
IB => dphy_clk(0)
);
iclkbufio: BUFIO
port map (
O => bit_clock_int,
I => bit_clock_int_pre
);
bit_clock_b_int <= NOT bit_clock_int;
clkdiv : BUFR
generic map (
BUFR_DIVIDE => "4",
SIM_DEVICE => series
)
port map (
O => byte_clock_int,
CE => '1',
CLR => reset,
I => bit_clock_int_pre
);
ddr_bit_clock <= bit_clock_int;
ddr_bit_clock_b <= bit_clock_b_int;
byte_clock <= byte_clock_int;
end Behavioral;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 1;
begin -- process
x := x + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 1;
begin -- process
x := x + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 1;
begin -- process
x := x + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
library verilog;
use verilog.vl_types.all;
entity ApbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
pRegReq : out vl_logic;
pRegWrite : out vl_logic;
pFMInvalidXfer : out vl_logic;
wrapperWData : out vl_logic_vector(31 downto 0);
wrapperRData : in vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
APB16_XHOLD : out vl_logic_vector(15 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic;
F_FM_HREADYOUT : in vl_logic
);
end ApbWrapper_FM;
|
library verilog;
use verilog.vl_types.all;
entity ApbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
pRegReq : out vl_logic;
pRegWrite : out vl_logic;
pFMInvalidXfer : out vl_logic;
wrapperWData : out vl_logic_vector(31 downto 0);
wrapperRData : in vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
APB16_XHOLD : out vl_logic_vector(15 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic;
F_FM_HREADYOUT : in vl_logic
);
end ApbWrapper_FM;
|
library verilog;
use verilog.vl_types.all;
entity ApbWrapper_FM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
clientReady : in vl_logic;
clientError : in vl_logic;
dataPhAck : in vl_logic;
pRegReq : out vl_logic;
pRegWrite : out vl_logic;
pFMInvalidXfer : out vl_logic;
wrapperWData : out vl_logic_vector(31 downto 0);
wrapperRData : in vl_logic_vector(31 downto 0);
F_FM_ADDR : in vl_logic_vector(31 downto 0);
APB16_XHOLD : out vl_logic_vector(15 downto 0);
F_FM_WDATA : in vl_logic_vector(31 downto 0);
F_FM_RDATA : out vl_logic_vector(31 downto 0);
F_FM_PSEL : in vl_logic;
F_FM_PENABLE : in vl_logic;
F_FM_PWRITE : in vl_logic;
F_FM_PREADY : out vl_logic;
F_FM_PSLVERR : out vl_logic;
F_FM_HREADYOUT : in vl_logic
);
end ApbWrapper_FM;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end PROCEDURE proc_name;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02150ent IS
END c07s02b04x00p21n01i02150ent;
ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real_4 := ( 12.34, 56.78, 12.34, 56.78 );
variable r_operand : real := 12.34;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***PASSED TEST: c07s02b04x00p21n01i02150"
severity NOTE;
assert ((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02150arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02150ent IS
END c07s02b04x00p21n01i02150ent;
ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real_4 := ( 12.34, 56.78, 12.34, 56.78 );
variable r_operand : real := 12.34;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***PASSED TEST: c07s02b04x00p21n01i02150"
severity NOTE;
assert ((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02150arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02150ent IS
END c07s02b04x00p21n01i02150ent;
ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real_4 := ( 12.34, 56.78, 12.34, 56.78 );
variable r_operand : real := 12.34;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***PASSED TEST: c07s02b04x00p21n01i02150"
severity NOTE;
assert ((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02150arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.aes_types.all;
entity aes_MixColumns is
port(
data_in : in matrix(3 downto 0, 3 downto 0);
data_out : out matrix(3 downto 0, 3 downto 0);
start : in std_logic;
done : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity aes_MixColumns;
architecture RTL of aes_MixColumns is
type state is (IDLE, PROCESSING);
signal current_state : state := IDLE;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
for i in 0 to 3 loop
for j in 0 to 3 loop
data_out(i, j) <= (others => '0');
end loop;
end loop;
else
for i in 0 to 3 loop
for j in 0 to 3 loop
data_out(j, i) <= column_modulo_mul(column_rotate(matrix2column(data_in, i), j));
end loop;
end loop;
case current_state is
when IDLE =>
if (start = '1') then
current_state <= PROCESSING;
else
current_state <= current_state;
end if;
done <= '0';
when PROCESSING =>
current_state <= IDLE;
done <= '1';
end case;
end if;
end if;
end process;
end architecture RTL; |
----------------------------------------------------------------------------------
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.TRIGGERS.OneShot;
entity PPSToCR is
port( trigger : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC);
end PPSToCR;
architecture Behavioral of PPSToCR is
type fsm_type is (ST_WAIT,ST_TRIGGERED);
signal curr_state: fsm_type;
signal trig_pulse: STD_LOGIC;
constant ser_cr : STD_LOGIC_VECTOR(0 to 9) := "0101100001";
begin
process (clk)
variable clk_div_cnt: natural range 0 to 1023:=0;
variable bit_cnt: natural range 0 to 15:=0;
begin
if rising_edge(clk) then
case curr_state is
when ST_WAIT =>
curr_state <= ST_WAIT;
serial_out <= '1';
if trig_pulse='1' then
curr_state <= ST_TRIGGERED;
end if;
when ST_TRIGGERED=>
serial_out<=ser_cr(bit_cnt);
clk_div_cnt:=clk_div_cnt+1;
if clk_div_cnt = 868 then -- main clock divider
bit_cnt := bit_cnt+1;
clk_div_cnt:=0;
if bit_cnt=10 then
curr_state <= ST_WAIT;
bit_cnt:=0;
clk_div_cnt:=0;
end if;
end if;
when others =>
curr_state <= ST_WAIT;
serial_out <= '1';
end case;
end if;
end process;
trigin: OneShot port map (trigger=>trigger,clk=>clk,pulse=>trig_pulse);
end Behavioral;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DemoClipAdder is
port (
clk : in std_logic;
aReset : in std_logic;
cPortA : in std_logic_vector(15 downto 0);
cPortB : in std_logic_vector(15 downto 0);
cAddOut : out std_logic_vector(15 downto 0) := (others => '0')
);
end DemoClipAdder;
architecture rtl of DemoClipAdder is
begin
process(aReset, clk) begin
if(aReset = '1') then
cAddOut <= (others => '0');
elsif rising_edge(clk) then
cAddOut <= std_logic_vector(signed(cPortA) + signed(cPortB));
end if;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity alu is
port(
I_clk: in std_logic;
I_en: in std_logic;
I_dataS1: in std_logic_vector(XLEN-1 downto 0);
I_dataS2: in std_logic_vector(XLEN-1 downto 0);
I_reset: in std_logic := '0';
I_aluop: in aluops_t;
O_busy: out std_logic := '0';
O_data: out std_logic_vector(XLEN-1 downto 0);
O_lt: out boolean := false;
O_ltu: out boolean := false;
O_eq: out boolean := false
);
end alu;
architecture Behavioral of alu is
alias op1 is I_dataS1(XLEN-1 downto 0);
alias op2 is I_dataS2(XLEN-1 downto 0);
signal result: std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO;
signal sum,myxor,myand,myor: std_logic_vector(XLEN-1 downto 0);
signal sub: std_logic_vector(XLEN downto 0); -- one additional bit to detect underflow
signal lt,ltu,eq: boolean;
signal busy: std_logic := '0';
begin
-- combinatorial logic for basic operations
process(op1, op2)
begin
sum <= std_logic_vector(unsigned(op1) + unsigned(op2));
sub <= std_logic_vector(unsigned('0' & op1) - unsigned('0' & op2));
myxor <= op1 xor op2;
myor <= op1 or op2;
myand <= op1 and op2;
end process;
-- determine flag values
process(sub, myxor)
begin
-- unsigned comparision: simply look at underflow bit
ltu <= sub(XLEN) = '1';
-- signed comparison: xor underflow bit with xored sign bits
lt <= (sub(XLEN) xor myxor(XLEN-1)) = '1';
eq <= sub = ('0' & XLEN_ZERO);
end process;
process(I_clk, I_en, I_dataS1, I_dataS2, I_reset, I_aluop, sum, sub, ltu, myxor, myor, myand, lt, eq)
variable shiftcnt: std_logic_vector(4 downto 0);
begin
if rising_edge(I_clk) then
-- check for reset
if(I_reset = '1') then
busy <= '0';
elsif I_en = '1' then
-------------------------------
-- ALU core operations
-------------------------------
case I_aluop is
when ALU_ADD =>
result <= sum;
when ALU_SUB =>
result <= sub(XLEN-1 downto 0);
when ALU_AND =>
result <= myand;
when ALU_OR =>
result <= myor;
when ALU_XOR =>
result <= myxor;
when ALU_SLT =>
result <= XLEN_ZERO;
if lt then
result(0) <= '1';
end if;
when ALU_SLTU =>
result <= XLEN_ZERO;
if ltu then
result(0) <= '1';
end if;
when ALU_SLL | ALU_SRL | ALU_SRA =>
if busy = '0' then
busy <= '1';
result <= op1;
shiftcnt := op2(4 downto 0);
elsif shiftcnt /= "00000" then
case I_aluop is
when ALU_SLL => result <= result(30 downto 0) & '0';
when ALU_SRL => result <= '0' & result(31 downto 1);
when others => result <= result(31) & result(31 downto 1);
end case;
shiftcnt := std_logic_vector(unsigned(shiftcnt) - 1);
else
busy <= '0';
end if;
end case;
O_lt <= lt;
O_ltu <= ltu;
O_eq <= eq;
end if;
end if;
end process;
process(result, busy)
begin
O_data <= result;
O_busy <= busy;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_230 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_230;
architecture augh of mul_230 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_230 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_230;
architecture augh of mul_230 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
rd_address : in unsigned(g_depth_bits-1 downto 0);
rd_data : out std_logic_vector(g_width_bits-1 downto 0);
rd_en : in std_logic := '1';
wr_address : in unsigned(g_depth_bits-1 downto 0);
wr_data : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
wr_en : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of pseudo_dpram : entity is "yes";
end entity;
architecture xilinx of pseudo_dpram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
attribute ramstyle : string;
attribute ramstyle of ram : variable is g_storage;
begin
process(clock)
begin
if rising_edge(clock) then
if g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
if wr_en='1' then
ram(to_integer(wr_address)) := wr_data;
end if;
if not g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- TDC sample preparation
--
-- This component processes the input signals looking for events, rising edges
-- for digital, maxfind for analog. The module also includes a sample counter
-- which also generates an event on overflow.
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
use work.maxfinder_pkg.all;
use work.tdc_sample_prep_pkg.all;
entity tdc_sample_prep is
generic (
CNT_BITS: natural := 16
);
port (
clk: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
--
samples_d_out: out din_samples_t(0 to 3);
samples_a_out: out a_samples_t(0 to 1);
cnt: out unsigned(CNT_BITS-1 downto 0);
tdc_events: out tdc_events_t
);
end tdc_sample_prep;
architecture tdc_sample_prep_arch of tdc_sample_prep is
-- input filtering
signal samples_a_in_avg, samples_a_in_filt: adc_samples_t(0 to 1);
-- queue samples for sample out alignment after rising/maximum detection
constant D_QUEUE_LEN: natural := 2;
constant A_QUEUE_LEN: natural := 8; -- 8
type samples_d_buf_t is array(0 to D_QUEUE_LEN-1) of din_samples_t(0 to 3);
type samples_a_buf_t is array(0 to A_QUEUE_LEN-1) of a_samples_t(0 to 1);
signal samples_d_buf: samples_d_buf_t := (others => (others => (others => '0')));
signal samples_a_buf: samples_a_buf_t := (others => (others => (others => '0')));
-- sample counter
signal sample_cnt_int: unsigned(CNT_BITS-1 downto 0) := (others => '0');
-- digital processing
component digital_edge_detect
port (
clk: in std_logic;
samples_d: in din_samples_t(0 to 3);
rising_d: out din_samples_t(0 to 3);
falling_d: out din_samples_t(0 to 3)
);
end component;
signal rising_d, falling_d: din_samples_t(0 to 3);
signal d1_rising_int, d1_falling_int: std_logic_vector(3 downto 0) := (others => '0');
signal d2_rising_int, d2_falling_int: std_logic_vector(3 downto 0) := (others => '0');
-- analog processing
component maxfinder_simple
generic (
N_FRAC_BITS: natural := 1;
N_ADIFF_CLIP: natural := 0
);
port (
clk: in std_logic;
samples_in: in a_samples_t(0 to 1);
threshold: in a_sample_t;
max_found: out std_logic;
max_pos: out unsigned(1+N_FRAC_BITS-1 downto 0);
max_height: out a_sample_t
);
end component;
signal max_samples_in: a_samples_t(0 to 1);
signal max_found: std_logic;
signal max_pos: unsigned(1 downto 0) := (others => '0');
signal max_height: a_sample_t := (others => '0');
signal a_maxfound_int: tdc_event_t;
begin
-- input filter
a_filter: entity work.sample_average
port map (
clk => clk,
n => a_average,
samples_a_in => samples_a_in,
samples_a_out => samples_a_in_avg
);
process(clk)
begin
if rising_edge(clk) then
for I in samples_a_in_avg'low to samples_a_in_avg'high loop
samples_a_in_filt(I) <= samples_a_in_avg(I);
if a_invert = '1' then
samples_a_in_filt(I).data <= -samples_a_in_avg(I).data;
end if;
end loop;
end if;
end process;
-- sample counter
proc_sample_counter: process(clk)
constant X: unsigned(CNT_BITS-1 downto 0) := (others => '1');
begin
if rising_edge(clk) then
sample_cnt_int <= sample_cnt_int + 1;
end if;
end process;
-- digital rising edges
digital_edge_detect_inst: digital_edge_detect
port map(
clk => clk,
samples_d => samples_d_in,
rising_d => rising_d,
falling_d => falling_d
);
d1_rising_int <= rising_d(0)(0) & rising_d(1)(0) & rising_d(2)(0) & rising_d(3)(0);
d2_rising_int <= rising_d(0)(1) & rising_d(1)(1) & rising_d(2)(1) & rising_d(3)(1);
d1_falling_int <= falling_d(0)(0) & falling_d(1)(0) & falling_d(2)(0) & falling_d(3)(0);
d2_falling_int <= falling_d(0)(1) & falling_d(1)(1) & falling_d(2)(1) & falling_d(3)(1);
-- analog maximum finder
maxfinder_inst: maxfinder_simple
port map(
clk => clk,
samples_in => max_samples_in,
threshold => a_threshold,
max_found => max_found,
max_pos => max_pos,
max_height => max_height
);
max_samples_in(0) <= samples_a_in_filt(0).data;
max_samples_in(1) <= samples_a_in_filt(1).data;
a_maxfound_int <= (valid => max_found, pos => max_pos);
--------------------------------------------------------------------------------
-- output
-- shift in/out input samples, use queue to align input samples with event outputs
process(clk)
begin
if rising_edge(clk) then
-- digital
samples_d_buf(1 to samples_d_buf'high) <= samples_d_buf(0 to samples_d_buf'high-1);
samples_d_buf(0) <= samples_d_in;
samples_d_out <= samples_d_buf(samples_d_buf'high);
-- analog
samples_a_buf(1 to samples_a_buf'high) <= samples_a_buf(0 to samples_a_buf'high-1);
for I in samples_a_in_filt'low to samples_a_in_filt'high loop
samples_a_buf(0)(I) <= samples_a_in_filt(I).data;
end loop;
samples_a_out <= samples_a_buf(samples_a_buf'high);
end if;
end process;
-- register event outputs
process(clk)
begin
if rising_edge(clk) then
cnt <= sample_cnt_int;
tdc_events <= (
d1_rising => flat_events_to_event_t(d1_rising_int),
d1_falling => flat_events_to_event_t(d1_falling_int),
d2_rising => flat_events_to_event_t(d2_rising_int),
d2_falling => flat_events_to_event_t(d2_falling_int),
a_maxfound => a_maxfound_int,
a_maxvalue => max_height
);
end if;
end process;
end tdc_sample_prep_arch;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:44:40 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_gcd_0_0_sim_netlist.vhdl
-- Design : gcd_zynq_snick_gcd_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
interrupt : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\b_read_reg_102_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\a_read_reg_107_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BREADY : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\result_reg_56_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
\p_s_reg_45_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^a_read_reg_107_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal \^b_read_reg_102_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_a0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_a[15]_i_1_n_0\ : STD_LOGIC;
signal \int_a[15]_i_3_n_0\ : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_done1 : STD_LOGIC;
signal int_ap_done_i_1_n_0 : STD_LOGIC;
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_start3_out : STD_LOGIC;
signal int_ap_start_i_10_n_0 : STD_LOGIC;
signal int_ap_start_i_1_n_0 : STD_LOGIC;
signal int_ap_start_i_5_n_0 : STD_LOGIC;
signal int_ap_start_i_6_n_0 : STD_LOGIC;
signal int_ap_start_i_7_n_0 : STD_LOGIC;
signal int_ap_start_i_8_n_0 : STD_LOGIC;
signal int_ap_start_i_9_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_2_n_3 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_1 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_2 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_3 : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_auto_restart_i_1_n_0 : STD_LOGIC;
signal int_b0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_b[15]_i_1_n_0\ : STD_LOGIC;
signal int_gie_i_1_n_0 : STD_LOGIC;
signal int_gie_reg_n_0 : STD_LOGIC;
signal \int_ier[0]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_2_n_0\ : STD_LOGIC;
signal \int_ier_reg_n_0_[0]\ : STD_LOGIC;
signal \int_ier_reg_n_0_[1]\ : STD_LOGIC;
signal int_isr6_out : STD_LOGIC;
signal \int_isr[0]_i_1_n_0\ : STD_LOGIC;
signal \int_isr[1]_i_1_n_0\ : STD_LOGIC;
signal \int_isr_reg_n_0_[0]\ : STD_LOGIC;
signal int_pResult : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_pResult_ap_vld : STD_LOGIC;
signal int_pResult_ap_vld1 : STD_LOGIC;
signal int_pResult_ap_vld_i_1_n_0 : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_1_in : STD_LOGIC;
signal \rdata[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[0]_i_3_n_0\ : STD_LOGIC;
signal \rdata[0]_i_4_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_2_n_0\ : STD_LOGIC;
signal \rdata[1]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_4_n_0\ : STD_LOGIC;
signal \rdata[1]_i_5_n_0\ : STD_LOGIC;
signal \rdata[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata[2]_i_2_n_0\ : STD_LOGIC;
signal \rdata[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata[3]_i_2_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_2_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axi_gcd_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_gcd_bus_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
signal \waddr_reg_n_0_[5]\ : STD_LOGIC;
signal NLW_int_ap_start_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_int_ap_start_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_int_ap_start_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[15]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of int_ap_start_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[15]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0";
begin
CO(0) <= \^co\(0);
SR(0) <= \^sr\(0);
\a_read_reg_107_reg[15]\(15 downto 0) <= \^a_read_reg_107_reg[15]\(15 downto 0);
\b_read_reg_102_reg[15]\(15 downto 0) <= \^b_read_reg_102_reg[15]\(15 downto 0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RVALID(1 downto 0) <= \^s_axi_gcd_bus_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F747"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88F8"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888BFF8B"
)
port map (
I0 => s_axi_gcd_bus_BREADY,
I1 => \^out\(2),
I2 => \^out\(1),
I3 => \^out\(0),
I4 => s_axi_gcd_bus_AWVALID,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_AWVALID,
I1 => \^out\(0),
I2 => s_axi_gcd_bus_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_WVALID,
I1 => \^out\(1),
I2 => s_axi_gcd_bus_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_2_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_2_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FA30"
)
port map (
I0 => \^co\(0),
I1 => ap_start,
I2 => Q(0),
I3 => Q(2),
O => D(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(1),
I1 => Q(3),
I2 => Q(0),
I3 => ap_start,
I4 => Q(2),
O => D(1)
);
\b_read_reg_102[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => E(0)
);
\int_a[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(0),
O => int_a0(0)
);
\int_a[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(10),
O => int_a0(10)
);
\int_a[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(11),
O => int_a0(11)
);
\int_a[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(12),
O => int_a0(12)
);
\int_a[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(13),
O => int_a0(13)
);
\int_a[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(14),
O => int_a0(14)
);
\int_a[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \waddr_reg_n_0_[4]\,
I1 => \int_a[15]_i_3_n_0\,
I2 => \waddr_reg_n_0_[2]\,
I3 => \waddr_reg_n_0_[3]\,
O => \int_a[15]_i_1_n_0\
);
\int_a[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(15),
O => int_a0(15)
);
\int_a[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[5]\,
I2 => \^out\(1),
I3 => s_axi_gcd_bus_WVALID,
I4 => \waddr_reg_n_0_[1]\,
O => \int_a[15]_i_3_n_0\
);
\int_a[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(1),
O => int_a0(1)
);
\int_a[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(2),
O => int_a0(2)
);
\int_a[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(3),
O => int_a0(3)
);
\int_a[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(4),
O => int_a0(4)
);
\int_a[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(5),
O => int_a0(5)
);
\int_a[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(6),
O => int_a0(6)
);
\int_a[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(7),
O => int_a0(7)
);
\int_a[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(8),
O => int_a0(8)
);
\int_a[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(9),
O => int_a0(9)
);
\int_a_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(0),
Q => \^a_read_reg_107_reg[15]\(0),
R => \^sr\(0)
);
\int_a_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(10),
Q => \^a_read_reg_107_reg[15]\(10),
R => \^sr\(0)
);
\int_a_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(11),
Q => \^a_read_reg_107_reg[15]\(11),
R => \^sr\(0)
);
\int_a_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(12),
Q => \^a_read_reg_107_reg[15]\(12),
R => \^sr\(0)
);
\int_a_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(13),
Q => \^a_read_reg_107_reg[15]\(13),
R => \^sr\(0)
);
\int_a_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(14),
Q => \^a_read_reg_107_reg[15]\(14),
R => \^sr\(0)
);
\int_a_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(15),
Q => \^a_read_reg_107_reg[15]\(15),
R => \^sr\(0)
);
\int_a_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(1),
Q => \^a_read_reg_107_reg[15]\(1),
R => \^sr\(0)
);
\int_a_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(2),
Q => \^a_read_reg_107_reg[15]\(2),
R => \^sr\(0)
);
\int_a_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(3),
Q => \^a_read_reg_107_reg[15]\(3),
R => \^sr\(0)
);
\int_a_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(4),
Q => \^a_read_reg_107_reg[15]\(4),
R => \^sr\(0)
);
\int_a_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(5),
Q => \^a_read_reg_107_reg[15]\(5),
R => \^sr\(0)
);
\int_a_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(6),
Q => \^a_read_reg_107_reg[15]\(6),
R => \^sr\(0)
);
\int_a_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(7),
Q => \^a_read_reg_107_reg[15]\(7),
R => \^sr\(0)
);
\int_a_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(8),
Q => \^a_read_reg_107_reg[15]\(8),
R => \^sr\(0)
);
\int_a_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(9),
Q => \^a_read_reg_107_reg[15]\(9),
R => \^sr\(0)
);
int_ap_done_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_ap_done1,
I5 => int_ap_done,
O => int_ap_done_i_1_n_0
);
int_ap_done_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(2),
O => int_ap_done1
);
int_ap_done_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_done_i_1_n_0,
Q => int_ap_done,
R => \^sr\(0)
);
int_ap_idle_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => ap_idle
);
int_ap_idle_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_idle,
Q => int_ap_idle,
R => \^sr\(0)
);
int_ap_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^co\(0),
I1 => Q(2),
O => ap_done
);
int_ap_ready_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_done,
Q => int_ap_ready,
R => \^sr\(0)
);
int_ap_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBFFF80"
)
port map (
I0 => int_auto_restart,
I1 => Q(2),
I2 => \^co\(0),
I3 => int_ap_start3_out,
I4 => ap_start,
O => int_ap_start_i_1_n_0
);
int_ap_start_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(0),
I1 => \p_s_reg_45_reg[15]\(0),
I2 => \p_s_reg_45_reg[15]\(2),
I3 => \result_reg_56_reg[15]\(2),
I4 => \p_s_reg_45_reg[15]\(1),
I5 => \result_reg_56_reg[15]\(1),
O => int_ap_start_i_10_n_0
);
int_ap_start_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[2]\,
I3 => \int_ier[1]_i_2_n_0\,
I4 => \waddr_reg_n_0_[3]\,
O => int_ap_start3_out
);
int_ap_start_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \p_s_reg_45_reg[15]\(15),
I1 => \result_reg_56_reg[15]\(15),
O => int_ap_start_i_5_n_0
);
int_ap_start_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(12),
I1 => \p_s_reg_45_reg[15]\(12),
I2 => \p_s_reg_45_reg[15]\(14),
I3 => \result_reg_56_reg[15]\(14),
I4 => \p_s_reg_45_reg[15]\(13),
I5 => \result_reg_56_reg[15]\(13),
O => int_ap_start_i_6_n_0
);
int_ap_start_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(9),
I1 => \p_s_reg_45_reg[15]\(9),
I2 => \p_s_reg_45_reg[15]\(11),
I3 => \result_reg_56_reg[15]\(11),
I4 => \p_s_reg_45_reg[15]\(10),
I5 => \result_reg_56_reg[15]\(10),
O => int_ap_start_i_7_n_0
);
int_ap_start_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(6),
I1 => \p_s_reg_45_reg[15]\(6),
I2 => \p_s_reg_45_reg[15]\(8),
I3 => \result_reg_56_reg[15]\(8),
I4 => \p_s_reg_45_reg[15]\(7),
I5 => \result_reg_56_reg[15]\(7),
O => int_ap_start_i_8_n_0
);
int_ap_start_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(3),
I1 => \p_s_reg_45_reg[15]\(3),
I2 => \p_s_reg_45_reg[15]\(5),
I3 => \result_reg_56_reg[15]\(5),
I4 => \p_s_reg_45_reg[15]\(4),
I5 => \result_reg_56_reg[15]\(4),
O => int_ap_start_i_9_n_0
);
int_ap_start_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_start_i_1_n_0,
Q => ap_start,
R => \^sr\(0)
);
int_ap_start_reg_i_2: unisim.vcomponents.CARRY4
port map (
CI => int_ap_start_reg_i_4_n_0,
CO(3 downto 2) => NLW_int_ap_start_reg_i_2_CO_UNCONNECTED(3 downto 2),
CO(1) => \^co\(0),
CO(0) => int_ap_start_reg_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_2_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => int_ap_start_i_5_n_0,
S(0) => int_ap_start_i_6_n_0
);
int_ap_start_reg_i_4: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => int_ap_start_reg_i_4_n_0,
CO(2) => int_ap_start_reg_i_4_n_1,
CO(1) => int_ap_start_reg_i_4_n_2,
CO(0) => int_ap_start_reg_i_4_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_4_O_UNCONNECTED(3 downto 0),
S(3) => int_ap_start_i_7_n_0,
S(2) => int_ap_start_i_8_n_0,
S(1) => int_ap_start_i_9_n_0,
S(0) => int_ap_start_i_10_n_0
);
int_auto_restart_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => \waddr_reg_n_0_[3]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => s_axi_gcd_bus_WSTRB(0),
I5 => int_auto_restart,
O => int_auto_restart_i_1_n_0
);
int_auto_restart_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_auto_restart_i_1_n_0,
Q => int_auto_restart,
R => \^sr\(0)
);
\int_b[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(0),
O => int_b0(0)
);
\int_b[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(10),
O => int_b0(10)
);
\int_b[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(11),
O => int_b0(11)
);
\int_b[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(12),
O => int_b0(12)
);
\int_b[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(13),
O => int_b0(13)
);
\int_b[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(14),
O => int_b0(14)
);
\int_b[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \waddr_reg_n_0_[3]\,
I1 => \waddr_reg_n_0_[4]\,
I2 => \int_a[15]_i_3_n_0\,
I3 => \waddr_reg_n_0_[2]\,
O => \int_b[15]_i_1_n_0\
);
\int_b[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(15),
O => int_b0(15)
);
\int_b[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(1),
O => int_b0(1)
);
\int_b[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(2),
O => int_b0(2)
);
\int_b[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(3),
O => int_b0(3)
);
\int_b[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(4),
O => int_b0(4)
);
\int_b[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(5),
O => int_b0(5)
);
\int_b[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(6),
O => int_b0(6)
);
\int_b[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(7),
O => int_b0(7)
);
\int_b[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(8),
O => int_b0(8)
);
\int_b[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(9),
O => int_b0(9)
);
\int_b_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(0),
Q => \^b_read_reg_102_reg[15]\(0),
R => \^sr\(0)
);
\int_b_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(10),
Q => \^b_read_reg_102_reg[15]\(10),
R => \^sr\(0)
);
\int_b_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(11),
Q => \^b_read_reg_102_reg[15]\(11),
R => \^sr\(0)
);
\int_b_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(12),
Q => \^b_read_reg_102_reg[15]\(12),
R => \^sr\(0)
);
\int_b_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(13),
Q => \^b_read_reg_102_reg[15]\(13),
R => \^sr\(0)
);
\int_b_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(14),
Q => \^b_read_reg_102_reg[15]\(14),
R => \^sr\(0)
);
\int_b_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(15),
Q => \^b_read_reg_102_reg[15]\(15),
R => \^sr\(0)
);
\int_b_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(1),
Q => \^b_read_reg_102_reg[15]\(1),
R => \^sr\(0)
);
\int_b_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(2),
Q => \^b_read_reg_102_reg[15]\(2),
R => \^sr\(0)
);
\int_b_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(3),
Q => \^b_read_reg_102_reg[15]\(3),
R => \^sr\(0)
);
\int_b_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(4),
Q => \^b_read_reg_102_reg[15]\(4),
R => \^sr\(0)
);
\int_b_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(5),
Q => \^b_read_reg_102_reg[15]\(5),
R => \^sr\(0)
);
\int_b_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(6),
Q => \^b_read_reg_102_reg[15]\(6),
R => \^sr\(0)
);
\int_b_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(7),
Q => \^b_read_reg_102_reg[15]\(7),
R => \^sr\(0)
);
\int_b_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(8),
Q => \^b_read_reg_102_reg[15]\(8),
R => \^sr\(0)
);
\int_b_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(9),
Q => \^b_read_reg_102_reg[15]\(9),
R => \^sr\(0)
);
int_gie_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[3]\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \int_ier[1]_i_2_n_0\,
I5 => int_gie_reg_n_0,
O => int_gie_i_1_n_0
);
int_gie_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_gie_i_1_n_0,
Q => int_gie_reg_n_0,
R => \^sr\(0)
);
\int_ier[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[0]\,
O => \int_ier[0]_i_1_n_0\
);
\int_ier[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[1]\,
O => \int_ier[1]_i_1_n_0\
);
\int_ier[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \waddr_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_WVALID,
I2 => \^out\(1),
I3 => \waddr_reg_n_0_[5]\,
I4 => \waddr_reg_n_0_[0]\,
I5 => \waddr_reg_n_0_[4]\,
O => \int_ier[1]_i_2_n_0\
);
\int_ier_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[0]_i_1_n_0\,
Q => \int_ier_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_ier_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[1]_i_1_n_0\,
Q => \int_ier_reg_n_0_[1]\,
R => \^sr\(0)
);
\int_isr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[0]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => \int_isr_reg_n_0_[0]\,
O => \int_isr[0]_i_1_n_0\
);
\int_isr[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_gcd_bus_WSTRB(0),
I1 => \waddr_reg_n_0_[2]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[3]\,
O => int_isr6_out
);
\int_isr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[1]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => p_1_in,
O => \int_isr[1]_i_1_n_0\
);
\int_isr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[0]_i_1_n_0\,
Q => \int_isr_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_isr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[1]_i_1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
int_pResult_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_pResult_ap_vld1,
I5 => int_pResult_ap_vld,
O => int_pResult_ap_vld_i_1_n_0
);
int_pResult_ap_vld_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(5),
I3 => s_axi_gcd_bus_ARADDR(2),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(0),
O => int_pResult_ap_vld1
);
int_pResult_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_pResult_ap_vld_i_1_n_0,
Q => int_pResult_ap_vld,
R => \^sr\(0)
);
\int_pResult_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(0),
Q => int_pResult(0),
R => \^sr\(0)
);
\int_pResult_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(10),
Q => int_pResult(10),
R => \^sr\(0)
);
\int_pResult_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(11),
Q => int_pResult(11),
R => \^sr\(0)
);
\int_pResult_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(12),
Q => int_pResult(12),
R => \^sr\(0)
);
\int_pResult_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(13),
Q => int_pResult(13),
R => \^sr\(0)
);
\int_pResult_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(14),
Q => int_pResult(14),
R => \^sr\(0)
);
\int_pResult_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(15),
Q => int_pResult(15),
R => \^sr\(0)
);
\int_pResult_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(1),
Q => int_pResult(1),
R => \^sr\(0)
);
\int_pResult_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(2),
Q => int_pResult(2),
R => \^sr\(0)
);
\int_pResult_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(3),
Q => int_pResult(3),
R => \^sr\(0)
);
\int_pResult_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(4),
Q => int_pResult(4),
R => \^sr\(0)
);
\int_pResult_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(5),
Q => int_pResult(5),
R => \^sr\(0)
);
\int_pResult_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(6),
Q => int_pResult(6),
R => \^sr\(0)
);
\int_pResult_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(7),
Q => int_pResult(7),
R => \^sr\(0)
);
\int_pResult_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(8),
Q => int_pResult(8),
R => \^sr\(0)
);
\int_pResult_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(9),
Q => int_pResult(9),
R => \^sr\(0)
);
interrupt_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => p_1_in,
I1 => \int_isr_reg_n_0_[0]\,
I2 => int_gie_reg_n_0,
O => interrupt
);
\rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[0]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(0),
O => \rdata[0]_i_1_n_0\
);
\rdata[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[0]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[0]_i_4_n_0\,
O => \rdata[0]_i_2_n_0\
);
\rdata[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033223000002230"
)
port map (
I0 => int_pResult_ap_vld,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_gie_reg_n_0,
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \int_isr_reg_n_0_[0]\,
O => \rdata[0]_i_3_n_0\
);
\rdata[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(0),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => ap_start,
O => \rdata[0]_i_4_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(10),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(10),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(11),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(11),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(12),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(12),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(13),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(13),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(14),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(14),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88888880"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(2),
O => \rdata[15]_i_1_n_0\
);
\rdata[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_gcd_bus_rvalid\(0),
I1 => s_axi_gcd_bus_ARVALID,
O => ar_hs
);
\rdata[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(15),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(15),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(15),
O => \rdata[15]_i_3_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[1]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[1]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(1),
O => \rdata[1]_i_1_n_0\
);
\rdata[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[1]_i_5_n_0\,
O => \rdata[1]_i_2_n_0\
);
\rdata[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(4),
I1 => s_axi_gcd_bus_ARADDR(5),
I2 => s_axi_gcd_bus_ARADDR(3),
I3 => p_1_in,
O => \rdata[1]_i_3_n_0\
);
\rdata[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(0),
O => \rdata[1]_i_4_n_0\
);
\rdata[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_done,
O => \rdata[1]_i_5_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(2),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[2]_i_2_n_0\,
O => \rdata[2]_i_1_n_0\
);
\rdata[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(2),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(2),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_idle,
O => \rdata[2]_i_2_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(3),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[3]_i_2_n_0\,
O => \rdata[3]_i_1_n_0\
);
\rdata[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(3),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(3),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_ready,
O => \rdata[3]_i_2_n_0\
);
\rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(4),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(4),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(5),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(5),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(6),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(6),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(7),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[7]_i_2_n_0\,
O => \rdata[7]_i_1_n_0\
);
\rdata[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(7),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(7),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_auto_restart,
O => \rdata[7]_i_2_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(8),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(8),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(9),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(9),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[0]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(10),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(11),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(12),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(13),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(14),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_3_n_0\,
Q => \^s_axi_gcd_bus_rdata\(15),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(1),
R => '0'
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(2),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[3]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(3),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(4),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(5),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(6),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[7]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(7),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(8),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(9),
R => \rdata[15]_i_1_n_0\
);
\waddr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^out\(0),
I1 => s_axi_gcd_bus_AWVALID,
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
\waddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(5),
Q => \waddr_reg_n_0_[5]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt : out STD_LOGIC
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b1000";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
signal \<const0>\ : STD_LOGIC;
signal a : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_fu_78_p21_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_121 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_1210 : STD_LOGIC;
signal \a_assign_reg_121[11]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_3\ : STD_LOGIC;
signal a_read_reg_107 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
signal ap_CS_fsm_state4 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal b : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_fu_84_p20_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_reg_126 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \b_assign_reg_126[11]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_3\ : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_s_reg_45 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \p_s_reg_45[0]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[10]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[11]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[12]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[13]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[14]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_2_n_0\ : STD_LOGIC;
signal \p_s_reg_45[1]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[2]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[3]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[4]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[5]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[6]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[7]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[8]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[9]_i_1_n_0\ : STD_LOGIC;
signal result_reg_56 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \result_reg_56[15]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal tmp_2_fu_66_p2 : STD_LOGIC;
signal tmp_3_fu_72_p2 : STD_LOGIC;
signal tmp_3_reg_115 : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_10_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_11_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_12_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_13_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_14_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_15_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_16_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_17_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_18_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_3_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_4_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_5_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_6_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_7_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_8_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_9_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none";
begin
s_axi_gcd_bus_BRESP(1) <= \<const0>\;
s_axi_gcd_bus_BRESP(0) <= \<const0>\;
s_axi_gcd_bus_RDATA(31) <= \<const0>\;
s_axi_gcd_bus_RDATA(30) <= \<const0>\;
s_axi_gcd_bus_RDATA(29) <= \<const0>\;
s_axi_gcd_bus_RDATA(28) <= \<const0>\;
s_axi_gcd_bus_RDATA(27) <= \<const0>\;
s_axi_gcd_bus_RDATA(26) <= \<const0>\;
s_axi_gcd_bus_RDATA(25) <= \<const0>\;
s_axi_gcd_bus_RDATA(24) <= \<const0>\;
s_axi_gcd_bus_RDATA(23) <= \<const0>\;
s_axi_gcd_bus_RDATA(22) <= \<const0>\;
s_axi_gcd_bus_RDATA(21) <= \<const0>\;
s_axi_gcd_bus_RDATA(20) <= \<const0>\;
s_axi_gcd_bus_RDATA(19) <= \<const0>\;
s_axi_gcd_bus_RDATA(18) <= \<const0>\;
s_axi_gcd_bus_RDATA(17) <= \<const0>\;
s_axi_gcd_bus_RDATA(16) <= \<const0>\;
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RRESP(1) <= \<const0>\;
s_axi_gcd_bus_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\a_assign_reg_121[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(11),
I1 => p_s_reg_45(11),
O => \a_assign_reg_121[11]_i_2_n_0\
);
\a_assign_reg_121[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
O => \a_assign_reg_121[11]_i_3_n_0\
);
\a_assign_reg_121[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(9),
I1 => p_s_reg_45(9),
O => \a_assign_reg_121[11]_i_4_n_0\
);
\a_assign_reg_121[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
O => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(15),
I1 => p_s_reg_45(15),
O => \a_assign_reg_121[15]_i_2_n_0\
);
\a_assign_reg_121[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
O => \a_assign_reg_121[15]_i_3_n_0\
);
\a_assign_reg_121[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(13),
I1 => p_s_reg_45(13),
O => \a_assign_reg_121[15]_i_4_n_0\
);
\a_assign_reg_121[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
O => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(3),
I1 => p_s_reg_45(3),
O => \a_assign_reg_121[3]_i_2_n_0\
);
\a_assign_reg_121[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
O => \a_assign_reg_121[3]_i_3_n_0\
);
\a_assign_reg_121[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(1),
I1 => p_s_reg_45(1),
O => \a_assign_reg_121[3]_i_4_n_0\
);
\a_assign_reg_121[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
O => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(7),
I1 => p_s_reg_45(7),
O => \a_assign_reg_121[7]_i_2_n_0\
);
\a_assign_reg_121[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
O => \a_assign_reg_121[7]_i_3_n_0\
);
\a_assign_reg_121[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(5),
I1 => p_s_reg_45(5),
O => \a_assign_reg_121[7]_i_4_n_0\
);
\a_assign_reg_121[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
O => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(0),
Q => a_assign_reg_121(0),
R => '0'
);
\a_assign_reg_121_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(10),
Q => a_assign_reg_121(10),
R => '0'
);
\a_assign_reg_121_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(11),
Q => a_assign_reg_121(11),
R => '0'
);
\a_assign_reg_121_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[11]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[11]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(11 downto 8),
O(3 downto 0) => a_assign_fu_78_p21_out(11 downto 8),
S(3) => \a_assign_reg_121[11]_i_2_n_0\,
S(2) => \a_assign_reg_121[11]_i_3_n_0\,
S(1) => \a_assign_reg_121[11]_i_4_n_0\,
S(0) => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(12),
Q => a_assign_reg_121(12),
R => '0'
);
\a_assign_reg_121_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(13),
Q => a_assign_reg_121(13),
R => '0'
);
\a_assign_reg_121_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(14),
Q => a_assign_reg_121(14),
R => '0'
);
\a_assign_reg_121_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(15),
Q => a_assign_reg_121(15),
R => '0'
);
\a_assign_reg_121_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(3) => \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \a_assign_reg_121_reg[15]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[15]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => result_reg_56(14 downto 12),
O(3 downto 0) => a_assign_fu_78_p21_out(15 downto 12),
S(3) => \a_assign_reg_121[15]_i_2_n_0\,
S(2) => \a_assign_reg_121[15]_i_3_n_0\,
S(1) => \a_assign_reg_121[15]_i_4_n_0\,
S(0) => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(1),
Q => a_assign_reg_121(1),
R => '0'
);
\a_assign_reg_121_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(2),
Q => a_assign_reg_121(2),
R => '0'
);
\a_assign_reg_121_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(3),
Q => a_assign_reg_121(3),
R => '0'
);
\a_assign_reg_121_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[3]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[3]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => result_reg_56(3 downto 0),
O(3 downto 0) => a_assign_fu_78_p21_out(3 downto 0),
S(3) => \a_assign_reg_121[3]_i_2_n_0\,
S(2) => \a_assign_reg_121[3]_i_3_n_0\,
S(1) => \a_assign_reg_121[3]_i_4_n_0\,
S(0) => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(4),
Q => a_assign_reg_121(4),
R => '0'
);
\a_assign_reg_121_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(5),
Q => a_assign_reg_121(5),
R => '0'
);
\a_assign_reg_121_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(6),
Q => a_assign_reg_121(6),
R => '0'
);
\a_assign_reg_121_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(7),
Q => a_assign_reg_121(7),
R => '0'
);
\a_assign_reg_121_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[7]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[7]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(7 downto 4),
O(3 downto 0) => a_assign_fu_78_p21_out(7 downto 4),
S(3) => \a_assign_reg_121[7]_i_2_n_0\,
S(2) => \a_assign_reg_121[7]_i_3_n_0\,
S(1) => \a_assign_reg_121[7]_i_4_n_0\,
S(0) => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(8),
Q => a_assign_reg_121(8),
R => '0'
);
\a_assign_reg_121_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(9),
Q => a_assign_reg_121(9),
R => '0'
);
\a_read_reg_107_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(0),
Q => a_read_reg_107(0),
R => '0'
);
\a_read_reg_107_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(10),
Q => a_read_reg_107(10),
R => '0'
);
\a_read_reg_107_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(11),
Q => a_read_reg_107(11),
R => '0'
);
\a_read_reg_107_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(12),
Q => a_read_reg_107(12),
R => '0'
);
\a_read_reg_107_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(13),
Q => a_read_reg_107(13),
R => '0'
);
\a_read_reg_107_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(14),
Q => a_read_reg_107(14),
R => '0'
);
\a_read_reg_107_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(15),
Q => a_read_reg_107(15),
R => '0'
);
\a_read_reg_107_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(1),
Q => a_read_reg_107(1),
R => '0'
);
\a_read_reg_107_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(2),
Q => a_read_reg_107(2),
R => '0'
);
\a_read_reg_107_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(3),
Q => a_read_reg_107(3),
R => '0'
);
\a_read_reg_107_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(4),
Q => a_read_reg_107(4),
R => '0'
);
\a_read_reg_107_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(5),
Q => a_read_reg_107(5),
R => '0'
);
\a_read_reg_107_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(6),
Q => a_read_reg_107(6),
R => '0'
);
\a_read_reg_107_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(7),
Q => a_read_reg_107(7),
R => '0'
);
\a_read_reg_107_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(8),
Q => a_read_reg_107(8),
R => '0'
);
\a_read_reg_107_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(9),
Q => a_read_reg_107(9),
R => '0'
);
\ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ap_CS_fsm_state2,
I1 => ap_CS_fsm_state4,
O => ap_NS_fsm(2)
);
\ap_CS_fsm[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ap_CS_fsm_state3,
I1 => tmp_2_fu_66_p2,
O => a_assign_reg_1210
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(2),
Q => ap_CS_fsm_state3,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => a_assign_reg_1210,
Q => ap_CS_fsm_state4,
R => ap_rst_n_inv
);
\b_assign_reg_126[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(11),
I1 => result_reg_56(11),
O => \b_assign_reg_126[11]_i_2_n_0\
);
\b_assign_reg_126[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(10),
I1 => result_reg_56(10),
O => \b_assign_reg_126[11]_i_3_n_0\
);
\b_assign_reg_126[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(9),
I1 => result_reg_56(9),
O => \b_assign_reg_126[11]_i_4_n_0\
);
\b_assign_reg_126[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(8),
I1 => result_reg_56(8),
O => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(15),
I1 => result_reg_56(15),
O => \b_assign_reg_126[15]_i_2_n_0\
);
\b_assign_reg_126[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(14),
I1 => result_reg_56(14),
O => \b_assign_reg_126[15]_i_3_n_0\
);
\b_assign_reg_126[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(13),
I1 => result_reg_56(13),
O => \b_assign_reg_126[15]_i_4_n_0\
);
\b_assign_reg_126[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(12),
I1 => result_reg_56(12),
O => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(3),
I1 => result_reg_56(3),
O => \b_assign_reg_126[3]_i_2_n_0\
);
\b_assign_reg_126[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(2),
I1 => result_reg_56(2),
O => \b_assign_reg_126[3]_i_3_n_0\
);
\b_assign_reg_126[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(1),
I1 => result_reg_56(1),
O => \b_assign_reg_126[3]_i_4_n_0\
);
\b_assign_reg_126[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(0),
I1 => result_reg_56(0),
O => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(7),
I1 => result_reg_56(7),
O => \b_assign_reg_126[7]_i_2_n_0\
);
\b_assign_reg_126[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(6),
I1 => result_reg_56(6),
O => \b_assign_reg_126[7]_i_3_n_0\
);
\b_assign_reg_126[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(5),
I1 => result_reg_56(5),
O => \b_assign_reg_126[7]_i_4_n_0\
);
\b_assign_reg_126[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(4),
I1 => result_reg_56(4),
O => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(0),
Q => b_assign_reg_126(0),
R => '0'
);
\b_assign_reg_126_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(10),
Q => b_assign_reg_126(10),
R => '0'
);
\b_assign_reg_126_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(11),
Q => b_assign_reg_126(11),
R => '0'
);
\b_assign_reg_126_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[11]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[11]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(11 downto 8),
O(3 downto 0) => b_assign_fu_84_p20_out(11 downto 8),
S(3) => \b_assign_reg_126[11]_i_2_n_0\,
S(2) => \b_assign_reg_126[11]_i_3_n_0\,
S(1) => \b_assign_reg_126[11]_i_4_n_0\,
S(0) => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(12),
Q => b_assign_reg_126(12),
R => '0'
);
\b_assign_reg_126_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(13),
Q => b_assign_reg_126(13),
R => '0'
);
\b_assign_reg_126_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(14),
Q => b_assign_reg_126(14),
R => '0'
);
\b_assign_reg_126_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(15),
Q => b_assign_reg_126(15),
R => '0'
);
\b_assign_reg_126_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(3) => \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \b_assign_reg_126_reg[15]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[15]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => p_s_reg_45(14 downto 12),
O(3 downto 0) => b_assign_fu_84_p20_out(15 downto 12),
S(3) => \b_assign_reg_126[15]_i_2_n_0\,
S(2) => \b_assign_reg_126[15]_i_3_n_0\,
S(1) => \b_assign_reg_126[15]_i_4_n_0\,
S(0) => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(1),
Q => b_assign_reg_126(1),
R => '0'
);
\b_assign_reg_126_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(2),
Q => b_assign_reg_126(2),
R => '0'
);
\b_assign_reg_126_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(3),
Q => b_assign_reg_126(3),
R => '0'
);
\b_assign_reg_126_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[3]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[3]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_s_reg_45(3 downto 0),
O(3 downto 0) => b_assign_fu_84_p20_out(3 downto 0),
S(3) => \b_assign_reg_126[3]_i_2_n_0\,
S(2) => \b_assign_reg_126[3]_i_3_n_0\,
S(1) => \b_assign_reg_126[3]_i_4_n_0\,
S(0) => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(4),
Q => b_assign_reg_126(4),
R => '0'
);
\b_assign_reg_126_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(5),
Q => b_assign_reg_126(5),
R => '0'
);
\b_assign_reg_126_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(6),
Q => b_assign_reg_126(6),
R => '0'
);
\b_assign_reg_126_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(7),
Q => b_assign_reg_126(7),
R => '0'
);
\b_assign_reg_126_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[7]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[7]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(7 downto 4),
O(3 downto 0) => b_assign_fu_84_p20_out(7 downto 4),
S(3) => \b_assign_reg_126[7]_i_2_n_0\,
S(2) => \b_assign_reg_126[7]_i_3_n_0\,
S(1) => \b_assign_reg_126[7]_i_4_n_0\,
S(0) => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(8),
Q => b_assign_reg_126(8),
R => '0'
);
\b_assign_reg_126_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(9),
Q => b_assign_reg_126(9),
R => '0'
);
\b_read_reg_102_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(0),
Q => b_read_reg_102(0),
R => '0'
);
\b_read_reg_102_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(10),
Q => b_read_reg_102(10),
R => '0'
);
\b_read_reg_102_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(11),
Q => b_read_reg_102(11),
R => '0'
);
\b_read_reg_102_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(12),
Q => b_read_reg_102(12),
R => '0'
);
\b_read_reg_102_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(13),
Q => b_read_reg_102(13),
R => '0'
);
\b_read_reg_102_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(14),
Q => b_read_reg_102(14),
R => '0'
);
\b_read_reg_102_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(15),
Q => b_read_reg_102(15),
R => '0'
);
\b_read_reg_102_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(1),
Q => b_read_reg_102(1),
R => '0'
);
\b_read_reg_102_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(2),
Q => b_read_reg_102(2),
R => '0'
);
\b_read_reg_102_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(3),
Q => b_read_reg_102(3),
R => '0'
);
\b_read_reg_102_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(4),
Q => b_read_reg_102(4),
R => '0'
);
\b_read_reg_102_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(5),
Q => b_read_reg_102(5),
R => '0'
);
\b_read_reg_102_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(6),
Q => b_read_reg_102(6),
R => '0'
);
\b_read_reg_102_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(7),
Q => b_read_reg_102(7),
R => '0'
);
\b_read_reg_102_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(8),
Q => b_read_reg_102(8),
R => '0'
);
\b_read_reg_102_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(9),
Q => b_read_reg_102(9),
R => '0'
);
gcd_gcd_bus_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi
port map (
CO(0) => tmp_2_fu_66_p2,
D(1 downto 0) => ap_NS_fsm(1 downto 0),
E(0) => ap_NS_fsm1,
Q(3) => ap_CS_fsm_state4,
Q(2) => ap_CS_fsm_state3,
Q(1) => ap_CS_fsm_state2,
Q(0) => \ap_CS_fsm_reg_n_0_[0]\,
SR(0) => ap_rst_n_inv,
\a_read_reg_107_reg[15]\(15 downto 0) => a(15 downto 0),
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\b_read_reg_102_reg[15]\(15 downto 0) => b(15 downto 0),
interrupt => interrupt,
\out\(2) => s_axi_gcd_bus_BVALID,
\out\(1) => s_axi_gcd_bus_WREADY,
\out\(0) => s_axi_gcd_bus_AWREADY,
\p_s_reg_45_reg[15]\(15 downto 0) => p_s_reg_45(15 downto 0),
\result_reg_56_reg[15]\(15 downto 0) => result_reg_56(15 downto 0),
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_RDATA(15 downto 0) => \^s_axi_gcd_bus_rdata\(15 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RVALID(1) => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RVALID(0) => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_WDATA(15 downto 0) => s_axi_gcd_bus_WDATA(15 downto 0),
s_axi_gcd_bus_WSTRB(1 downto 0) => s_axi_gcd_bus_WSTRB(1 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
\p_s_reg_45[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(0),
I1 => b_read_reg_102(0),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[0]_i_1_n_0\
);
\p_s_reg_45[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(10),
I1 => b_read_reg_102(10),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[10]_i_1_n_0\
);
\p_s_reg_45[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(11),
I1 => b_read_reg_102(11),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[11]_i_1_n_0\
);
\p_s_reg_45[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(12),
I1 => b_read_reg_102(12),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[12]_i_1_n_0\
);
\p_s_reg_45[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(13),
I1 => b_read_reg_102(13),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[13]_i_1_n_0\
);
\p_s_reg_45[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(14),
I1 => b_read_reg_102(14),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[14]_i_1_n_0\
);
\p_s_reg_45[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \p_s_reg_45[15]_i_1_n_0\
);
\p_s_reg_45[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(15),
I1 => b_read_reg_102(15),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[15]_i_2_n_0\
);
\p_s_reg_45[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(1),
I1 => b_read_reg_102(1),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[1]_i_1_n_0\
);
\p_s_reg_45[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(2),
I1 => b_read_reg_102(2),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[2]_i_1_n_0\
);
\p_s_reg_45[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(3),
I1 => b_read_reg_102(3),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[3]_i_1_n_0\
);
\p_s_reg_45[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(4),
I1 => b_read_reg_102(4),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[4]_i_1_n_0\
);
\p_s_reg_45[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(5),
I1 => b_read_reg_102(5),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[5]_i_1_n_0\
);
\p_s_reg_45[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(6),
I1 => b_read_reg_102(6),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[6]_i_1_n_0\
);
\p_s_reg_45[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(7),
I1 => b_read_reg_102(7),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[7]_i_1_n_0\
);
\p_s_reg_45[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(8),
I1 => b_read_reg_102(8),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[8]_i_1_n_0\
);
\p_s_reg_45[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(9),
I1 => b_read_reg_102(9),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[9]_i_1_n_0\
);
\p_s_reg_45_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[0]_i_1_n_0\,
Q => p_s_reg_45(0),
R => '0'
);
\p_s_reg_45_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[10]_i_1_n_0\,
Q => p_s_reg_45(10),
R => '0'
);
\p_s_reg_45_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[11]_i_1_n_0\,
Q => p_s_reg_45(11),
R => '0'
);
\p_s_reg_45_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[12]_i_1_n_0\,
Q => p_s_reg_45(12),
R => '0'
);
\p_s_reg_45_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[13]_i_1_n_0\,
Q => p_s_reg_45(13),
R => '0'
);
\p_s_reg_45_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[14]_i_1_n_0\,
Q => p_s_reg_45(14),
R => '0'
);
\p_s_reg_45_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[15]_i_2_n_0\,
Q => p_s_reg_45(15),
R => '0'
);
\p_s_reg_45_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[1]_i_1_n_0\,
Q => p_s_reg_45(1),
R => '0'
);
\p_s_reg_45_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[2]_i_1_n_0\,
Q => p_s_reg_45(2),
R => '0'
);
\p_s_reg_45_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[3]_i_1_n_0\,
Q => p_s_reg_45(3),
R => '0'
);
\p_s_reg_45_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[4]_i_1_n_0\,
Q => p_s_reg_45(4),
R => '0'
);
\p_s_reg_45_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[5]_i_1_n_0\,
Q => p_s_reg_45(5),
R => '0'
);
\p_s_reg_45_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[6]_i_1_n_0\,
Q => p_s_reg_45(6),
R => '0'
);
\p_s_reg_45_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[7]_i_1_n_0\,
Q => p_s_reg_45(7),
R => '0'
);
\p_s_reg_45_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[8]_i_1_n_0\,
Q => p_s_reg_45(8),
R => '0'
);
\p_s_reg_45_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[9]_i_1_n_0\,
Q => p_s_reg_45(9),
R => '0'
);
\result_reg_56[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(0),
I1 => a_read_reg_107(0),
I2 => ap_CS_fsm_state4,
O => p_1_in(0)
);
\result_reg_56[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(10),
I1 => a_read_reg_107(10),
I2 => ap_CS_fsm_state4,
O => p_1_in(10)
);
\result_reg_56[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(11),
I1 => a_read_reg_107(11),
I2 => ap_CS_fsm_state4,
O => p_1_in(11)
);
\result_reg_56[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(12),
I1 => a_read_reg_107(12),
I2 => ap_CS_fsm_state4,
O => p_1_in(12)
);
\result_reg_56[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(13),
I1 => a_read_reg_107(13),
I2 => ap_CS_fsm_state4,
O => p_1_in(13)
);
\result_reg_56[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(14),
I1 => a_read_reg_107(14),
I2 => ap_CS_fsm_state4,
O => p_1_in(14)
);
\result_reg_56[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \result_reg_56[15]_i_1_n_0\
);
\result_reg_56[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(15),
I1 => a_read_reg_107(15),
I2 => ap_CS_fsm_state4,
O => p_1_in(15)
);
\result_reg_56[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(1),
I1 => a_read_reg_107(1),
I2 => ap_CS_fsm_state4,
O => p_1_in(1)
);
\result_reg_56[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(2),
I1 => a_read_reg_107(2),
I2 => ap_CS_fsm_state4,
O => p_1_in(2)
);
\result_reg_56[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(3),
I1 => a_read_reg_107(3),
I2 => ap_CS_fsm_state4,
O => p_1_in(3)
);
\result_reg_56[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(4),
I1 => a_read_reg_107(4),
I2 => ap_CS_fsm_state4,
O => p_1_in(4)
);
\result_reg_56[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(5),
I1 => a_read_reg_107(5),
I2 => ap_CS_fsm_state4,
O => p_1_in(5)
);
\result_reg_56[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(6),
I1 => a_read_reg_107(6),
I2 => ap_CS_fsm_state4,
O => p_1_in(6)
);
\result_reg_56[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(7),
I1 => a_read_reg_107(7),
I2 => ap_CS_fsm_state4,
O => p_1_in(7)
);
\result_reg_56[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(8),
I1 => a_read_reg_107(8),
I2 => ap_CS_fsm_state4,
O => p_1_in(8)
);
\result_reg_56[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(9),
I1 => a_read_reg_107(9),
I2 => ap_CS_fsm_state4,
O => p_1_in(9)
);
\result_reg_56_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(0),
Q => result_reg_56(0),
R => '0'
);
\result_reg_56_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(10),
Q => result_reg_56(10),
R => '0'
);
\result_reg_56_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(11),
Q => result_reg_56(11),
R => '0'
);
\result_reg_56_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(12),
Q => result_reg_56(12),
R => '0'
);
\result_reg_56_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(13),
Q => result_reg_56(13),
R => '0'
);
\result_reg_56_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(14),
Q => result_reg_56(14),
R => '0'
);
\result_reg_56_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(15),
Q => result_reg_56(15),
R => '0'
);
\result_reg_56_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(1),
Q => result_reg_56(1),
R => '0'
);
\result_reg_56_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(2),
Q => result_reg_56(2),
R => '0'
);
\result_reg_56_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(3),
Q => result_reg_56(3),
R => '0'
);
\result_reg_56_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(4),
Q => result_reg_56(4),
R => '0'
);
\result_reg_56_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(5),
Q => result_reg_56(5),
R => '0'
);
\result_reg_56_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(6),
Q => result_reg_56(6),
R => '0'
);
\result_reg_56_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(7),
Q => result_reg_56(7),
R => '0'
);
\result_reg_56_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(8),
Q => result_reg_56(8),
R => '0'
);
\result_reg_56_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(9),
Q => result_reg_56(9),
R => '0'
);
\tmp_3_reg_115[0]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => result_reg_56(9),
I3 => p_s_reg_45(9),
O => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115[0]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => p_s_reg_45(7),
I3 => result_reg_56(7),
O => \tmp_3_reg_115[0]_i_11_n_0\
);
\tmp_3_reg_115[0]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => p_s_reg_45(5),
I3 => result_reg_56(5),
O => \tmp_3_reg_115[0]_i_12_n_0\
);
\tmp_3_reg_115[0]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => p_s_reg_45(3),
I3 => result_reg_56(3),
O => \tmp_3_reg_115[0]_i_13_n_0\
);
\tmp_3_reg_115[0]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => p_s_reg_45(1),
I3 => result_reg_56(1),
O => \tmp_3_reg_115[0]_i_14_n_0\
);
\tmp_3_reg_115[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => result_reg_56(7),
I3 => p_s_reg_45(7),
O => \tmp_3_reg_115[0]_i_15_n_0\
);
\tmp_3_reg_115[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => result_reg_56(5),
I3 => p_s_reg_45(5),
O => \tmp_3_reg_115[0]_i_16_n_0\
);
\tmp_3_reg_115[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => result_reg_56(3),
I3 => p_s_reg_45(3),
O => \tmp_3_reg_115[0]_i_17_n_0\
);
\tmp_3_reg_115[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => result_reg_56(1),
I3 => p_s_reg_45(1),
O => \tmp_3_reg_115[0]_i_18_n_0\
);
\tmp_3_reg_115[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => result_reg_56(15),
I3 => p_s_reg_45(15),
O => \tmp_3_reg_115[0]_i_3_n_0\
);
\tmp_3_reg_115[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => p_s_reg_45(13),
I3 => result_reg_56(13),
O => \tmp_3_reg_115[0]_i_4_n_0\
);
\tmp_3_reg_115[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => p_s_reg_45(11),
I3 => result_reg_56(11),
O => \tmp_3_reg_115[0]_i_5_n_0\
);
\tmp_3_reg_115[0]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => p_s_reg_45(9),
I3 => result_reg_56(9),
O => \tmp_3_reg_115[0]_i_6_n_0\
);
\tmp_3_reg_115[0]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => p_s_reg_45(15),
I3 => result_reg_56(15),
O => \tmp_3_reg_115[0]_i_7_n_0\
);
\tmp_3_reg_115[0]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => result_reg_56(13),
I3 => p_s_reg_45(13),
O => \tmp_3_reg_115[0]_i_8_n_0\
);
\tmp_3_reg_115[0]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => result_reg_56(11),
I3 => p_s_reg_45(11),
O => \tmp_3_reg_115[0]_i_9_n_0\
);
\tmp_3_reg_115_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => tmp_3_fu_72_p2,
Q => tmp_3_reg_115,
R => '0'
);
\tmp_3_reg_115_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(3) => tmp_3_fu_72_p2,
CO(2) => \tmp_3_reg_115_reg[0]_i_1_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_1_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_3_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_4_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_5_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_6_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_7_n_0\,
S(2) => \tmp_3_reg_115[0]_i_8_n_0\,
S(1) => \tmp_3_reg_115[0]_i_9_n_0\,
S(0) => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(2) => \tmp_3_reg_115_reg[0]_i_2_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_2_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_11_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_12_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_13_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_14_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_15_n_0\,
S(2) => \tmp_3_reg_115[0]_i_16_n_0\,
S(1) => \tmp_3_reg_115[0]_i_17_n_0\,
S(0) => \tmp_3_reg_115[0]_i_18_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_zynq_snick_gcd_0_0,gcd,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of inst : label is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of inst : label is "4'b1000";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_gcd_bus_RREADY : signal is "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARREADY => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWREADY => s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_BRESP(1 downto 0) => s_axi_gcd_bus_BRESP(1 downto 0),
s_axi_gcd_bus_BVALID => s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_RDATA(31 downto 0) => s_axi_gcd_bus_RDATA(31 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RRESP(1 downto 0) => s_axi_gcd_bus_RRESP(1 downto 0),
s_axi_gcd_bus_RVALID => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_WDATA(31 downto 0) => s_axi_gcd_bus_WDATA(31 downto 0),
s_axi_gcd_bus_WREADY => s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_WSTRB(3 downto 0) => s_axi_gcd_bus_WSTRB(3 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity ProgramCounterRegister_x16 is
port (
clock : in STD_LOGIC;
input: in STD_LOGIC_VECTOR(15 DOWNTO 0);
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end ProgramCounterRegister_x16;
architecture skeleton of ProgramCounterRegister_x16 is
begin
process (clock, input) is
begin
if (clock'event AND clock = '1') then
output <= input;
end if;
end process;
end skeleton; |
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_4 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 12.288 -fclkop 49.152 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -rst -fb_mode 1
-- Wed Jul 11 19:09:42 2018
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO3L;
use MACHXO3L.components.all;
-- synopsys translate_on
entity pll_4 is
port (
CLKI: in std_logic;
RST: in std_logic;
CLKOP: out std_logic);
end pll_4;
architecture Structure of pll_4 is
-- internal signal declarations
signal LOCK: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VLO
port (Z: out std_logic);
end component;
component EHXPLLJ
generic (INTFB_WAKE : in String; DDRST_ENA : in String;
DCRST_ENA : in String; MRST_ENA : in String;
PLLRST_ENA : in String; DPHASE_SOURCE : in String;
STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
OUTDIVIDER_MUXC2 : in String;
OUTDIVIDER_MUXB2 : in String;
OUTDIVIDER_MUXA2 : in String;
PREDIVIDER_MUXD1 : in Integer;
PREDIVIDER_MUXC1 : in Integer;
PREDIVIDER_MUXB1 : in Integer;
PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
PLL_LOCK_MODE : in Integer;
CLKOS_TRIM_DELAY : in Integer;
CLKOS_TRIM_POL : in String;
CLKOP_TRIM_DELAY : in Integer;
CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
FRACN_ENABLE : in String; FEEDBK_PATH : in String;
CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
port (CLKI: in std_logic; CLKFB: in std_logic;
PHASESEL1: in std_logic; PHASESEL0: in std_logic;
PHASEDIR: in std_logic; PHASESTEP: in std_logic;
LOADREG: in std_logic; STDBY: in std_logic;
PLLWAKESYNC: in std_logic; RST: in std_logic;
RESETM: in std_logic; RESETC: in std_logic;
RESETD: in std_logic; ENCLKOP: in std_logic;
ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
ENCLKOS3: in std_logic; PLLCLK: in std_logic;
PLLRST: in std_logic; PLLSTB: in std_logic;
PLLWE: in std_logic; PLLADDR4: in std_logic;
PLLADDR3: in std_logic; PLLADDR2: in std_logic;
PLLADDR1: in std_logic; PLLADDR0: in std_logic;
PLLDATI7: in std_logic; PLLDATI6: in std_logic;
PLLDATI5: in std_logic; PLLDATI4: in std_logic;
PLLDATI3: in std_logic; PLLDATI2: in std_logic;
PLLDATI1: in std_logic; PLLDATI0: in std_logic;
CLKOP: out std_logic; CLKOS: out std_logic;
CLKOS2: out std_logic; CLKOS3: out std_logic;
LOCK: out std_logic; INTLOCK: out std_logic;
REFCLK: out std_logic; CLKINTFB: out std_logic;
DPHSRC: out std_logic; PLLACK: out std_logic;
PLLDATO7: out std_logic; PLLDATO6: out std_logic;
PLLDATO5: out std_logic; PLLDATO4: out std_logic;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic);
end component;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "49.152000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "12.288000";
attribute ICP_CURRENT of PLLInst_0 : label is "8";
attribute LPF_RESISTOR of PLLInst_0 : label is "8";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLJ
generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
MRST_ENA=> "DISABLED", PLLRST_ENA=> "ENABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 10,
PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
CLKOS_DIV=> 1, CLKOP_DIV=> 11, CLKFB_DIV=> 4, CLKI_DIV=> 1,
FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
PLLWAKESYNC=>scuba_vlo, RST=>RST, RESETM=>scuba_vlo,
RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
PLLDATO1=>open, PLLDATO0=>open);
CLKOP <= CLKOP_t;
end Structure;
-- synopsys translate_off
library MACHXO3L;
configuration Structure_CON of pll_4 is
for Structure
for all:VLO use entity MACHXO3L.VLO(V); end for;
for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for;
end for;
end Structure_CON;
-- synopsys translate_on
|
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal enc : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal block_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
key => key,
block_in => block_in,
block_out => block_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- ==============================================
-- T_0: Test encryption and subsequent decryption
-- ==============================================
-- Test encryption
enc <= '0';
-- Initialize
rst <= '1';
-- SIMON 64/128 test vectors
block_in <= X"656b696c20646e75";
key <= X"1b1a1918131211100b0a090803020100";
-- Wait for initialization
wait for 2*clk_period;
-- Run
rst <= '0';
-- Do 44 rounds
wait for 43*clk_period;
assert block_out = X"44c8fc20b9dfa07a"
report "ENCRYPT ERROR (e_0)" severity FAILURE;
-- Use output of encryption as input for decryption
block_in <= block_out;
wait for clk_period;
-- Test decryption
enc <= '1';
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Do 44 rounds
wait for 43*clk_period;
assert block_out = X"656b696c20646e75"
report "DECRYPT ERROR (d_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:34 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_zed_hdmi_0_0 -prefix
-- system_zed_hdmi_0_0_ system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use WORK.constants.all;
entity WRF is
generic (
NBIT: integer;
numWindows: integer;
numRegsPerWin: integer;
logNumWindows: integer;
logNumRegsPerWin: integer
);
port (
CLK: IN std_logic;
RESET: IN std_logic;
ENABLE: IN std_logic;
CALL: IN std_logic; -- Call -> Next context
RET: IN std_logic; -- Return -> Previous context
RD1: IN std_logic; -- Read 1
RD2: IN std_logic; -- Read 2
WR: IN std_logic; -- Write
ADDR_RD1: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 1
ADDR_RD2: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 2
ADDR_WRC: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Write Address
ADDR_WR: IN std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address
REAL_ADDR_RD1: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 1
REAL_ADDR_RD2: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 2
REAL_ADDR_WR: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address
OUT1: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 1
OUT2: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 2
DATAIN: IN std_logic_vector(NBIT-1 downto 0) -- Write data
);
end WRF;
-- Architectures
architecture behavioral of WRF is
-- Suggested structures
subtype REG_ADDR is natural range 0 to 2*numWindows*numRegsPerWin+numRegsPerWin; -- Number of cells
type REG_ARRAY is array(REG_ADDR) of std_logic_vector(NBIT-1 downto 0);
-- Signal instantiation
signal REGISTERS : REG_ARRAY := ((others=> (others=>'0'))); -- Registers
signal CWP : integer := 0;
signal CWPPLUSONE : integer := 1;
signal INT_REAL_ADDR_RD1 : integer;
signal INT_REAL_ADDR_RD2 : integer;
signal INT_REAL_ADDR_WR : integer;
begin
ADDRESS_CONVERTER_RD1 : process(CWP, ADDR_RD1)
variable baseAddr : std_logic_vector(logNumWindows+1 downto 0);
variable rCWP : natural range 0 to numWindows;
variable vCWP : std_logic_vector(logNumWindows-1 downto 0);
variable vGlob : std_logic;
variable INNOTLOCAL : std_logic;
variable vRealAddress : std_logic_vector(2+logNumWindows+logNumRegsPerWin-1 downto 0);
begin
vGlob := '0';
-- report "Converted " & integer'image(conv_integer(ADDR_RD1));
-- Either OUT or GLOBAL
if ADDR_RD1(logNumRegsPerWin+1) = '1' then
INNOTLOCAL := '0';
-- Global
if ADDR_RD1(logNumRegsPerWin) = '1' then
rCWP := 0;
vGlob := '1';
-- report "Global";
-- Out
else
rCWP := CWPPLUSONE;
-- report "Out";
end if;
else
rCWP := CWP;
INNOTLOCAL := ADDR_RD1(logNumRegsPerWin);
-- report "Local";
end if;
vCWP := std_logic_vector(to_unsigned(rCWP, logNumWindows));
baseAddr := vGlob & vCWP & INNOTLOCAL;
vRealAddress := baseAddr & ADDR_RD1(logNumRegsPerWin-1 downto 0);
REAL_ADDR_RD1 <= vRealAddress;
INT_REAL_ADDR_RD1 <= conv_integer(vRealAddress);
-- report "to address " & integer'image(INT_REAL_ADDR_RD1);
end process;
ADDRESS_CONVERTER_RD2 : process(CWP, ADDR_RD2)
variable baseAddr : std_logic_vector(logNumWindows+1 downto 0);
variable rCWP : natural range 0 to numWindows;
variable vCWP : std_logic_vector(logNumWindows-1 downto 0);
variable vGlob : std_logic;
variable INNOTLOCAL : std_logic;
variable vRealAddress : std_logic_vector(2+logNumWindows+logNumRegsPerWin-1 downto 0);
begin
vGlob := '0';
-- Either OUT or GLOBAL
if ADDR_RD2(logNumRegsPerWin+1) = '1' then
INNOTLOCAL := '0';
-- Global
if ADDR_RD2(logNumRegsPerWin) = '1' then
rCWP := 0;
vGlob := '1';
-- Out
else
rCWP := CWPPLUSONE;
end if;
else
rCWP := CWP;
INNOTLOCAL := ADDR_RD2(logNumRegsPerWin);
end if;
vCWP := std_logic_vector(to_unsigned(rCWP, logNumWindows));
baseAddr := vGlob & vCWP & INNOTLOCAL;
vRealAddress := baseAddr & ADDR_RD2(logNumRegsPerWin-1 downto 0);
REAL_ADDR_RD2 <= vRealAddress;
INT_REAL_ADDR_RD2 <= conv_integer(vRealAddress);
end process;
ADDRESS_CONVERTER_WR : process(CWP, ADDR_WRC)
variable baseAddr : std_logic_vector(logNumWindows+1 downto 0);
variable rCWP : natural range 0 to numWindows;
variable vCWP : std_logic_vector(logNumWindows-1 downto 0);
variable vGlob : std_logic;
variable INNOTLOCAL : std_logic;
variable vRealAddress : std_logic_vector(2+logNumWindows+logNumRegsPerWin-1 downto 0);
begin
vGlob := '0';
-- Either OUT or GLOBAL
if ADDR_WRC(logNumRegsPerWin+1) = '1' then
INNOTLOCAL := '0';
-- Global
if ADDR_WRC(logNumRegsPerWin) = '1' then
rCWP := 0;
vGlob := '1';
-- Out
else
rCWP := CWPPLUSONE;
end if;
else
rCWP := CWP;
INNOTLOCAL := ADDR_WRC(logNumRegsPerWin);
end if;
vCWP := std_logic_vector(to_unsigned(rCWP, logNumWindows));
baseAddr := vGlob & vCWP & INNOTLOCAL;
vRealAddress := baseAddr & ADDR_WRC(logNumRegsPerWin-1 downto 0);
REAL_ADDR_WR <= vRealAddress;
end process;
--
-- Handle CALL and RETURN and WRITES
--
-- This process handles the three cases concurrently as they all need to drive the MEMBUS signal vector.
-- Because VHDL creates a driver per process, it wouldn't be possible to create a different process per
-- task as the drivers would conflict and force the vector to the undefined state. The solutions available
-- were to instantiate REGISTERS as a shared variable, or to manage the three tasks with a single process.
-- The latter is the choice we made.
--
PROCESS_CALLRETWR: process(CLK, RESET, RET, CALL, WR, DATAIN, ADDR_WR)
variable index: integer := 0;
begin
-- Synchronous
-- if CLK'event and CLK = '1' then
-- Synchronous on double fronts
if CLK'event and CLK = '0' then
-- If 'reset'
if(RESET = '1') then
CWP <= 0; -- Reset the CWP
REGISTERS <= (others =>(others =>'0'));
else
-- Is RETURN active?
if(RET = '1') then
if( CWP = 0 ) then
-- report "ERROR: CWP IS ZERO! UNABLE TO RETURN";
else
CWPPLUSONE <= CWP;
CWP <= CWP-1; -- Decrease the CWP
end if;
else
-- Is CALL active?
if(CALL = '1') then
CWP <= CWPPLUSONE;
CWPPLUSONE <= CWPPLUSONE+1; -- Increase the CWP
end if; -- CALL
end if; -- RET
-- Is WRITE active?
if WR = '1' then
-- report "Im writing " & integer'image(conv_integer(DATAIN)) & " to " & integer'image(conv_integer(ADDR_WR));
REGISTERS(conv_integer(ADDR_WR)) <= DATAIN;
end if; -- WRITE
end if; -- RESET
end if;
end process;
OUT1 <= REGISTERS(INT_REAL_ADDR_RD1) when ( RD1 = '1' and ENABLE = '1' ) else (others => '0');
OUT2 <= REGISTERS(INT_REAL_ADDR_RD2) when ( RD2 = '1' and ENABLE = '1' ) else (others => '0');
end behavioral;
|
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_onehot <= '0';
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_mismatch <= '0';
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
end if;
end process;
process (flit_type, Requests_FF, Requests_in)
begin
err_header_tail_Requests_FF_Requests_in <= '0';
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_not_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_not_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_not_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_not_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_not_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
err_header_not_empty_faulty_drop_packet_in <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
err_header_not_empty_faulty_Req_in_all_zero <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
end if;
end process;
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
err_header_not_empty_Req_N_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
end if;
end process;
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_E_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
end if;
end process;
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_W_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
end if;
end process;
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_S_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (packet_drop_order, packet_drop)
begin
err_packet_drop_order <= '0';
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_onehot <= '0';
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_mismatch <= '0';
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
end if;
end process;
process (flit_type, Requests_FF, Requests_in)
begin
err_header_tail_Requests_FF_Requests_in <= '0';
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_not_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_not_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_not_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_not_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_not_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
err_header_not_empty_faulty_drop_packet_in <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
err_header_not_empty_faulty_Req_in_all_zero <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
end if;
end process;
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
err_header_not_empty_Req_N_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
end if;
end process;
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_E_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
end if;
end process;
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_W_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
end if;
end process;
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_S_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (packet_drop_order, packet_drop)
begin
err_packet_drop_order <= '0';
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_onehot <= '0';
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
end if;
end process;
process (grant_signals, grants)
begin
err_grants_mismatch <= '0';
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
end if;
end process;
process (flit_type, Requests_FF, Requests_in)
begin
err_header_tail_Requests_FF_Requests_in <= '0';
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, N1_out)
begin
err_dst_addr_cur_addr_not_N1 <= '0';
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, E1_out)
begin
err_dst_addr_cur_addr_not_E1 <= '0';
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, W1_out)
begin
err_dst_addr_cur_addr_not_W1 <= '0';
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
end if;
end process;
process (cur_addr, dst_addr, S1_out)
begin
err_dst_addr_cur_addr_not_S1 <= '0';
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
err_dst_addr_cur_addr_not_Req_L_in <= '0';
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
err_header_not_empty_faulty_drop_packet_in <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
end if;
end process;
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
err_header_not_empty_faulty_Req_in_all_zero <= '0';
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
end if;
end process;
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
err_header_not_empty_Req_N_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
end if;
end process;
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_E_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
end if;
end process;
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_W_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
end if;
end process;
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
err_header_not_empty_Req_S_in <= '0';
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
end if;
end process;
process (flit_type, empty, packet_drop, packet_drop_in)
begin
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (flit_type, empty, packet_drop_in, packet_drop)
begin
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
end if;
end process;
process (packet_drop_order, packet_drop)
begin
err_packet_drop_order <= '0';
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
end if;
end process;
end behavior; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc970.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00970ent IS
END c06s03b00x00p05n01i00970ent;
ARCHITECTURE c06s03b00x00p05n01i00970arch OF c06s03b00x00p05n01i00970ent IS
BEGIN
TESTING: PROCESS
type x is
record
y : integer;
z : boolean;
end record;
type a is
record
b : real;
c : integer;
end record;
variable r : a;
variable p : x;
BEGIN
p.b := 1; -- the prefix is not of an appropriate type as the 'p' does
a.y := 1; -- not have field 'b' and 'a' does not have field 'y'.
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00970 - Prefix is not apropraite for the type of the suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00970arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc970.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00970ent IS
END c06s03b00x00p05n01i00970ent;
ARCHITECTURE c06s03b00x00p05n01i00970arch OF c06s03b00x00p05n01i00970ent IS
BEGIN
TESTING: PROCESS
type x is
record
y : integer;
z : boolean;
end record;
type a is
record
b : real;
c : integer;
end record;
variable r : a;
variable p : x;
BEGIN
p.b := 1; -- the prefix is not of an appropriate type as the 'p' does
a.y := 1; -- not have field 'b' and 'a' does not have field 'y'.
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00970 - Prefix is not apropraite for the type of the suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00970arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc970.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00970ent IS
END c06s03b00x00p05n01i00970ent;
ARCHITECTURE c06s03b00x00p05n01i00970arch OF c06s03b00x00p05n01i00970ent IS
BEGIN
TESTING: PROCESS
type x is
record
y : integer;
z : boolean;
end record;
type a is
record
b : real;
c : integer;
end record;
variable r : a;
variable p : x;
BEGIN
p.b := 1; -- the prefix is not of an appropriate type as the 'p' does
a.y := 1; -- not have field 'b' and 'a' does not have field 'y'.
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00970 - Prefix is not apropraite for the type of the suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00970arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lib;
USE lib.io.all;
entity kbd_input is
port
(
clock_i : in std_logic;
reset_i : in std_logic;
hold_i : in std_logic;
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
shot_o : buffer std_logic;
move_o : buffer std_logic;
control_o : buffer std_logic_vector(2 downto 0)
);
end;
architecture struct of kbd_input is
component kbdex_ctrl
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
lights : in std_logic_vector(2 downto 0); -- lights(Caps, Nun, Scroll)
key_on : out std_logic_vector(2 downto 0);
key_code : out std_logic_vector(47 downto 0)
);
end component;
signal CLOCKHZ, resetn : std_logic;
signal keys : std_logic_vector(31 downto 0);
signal control_s1, control_s2 : std_logic_vector(2 downto 0);
signal lights : std_logic_vector(2 downto 0);
begin
resetn <= reset_i;
kbd_ctrl : kbdex_ctrl generic map(24000) port map(
PS2_DAT, PS2_CLK, clock_i, hold_i, resetn, lights,
open, key_code(31 downto 0) => keys
);
-- Clock divider
process(clock_i)
constant F_HZ : integer := 5;
constant DIVIDER : integer := 24000000/F_HZ;
variable count : integer range 0 to DIVIDER := 0;
begin
if rising_edge(clock_i) then
if count < DIVIDER / 2 then
CLOCKHZ <= '1';
else
CLOCKHZ <= '0';
end if;
if count = DIVIDER then
count := 0;
end if;
count := count + 1;
end if;
end process;
---------------------------------------------
-- MUX FOR KEYBOARD CONTROL --
-- NUMERIC KEYPAD:
-- 4: Move left
-- 5: Shoot
-- 6: Move right
-- SPACE: Shoot
-- This component can handle two commands at
-- the same time, such as a movement key and
-- a shooting key.
---------------------------------------------
-- MUX for the first pressed key
with keys(15 downto 0) select
control_s1 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
-- MUX for the second pressed key
with keys(31 downto 16) select
control_s2 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
shot_o <= control_s1(1) or control_s2(1); -- Shot
move_o <= (control_s1(2) or control_s1(0)) xor (control_s2(2) or control_s2(0)); -- Movement
control_o <= control_s1 xor control_s2; -- Controls
end struct;
|
--
-- io.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2004,2005 Stephen A. Rodgers
--
-- Steve Rodgers <[email protected]>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity io is
port
(
arn : in std_logic;
clk : in std_logic;
wrn : in std_logic;
rd : in std_logic;
sel_uio : in std_logic;
sel_testptt : in std_logic;
sel_ctrl1 : in std_logic;
sel_ctrl2 : in std_logic;
sel_leds : in std_logic;
sel_irqmask : in std_logic;
sel_uarttx : in std_logic;
rbsclk : in std_logic;
rbsdata : in std_logic;
irq_mx828 : in std_logic;
ledpwm : in std_logic;
rbs_busy : in std_logic;
busy_mx828 : in std_logic;
mxaccess : in std_logic;
uioinlsb : in std_logic_vector(3 downto 0);
cor : in std_logic_vector(3 downto 0);
wdb : in std_logic_vector(7 downto 0);
tjirq : out std_logic;
led0 : out std_logic_vector(1 downto 0);
led1 : out std_logic_vector(1 downto 0);
led2 : out std_logic_vector(1 downto 0);
led3 : out std_logic_vector(1 downto 0);
uioout : out std_logic_vector(7 downto 0);
testpttout : out std_logic_vector(7 downto 0);
ctrlout1 : out std_logic_vector(7 downto 0);
ctrlout2 : out std_logic_vector(7 downto 0);
statusreg : out std_logic_vector(7 downto 0);
corbits : out std_logic_vector(7 downto 0);
irqmaskbits : out std_logic_vector(7 downto 0);
uart_rxdata : out std_logic_vector(7 downto 0)
);
end io;
architecture rtl of io is
signal irqsum : std_logic;
signal rxd : std_logic;
signal txd : std_logic;
signal ovrrun : std_logic;
signal dirty : std_logic;
signal dav : std_logic;
signal txgo : std_logic;
signal txdone : std_logic;
signal txbusy : std_logic;
signal bce9600 : std_logic;
signal txwdtrip: std_logic;
signal rxba : std_logic;
signal leds2 : std_logic_vector(1 downto 0);
signal txgosync: std_logic_vector(2 downto 0);
signal rdsuart : std_logic_vector(2 downto 0);
signal wdptts : std_logic_vector(3 downto 0);
signal irqmbits: std_logic_vector(3 downto 0);
signal plsdone : std_logic_vector(3 downto 0);
signal rbsdone : std_logic_vector(3 downto 0);
signal leds4 : std_logic_vector(3 downto 0);
signal davshift: std_logic_vector(4 downto 0);
signal leds6 : std_logic_vector(5 downto 0);
signal uarttx : std_logic_vector(7 downto 0);
signal ledport : std_logic_vector(7 downto 0);
signal ledctrl : std_logic_vector(7 downto 0);
signal ledsync : std_logic_vector(7 downto 0);
signal uiobits : std_logic_vector(7 downto 0);
signal ctrl2 : std_logic_vector(7 downto 0);
component tinyuart
port
(
arn : in std_logic;
clk : in std_logic;
txgo : in std_logic;
rxrd : in std_logic;
rxd : in std_logic;
txdata : in std_logic_vector(7 downto 0);
ovrrun : out std_logic;
dirty : out std_logic;
dav : out std_logic;
txdone : out std_logic;
txd : out std_logic;
bce9600 : out std_logic;
rxdata : out std_logic_vector(7 downto 0)
);
end component;
component txwdog
port
(
arn : in std_logic;
clk : in std_logic;
mxaccess : in std_logic;
bce9600 : in std_logic;
pttin : in std_logic_vector(3 downto 0);
txwdtrip : out std_logic;
pttout : out std_logic_vector(3 downto 0)
);
end component;
begin
mtinyuart : tinyuart
port map
(
arn => arn,
clk => clk,
txgo => txgo,
rxrd => rdsuart(2),
rxd => rxd,
txdata => uarttx,
ovrrun => ovrrun,
dirty => dirty,
dav => dav,
txdone => txdone,
txd => txd,
bce9600 => bce9600,
rxdata => uart_rxdata
);
mtxwdog : txwdog
port map
(
arn => arn,
clk => clk,
mxaccess => mxaccess,
bce9600 => bce9600,
txwdtrip => txwdtrip,
pttin => wdptts,
pttout => testpttout(3 downto 0)
);
uiop : process(arn, wrn)
begin
if(arn = '0') then
uiobits <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_uio = '1') then
uiobits <= wdb;
end if;
end if;
end process uiop;
testpttp : process(arn, wrn)
begin
if(arn = '0') then
testpttout(7 downto 4) <= "0000";
wdptts <= "0000";
elsif(wrn'event) and (wrn = '1') then
if(sel_testptt = '1') then
testpttout(7 downto 4) <= wdb(7 downto 4);
wdptts <= wdb(3 downto 0);
end if;
end if;
end process testpttp;
ledp : process(arn, wrn)
begin
if(arn = '0') then
ledport <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_leds = '1') then
ledport <= wdb;
end if;
end if;
end process ledp;
ctrlp1 : process(arn, wrn)
begin
if(arn = '0') then
ctrlout1 <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_ctrl1 = '1') then
ctrlout1 <= wdb;
end if;
end if;
end process ctrlp1;
ctrlp2 : process(arn, wrn)
begin
if(arn = '0') then
ctrl2 <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_ctrl2 = '1') then
ctrl2 <= wdb;
end if;
end if;
end process ctrlp2;
irqmrp : process(arn, wrn)
begin
if(arn = '0') then
irqmbits <= "0000";
elsif(wrn'event) and (wrn = '1') then
if(sel_irqmask = '1') then
irqmbits(2 downto 0) <= not wdb(2 downto 0);
irqmbits(3) <= not wdb(7);
end if;
end if;
end process irqmrp;
-- prevent glitches on tjirq
irqsync : process(arn, clk)
begin
if(arn = '0') then
tjirq <= '0';
elsif(clk'event) and (clk = '1') then
tjirq <= irqsum;
end if;
end process irqsync;
-- Generate UART unload strobe
rdsynca : process(arn, rdsuart, rd)
begin
if(arn = '0') or (rdsuart(2) = '1') then
rdsuart(0) <= '0';
elsif(rd'event) and (rd = '0') then
if(sel_uarttx = '1') then -- receive register read
rdsuart(0) <= '1';
end if;
end if;
end process rdsynca;
rdsyncb : process(arn, clk, rdsuart)
begin
if(arn = '0') then
rdsuart(2 downto 1) <= "00";
elsif(clk'event) and (clk = '1') then
rdsuart(2) <= rdsuart(1);
rdsuart(1) <= rdsuart(0);
end if;
end process rdsyncb;
-- delay dav by 5 clocks
davshftp : process(arn, clk)
begin
if(arn = '0') then
davshift <= "00000";
elsif(clk'event) and (clk = '1') then
davshift <= davshift(3 downto 0) & dav;
end if;
end process davshftp;
-- rxba latch
rxbafm : process(arn, rd, davshift(4))
begin
if(arn = '0') then
rxba <= '0';
elsif(davshift(4) = '1') then
rxba <= '1'; -- byte available asynchronously sets
elsif(rd'event) and (rd = '0') then
if(sel_uarttx = '1') then -- receive register read
rxba <= '0'; -- byte available clears on rising edge of rd.
end if;
end if;
end process rxbafm;
-- start to generate a load pulse from a tx write
puarttx1 : process(arn, txgosync(2), wrn)
begin
if(arn = '0') then
txgosync(0) <= '0';
elsif(txgosync(2) = '1') then
txgosync(0) <= '0';
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
txgosync(0) <= '1';
end if;
end if;
end process puarttx1;
-- set or clear txbusy
puarttx2 : process(arn, wrn, txdone)
begin
if(arn = '0') or (txdone = '1') then
txbusy <= '0';
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
txbusy <= '1';
end if;
end if;
end process puarttx2;
-- save byte to be transmitted
puarttx3 : process(arn, wrn)
begin
if(arn = '0') then
uarttx <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
uarttx <= wdb;
end if;
end if;
end process puarttx3;
-- sequence the load pulse for the tx write
puarttx4 : process(arn, clk)
begin
if(arn = '0') then
txgosync(2 downto 1) <= "00";
elsif(clk'event) and (clk = '1') then
txgosync(1) <= txgosync(0);
txgosync(2) <= txgosync(1);
end if;
end process puarttx4;
-- latch the transition of pl serializer busy from high to low
mxdnp : process(arn, clk)
begin
if(arn = '0') then
plsdone(2 downto 0) <= "000";
elsif(clk'event) and (clk = '1') then
plsdone(1) <= plsdone(0);
plsdone(0) <= busy_mx828;
if( irqmbits(0) = '0') then
plsdone(2) <= '0';
elsif(plsdone(3) = '1') then
plsdone(2) <= '1';
end if;
end if;
end process mxdnp;
-- latch the transition of remote serializer busy from high to low
rbdnp : process(arn, clk)
begin
if(arn = '0') then
rbsdone(2 downto 0) <= "000";
elsif(clk'event) and (clk = '1') then
rbsdone(1) <= rbsdone(0);
rbsdone(0) <= rbs_busy;
if(irqmbits(1) = '0') then
rbsdone(2) <= '0';
elsif(rbsdone(3) = '1') then
rbsdone(2) <= '1';
end if;
end if;
end process rbdnp;
-- handle status led modulation
ledmod : process(ledpwm, ledport)
begin
case ledport(1 downto 0) is
when "00" =>
ledctrl(1 downto 0) <= "00";
when "01" =>
ledctrl(1 downto 0) <= "01";
when "10" =>
ledctrl(1 downto 0) <= "10";
when "11" =>
ledctrl(0) <= ledpwm;
ledctrl(1) <= not ledpwm;
when others =>
ledctrl(1 downto 0) <= "00";
end case;
case ledport(3 downto 2) is
when "00" =>
ledctrl(3 downto 2) <= "00";
when "01" =>
ledctrl(3 downto 2) <= "01";
when "10" =>
ledctrl(3 downto 2) <= "10";
when "11" =>
ledctrl(2) <= ledpwm;
ledctrl(3) <= not ledpwm;
when others =>
ledctrl(3 downto 2) <= "00";
end case;
case ledport(5 downto 4) is
when "00" =>
ledctrl(5 downto 4) <= "00";
when "01" =>
ledctrl(5 downto 4) <= "01";
when "10" =>
ledctrl(5 downto 4) <= "10";
when "11" =>
ledctrl(4) <= ledpwm;
ledctrl(5) <= not ledpwm;
when others =>
ledctrl(5 downto 4) <= "00";
end case;
case ledport(7 downto 6) is
when "00" =>
ledctrl(7 downto 6) <= "00";
when "01" =>
ledctrl(7 downto 6) <= "01";
when "10" =>
ledctrl(7 downto 6) <= "10";
when "11" =>
ledctrl(6) <= ledpwm;
ledctrl(7) <= not ledpwm;
when others =>
ledctrl(7 downto 6) <= "00";
end case;
end process ledmod;
-- skew LED control signals to meet simultaneous switching limitations.
ledskew : process(arn, clk)
begin
if(arn = '0') then
ledsync <= "00000000";
leds6 <= "000000";
leds4 <= "0000";
leds2 <= "00";
elsif(clk'event) and (clk = '1') then
ledsync <= ledctrl;
leds6 <= ledsync(5 downto 0);
leds4 <= leds6(3 downto 0);
leds2 <= leds4(1 downto 0);
end if;
end process ledskew;
-- map outbut modes to correct uioa/b bit pairs
--
outselp : process(ctrl2, uiobits, rbsdata, rbsclk, txd, uioinlsb)
begin
if(ctrl2(7 downto 6) = "01") then -- select RBS on a port.
rxd <= '1';
case ctrl2(5 downto 4) is
when "00" =>
uioout <= uiobits(7 downto 5) & rbsdata & uiobits(3 downto 1) & rbsclk;
when "01" =>
uioout <= uiobits(7 downto 6) & rbsdata & uiobits(4 downto 2) & rbsclk & uiobits(0);
when "10" =>
uioout <= uiobits(7) & rbsdata & uiobits(5 downto 3) & rbsclk & uiobits(1 downto 0);
when "11" =>
uioout <= rbsdata & uiobits(6 downto 4) & rbsclk & uiobits(2 downto 0);
when others =>
uioout <= "00000000";
end case;
elsif(ctrl2(7 downto 6) = "10") then -- select UART on a port
case ctrl2(5 downto 4) is
when "00" =>
rxd <= uioinlsb(0);
uioout <= uiobits(7 downto 5) & txd & uiobits(3 downto 1) & '1';
when "01" =>
rxd <= uioinlsb(1);
uioout <= uiobits(7 downto 6) & txd & uiobits(4 downto 2) & '1' & uiobits(0);
when "10" =>
rxd <= uioinlsb(2);
uioout <= uiobits(7) & txd & uiobits(5 downto 3) & '1' & uiobits(1 downto 0);
when "11" =>
rxd <= uioinlsb(3);
uioout <= txd & uiobits(6 downto 4) & '1' & uiobits(2 downto 0);
when others =>
rxd <= '1';
uioout <= "00000000";
end case;
else
rxd <= '1';
uioout <= uiobits;
end if;
end process outselp;
--
-- Concurrent statements
--
led0 <= leds2;
led1 <= leds4(3 downto 2);
led2 <= leds6(5 downto 4);
led3 <= ledsync(7 downto 6);
ctrlout2 <= ctrl2;
plsdone(3) <= '1' when plsdone(0) = '0' and plsdone(1) = '1' else '0';
rbsdone(3) <= '1' when rbsdone(0) = '0' and rbsdone(1) = '1' else '0';
irqsum <= '1' when irqmbits(3) = '1' and ((irqmbits(2) = '1' and irq_mx828 = '1') or
(irqmbits(1) = '1' and rbsdone(2) = '1') or
(irqmbits(0) = '1' and plsdone(2) = '1')) else '0';
-- assemble general status register bits
statusreg <= irqsum & irq_mx828 & rbsdone(2) & plsdone(2) & '0' & txwdtrip & rbs_busy & busy_mx828;
-- assemble cbits for uart status/cor register
corbits <= txbusy & ovrrun & dirty & rxba & cor(3 downto 0);
-- assemble irqmaskbits
irqmaskbits <= not irqmbits(3) & "0000" & not irqmbits(2 downto 0);
txgo <= txgosync(1) and not txgosync(2);
end rtl;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
`protect data_block
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
`protect data_block
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`protect begin_protected
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:19:54 10/27/2009
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-- Description: The ALU for the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.30 - File written and syntax checked
-- Revision 0.90 - Successfully simulated
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0);
cond_bits : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
main: process(A, B, sel) is
variable out_reg : STD_LOGIC_VECTOR(32 downto 0);
begin
cond_bits <= "0000";
--operations
case sel is
when "0000" => --add
out_reg := ('0' & A(31 downto 0)) + ('0' & B(31 downto 0));
when "0001" => --sub
out_reg := ('0' & A(31 downto 0)) - ('0' & B(31 downto 0));
when "0010" => --and
out_reg := '0' & (A and B);
when "0011" => --or
out_reg := '0' & (A or B);
when "0100" => --xor
out_reg := '0' & (A xor B);
when "0101" => --cp
out_reg := ('0' & A);
when "0110" => --sll
out_reg := (A(31 downto 0) & '0');
when "0111" => --srl
out_reg := ("00" & A(31 downto 1));
when "1000" => --rol
out_reg := (A(0) & A(0) & A(31 downto 1));
when "1001" => --ror
out_reg := (A(30) & A(30 downto 0) & A(31));
when others =>
out_reg := ('0' & A);
end case;
--condition bit logic
if (A > B) then
cond_bits(1) <= '1';
elsif (A = B) then
cond_bits(2) <= '1';
elsif (A < B) then
cond_bits(3) <= '1';
end if;
cond_bits(0) <= out_reg(32); --carry
result <= out_reg(31 downto 0);
end process;
end Behavioral;
|
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