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-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
-- Description: This module sends a character over a serial line
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
tick : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
cts : in std_logic := '1';
txd : out std_logic;
done : out std_logic );
end tx;
architecture gideon of tx is
signal bitcnt : integer range 0 to 9;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, Waiting, Transmitting);
signal state : state_t;
signal cts_c : std_logic := '1';
begin
process(clk, reset)
begin
if rising_edge(clk) then
cts_c <= cts;
case state is
when Idle =>
if DoTx='1' then
if cts_c='1' then
state <= Transmitting;
else
state <= Waiting;
end if;
bitcnt <= 9;
bitvec <= not(txchar) & '1';
timer <= clks_per_bit - 1;
end if;
when Waiting =>
if cts_c='1' then
state <= Transmitting;
end if;
when Transmitting =>
if tick = '1' then
if timer=0 then
timer <= clks_per_bit - 1;
if bitcnt = 0 then
state <= Idle;
else
bitcnt <= bitcnt - 1;
bitvec <= '0' & bitvec(8 downto 1);
end if;
else
timer <= timer - 1;
end if;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
done <= '1' when state=Idle else '0';
txd <= not(bitvec(0));
end gideon;
|
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
entity Receiver is
port ( rxd, reset, clk_baud : in std_logic;
rxdata : out std_logic_vector(0 to 7); -- Reverse order to load in from the right end
rxvalid : out std_logic
);
end Receiver;
architecture Rec of Receiver is
type state is (idle, reading, stopping, latchData);
type state2 is (idle, cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7);
signal present_state, next_state : state;
signal cnt_present_state, cnt_next_state : state2;
begin
state_reg : process(clk_baud, reset)
begin
if reset = '0' then
present_state <= idle;
elsif rising_edge(clk_baud) then
present_state <= next_state;
end if;
end process;
cnt_reg : process(clk_baud, reset)
begin
if reset = '0' then
cnt_present_state <= idle;
elsif rising_edge(clk_baud) then
cnt_present_state <= cnt_next_state;
end if;
end process;
nxt_state : process(present_state, clk_baud)
begin
next_state <= present_state;
case present_state is
when idle =>
if rxd = '0' then
next_state <= reading;
end if;
when reading =>
if cnt_present_state = cnt7 then
next_state <= stopping;
else
null;
end if;
when stopping =>
if rxd = '1' then
next_state <= latchData;
else
next_state <= idle;
end if;
when latchData =>
next_state <= idle;
when others =>
next_state <= idle;
end case;
end process;
cnt_nxt : process(present_state, clk_baud)
begin
cnt_next_state <= cnt_present_state;
if present_state = reading then
case cnt_present_state is
when idle =>
cnt_next_state <= cnt0;
when cnt0 =>
cnt_next_state <= cnt1;
when cnt1 =>
cnt_next_state <= cnt2;
when cnt2 =>
cnt_next_state <= cnt3;
when cnt3 =>
cnt_next_state <= cnt4;
when cnt4 =>
cnt_next_state <= cnt5;
when cnt5 =>
cnt_next_state <= cnt6;
when cnt6 =>
cnt_next_state <= cnt7;
when cnt7 =>
cnt_next_state <= idle;
when others =>
cnt_next_state <= idle;
end case;
else
null;
end if;
end process;
output : process(present_state)
begin
case present_state is
when latchData =>
rxvalid <= '1';
when others =>
rxvalid <= '0';
end case;
end process;
cnt_output : process(cnt_present_state)
begin
if falling_edge(clk_baud) then
case cnt_present_state is
when cnt0 =>
rxdata(0) <= rxd;
when cnt1 =>
rxdata(1) <= rxd;
when cnt2 =>
rxdata(2) <= rxd;
when cnt3 =>
rxdata(3) <= rxd;
when cnt4 =>
rxdata(4) <= rxd;
when cnt5 =>
rxdata(5) <= rxd;
when cnt6 =>
rxdata(6) <= rxd;
when cnt7 =>
rxdata(7) <= rxd;
when others =>
null;
end case;
else
null;
end if;
end process;
end Rec; |
-- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:52:30 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.4 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_osc
-- No Generated Generics
port (
-- Generated Port for Entity w_osc
pd : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
xo : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_osc
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
-- __I_NODRV_I signal clki2c : std_ulogic;
signal clki3c : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic0_0 <= '0';
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for data_10_pad
data_10_pad: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for data_10_pad
-- Generated Instance Port Map for data_9_pad
data_9_pad: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for data_9_pad
-- Generated Instance Port Map for data_i1_pad
data_i1_pad: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for data_i1_pad
-- Generated Instance Port Map for data_i33_pad
data_i33_pad: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for data_i33_pad
-- Generated Instance Port Map for data_i34_pad
data_i34_pad: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for data_i34_pad
-- Generated Instance Port Map for data_o1_pad
data_o1_pad: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for data_o1_pad
-- Generated Instance Port Map for data_o35_pad
data_o35_pad: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for data_o35_pad
-- Generated Instance Port Map for data_o36_pad
data_o36_pad: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for data_o36_pad
-- Generated Instance Port Map for disp_10_pad
disp_10_pad: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for disp_10_pad
-- Generated Instance Port Map for disp_2_pad
disp_2_pad: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for disp_2_pad
-- Generated Instance Port Map for disp_3_pad
disp_3_pad: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for disp_3_pad
-- Generated Instance Port Map for disp_4_pad
disp_4_pad: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for disp_4_pad
-- Generated Instance Port Map for disp_5_pad
disp_5_pad: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for disp_5_pad
-- Generated Instance Port Map for disp_6_pad
disp_6_pad: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for disp_6_pad
-- Generated Instance Port Map for disp_7_pad
disp_7_pad: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for disp_7_pad
-- Generated Instance Port Map for disp_8_pad
disp_8_pad: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for disp_8_pad
-- Generated Instance Port Map for disp_9_pad
disp_9_pad: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for disp_9_pad
-- Generated Instance Port Map for osc_1_pad
osc_1_pad: w_osc
port map (
pd => mix_logic1_0,
-- __I_NODRV_I xo => __nodrv__/clki2c
);
-- End of Generated Instance Port Map for osc_1_pad
-- Generated Instance Port Map for osc_2_pad
osc_2_pad: w_osc
port map (
pd => mix_logic1_1,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_2_pad
-- Generated Instance Port Map for osc_3_pad
osc_3_pad: w_osc
port map (
pd => mix_logic0_0,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_3_pad
-- Generated Instance Port Map for pad_dire_pad
pad_dire_pad: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_dire_pad
-- Generated Instance Port Map for pad_dirli_pad
pad_dirli_pad: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_dirli_pad
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc624.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00624ent IS
END c03s04b01x00p01n01i00624ent;
ARCHITECTURE c03s04b01x00p01n01i00624arch OF c03s04b01x00p01n01i00624ent IS
type four_value is ('Z','0','1','X');
type four_value_file is file of four_value;
constant C38 : four_value := 'X';
BEGIN
TESTING: PROCESS
file filein : four_value_file open write_mode is "iofile.36";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00624 - The output file will be verified by test s010274.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc624.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00624ent IS
END c03s04b01x00p01n01i00624ent;
ARCHITECTURE c03s04b01x00p01n01i00624arch OF c03s04b01x00p01n01i00624ent IS
type four_value is ('Z','0','1','X');
type four_value_file is file of four_value;
constant C38 : four_value := 'X';
BEGIN
TESTING: PROCESS
file filein : four_value_file open write_mode is "iofile.36";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00624 - The output file will be verified by test s010274.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc624.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00624ent IS
END c03s04b01x00p01n01i00624ent;
ARCHITECTURE c03s04b01x00p01n01i00624arch OF c03s04b01x00p01n01i00624ent IS
type four_value is ('Z','0','1','X');
type four_value_file is file of four_value;
constant C38 : four_value := 'X';
BEGIN
TESTING: PROCESS
file filein : four_value_file open write_mode is "iofile.36";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00624 - The output file will be verified by test s010274.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00624arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n01i01908ent IS
END c07s02b00x00p09n01i01908ent;
ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***PASSED TEST: c07s02b00x00p09n01i01908"
severity NOTE;
assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n01i01908arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n01i01908ent IS
END c07s02b00x00p09n01i01908ent;
ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***PASSED TEST: c07s02b00x00p09n01i01908"
severity NOTE;
assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n01i01908arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n01i01908ent IS
END c07s02b00x00p09n01i01908ent;
ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***PASSED TEST: c07s02b00x00p09n01i01908"
severity NOTE;
assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n01i01908arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_7_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_7_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_ok_7_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ok_7_e
--
architecture rtl of inst_ok_7_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
#
# Generated Signal List
#
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1_10.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1_10.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1_10.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1_10.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1_10.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1_10.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
|
library work;
use work.numeric_std.all;
use work.std_logic_1164.all;
entity bram_sp is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 8;
RAM_RDWR_ORDER : string := "READ_FIRST"; -- {READ_FIRST, WRITE_FIRST}
RAM_INIT : string := "DEFAULT"; -- {DEFAULT, INIT_DATA, INIT_FILE}
RAM_INIT_DATA : std_logic_vector(RAM_DEPTH*RAM_WIDTH-1 downto 0) :=
(others => '0');
RAM_INIT_FILE : string
);
port (
clk_i : std_logic;
wraddr_i : std_logic_vector(clog2(RAM_DEPTH)-1 downto 0);
wren_i : std_logic;
wrdata_i : std_logic_vector(RAM_WIDTH-1 downto 0);
rdaddr_i : std_logic_vector(clog2(RAM_DEPTH)-1 downto 0);
rddata_o : std_logic_vector(RAM_WIDTH-1 downto 0)
);
end entity bram_sp;
architecture rtl of bram_sp is
type ram_t is array 0 to RAM_DEPTH-1 of std_logic_vector(RAM_WIDTH-1 downto 0);
function initialize_ram(
init_type : string;
init_data : std_logic_vector;
init_file : string
) return ram_t is
variable reval : ram_t;
begin
case init_type is
when "INIT_DATA" =>
for i in 0 to RAM_DEPTH-1 loop
reval(i) := RAM_INIT_DATA((i+1)*RAM_WIDTH-1 downto i*RAM_WIDTH);
end loop;
when "INIT_FILE" =>
when others =>
reval := (others => 'U');
end case;
return reval;
end function initialize_ram;
shared variable ram : ram_t := initialize_ram(RAM_INIT, RAM_INIT_DATA, RAM_INIT_FILE);
begin
p_bram_sp: process (clk_i) is
variable wraddr_int : integer;
variable rdaddr_int : integer;
begin
if rising_edge(clk_i) then
wraddr_int := to_integer(unsigned(wraddr_i));
if (RAM_RDWR_ORDER = "READ_FIRST") then
rddata_o <= ram(rdaddr_int);
end if;
if (wren_i = '1') then
ram(wraddr_int) := wrdata_i;
end if;
if (RAM_RDWR_ORDER = "WRITE_FIRST") then
rddata_o <= ram(rdaddr_int);
end if;
end if;
end process p_bram_sp;
end architecture rtl;
|
----------------------------------------------------------------------------------------------------
-- ENTITY - Parallel In Serial Out Register
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz ([email protected])
-- Date: 29.06.2017
-- Last change: 22.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_nm_piso_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
load_i : IN std_logic;
data_i : IN std_logic_vector(M-1 DOWNTO 0);
data_o : OUT std_logic_vector(U-1 DOWNTO 0)
);
END e_nm_piso_register;
ARCHITECTURE rtl OF e_nm_piso_register IS
SIGNAL temp : std_logic_vector(M-1 DOWNTO 0);
BEGIN
PROCESS (clk_i, rst_i, load_i, data_i) IS
BEGIN
IF (rst_i='1') THEN
temp <= (OTHERS=>'0');
ELSIF rising_edge(clk_i) THEN
IF load_i = '1' THEN
temp <= data_i ;
END IF;
IF enable_i='1' THEN
temp(M-U-1 DOWNTO 0) <= temp(M-1 DOWNTO U);
END IF;
END IF;
END PROCESS;
data_o(U-1 DOWNTO 0) <= temp(U-1 DOWNTO 0);
END rtl; |
-- asynchronous_quadrature_decoder - quadrature decoder without synchronizing clock input
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
-- prior debouncing of rotary input is unnecessary
entity asynchronous_quadrature_decoder is
port (
rotary : in std_logic_vector (1 downto 0);
direction : out std_logic;
pulse : out std_logic
);
end asynchronous_quadrature_decoder;
architecture gate_level of asynchronous_quadrature_decoder is
signal a, b, c, d, e, f : std_logic;
signal pul, pul_n, dir, dir_n : std_logic;
begin
a <= rotary(0);
b <= rotary(1);
c <= a and b;
d <= a nor b;
e <= a and not b;
f <= b and not a;
dir <= dir_n nor e;
dir_n <= dir nor f;
pul <= pul_n nor d;
pul_n <= pul nor c;
pulse <= pul;
direction <= dir;
end gate_level;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.cpu_constant_library.all;
entity alu_control is
port (
alu_op : in std_logic_vector(1 downto 0);
instruction_5_0 : in std_logic_vector(5 downto 0);
alu_out : out std_logic_vector(3 downto 0)
);
end alu_control;
architecture Behavioral of alu_control is
begin
process (alu_op, instruction_5_0)
begin
case alu_op is
when "00" => --lw and sw
alu_out <= "0010";
when "01" => --branch
alu_out <= "0110";
when "10" => --r type
case instruction_5_0 is
when "100000" => --add
alu_out <= "0010";
when "100010" => --sub
alu_out <= "0110";
when "100100" => --AND
alu_out <= "0000";
when "100101" => --OR
alu_out <= "0001";
when "101010" => --slt
alu_out <= "0111";
when "100111" => --NOR
alu_out <= "1100";
when others => --bad input
alu_out <= "XXXX";
end case;
when others => --bad input
alu_out <= "XXXX";
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl
-- File: irqctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Interrupt controller. Implements a two-level interrupt
-- controller for the 15 SPARC interrupts.
------------------------------------------------------------------------------
-- Version control:
-- 07-08-1998: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.macro.decode;
use work.amba.all;
entity irqctrl is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_in_type;
irqo : out irq_out_type
);
end;
architecture rtl of irqctrl is
type irqregs is record
imask : std_logic_vector(15 downto 1);
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : std_logic_vector(15 downto 1);
irl : std_logic_vector( 3 downto 0);
end record;
function priority(v : std_logic_vector(15 downto 1)) return std_logic_vector is
begin
if v(15) = '1' then return("1111");
elsif v(14) = '1' then return("1110");
elsif v(13) = '1' then return("1101");
elsif v(12) = '1' then return("1100");
elsif v(11) = '1' then return("1011");
elsif v(10) = '1' then return("1010");
elsif v( 9) = '1' then return("1001");
elsif v( 8) = '1' then return("1000");
elsif v( 7) = '1' then return("0111");
elsif v( 6) = '1' then return("0110");
elsif v( 5) = '1' then return("0101");
elsif v( 4) = '1' then return("0100");
elsif v( 3) = '1' then return("0011");
elsif v( 2) = '1' then return("0010");
elsif v( 1) = '1' then return("0001");
else return ("0000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable temp : std_logic_vector(15 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
temp := ((ir.iforce or ir.ipend) and ir.imask) & '0';
irv.irl := priority(temp(15 downto 1) and ir.ilevel);
if irv.irl = "0000" then
irv.irl := priority(temp(15 downto 1) and not ir.ilevel);
end if;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(31 downto 17) := ir.ilevel;
rdata(15 downto 1) := ir.imask;
when "01" => rdata(15 downto 1) := ir.ipend;
when "10" => rdata(15 downto 1) := ir.iforce;
when others => rdata := (others => '-');
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.ilevel := apbi.pwdata(31 downto 17);
irv.imask := apbi.pwdata(15 downto 1);
when "01" => irv.ipend := apbi.pwdata(15 downto 1);
when "10" => irv.iforce := apbi.pwdata(15 downto 1);
when "11" => irv.ipend := ir.ipend and not apbi.pwdata(15 downto 1);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or irqi.irq; -- merge incoming interrupts
-- clear irq pending/force on intack
if irqi.intack = '1' then
temp := decode(irqi.irl);
irv.iforce := ir.iforce and not temp(15 downto 1);
irv.ipend := irv.ipend and not ((not ir.iforce) and temp(15 downto 1));
end if;
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irl <= ir.irl;
end process;
regs : process(clk)
begin if rising_edge(clk) then ir <= irin; end if; end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl
-- File: irqctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Interrupt controller. Implements a two-level interrupt
-- controller for the 15 SPARC interrupts.
------------------------------------------------------------------------------
-- Version control:
-- 07-08-1998: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.macro.decode;
use work.amba.all;
entity irqctrl is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_in_type;
irqo : out irq_out_type
);
end;
architecture rtl of irqctrl is
type irqregs is record
imask : std_logic_vector(15 downto 1);
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : std_logic_vector(15 downto 1);
irl : std_logic_vector( 3 downto 0);
end record;
function priority(v : std_logic_vector(15 downto 1)) return std_logic_vector is
begin
if v(15) = '1' then return("1111");
elsif v(14) = '1' then return("1110");
elsif v(13) = '1' then return("1101");
elsif v(12) = '1' then return("1100");
elsif v(11) = '1' then return("1011");
elsif v(10) = '1' then return("1010");
elsif v( 9) = '1' then return("1001");
elsif v( 8) = '1' then return("1000");
elsif v( 7) = '1' then return("0111");
elsif v( 6) = '1' then return("0110");
elsif v( 5) = '1' then return("0101");
elsif v( 4) = '1' then return("0100");
elsif v( 3) = '1' then return("0011");
elsif v( 2) = '1' then return("0010");
elsif v( 1) = '1' then return("0001");
else return ("0000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable temp : std_logic_vector(15 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
temp := ((ir.iforce or ir.ipend) and ir.imask) & '0';
irv.irl := priority(temp(15 downto 1) and ir.ilevel);
if irv.irl = "0000" then
irv.irl := priority(temp(15 downto 1) and not ir.ilevel);
end if;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(31 downto 17) := ir.ilevel;
rdata(15 downto 1) := ir.imask;
when "01" => rdata(15 downto 1) := ir.ipend;
when "10" => rdata(15 downto 1) := ir.iforce;
when others => rdata := (others => '-');
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.ilevel := apbi.pwdata(31 downto 17);
irv.imask := apbi.pwdata(15 downto 1);
when "01" => irv.ipend := apbi.pwdata(15 downto 1);
when "10" => irv.iforce := apbi.pwdata(15 downto 1);
when "11" => irv.ipend := ir.ipend and not apbi.pwdata(15 downto 1);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or irqi.irq; -- merge incoming interrupts
-- clear irq pending/force on intack
if irqi.intack = '1' then
temp := decode(irqi.irl);
irv.iforce := ir.iforce and not temp(15 downto 1);
irv.ipend := irv.ipend and not ((not ir.iforce) and temp(15 downto 1));
end if;
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irl <= ir.irl;
end process;
regs : process(clk)
begin if rising_edge(clk) then ir <= irin; end if; end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: irqctrl
-- File: irqctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Interrupt controller. Implements a two-level interrupt
-- controller for the 15 SPARC interrupts.
------------------------------------------------------------------------------
-- Version control:
-- 07-08-1998: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.macro.decode;
use work.amba.all;
entity irqctrl is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_in_type;
irqo : out irq_out_type
);
end;
architecture rtl of irqctrl is
type irqregs is record
imask : std_logic_vector(15 downto 1);
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : std_logic_vector(15 downto 1);
irl : std_logic_vector( 3 downto 0);
end record;
function priority(v : std_logic_vector(15 downto 1)) return std_logic_vector is
begin
if v(15) = '1' then return("1111");
elsif v(14) = '1' then return("1110");
elsif v(13) = '1' then return("1101");
elsif v(12) = '1' then return("1100");
elsif v(11) = '1' then return("1011");
elsif v(10) = '1' then return("1010");
elsif v( 9) = '1' then return("1001");
elsif v( 8) = '1' then return("1000");
elsif v( 7) = '1' then return("0111");
elsif v( 6) = '1' then return("0110");
elsif v( 5) = '1' then return("0101");
elsif v( 4) = '1' then return("0100");
elsif v( 3) = '1' then return("0011");
elsif v( 2) = '1' then return("0010");
elsif v( 1) = '1' then return("0001");
else return ("0000"); end if;
end;
signal ir, irin : irqregs;
begin
irqhandler : process(rst, ir, apbi, irqi)
variable irv : irqregs;
variable temp : std_logic_vector(15 downto 0);
variable rdata : std_logic_vector(31 downto 0);
begin
irv := ir;
-- resolve interrupts
temp := ((ir.iforce or ir.ipend) and ir.imask) & '0';
irv.irl := priority(temp(15 downto 1) and ir.ilevel);
if irv.irl = "0000" then
irv.irl := priority(temp(15 downto 1) and not ir.ilevel);
end if;
-- register read/write
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => rdata(31 downto 17) := ir.ilevel;
rdata(15 downto 1) := ir.imask;
when "01" => rdata(15 downto 1) := ir.ipend;
when "10" => rdata(15 downto 1) := ir.iforce;
when others => rdata := (others => '-');
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" => irv.ilevel := apbi.pwdata(31 downto 17);
irv.imask := apbi.pwdata(15 downto 1);
when "01" => irv.ipend := apbi.pwdata(15 downto 1);
when "10" => irv.iforce := apbi.pwdata(15 downto 1);
when "11" => irv.ipend := ir.ipend and not apbi.pwdata(15 downto 1);
when others => null;
end case;
end if;
irv.ipend := irv.ipend or irqi.irq; -- merge incoming interrupts
-- clear irq pending/force on intack
if irqi.intack = '1' then
temp := decode(irqi.irl);
irv.iforce := ir.iforce and not temp(15 downto 1);
irv.ipend := irv.ipend and not ((not ir.iforce) and temp(15 downto 1));
end if;
-- clear irq mask and pending on reset
if rst = '0' then
irv.imask := (others => '0');
end if;
irin <= irv;
apbo.prdata <= rdata;
irqo.irl <= ir.irl;
end process;
regs : process(clk)
begin if rising_edge(clk) then ir <= irin; end if; end process;
end;
|
entity issue335 is
end entity;
use std.textio.all;
architecture a of issue335 is
begin
main : process is
variable tmp : integer;
variable l : line;
begin
l := new string'("1");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "1";
read(l, tmp);
assert tmp = 1;
l := new string'("22");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "22";
-- Uncomment this to make it work
l := new string'("333");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "333";
wait;
end process;
end architecture;
|
entity issue335 is
end entity;
use std.textio.all;
architecture a of issue335 is
begin
main : process is
variable tmp : integer;
variable l : line;
begin
l := new string'("1");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "1";
read(l, tmp);
assert tmp = 1;
l := new string'("22");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "22";
-- Uncomment this to make it work
l := new string'("333");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "333";
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: my.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- Proceduuras dazhaadu figuuru ziimeeshanai uz ekraana.
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--h_pulse : INTEGER := 96; --horiztonal sync pulse width in pixels 800 un 525
--h_bp : INTEGER := 48; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 640; --horiztonal display width in pixels
--h_fp : INTEGER := 16; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 2; --vertical sync pulse width in rows
--v_bp : INTEGER := 33; --vertical back porch width in rows
--v_pixels : INTEGER := 480; --vertical display width in rows
--v_fp : INTEGER := 10 --vertical front porch width in rows
--h_pulse : INTEGER := 112; --horiztonal sync pulse width in pixels 1688 un 1066
--h_bp : INTEGER := 248; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 1280; --horiztonal display width in pixels
--h_fp : INTEGER := 48; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 3; --vertical sync pulse width in rows
--v_bp : INTEGER := 38; --vertical back porch width in rows
--v_pixels : INTEGER := 1024; --vertical display width in rows
--v_fp : INTEGER := 1 --vertical front porch width in rows
--h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels 1056 un 628
--h_bp : INTEGER := 88; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 800; --horiztonal display width in pixels
--h_fp : INTEGER := 40; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 4; --vertical sync pulse width in rows
--v_bp : INTEGER := 23; --vertical back porch width in rows
--v_pixels : INTEGER := 600; --vertical display width in rows
--v_fp : INTEGER := 1 --vertical front porch width in rows
PACKAGE MY IS
---------------------------------------------------------
-- Procedura sanjem pashreizejas koordinatas ekrana un --
-- ari koordinatu, no kuras sakt zimet kvadratu. --
-- Procedura atgriez RGB signalu un DRAW indikatoru, --
-- kursh pasaka, vai tiek zimets vai ne. --
---------------------------------------------------------
PROCEDURE SQ(
SIGNAL Xcur : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ycur : IN INTEGER RANGE 0 TO 1066;
SIGNAL Xpos : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ypos : IN INTEGER RANGE 0 TO 1688;
SIGNAL RGB : OUT STD_LOGIC;
SIGNAL DRAW : OUT STD_LOGIC
);
END MY;
PACKAGE BODY MY IS
PROCEDURE SQ(
SIGNAL Xcur : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ycur : IN INTEGER RANGE 0 TO 1066;
SIGNAL Xpos : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ypos : IN INTEGER RANGE 0 TO 1688;
SIGNAL RGB : OUT STD_LOGIC;
SIGNAL DRAW : OUT STD_LOGIC
) IS
BEGIN
IF(Xcur>Xpos AND Xcur<(Xpos+100) AND Ycur>Ypos AND Ycur<(Ypos+100))THEN -- 100x100 pikselu kvadrats.
RGB<='1';
DRAW<='1';
ELSE
DRAW<='0';
END IF;
END SQ;
END MY; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
-- OneWire_i : in std_logic;
-- OneWire_o : out std_logic;
-- PWMInput_i : in std_logic;
-- SENTInput_i : in std_logic;
-- SPCInput_i : in std_logic;
-- SPCTrigger_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7410_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
i2c_addr_i : in std_logic_vector(1 downto 0);
int_o : out std_logic;
ct_o : out std_logic;
temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal LFXT_Clk_i : std_logic;
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic := '0';
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic := 'H';
signal Dbg_SDA_Out_o : std_logic;
signal Dbg_SDA_In_i : std_logic := 'H';
signal P1_DOut_o : std_logic_vector(7 downto 0);
signal P1_En_o : std_logic_vector(7 downto 0);
signal P1_DIn_i : std_logic_vector(7 downto 0);
signal P2_DOut_o : std_logic_vector(7 downto 0);
signal P2_En_o : std_logic_vector(7 downto 0);
signal P2_DIn_i : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic := '1';
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic := '0';
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_o : std_logic;
signal I2CSDA_i : std_logic;
signal I2CSDA_o : std_logic;
-- signal OneWire_i : std_logic;
-- signal OneWire_o : std_logic;
-- signal PWMInput_i : std_logic;
-- signal SENTInput_i : std_logic;
-- signal SPCInput_i : std_logic;
-- signal SPCTrigger_o : std_logic;
signal AdcConvComplete_i : std_logic := '0';
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0) := (others => '0');
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_e : std_logic; -- directly from inside I2C_FSM
signal CpuIntr_e : std_logic; -- directly from inside I2C_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- ADT7410 component ports
signal I2C_SDA_s : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
signal TempBin_s : std_logic_vector(15 downto 0);
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: Core
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
LFXT_Clk_i => LFXT_Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_Out_o => Dbg_SDA_Out_o,
Dbg_SDA_In_i => Dbg_SDA_In_i,
P1_DOut_o => P1_DOut_o,
P1_En_o => P1_En_o,
P1_DIn_i => P1_DIn_i,
P2_DOut_o => P2_DOut_o,
P2_En_o => P2_En_o,
P2_DIn_i => P2_DIn_i,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_o => I2CSCL_o,
I2CSDA_i => I2CSDA_i,
I2CSDA_o => I2CSDA_o,
-- OneWire_i => OneWire_i,
-- OneWire_o => OneWire_o,
-- PWMInput_i => PWMInput_i,
-- SENTInput_i => SENTInput_i,
-- SPCInput_i => SPCInput_i,
-- SPCTrigger_o => SPCTrigger_o,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
Inputs_i <= (others => '0');
P1_DIn_i <= (others => '0');
P2_DIn_i <= (others => '0');
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
I2CFSM_Done_d <= I2CFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
TempBin_s <= std_logic_vector(to_unsigned(integer(Temp_s*128.0),16));
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
I2C_SDA_s <= 'H'; -- weak 1 -> simulate pull-up
I2C_SDA_s <= '0' when I2CSDA_o = '0' else 'Z';
I2CSDA_i <= to_X01(I2C_SDA_s) after 0.2 us;
adt7410_1: adt7410_model
port map (
scl_i => I2CSCL_o,
sda_io => I2C_SDA_s,
i2c_addr_i => "00",
INT_o => INT_n_s,
CT_o => CT_n_s,
temp_i => TempBin_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
wait until I2CFSM_Done_d = '1';
report "Starting with test pattern" severity note;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'high = 3 report "TEST FAILED high = 3" severity failure;
report "TEST PASSED high = 3";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'high = 3 report "TEST FAILED high = 3" severity failure;
report "TEST PASSED high = 3";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'high = 3 report "TEST FAILED high = 3" severity failure;
report "TEST PASSED high = 3";
wait;
end process p;
end only;
|
library verilog;
use verilog.vl_types.all;
entity receive_top_module is
port(
clk_50M : in vl_logic;
clk_100M : in vl_logic;
reset_n : in vl_logic;
Trans_Data : out vl_logic_vector(7 downto 0)
);
end receive_top_module;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity instr_cache is
port (
clk : in std_logic;
reset : in std_logic;
-- cache/if
id_instr_addr : in word_t;
id_instr_valid : out std_logic;
id_instr : out word_t;
-- cache/mmu
mmu_instr_addr : out word_t;
mmu_enable : out std_logic;
mmu_instr_valid : in std_logic;
--~ invalidate
mmu_instr : in word_t
);
end instr_cache;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- Only if you want/need to change/adjust the resampling algorithm
-- you can change it here.
--
-- Here the Residual Systematic Resampling Algorithm is used.
-- It is not easy to change to a complete other resampling algorithm,
-- because the framework is adjusted to use a algorithm, which
-- only uses one cycle of iterations and so without any correction cycle.
--
-- Some basic information about the resampling user function:
--
-- The particle weights are loaded into the local RAM by the Framework
-- The first 63 * 128 bytes (of 64 * 128 bytes) are filled with
-- all the particle weights needed. There will not be any space
-- between the particle weights.
--
-- The last 128 bytes are used for the resampling.
-- The user has to store two values for every particle.
-- 1. the index of the particle (as integer)
-- 2. the replication factor of the particle (as integer)
-- The ordering of this two values must not be changed,
-- because it is used later for the sampling step.
--
-- The two integer values (also known as index_type) are written
-- into the last 128 byte. Since two integer values need 8 bytes,
-- information about 16 particles can be written into the last 128 bytes
-- of the local ram before they have to be written by the Framework.
--
-- The outgoing signal write_burst has to be '1', if the the indexes
-- and replication factors should be written into the Main Memory.
-- This should only happen, if the information about 16
-- particles is resampled or the last particle has been resampled.
--
-- The incoming signal write_burst_done is equal to '1', if the
-- Framework has written the information to the Main Memory
--
-- If resampling is finished the outgoing signal finish has to be set to '1'.
-- A new run of the resampling will be started if the next particles are
-- loaded into local RAM. This is the case when the incoming signal
-- particles_loaded is equal to '1'.
--
------------------------------------------------------------------------------------
entity uf_resampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- additional incoming signals
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- additional outgoing signals
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_resampling;
architecture Behavioral of uf_resampling is
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- local RAM read/write address
signal local_ram_read_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_write_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- particle counter for allready resampled particles at all
signal counter_resampled_particles : integer := 0;
-- write counter (used bytes)
signal write_counter :integer := 0;
-- current particle weight
signal current_particle_weight : integer := 0;
-- signals needed for residual systematic resampling
signal temp : integer := 0;
signal fact : integer := 0; -- replication factor
signal U : integer := 0;
-- states
type t_state is (initialize,
load_particle_1, load_particle_2, load_weight,
calculate_replication_factor_1, calculate_replication_factor_2,
calculate_replication_factor_3, calculate_replication_factor_4,
calculate_replication_factor_5, calculate_replication_factor_6,
write_particle_index, write_particle_replication,
write_burst_decision, write_burst, write_burst_done_ack,
write_burst_done_ack_2, finish
);
-- current state
signal state : t_state := initialize;
begin
-- burst ram clock
o_RAMClk <= clk;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
-- (0) initialize
--
-- i = 0; // current particle
-- j = 0; // current replication factor
-- k = 0; // current number of cloned particles
-- finished = 0;
--
--
-- (1) load particle and weight
--
-- load weight of i-th particle from local memory
-- i ++;
--
--
-- (2) calculate replication
--
-- calculate replication factor
--
--
-- (3) write particle index and replication
--
-- write particle index + replicationfactor to local ram
--
--
-- (4) write burst
--
-- write_burst = 1;
-- if (write_burst_done)
-- write_burst = 0;
-- go to step 4
--
--
-- (5) finished
--
-- finished = 1;
-- if (particles_loaded)
-- go to step 0;
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= initialize;
elsif rising_edge(clk) then
if init = '1' then
state <= initialize;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
U <= U_init;
elsif enable = '1' then
case state is
when initialize =>
--! init data
local_ram_read_address <= (others => '0');
local_ram_write_address <= write_address;
counter_resampled_particles <= 0;
counter <= start_particle_index;
current_particle_weight <= 0;
temp <= 0;
fact <= 0;
--U <= U_init;
write_counter <= 0;
written_values <= 0;
write_burst <= '0';
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
state <= load_particle_1;
end if;
when load_particle_1 =>
--! load a particle
write_burst <= '0';
if (number_of_particles <= counter_resampled_particles) then
state <= write_burst_decision;
else
o_RAMAddr <= local_ram_read_address;
state <= load_particle_2;
end if;
when load_particle_2 =>
--!needed because reading from local RAM needs two clock steps
state <= load_weight;
when load_weight =>
--! load particle weight
current_particle_weight <= TO_INTEGER(SIGNED(i_RAMData));
state <= calculate_replication_factor_1;
when calculate_replication_factor_1 =>
--! calculate replication factor (step 2/6)
temp <= current_particle_weight * number_of_particles_in_total;
state <= calculate_replication_factor_2;
when calculate_replication_factor_2 =>
--! calculate replication factor (step 2/6)
temp <= temp - U;
state <= calculate_replication_factor_3;
when calculate_replication_factor_3 =>
--! calculate replication factor (step 3/6)
fact <= temp + GRANULARITY;
state <= calculate_replication_factor_4;
when calculate_replication_factor_4 =>
--! calculate replication factor (step 4/6)
fact <= fact / GRANULARITY;
state <= calculate_replication_factor_5;
when calculate_replication_factor_5 =>
--! calculate replication factor (step 5/6)
U <= fact * GRANULARITY;
state <= calculate_replication_factor_6;
when calculate_replication_factor_6 =>
--! calculate replication factor (step 6/6)
U <= U - temp;
state <= write_particle_index;
-- todo: change back
--state <= write_burst_decision;
when write_particle_index =>
--! read particle from local ram
-- copy particle_size / 32 from local RAM to local RAM
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(counter, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
state <= write_particle_replication;
when write_particle_replication =>
--! needed because reading takes 2 clock steps
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(fact, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
write_counter <= write_counter + 1;
state <= write_burst_decision;
when write_burst_decision =>
--! write burst to main memory
o_RAMWE <= '0';
if (16 <= write_counter) then
-- write burst
state <= write_burst;
-- todo change back
--state <= write_burst_decision;
write_counter <= 0;
local_ram_write_address <= write_address;
written_values <= 16;
elsif (number_of_particles <= counter_resampled_particles and write_counter > 0) then
-- write burst
state <= write_burst;
--todo: changed back
--state <= write_burst_decision;
write_counter <= 0;
--write_burst <= '1';
written_values <= write_counter;
elsif (number_of_particles <= counter_resampled_particles) then
state <= finish;
else
-- get next particle
counter <= counter + 1;
counter_resampled_particles <= counter_resampled_particles + 1;
local_ram_read_address <= local_ram_read_address + 1;
state <= load_particle_1;
end if;
when write_burst =>
--! write burst to main memory
--write_burst <= '1';
--written_values <= write_counter;
write_burst <= '1';
write_burst_done_ack <= '0';
--change back
--write_counter <= 0;
if (write_burst_done = '1') then
write_burst <= '0';
state <= write_burst_done_ack;
end if;
when write_burst_done_ack =>
--! write burst to main memory
write_burst_done_ack <= '1';
write_counter <= 0;
write_burst <= '0';
if (write_burst_done = '0') then
state <= write_burst_done_ack_2;
end if;
when write_burst_done_ack_2 =>
--! write burst to main memory
write_burst_done_ack <= '0';
if (number_of_particles <= counter_resampled_particles) then
state <= finish;
else
--todo: changed for hopefully good
--state <= load_particle_1;
state <= write_burst_decision;
end if;
when finish =>
--! write finished signal
write_burst <= '0';
finished <= '1';
if (particles_loaded = '1') then
state <= initialize;
end if;
when others =>
state <= initialize;
end case;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- FILE: Div
-- DESC: Divider
--
-- Author:
-- Create: 2015-09-09
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
DIV_STAGE : integer := C_DIV_STAGE;
SQRT_STAGE : integer := C_SQRT_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
lock: in std_logic:='0';
sign: in std_logic:='0'; -- 0 UNSIGNED, 1 SIGNED
func: in std_logic:='0'; -- 0 DIV, 1 SQRT
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end Div;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture div_arch of Div is
component AddSub is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
as: in std_logic; -- Add(Active High)/Sub(Active Low)
a, b: in std_logic_vector(DATA_SIZE-1 downto 0); -- Operands
re: out std_logic_vector(DATA_SIZE-1 downto 0); -- Return value
cout: out std_logic -- Carry
);
end component;
component Sipo is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic;
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Mux is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic;
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
signal a_adj, b_adj: std_logic_vector(DATA_SIZE-1 downto 0);
signal a_mod_dir, b_mod_dir, b_mod, a_mod: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal a_mux, b_mux: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal a_shf_div, a_shf_sqrt, a_shf : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal b_shf_div, b_shf_sqrt, b_shf : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal r_es : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal r: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal q : std_logic_vector(DATA_SIZE-1 downto 0);
signal not_r_es_sign, not_r_sign: std_logic;
signal en_input, sel_r, en_r, en_q : std_logic:='0';
signal c_state, n_state : integer:=0;
signal inv_a_flag, inv_b_flag, inv_q_flag, inv_q_flag_mod : std_logic:='0';
-- signal o_div, o_sqrt: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal local_rst, reg_rst : std_logic:='1';
signal zeros32: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
-- Datapath
-- INPUT ADJUST
P0: process(clk, en_input)
begin
if rising_edge(clk) and en_input='1' then
a_mod <= a_mod_dir;
b_mod <= b_mod_dir;
inv_q_flag_mod <= inv_q_flag;
end if;
end process;
inv_a_flag <= sign and a(DATA_SIZE-1) and (not func);
inv_b_flag <= sign and b(DATA_SIZE-1) and (not func);
inv_q_flag <= sign and (a(DATA_SIZE-1) xor b(DATA_SIZE-1)) and (not func);
ADJUST0a: AddSub
generic map(DATA_SIZE)
port map(inv_a_flag, zeros32 , a, a_adj, open);
ADJUST0b: AddSub
generic map(DATA_SIZE)
port map(inv_b_flag, zeros32 , b, b_adj, open);
a_mod_dir(DATA_SIZE-1 downto 0) <= a_adj;
a_mod_dir(DATA_SIZE*2-1 downto DATA_SIZE) <= (others=>'0');
b_mod_dir(DATA_SIZE-1 downto 0) <= (others=>'0');
b_mod_dir(DATA_SIZE*2-1 downto DATA_SIZE) <= b_adj;
-- DIV & SQRT CALCULATION
MUXa: Mux
generic map(DATA_SIZE*2)
port map(sel_r, a_mod, r, a_mux);
b_mux <= b_mod;
not_r_sign <= not a_mux(DATA_SIZE*2-1);
a_shf_div(DATA_SIZE*2-1 downto 1) <= a_mux(DATA_SIZE*2-2 downto 0);
a_shf_div(0) <= '0';
a_shf_sqrt(DATA_SIZE*2-1 downto 2) <= a_mux(DATA_SIZE*2-3 downto 0);
a_shf_sqrt(1 downto 0) <= "00";
a_shf <= a_shf_sqrt when func='1' else a_shf_div;
b_shf_div <= b_mux;
b_shf_sqrt(DATA_SIZE*2-1 downto DATA_SIZE+2) <= q(DATA_SIZE-3 downto 0);
b_shf_sqrt(DATA_SIZE+1 downto DATA_SIZE) <= "01" when not_r_sign='1' else "11";
b_shf_sqrt(DATA_SIZE-1 downto 0) <= (others=>'0');
b_shf <= b_shf_sqrt when func='1' else b_shf_div;
ADD0: AddSub
generic map(DATA_SIZE*2)
port map(not_r_sign, a_shf, b_shf, r_es, open);
reg_rst <= rst and local_rst;
REG_R: Reg
generic map(DATA_SIZE*2)
port map(reg_rst, en_r, clk, r_es, r);
not_r_es_sign <= not r_es(DATA_SIZE*2-1);
REG_Q: Sipo
generic map(DATA_SIZE)
port map(reg_rst, en_q, clk, not_r_es_sign, q);
-- OUTPUT ADJUST
-- NEG q IF NEEDED (FOR DIV)
ADJUST: AddSub
generic map(DATA_SIZE)
port map(inv_q_flag_mod, zeros32, q, o, open);
-- MASK HIGH 16 bits to '0' (FOR SQRT)
-- o_sqrt <= q and x"0000ffff";
-- CHOOSE OUTPUT BASED ON func
-- o <= o_sqrt when func='1' else o_div;
-- Control Logic (FSM)
-- NEXT STATE GENERATOR
P_NSG1: process(en, c_state, lock)
begin
if en='1' and lock='1' then
n_state<=SG_ST0;
else
if en='1' and c_state = SG_ST0 and lock='0' then
n_state<=SG_ST1;
else
if c_state = SG_ST0 or (c_state>=DIV_STAGE-1 and func='0') or (c_state>=SQRT_STAGE-1 and func='1') then
n_state <= SG_ST0;
else
n_state <= c_state + 1;
end if;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT1: process(c_state)
begin
if c_state=SG_ST1 then
en_input <= '0';
sel_r <= '0';
en_r <= '1';
en_q <= '1';
local_rst <= '1';
elsif c_state>SG_ST1 and ((c_state<DIV_STAGE and func='0') or (c_state<SQRT_STAGE and func='1'))then
en_input <= '0';
sel_r <= '1';
en_r <= '1';
en_q <= '1';
local_rst <= '1';
else
en_input <= '1';
sel_r <= '0';
en_r <= '0';
en_q <= '0';
local_rst <= '0';
end if;
end process;
-- NEXT STATE REGISTER
P_REG1: process(rst, clk)
begin
if rst='0' then
c_state <= SG_ST0;
else
if rising_edge(clk) then
c_state <= n_state;
end if;
end if;
end process;
end div_arch;
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : 7-Segment-Display Model
-- Last update : 04.12.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
entity seven_seg_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns -- 50 MHz
);
port (
-- global signals
end_simulation : in std_ulogic;
-- 7-seg connections
hex0_n : in std_ulogic_vector(6 downto 0);
hex1_n : in std_ulogic_vector(6 downto 0);
hex2_n : in std_ulogic_vector(6 downto 0);
hex3_n : in std_ulogic_vector(6 downto 0);
hex4_n : in std_ulogic_vector(6 downto 0);
hex5_n : in std_ulogic_vector(6 downto 0);
hex6_n : in std_ulogic_vector(6 downto 0);
hex7_n : in std_ulogic_vector(6 downto 0)
);
end seven_seg_model;
architecture sim of seven_seg_model is
-- model can only be used with the iac-seven_seg-interface, only 0,1,2,3,4,5,6,7,8,9,0,A,b,C,d,E,F, ,-,X are possible values
-- convert 7-seg to character
function seg_to_char(segments : std_ulogic_vector(6 downto 0)) return character is
variable tmp : character;
begin
-- decode 7-segment (inverted!)
case segments is
when "1000000" => tmp := '0'; -- 0
when "1111001" => tmp := '1'; -- 1
when "0100100" => tmp := '2'; -- 2
when "0110000" => tmp := '3'; -- 3
when "0011001" => tmp := '4'; -- 4
when "0010010" => tmp := '5'; -- 5
when "0000010" => tmp := '6'; -- 6
when "1111000" => tmp := '7'; -- 7
when "0000000" => tmp := '8'; -- 8
when "0010000" => tmp := '9'; -- 9
when "0001000" => tmp := 'A'; -- A
when "0000011" => tmp := 'b'; -- b
when "1000110" => tmp := 'C'; -- C
when "0100001" => tmp := 'd'; -- d
when "0000110" => tmp := 'E'; -- E
when "0001110" => tmp := 'F'; -- F
when "1111111" => tmp := ' '; -- off
when "0111111" => tmp := '-'; -- - (minus)
when others => tmp := 'X'; -- unexpected value: X
end case;
return tmp;
end function seg_to_char;
begin
process
-- line for textio
variable active_line : line;
-- internal vars for display-content, initialize empty
variable seg0 : character := ' ';
variable seg1 : character := ' ';
variable seg2 : character := ' ';
variable seg3 : character := ' ';
variable seg4 : character := ' ';
variable seg5 : character := ' ';
variable seg6 : character := ' ';
variable seg7 : character := ' ';
variable display_changed : boolean := false;
begin
loop
-- stop when simulation has ended
exit when end_simulation = '1';
-- check if display should change (any display not turned off, and value differs from active display)
--if (hex0_n /= "1111111") and (seg0 /= seg_to_char(hex0_n)) and hex0_n /= "UUUUUUU" then
if (seg0 /= seg_to_char(hex0_n)) and hex0_n /= "UUUUUUU" then
seg0 := seg_to_char(hex0_n);
display_changed := true;
end if;
if (seg1 /= seg_to_char(hex1_n)) and hex1_n /= "UUUUUUU" then
seg1 := seg_to_char(hex1_n);
display_changed := true;
end if;
if (seg2 /= seg_to_char(hex2_n)) and hex2_n /= "UUUUUUU" then
seg2 := seg_to_char(hex2_n);
display_changed := true;
end if;
if (seg3 /= seg_to_char(hex3_n)) and hex3_n /= "UUUUUUU" then
seg3 := seg_to_char(hex3_n);
display_changed := true;
end if;
if (seg4 /= seg_to_char(hex4_n)) and hex4_n /= "UUUUUUU" then
seg4 := seg_to_char(hex4_n);
display_changed := true;
end if;
if (seg5 /= seg_to_char(hex5_n)) and hex5_n /= "UUUUUUU" then
seg5 := seg_to_char(hex5_n);
display_changed := true;
end if;
if (seg6 /= seg_to_char(hex6_n)) and hex6_n /= "UUUUUUU" then
seg6 := seg_to_char(hex6_n);
display_changed := true;
end if;
if (seg7 /= seg_to_char(hex7_n)) and hex7_n /= "UUUUUUU" then
seg7 := seg_to_char(hex7_n);
display_changed := true;
end if;
-- display change -> printout
if display_changed = true then
-- generate printout
write(active_line, string'("[7-SEG] ["));
write(active_line, seg7);
write(active_line, string'("]["));
write(active_line, seg6);
write(active_line, string'("] ["));
write(active_line, seg5);
write(active_line, string'("]["));
write(active_line, seg4);
write(active_line, string'("] ["));
write(active_line, seg3);
write(active_line, string'("]["));
write(active_line, seg2);
write(active_line, string'("]["));
write(active_line, seg1);
write(active_line, string'("]["));
write(active_line, seg0);
write(active_line, string'("]"));
writeline(output, active_line);
-- reset display_changed
display_changed := false;
end if;
-- wait for one cycle
wait for SYSTEM_CYCLE_TIME;
end loop;
-- wait forever
wait;
end process;
end sim;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp)
port map (
clk => gnd,
gclk2 => gclk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
clk : in std_logic; -- simulation clock (slow)
clk_x32 : in std_logic; -- prng clock (fast)
-- Write channel
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
-- Read channel
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0)
);
attribute syn_hier : string;
attribute syn_hier of faultify_top : entity is "hard";
end faultify_top;
architecture behav of faultify_top is
component flag_cdc
port (
clkA : in std_logic;
clkB : in std_logic;
FlagIn_clkA : in std_logic;
FlagOut_clkB : out std_logic;
rst_n : in std_logic);
end component;
component faultify_simulator
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end component;
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
type vector is array (0 to numOut-1) of std_logic_vector(31 downto 0);
signal errorSum : vector;
signal errorSumReg : vector;
signal errorSumReg_cdc_0 : vector;
signal errorSumReg_cdc_1 : vector;
signal errorVec : std_logic_vector(numOut-1 downto 0);
signal cnt : integer;
signal cnt_cdc_0 : integer;
signal cnt_cdc_1 : integer;
-- Asymmetric ram larger than 36 bit not supported in synplify I-2013
--type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(63 downto 0);
--signal seed_ram : seed_ram_matr;
-- workaround 2 32-bit rams
type seed_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal seed_ram_low : seed_ram_matr;
signal seed_ram_high : seed_ram_matr;
--subtype seed_ram_matr_word_t is std_logic_vector(63 downto 0);
--type seed_ram_matr_memory_t is array (0 to numInj-1) of seed_ram_matr_word_t;
--signal seed_ram : seed_ram_matr_memory_t;
type prob_ram_matr is array (0 to numInj-1) of std_logic_vector(31 downto 0);
signal prob_ram : prob_ram_matr;
type reg_type is record
control : std_logic_vector(31 downto 0);
status : std_logic_vector(31 downto 0);
pe_location : std_logic_vector(31 downto 0);
pe_seed_low : std_logic_vector(31 downto 0);
pe_seed_high : std_logic_vector(31 downto 0);
pe_probability : std_logic_vector(31 downto 0);
output : std_logic_vector(31 downto 0);
ovalid : std_logic;
simtime : std_logic_vector(31 downto 0);
sel_soe : std_logic_vector(31 downto 0);
adr_soe : std_logic_vector(31 downto 0);
awaddr : std_logic_vector(31 downto 0);
test : std_logic_vector(31 downto 0);
circreset : std_logic_vector(31 downto 0);
cnt_tmp : std_logic_vector(31 downto 0);
sumoferrors : vector;
end record;
signal busy_loading : std_logic;
signal busy_simulating : std_logic;
signal busy_loading_reg : std_logic_vector(1 downto 0);
signal busy_simulating_reg : std_logic_vector(1 downto 0);
signal sim_done : std_logic;
signal r : reg_type;
type load_fsm_states is (IDLE, LOADSEED, LOADPROB);
signal l_state : load_fsm_states;
type sim_states is (IDLE, DELAY_Z, DELAY, SIMULATION, DELAY2, DELAY3, DELAY4, FREE_SIMULATION);
signal s_state : sim_states;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
signal seed_in_en : std_logic;
signal seed_in : std_logic;
signal prob_in_en : std_logic;
signal prob_in : std_logic;
signal shift_en : std_logic;
signal shift_en_l : std_logic;
signal shift_en_s : std_logic;
signal load_seed_prob : std_logic;
signal start_simulation : std_logic;
signal start_free_simulation : std_logic;
signal stop_simulation : std_logic;
signal circ_ce, circ_rst, circ_rst_sim : std_logic;
signal tvec : std_logic_vector(127 downto 0);
signal test : std_logic_vector(31 downto 0);
signal rst_cdc, rst_cdc_n : std_logic;
type tb_state_defs is (IDLE, DATA, WAITING);
signal tb_state : tb_state_defs;
begin -- behav
-----------------------------------------------------------------------------
-- PRNG shifting
-----------------------------------------------------------------------------
shift_en <= shift_en_l or shift_en_s;
-----------------------------------------------------------------------------
-- Testvector
-----------------------------------------------------------------------------
--testvector <= (others => '0');
lfsr_1 : lfsr
generic map (
width => 128,
seed => 3498327)
port map (
clk => clk,
rand_out => tvec);
testvector(63 downto 0) <= tvec(63 downto 0);
testvector(66 downto 64) <= "010";
testvector(68 downto 67) <= "00";
--testvector(69) <= tvec(64);
process (clk, circ_rst_sim) is
begin -- process
if circ_rst_sim = '1' then -- asynchronous reset (active low)
testvector(69) <= '0';
tb_state <= IDLE;
elsif clk'event and clk = '1' then -- rising clock edge
case tb_state is
when IDLE =>
tb_state <= DATA;
testvector(69) <= '1';
when DATA =>
tb_state <= WAITING;
testvector(69) <= '0';
when WAITING =>
if resultvector_o(32) = '1' then
tb_state <= DATA;
testvector(69) <= '1';
end if;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Simulator
-----------------------------------------------------------------------------
circ_rst <= circ_rst_sim when r.circreset(0) = '1' else '0';
faultify_simulator_1 : faultify_simulator
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
clk => clk_x32,
clk_m => clk,
circ_ce => circ_ce,
circ_rst => circ_rst,
test => test,
testvector => testvector,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
seed_in_en => seed_in_en,
seed_in => seed_in,
prob_in_en => prob_in_en,
prob_in => prob_in,
shift_en => shift_en,
rst_n => arst_n);
-------------------------------------------------------------------------------
-- One Process Flow
-------------------------------------------------------------------------------
register_process : process (aclk, arst_n)
variable write_addr : std_logic_vector(31 downto 0);
begin -- process register_process
if arst_n = '0' then -- asynchronous reset (active low)
r.control <= (others => '0');
r.status <= (others => '0');
r.pe_probability <= (others => '0');
r.pe_seed_high <= (others => '0');
r.pe_seed_low <= (others => '0');
r.pe_location <= (others => '0');
r.ovalid <= '0';
r.simtime <= (others => '0');
r.sel_soe <= (others => '0');
r.adr_soe <= (others => '0');
r.sumoferrors <= (others => (others => '0'));
r.output <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
r.control <= (others => '0');
if awvalid = '1' then
r.awaddr <= awaddr;
write_addr := awaddr;
end if;
if wvalid = '1' then
if write_addr = x"00000000" then
r.control <= wdata;
elsif write_addr = x"00000001" then
r.pe_location <= wdata;
elsif write_addr = x"00000002" then
r.pe_seed_low <= wdata;
elsif write_addr = x"00000003" then
r.pe_seed_high <= wdata;
elsif write_addr = x"00000004" then
r.pe_probability <= wdata;
elsif write_addr = x"00000005" then
r.cnt_tmp <= std_logic_vector(to_unsigned(cnt_cdc_1, 32));
r.adr_soe <= wdata;
elsif write_addr = x"00000007" then
r.simtime <= wdata;
elsif write_addr = x"00000009" then
r.circreset <= wdata;
end if;
end if;
if arvalid = '1' then
if araddr = x"0000000F" then
r.output <= r.status;
elsif araddr = x"00000001" then
r.output <= r.pe_location;
elsif araddr = x"00000002" then
r.output <= r.pe_seed_low;
elsif araddr = x"00000003" then
r.output <= r.pe_seed_high;
elsif araddr = x"00000004" then
r.output <= r.pe_probability;
elsif araddr = x"00000006" then
r.output <= r.sel_soe;
elsif araddr = x"00000008" then
r.output <= r.test;
elsif araddr = x"0000000A" then
r.output <= r.cnt_tmp;
end if;
r.ovalid <= '1';
else
r.ovalid <= '0';
end if;
if busy_loading_reg(1) = '1' then
r.status(0) <= '1';
else
r.status(0) <= '0';
end if;
if busy_simulating_reg(1) = '1' then
r.status(1) <= '1';
else
r.status(1) <= '0';
end if;
r.sel_soe <= r.sumoferrors(to_integer(unsigned(r.adr_soe)));
rdata <= r.output;
rvalid <= r.ovalid;
r.sumoferrors <= errorSumReg_cdc_1;
r.test <= errorSum(0);
end if;
end process register_process;
-----------------------------------------------------------------------------
-- simple clock domain crossing
-----------------------------------------------------------------------------
process (aclk, arst_n)
begin -- process
if arst_n = '0' then -- asynchronous reset (active low)
busy_simulating_reg <= (others => '0');
busy_loading_reg <= (others => '0');
elsif aclk'event and aclk = '1' then -- rising clock edge
busy_simulating_reg(0) <= busy_simulating;
busy_loading_reg(0) <= busy_loading;
busy_simulating_reg(1) <= busy_simulating_reg(0);
busy_loading_reg(1) <= busy_loading_reg(0);
cnt_cdc_0 <= cnt;
cnt_cdc_1 <= cnt_cdc_0;
errorSumReg_cdc_0 <= errorSumReg;
errorSumReg_cdc_1 <= errorSumReg_cdc_0;
end if;
end process;
-------------------------------------------------------------------------------
-- Store seeed/prob
-------------------------------------------------------------------------------
store_seed : process (aclk, arst_n)
begin -- process store_seed
if arst_n = '0' then -- asynchronous reset (active low)
elsif aclk'event and aclk = '1' then -- rising clock edge
if r.control(0) = '1' then
-- Synplify bug workaround
--seed_ram(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high & r.pe_seed_low;
seed_ram_low(to_integer(unsigned(r.pe_location))) <= r.pe_seed_low;
seed_ram_high(to_integer(unsigned(r.pe_location))) <= r.pe_seed_high;
prob_ram(to_integer(unsigned(r.pe_location))) <= r.pe_probability;
end if;
end if;
end process store_seed;
-----------------------------------------------------------------------------
-- Seed/prob loading FSM
-----------------------------------------------------------------------------
--flag_cdc_1 : flag_cdc
-- port map (
-- clkA => aclk,
-- clkB => clk_x32,
-- FlagIn_clkA => r.control(1),
-- FlagOut_clkB => load_seed_prob,
-- rst_n => arst_n);
load_seed_prob <= r.control(1);
seed_prob_loading : process (clk_x32, arst_n)
variable cnt_seed : integer range 0 to 64;
variable cnt_inj : integer range 0 to numInj;
variable cnt_prob : integer range 0 to 32;
begin -- process seed_prob_loading
if arst_n = '0' then -- asynchronous reset (active low)
l_state <= IDLE;
seed_in <= '0';
seed_in_en <= '0';
prob_in <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
busy_loading <= '0';
elsif clk_x32'event and clk_x32 = '1' then -- rising clock edge
case l_state is
when IDLE =>
cnt_seed := 0;
cnt_inj := 0;
cnt_prob := 0;
busy_loading <= '0';
seed_in_en <= '0';
prob_in_en <= '0';
shift_en_l <= '0';
if load_seed_prob = '1' then
busy_loading <= '1';
l_state <= LOADSEED;
end if;
when LOADSEED =>
if cnt_seed < 64 then
shift_en_l <= '1';
seed_in_en <= '1';
-- not working in synplify I-2013
--seed_in <= seed_ram(cnt_inj)(cnt_seed);
--
if cnt_seed < 32 then
seed_in <= seed_ram_low(cnt_inj)(cnt_seed);
else
seed_in <= seed_ram_high(cnt_inj)(cnt_seed-32);
end if;
cnt_seed := cnt_seed + 1;
end if;
if cnt_seed = 64 then
cnt_seed := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= LOADPROB;
--seed_in_en <= '0';
cnt_inj := 0;
end if;
when LOADPROB =>
seed_in_en <= '0';
if cnt_prob < 32 then
prob_in_en <= '1';
prob_in <= prob_ram(cnt_inj)(cnt_prob);
cnt_prob := cnt_prob + 1;
end if;
if cnt_prob = 32 then
cnt_prob := 0;
cnt_inj := cnt_inj + 1;
end if;
if cnt_inj = numInj then
l_state <= IDLE;
cnt_inj := 0;
--prob_in_en <= '0';
end if;
end case;
end if;
end process seed_prob_loading;
-----------------------------------------------------------------------------
-- Simulation FSM
-----------------------------------------------------------------------------
flag_cdc_2 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(2),
FlagOut_clkB => start_simulation,
rst_n => arst_n);
flag_cdc_3 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(3),
FlagOut_clkB => start_free_simulation,
rst_n => arst_n);
flag_cdc_4 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => r.control(4),
FlagOut_clkB => stop_simulation,
rst_n => arst_n);
rst_cdc_5 : flag_cdc
port map (
clkA => aclk,
clkB => clk,
FlagIn_clkA => not arst_n,
FlagOut_clkB => rst_cdc,
rst_n => '1');
rst_cdc_n <= not rst_cdc;
process (clk, rst_cdc_n)
variable simtime : integer;
variable cnt_delay : integer range 0 to 9;
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if rst_cdc_n = '0' then -- asynchronous reset (active low)
s_state <= IDLE;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
busy_simulating <= '0';
sim_done <= '0';
errorSumReg <= (others => (others => '0'));
else
case s_state is
when IDLE =>
sim_done <= '0';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
errorVec <= (others => '0');
--errorSum <= errorSum;
errorSum <= (others => (others => '0'));
--cnt <= 0;
busy_simulating <= '0';
cnt_delay := 0;
if start_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
simtime := to_integer(unsigned(r.simtime));
s_state <= DELAY_Z;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
if start_free_simulation = '1' then
cnt <= 0;
busy_simulating <= '1';
errorSum <= (others => (others => '0'));
errorSumReg <= (others => (others => '0'));
s_state <= FREE_SIMULATION;
circ_ce <= '1';
circ_rst_sim <= '0';
shift_en_s <= '1';
end if;
when DELAY_z =>
cnt_delay := cnt_delay + 1;
if cnt_delay = 9 then
s_state <= DELAY;
end if;
when DELAY =>
s_state <= SIMULATION;
errorVec <= (others => '0');
errorSum <= (others => (others => '0'));
when SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if cnt = simtime-1 then
s_state <= DELAY2;
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when DELAY2 =>
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
s_state <= DELAY3;
when DELAY3 =>
s_state <= DELAY4;
errorSumReg <= errorSum;
errorSum <= (others => (others => '0'));
when DELAY4 =>
s_state <= IDLE;
sim_done <= '1';
when FREE_SIMULATION =>
circ_rst_sim <= '0';
shift_en_s <= '1';
-- collect errors
if (resultVector_o(32) = '1') then
errorVec <= resultvector_o xor resultvector_f;
else
errorVec <= (others => '0');
end if;
for i in 0 to (numOut-1) loop
if (errorVec(i) = '1') then
errorSum(i) <= std_logic_vector(unsigned(errorSum(i)) + 1);
end if;
end loop;
--
errorSumReg <= errorSum;
if stop_simulation = '1' then
s_state <= IDLE;
sim_done <= '1';
circ_ce <= '0';
circ_rst_sim <= '1';
shift_en_s <= '0';
end if;
cnt <= cnt +1;
when others =>
s_state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.aes_types.all;
entity aes_KeySchedule is
port(
key_in : in matrix(3 downto 0, 3 downto 0);
key_out : out matrix(3 downto 0, 3 downto 0);
Rcon : in std_logic_vector(7 downto 0);
en : in std_logic;
start : in std_logic;
done : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity aes_KeySchedule;
architecture RTL of aes_KeySchedule is
type state is (IDLE, COL0, COL1, COL2, COL3);
signal latched_key_in : matrix(3 downto 0, 3 downto 0);
signal temp_column0, temp_column1, temp_column2, temp_column3 : generic_memory(3 downto 0) := (others => (others => '0'));
signal current_state, next_state : state := IDLE;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
current_state <= IDLE;
next_state <= IDLE;
for i in 0 to 3 loop
for j in 0 to 3 loop
key_out(i, j) <= (others => '0');
end loop;
end loop;
else
key_out <= column2matrix(temp_column0, temp_column1, temp_column2, temp_column3);
if (en = '1') then
current_state <= next_state;
else
current_state <= current_state;
end if;
case current_state is
when IDLE =>
if (start = '1') then
latched_key_in <= key_in;
next_state <= COL0;
else
next_state <= IDLE;
end if;
done <= '0';
when COL0 =>
for I in temp_column0'range loop
if (I = 0) then
temp_column0(I) <= Sbox(to_integer(unsigned(column_rotate(matrix2column(latched_key_in, 3), 1)(I)))) XOR matrix2column(latched_key_in, 0)(I) XOR Rcon;
else
temp_column0(I) <= Sbox(to_integer(unsigned(column_rotate(matrix2column(latched_key_in, 3), 1)(I)))) XOR matrix2column(latched_key_in, 0)(I);
end if;
end loop;
done <= '0';
next_state <= COL1;
when COL1 =>
temp_column1 <= temp_column0 XOR matrix2column(latched_key_in, 1);
done <= '0';
next_state <= COL2;
when COL2 =>
temp_column2 <= temp_column1 XOR matrix2column(latched_key_in, 2);
done <= '0';
next_state <= COL3;
when COL3 =>
temp_column3 <= temp_column2 XOR matrix2column(latched_key_in, 3);
done <= '1';
next_state <= IDLE;
end case;
end if;
end if;
end process;
end architecture RTL;
|
-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
architecture syn of ram_2swsr_wfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
|
-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
architecture syn of ram_2swsr_wfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
|
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`protect end_protected
|
--
-- First Word Fall Through FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
library libstorage_1;
entity fifo_fwft_generic is
generic (
DEPTH : positive;
FWFT : boolean := false);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out std_ulogic_vector;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in std_ulogic_vector;
empty_o : out std_ulogic);
end entity fifo_fwft_generic;
architecture str of fifo_fwft_generic is
--FWFT signals
signal fifo_rd_data : std_ulogic_vector(wr_data_i'range);
signal fifo_rd_en : std_ulogic;
signal fifo_empty : std_ulogic;
signal fwft_rd_data : std_ulogic_vector(wr_data_i'range);
signal fwft_rd_en : std_ulogic;
signal fwft_empty : std_ulogic;
begin
fifo_rd_en <= fwft_rd_en when FWFT else rd_en_i;
rd_data_o <= fwft_rd_data when FWFT else fifo_rd_data;
empty_o <= fwft_empty when FWFT else fifo_empty;
fifo : entity libstorage_1.fifo_generic
generic map (
DEPTH => DEPTH)
port map (
clk => clk,
rst => rst,
rd_en_i => fifo_rd_en,
rd_data_o => fifo_rd_data,
empty_o => fifo_empty,
wr_en_i => wr_en_i,
wr_data_i => wr_data_i,
full_o => full_o);
gen_fwft: if FWFT generate
fifo_fwft_adapter: entity libstorage_1.fifo_fwft_adapter
port map (
clk => clk,
rst => rst,
fifo_rd_en_o => fwft_rd_en,
fifo_rd_data_i => fifo_rd_data,
fifo_empty_i => fifo_empty,
rd_en_i => rd_en_i,
rd_data_o => fwft_rd_data,
empty_o => fwft_empty);
end generate gen_fwft;
end architecture str;
|
--Latest version of all project files available at http://opencores.org/project,wrimm
--See License.txt for license details
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.WrimmPackage.all;
entity Wrimm is
port (
WbClk : in std_logic;
WbRst : out std_logic;
WbMasterIn : in WbMasterOutArray; --Signals from Masters
WbMasterOut : out WbSlaveOutArray; --Signals to Masters
--WbSlaveIn : out WbMasterOutArray;
--WbSlaveOut : in WbSlaveOutArray;
StatusRegs : in StatusArrayType;
SettingRegs : out SettingArrayType;
SettingRsts : in SettingArrayBitType;
Triggers : out TriggerArrayType;
TriggerClr : in TriggerArrayType;
rstZ : in std_logic); --Asynchronous reset
end entity Wrimm;
architecture behavior of Wrimm is
signal wbStrobe : std_logic; --Internal Wishbone signals
signal validAddress : std_logic;
signal wbAddr : WbAddrType;
signal wbSData,wbMData : WbDataType;
signal wbWrEn,wbCyc : std_logic;
signal wbAck,wbRty,wbErr : std_logic;
--signal wbMDataTag : std_logic_vector(0 to 1);
--signal wbCycType : std_logic_vector(0 to 2);
signal iSettingRegs : SettingArrayType;
signal iTriggers : TriggerArrayType;
signal statusEnable : StatusArrayBitType;
signal settingEnable : SettingArrayBitType;
signal triggerEnable : TriggerArrayType;
signal grant : WbMasterGrantType;
begin
SettingRegs <= iSettingRegs;
Triggers <= iTriggers;
--=============================================================================
-------------------------------------------------------------------------------
-- Master Round Robin Arbitration
-------------------------------------------------------------------------------
procArb: process(WbClk,rstZ) is --Round robin arbitration (descending)
variable vGrant : WbMasterGrantType;
begin
if (rstZ='0') then
vGrant := (Others=>'0');
vGrant(vGrant'left) := '1';
elsif rising_edge(WbClk) then
loopGrant: for i in WbMasterType loop
if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
loopNewGrantA: for j in i to WbMasterType'right loop --last master with cyc=1 will be selected
if WbMasterIn(j).Cyc='1' then
vGrant := (Others=>'0');
vGrant(j) := '1';
end if;
end loop loopNewGrantA;
if i/=WbMasterType'left then
loopNewGrantB: for j in WbMasterType'left to WbMasterType'pred(i) loop
if WbMasterIn(j).Cyc='1' then
vGrant := (Others=>'0');
vGrant(j) := '1';
end if;
end loop loopNewGrantB; --grant only moves after new requester
end if;
end if;
end loop loopGrant;
end if; --Clk
grant <= vGrant;
end process procArb;
--=============================================================================
-------------------------------------------------------------------------------
-- Master Multiplexers
-------------------------------------------------------------------------------
procWbMasterIn: process(grant,WbMasterIn) is
variable vSlaveOut : WbMasterOutType;
begin
loopGrantInMux: for i in WbMasterType loop
vSlaveOut := WbMasterIn(i);
exit when grant(i)='1';
end loop loopGrantInMux;
wbStrobe <= vSlaveOut.Strobe;
wbWrEn <= vSlaveOut.WrEn;
wbAddr <= vSlaveOut.Addr;
wbMData <= vSlaveOut.Data;
--wbMDataTag <= vSlaveOut.DataTag;
wbCyc <= vSlaveOut.Cyc;
--wbCycType <= vSlaveOut.CycType;
end process procWbMasterIn;
procWbMasterOut: process(grant,wbSData,wbAck,wbErr,wbRty) is
begin
loopGrantOutMux: for i in grant'range loop
WbMasterOut(i).Ack <= grant(i) and wbAck;
WbMasterOut(i).Err <= grant(i) and wbErr;
WbMasterOut(i).Rty <= grant(i) and wbRty;
WbMasterOut(i).Data <= wbSData; --Data out can always be active.
end loop loopGrantOutMux;
end process procWbMasterOut;
wbAck <= wbStrobe and validAddress;
wbErr <= wbStrobe and not(validAddress);
wbRty <= '0';
WbRst <= '0';
--=============================================================================
-------------------------------------------------------------------------------
-- Address Decode, Asynchronous
-------------------------------------------------------------------------------
procAddrDecode: process(wbAddr) is
variable vValidAddress : std_logic;
begin
vValidAddress := '0';
loopStatusEn: for f in StatusFieldType loop
if StatusParams(f).Address=wbAddr then
statusEnable(f) <= '1';
vValidAddress := '1';
else
statusEnable(f) <= '0';
end if;
end loop loopStatusEn;
loopSettingEn: for f in SettingFieldType loop
if SettingParams(f).Address=wbAddr then
settingEnable(f) <= '1';
vValidAddress := '1';
else
settingEnable(f) <= '0';
end if;
end loop loopSettingEn;
loopTriggerEn: for f in TriggerFieldType loop
if TriggerParams(f).Address=wbAddr then
triggerEnable(f) <= '1';
vValidAddress := '1';
else
triggerEnable(f) <= '0';
end if;
end loop loopTriggerEn;
validAddress <= vValidAddress;
end process procAddrDecode;
--=============================================================================
-------------------------------------------------------------------------------
-- Read
-------------------------------------------------------------------------------
procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is
variable vWbSData : WbDataType;
begin
vWbSData := (Others=>'0');
loopStatusRegs : for f in StatusFieldType loop
if statusEnable(f)='1' then
vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1);
end if; --Address
end loop loopStatusRegs;
loopSettingRegs : for f in SettingFieldType loop
if settingEnable(f)='1' then
vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1);
end if; --Address
end loop loopSettingRegs;
loopTriggerRegs : for f in TriggerFieldType loop
if triggerEnable(f)='1' then
vWbSData(TriggerParams(f).BitLoc) := iTriggers(f);
end if; --Address
end loop loopTriggerRegs;
wbSData <= vWbSData;
end process procRegRead;
--=============================================================================
-------------------------------------------------------------------------------
-- Write, Reset, Clear
-------------------------------------------------------------------------------
procRegWrite: process(WbClk,rstZ) is
begin
if (rstZ='0') then
loopSettingRegDefault : for f in SettingFieldType loop
iSettingRegs(f) <= SettingParams(f).Default;
end loop loopSettingRegDefault;
loopTriggerRegDefault : for f in TriggerFieldType loop
iTriggers(f) <= '0';
end loop loopTriggerRegDefault;
elsif rising_edge(WbClk) then
loopSettingRegWr : for f in SettingFieldType loop
if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1));
end if;
end loop loopSettingRegWr;
loopSettingRegRst : for f in SettingFieldType loop
if SettingRsts(f)='1' then
iSettingRegs(f) <= SettingParams(f).Default;
end if;
end loop loopSettingRegRst;
loopTriggerRegWr : for f in TriggerFieldType loop
if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
iTriggers(f) <= wbMData(TriggerParams(f).BitLoc);
elsif TriggerClr(f)='1' then
iTriggers(f) <= '0';
end if; --Address or clear
end loop loopTriggerRegWr;
end if; --Clk
end process procRegWrite;
end architecture behavior; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library iq_ram_top_v1_00_a;
use iq_ram_top_v1_00_a.user_logic;
entity iq_ram_top is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
-- IQ SX1255
data_en : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_q : in std_logic_vector(15 downto 0);
-- IT CPU
iRQ : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity iq_ram_top;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of iq_ram_top is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal rst_Bus2IP_Reset_tmp : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity iq_ram_top_v1_00_a.user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- IQ SX1255
data_en => data_en,
data_i => data_i,
data_q => data_q,
-- INT CPU
iRQ => iRQ,
-- AXi
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => rst_Bus2IP_Reset_tmp,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
rst_Bus2IP_Reset_tmp <= not rst_Bus2IP_Reset;
end IMP;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:22:48 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-rtl-conf-c.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_aa_e-rtl-conf-c.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_aa_e_rtl_conf / inst_aa_e
--
configuration inst_aa_e_rtl_conf of inst_aa_e is
for rtl
-- Generated Configuration
end for;
end inst_aa_e_rtl_conf;
--
-- End of Generated Configuration inst_aa_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
(0 + 0) => x"37", (0 + 1) => x"11", (0 + 2) => x"00", (0 + 3) => x"00", (0 + 4) => x"1b", (0 + 5) => x"01", (0 + 6) => x"71", (0 + 7) => x"80", (0 + 8) => x"13", (0 + 9) => x"11", (0 + 10) => x"41", (0 + 11) => x"01", (0 + 12) => x"6f", (0 + 13) => x"00", (0 + 14) => x"40", (0 + 15) => x"00", (0 + 16) => x"93", (0 + 17) => x"07", (0 + 18) => x"30", (0 + 19) => x"01", (0 + 20) => x"93", (0 + 21) => x"97", (0 + 22) => x"b7", (0 + 23) => x"01", (0 + 24) => x"13", (0 + 25) => x"07", (0 + 26) => x"10", (0 + 27) => x"00", (0 + 28) => x"23", (0 + 29) => x"90", (0 + 30) => x"e7", (0 + 31) => x"00", (0 + 32) => x"b7", (0 + 33) => x"17", (0 + 34) => x"80", (0 + 35) => x"09", (0 + 36) => x"97", (0 + 37) => x"06", (0 + 38) => x"00", (0 + 39) => x"00", (0 + 40) => x"93", (0 + 41) => x"86", (0 + 42) => x"46", (0 + 43) => x"09", (0 + 44) => x"13", (0 + 45) => x"07", (0 + 46) => x"10", (0 + 47) => x"02", (0 + 48) => x"93", (0 + 49) => x"97", (0 + 50) => x"47", (0 + 51) => x"00", (0 + 52) => x"93", (0 + 53) => x"05", (0 + 54) => x"10", (0 + 55) => x"00", (0 + 56) => x"03", (0 + 57) => x"c6", (0 + 58) => x"47", (0 + 59) => x"00", (0 + 60) => x"13", (0 + 61) => x"76", (0 + 62) => x"f6", (0 + 63) => x"0f", (0 + 64) => x"e3", (0 + 65) => x"0c", (0 + 66) => x"06", (0 + 67) => x"fe", (0 + 68) => x"a3", (0 + 69) => x"81", (0 + 70) => x"e7", (0 + 71) => x"00", (0 + 72) => x"a3", (0 + 73) => x"82", (0 + 74) => x"b7", (0 + 75) => x"00", (0 + 76) => x"93", (0 + 77) => x"86", (0 + 78) => x"16", (0 + 79) => x"00", (0 + 80) => x"03", (0 + 81) => x"c7", (0 + 82) => x"06", (0 + 83) => x"00", (0 + 84) => x"e3", (0 + 85) => x"12", (0 + 86) => x"07", (0 + 87) => x"fe", (0 + 88) => x"37", (0 + 89) => x"17", (0 + 90) => x"80", (0 + 91) => x"09", (0 + 92) => x"13", (0 + 93) => x"05", (0 + 94) => x"30", (0 + 95) => x"01", (0 + 96) => x"93", (0 + 97) => x"06", (0 + 98) => x"10", (0 + 99) => x"00", (0 + 100) => x"13", (0 + 101) => x"17", (0 + 102) => x"47", (0 + 103) => x"00", (0 + 104) => x"93", (0 + 105) => x"05", (0 + 106) => x"10", (0 + 107) => x"00", (0 + 108) => x"13", (0 + 109) => x"15", (0 + 110) => x"b5", (0 + 111) => x"01", (0 + 112) => x"83", (0 + 113) => x"47", (0 + 114) => x"17", (0 + 115) => x"00", (0 + 116) => x"93", (0 + 117) => x"f7", (0 + 118) => x"f7", (0 + 119) => x"0f", (0 + 120) => x"e3", (0 + 121) => x"8c", (0 + 122) => x"07", (0 + 123) => x"fe", (0 + 124) => x"03", (0 + 125) => x"46", (0 + 126) => x"07", (0 + 127) => x"00", (0 + 128) => x"9b", (0 + 129) => x"86", (0 + 130) => x"16", (0 + 131) => x"00", (0 + 132) => x"93", (0 + 133) => x"96", (0 + 134) => x"06", (0 + 135) => x"03", (0 + 136) => x"23", (0 + 137) => x"01", (0 + 138) => x"b7", (0 + 139) => x"00", (0 + 140) => x"93", (0 + 141) => x"d6", (0 + 142) => x"06", (0 + 143) => x"03", (0 + 144) => x"13", (0 + 145) => x"76", (0 + 146) => x"f6", (0 + 147) => x"0f", (0 + 148) => x"23", (0 + 149) => x"10", (0 + 150) => x"d5", (0 + 151) => x"00", (0 + 152) => x"83", (0 + 153) => x"47", (0 + 154) => x"47", (0 + 155) => x"00", (0 + 156) => x"93", (0 + 157) => x"f7", (0 + 158) => x"f7", (0 + 159) => x"0f", (0 + 160) => x"e3", (0 + 161) => x"8c", (0 + 162) => x"07", (0 + 163) => x"fe", (0 + 164) => x"a3", (0 + 165) => x"01", (0 + 166) => x"c7", (0 + 167) => x"00", (0 + 168) => x"a3", (0 + 169) => x"02", (0 + 170) => x"b7", (0 + 171) => x"00", (0 + 172) => x"6f", (0 + 173) => x"f0", (0 + 174) => x"5f", (0 + 175) => x"fc", (0 + 176) => x"00", (0 + 177) => x"00", (0 + 178) => x"00", (0 + 179) => x"00", (0 + 180) => x"00", (0 + 181) => x"00", (0 + 182) => x"00", (0 + 183) => x"00", (0 + 184) => x"21", (0 + 185) => x"21", (0 + 186) => x"21", (0 + 187) => x"45", (0 + 188) => x"43", (0 + 189) => x"48", (0 + 190) => x"4f", (0 + 191) => x"20", (0 + 192) => x"53", (0 + 193) => x"45", (0 + 194) => x"52", (0 + 195) => x"56", (0 + 196) => x"45", (0 + 197) => x"52", (0 + 198) => x"21", (0 + 199) => x"21", (0 + 200) => x"21", (0 + 201) => x"0a", (0 + 202) => x"00", (0 + 203) => x"00", (0 + 204) => x"00", (0 + 205) => x"00", (0 + 206) => x"00", (0 + 207) => x"00", (0 + 208) => x"00", (0 + 209) => x"00", (0 + 210) => x"00", (0 + 211) => x"00", (0 + 212) => x"00", (0 + 213) => x"00", (0 + 214) => x"00", (0 + 215) => x"00", (0 + 216) => x"00", (0 + 217) => x"00", (0 + 218) => x"00", (0 + 219) => x"00", (0 + 220) => x"00", (0 + 221) => x"00", (0 + 222) => x"00", (0 + 223) => x"00", (0 + 224) => x"00", (0 + 225) => x"00", (0 + 226) => x"00", (0 + 227) => x"00", (0 + 228) => x"00", (0 + 229) => x"00", (0 + 230) => x"00", (0 + 231) => x"00", (0 + 232) => x"00", (0 + 233) => x"00", (0 + 234) => x"00", (0 + 235) => x"00", (0 + 236) => x"00", (0 + 237) => x"00", (0 + 238) => x"00", (0 + 239) => x"00", (0 + 240) => x"00", (0 + 241) => x"00", (0 + 242) => x"00", (0 + 243) => x"00", (0 + 244) => x"00", (0 + 245) => x"00", (0 + 246) => x"00", (0 + 247) => x"00", (0 + 248) => x"00", (0 + 249) => x"00", (0 + 250) => x"00", (0 + 251) => x"00", (0 + 252) => x"00", (0 + 253) => x"00", (0 + 254) => x"00", (0 + 255) => x"00", (0 + 256) => x"00", (0 + 257) => x"00", (0 + 258) => x"00", (0 + 259) => x"00", (0 + 260) => x"00", (0 + 261) => x"00", (0 + 262) => x"00", (0 + 263) => x"00", (0 + 264) => x"00", (0 + 265) => x"00", (0 + 266) => x"00", (0 + 267) => x"00", (0 + 268) => x"00", (0 + 269) => x"00", (0 + 270) => x"00", (0 + 271) => x"00", (0 + 272) => x"00", (0 + 273) => x"00", (0 + 274) => x"00", (0 + 275) => x"00", (0 + 276) => x"00", (0 + 277) => x"00", (0 + 278) => x"00", (0 + 279) => x"00", (0 + 280) => x"00", (0 + 281) => x"00", (0 + 282) => x"00", (0 + 283) => x"00", (0 + 284) => x"00", (0 + 285) => x"00", (0 + 286) => x"00", (0 + 287) => x"00", (0 + 288) => x"00", (0 + 289) => x"00", (0 + 290) => x"00", (0 + 291) => x"00", (0 + 292) => x"00", (0 + 293) => x"00", (0 + 294) => x"00", (0 + 295) => x"00", (0 + 296) => x"00", (0 + 297) => x"00", (0 + 298) => x"00", (0 + 299) => x"00", (0 + 300) => x"00", (0 + 301) => x"00", (0 + 302) => x"00", (0 + 303) => x"00", (0 + 304) => x"00", (0 + 305) => x"00", (0 + 306) => x"00", (0 + 307) => x"00", (0 + 308) => x"00", (0 + 309) => x"00", (0 + 310) => x"00", (0 + 311) => x"00", (0 + 312) => x"00", (0 + 313) => x"00", (0 + 314) => x"00", (0 + 315) => x"00", (0 + 316) => x"00", (0 + 317) => x"00", (0 + 318) => x"00", (0 + 319) => x"00", (0 + 320) => x"00", (0 + 321) => x"00", (0 + 322) => x"00", (0 + 323) => x"00", (0 + 324) => x"00", (0 + 325) => x"00", (0 + 326) => x"00", (0 + 327) => x"00", (0 + 328) => x"00", (0 + 329) => x"00", (0 + 330) => x"00", (0 + 331) => x"00", (0 + 332) => x"00", (0 + 333) => x"00", (0 + 334) => x"00", (0 + 335) => x"00", (0 + 336) => x"00", (0 + 337) => x"00", (0 + 338) => x"00", (0 + 339) => x"00", (0 + 340) => x"00", (0 + 341) => x"00", (0 + 342) => x"00", (0 + 343) => x"00", (0 + 344) => x"00", (0 + 345) => x"00", (0 + 346) => x"00", (0 + 347) => x"00", (0 + 348) => x"00", (0 + 349) => x"00", (0 + 350) => x"00", (0 + 351) => x"00", (0 + 352) => x"00", (0 + 353) => x"00", (0 + 354) => x"00", (0 + 355) => x"00", (0 + 356) => x"00", (0 + 357) => x"00", (0 + 358) => x"00", (0 + 359) => x"00", (0 + 360) => x"00", (0 + 361) => x"00", (0 + 362) => x"00", (0 + 363) => x"00", (0 + 364) => x"00", (0 + 365) => x"00", (0 + 366) => x"00", (0 + 367) => x"00", (0 + 368) => x"00", (0 + 369) => x"00", (0 + 370) => x"00", (0 + 371) => x"00", (0 + 372) => x"00", (0 + 373) => x"00", (0 + 374) => x"00", (0 + 375) => x"00", (0 + 376) => x"00", (0 + 377) => x"00", (0 + 378) => x"00", (0 + 379) => x"00", (0 + 380) => x"00", (0 + 381) => x"00", (0 + 382) => x"00", (0 + 383) => x"00", (0 + 384) => x"00", (0 + 385) => x"00", (0 + 386) => x"00", (0 + 387) => x"00", (0 + 388) => x"00", (0 + 389) => x"00", (0 + 390) => x"00", (0 + 391) => x"00", (0 + 392) => x"00", (0 + 393) => x"00", (0 + 394) => x"00", (0 + 395) => x"00", (0 + 396) => x"00", (0 + 397) => x"00", (0 + 398) => x"00", (0 + 399) => x"00", (0 + 400) => x"00", (0 + 401) => x"00", (0 + 402) => x"00", (0 + 403) => x"00", (0 + 404) => x"00", (0 + 405) => x"00", (0 + 406) => x"00", (0 + 407) => x"00", (0 + 408) => x"00", (0 + 409) => x"00", (0 + 410) => x"00", (0 + 411) => x"00", (0 + 412) => x"00", (0 + 413) => x"00", (0 + 414) => x"00", (0 + 415) => x"00", (0 + 416) => x"00", (0 + 417) => x"00", (0 + 418) => x"00", (0 + 419) => x"00", (0 + 420) => x"00", (0 + 421) => x"00", (0 + 422) => x"00", (0 + 423) => x"00", (0 + 424) => x"00", (0 + 425) => x"00", (0 + 426) => x"00", (0 + 427) => x"00", (0 + 428) => x"00", (0 + 429) => x"00", (0 + 430) => x"00", (0 + 431) => x"00", (0 + 432) => x"00", (0 + 433) => x"00", (0 + 434) => x"00", (0 + 435) => x"00", (0 + 436) => x"00", (0 + 437) => x"00", (0 + 438) => x"00", (0 + 439) => x"00", (0 + 440) => x"00", (0 + 441) => x"00", (0 + 442) => x"00", (0 + 443) => x"00", (0 + 444) => x"00", (0 + 445) => x"00", (0 + 446) => x"00", (0 + 447) => x"00", (0 + 448) => x"00", (0 + 449) => x"00", (0 + 450) => x"00", (0 + 451) => x"00", (0 + 452) => x"00", (0 + 453) => x"00", (0 + 454) => x"00", (0 + 455) => x"00", (0 + 456) => x"00", (0 + 457) => x"00", (0 + 458) => x"00", (0 + 459) => x"00", (0 + 460) => x"00", (0 + 461) => x"00", (0 + 462) => x"00", (0 + 463) => x"00", (0 + 464) => x"00", (0 + 465) => x"00", (0 + 466) => x"00", (0 + 467) => x"00", (0 + 468) => x"00", (0 + 469) => x"00", (0 + 470) => x"00", (0 + 471) => x"00", (0 + 472) => x"00", (0 + 473) => x"00", (0 + 474) => x"00", (0 + 475) => x"00", (0 + 476) => x"00", (0 + 477) => x"00", (0 + 478) => x"00", (0 + 479) => x"00", (0 + 480) => x"00", (0 + 481) => x"00", (0 + 482) => x"00", (0 + 483) => x"00", (0 + 484) => x"00", (0 + 485) => x"00", (0 + 486) => x"00", (0 + 487) => x"00", (0 + 488) => x"00", (0 + 489) => x"00", (0 + 490) => x"00", (0 + 491) => x"00", (0 + 492) => x"00", (0 + 493) => x"00", (0 + 494) => x"00", (0 + 495) => x"00", (0 + 496) => x"00", (0 + 497) => x"00", (0 + 498) => x"00", (0 + 499) => x"00", (0 + 500) => x"00", (0 + 501) => x"00", (0 + 502) => x"00", (0 + 503) => x"00", (0 + 504) => x"00", (0 + 505) => x"00", (0 + 506) => x"00", (0 + 507) => x"00", (0 + 508) => x"00", (0 + 509) => x"00", (0 + 510) => x"00", (0 + 511) => x"00", (0 + 512) => x"00", (0 + 513) => x"00", (0 + 514) => x"00", (0 + 515) => x"00", (0 + 516) => x"00", (0 + 517) => x"00", (0 + 518) => x"00", (0 + 519) => x"00", (0 + 520) => x"00", (0 + 521) => x"00", (0 + 522) => x"00", (0 + 523) => x"00", (0 + 524) => x"00", (0 + 525) => x"00", (0 + 526) => x"00", (0 + 527) => x"00", (0 + 528) => x"00", (0 + 529) => x"00", (0 + 530) => x"00", (0 + 531) => x"00", (0 + 532) => x"00", (0 + 533) => x"00", (0 + 534) => x"00", (0 + 535) => x"00", (0 + 536) => x"00", (0 + 537) => x"00", (0 + 538) => x"00", (0 + 539) => x"00", (0 + 540) => x"00", (0 + 541) => x"00", (0 + 542) => x"00", (0 + 543) => x"00", (0 + 544) => x"00", (0 + 545) => x"00", (0 + 546) => x"00", (0 + 547) => x"00", (0 + 548) => x"00", (0 + 549) => x"00", (0 + 550) => x"00", (0 + 551) => x"00", (0 + 552) => x"00", (0 + 553) => x"00", (0 + 554) => x"00", (0 + 555) => x"00", (0 + 556) => x"00", (0 + 557) => x"00", (0 + 558) => x"00", (0 + 559) => x"00", (0 + 560) => x"00", (0 + 561) => x"00", (0 + 562) => x"00", (0 + 563) => x"00", (0 + 564) => x"00", (0 + 565) => x"00", (0 + 566) => x"00", (0 + 567) => x"00", (0 + 568) => x"00", (0 + 569) => x"00", (0 + 570) => x"00", (0 + 571) => x"00", (0 + 572) => x"00", (0 + 573) => x"00", (0 + 574) => x"00", (0 + 575) => x"00", (0 + 576) => x"00", (0 + 577) => x"00", (0 + 578) => x"00", (0 + 579) => x"00", (0 + 580) => x"00", (0 + 581) => x"00", (0 + 582) => x"00", (0 + 583) => x"00", (0 + 584) => x"00", (0 + 585) => x"00", (0 + 586) => x"00", (0 + 587) => x"00", (0 + 588) => x"00", (0 + 589) => x"00", (0 + 590) => x"00", (0 + 591) => x"00", (0 + 592) => x"00", (0 + 593) => x"00", (0 + 594) => x"00", (0 + 595) => x"00", (0 + 596) => x"00", (0 + 597) => x"00", (0 + 598) => x"00", (0 + 599) => x"00", (0 + 600) => x"00", (0 + 601) => x"00", (0 + 602) => x"00", (0 + 603) => x"00", (0 + 604) => x"00", (0 + 605) => x"00", (0 + 606) => x"00", (0 + 607) => x"00", (0 + 608) => x"00", (0 + 609) => x"00", (0 + 610) => x"00", (0 + 611) => x"00", (0 + 612) => x"00", (0 + 613) => x"00", (0 + 614) => x"00", (0 + 615) => x"00", (0 + 616) => x"00", (0 + 617) => x"00", (0 + 618) => x"00", (0 + 619) => x"00", (0 + 620) => x"00", (0 + 621) => x"00", (0 + 622) => x"00", (0 + 623) => x"00", (0 + 624) => x"00", (0 + 625) => x"00", (0 + 626) => x"00", (0 + 627) => x"00", (0 + 628) => x"00", (0 + 629) => x"00", (0 + 630) => x"00", (0 + 631) => x"00", (0 + 632) => x"00", (0 + 633) => x"00", (0 + 634) => x"00", (0 + 635) => x"00", (0 + 636) => x"00", (0 + 637) => x"00", (0 + 638) => x"00", (0 + 639) => x"00", (0 + 640) => x"00", (0 + 641) => x"00", (0 + 642) => x"00", (0 + 643) => x"00", (0 + 644) => x"00", (0 + 645) => x"00", (0 + 646) => x"00", (0 + 647) => x"00", (0 + 648) => x"00", (0 + 649) => x"00", (0 + 650) => x"00", (0 + 651) => x"00", (0 + 652) => x"00", (0 + 653) => x"00", (0 + 654) => x"00", (0 + 655) => x"00", (0 + 656) => x"00", (0 + 657) => x"00", (0 + 658) => x"00", (0 + 659) => x"00", (0 + 660) => x"00", (0 + 661) => x"00", (0 + 662) => x"00", (0 + 663) => x"00", (0 + 664) => x"00", (0 + 665) => x"00", (0 + 666) => x"00", (0 + 667) => x"00", (0 + 668) => x"00", (0 + 669) => x"00", (0 + 670) => x"00", (0 + 671) => x"00", (0 + 672) => x"00", (0 + 673) => x"00", (0 + 674) => x"00", (0 + 675) => x"00", (0 + 676) => x"00", (0 + 677) => x"00", (0 + 678) => x"00", (0 + 679) => x"00", (0 + 680) => x"00", (0 + 681) => x"00", (0 + 682) => x"00", (0 + 683) => x"00", (0 + 684) => x"00", (0 + 685) => x"00", (0 + 686) => x"00", (0 + 687) => x"00", (0 + 688) => x"00", (0 + 689) => x"00", (0 + 690) => x"00", (0 + 691) => x"00", (0 + 692) => x"00", (0 + 693) => x"00", (0 + 694) => x"00", (0 + 695) => x"00", (0 + 696) => x"00", (0 + 697) => x"00", (0 + 698) => x"00", (0 + 699) => x"00", (0 + 700) => x"00", (0 + 701) => x"00", (0 + 702) => x"00", (0 + 703) => x"00", (0 + 704) => x"00", (0 + 705) => x"00", (0 + 706) => x"00", (0 + 707) => x"00", (0 + 708) => x"00", (0 + 709) => x"00", (0 + 710) => x"00", (0 + 711) => x"00", (0 + 712) => x"00", (0 + 713) => x"00", (0 + 714) => x"00", (0 + 715) => x"00", (0 + 716) => x"00", (0 + 717) => x"00", (0 + 718) => x"00", (0 + 719) => x"00", (0 + 720) => x"00", (0 + 721) => x"00", (0 + 722) => x"00", (0 + 723) => x"00", (0 + 724) => x"00", (0 + 725) => x"00", (0 + 726) => x"00", (0 + 727) => x"00", (0 + 728) => x"00", (0 + 729) => x"00", (0 + 730) => x"00", (0 + 731) => x"00", (0 + 732) => x"00", (0 + 733) => x"00", (0 + 734) => x"00", (0 + 735) => x"00", (0 + 736) => x"00", (0 + 737) => x"00", (0 + 738) => x"00", (0 + 739) => x"00", (0 + 740) => x"00", (0 + 741) => x"00", (0 + 742) => x"00", (0 + 743) => x"00", (0 + 744) => x"00", (0 + 745) => x"00", (0 + 746) => x"00", (0 + 747) => x"00", (0 + 748) => x"00", (0 + 749) => x"00", (0 + 750) => x"00", (0 + 751) => x"00", (0 + 752) => x"00", (0 + 753) => x"00", (0 + 754) => x"00", (0 + 755) => x"00", (0 + 756) => x"00", (0 + 757) => x"00", (0 + 758) => x"00", (0 + 759) => x"00", (0 + 760) => x"00", (0 + 761) => x"00", (0 + 762) => x"00", (0 + 763) => x"00", (0 + 764) => x"00", (0 + 765) => x"00", (0 + 766) => x"00", (0 + 767) => x"00", (0 + 768) => x"00", (0 + 769) => x"00", (0 + 770) => x"00", (0 + 771) => x"00", (0 + 772) => x"00", (0 + 773) => x"00", (0 + 774) => x"00", (0 + 775) => x"00", (0 + 776) => x"00", (0 + 777) => x"00", (0 + 778) => x"00", (0 + 779) => x"00", (0 + 780) => x"00", (0 + 781) => x"00", (0 + 782) => x"00", (0 + 783) => x"00", (0 + 784) => x"00", (0 + 785) => x"00", (0 + 786) => x"00", (0 + 787) => x"00", (0 + 788) => x"00", (0 + 789) => x"00", (0 + 790) => x"00", (0 + 791) => x"00", (0 + 792) => x"00", (0 + 793) => x"00", (0 + 794) => x"00", (0 + 795) => x"00", (0 + 796) => x"00", (0 + 797) => x"00", (0 + 798) => x"00", (0 + 799) => x"00", (0 + 800) => x"00", (0 + 801) => x"00", (0 + 802) => x"00", (0 + 803) => x"00", (0 + 804) => x"00", (0 + 805) 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x"00", (0 + 3998) => x"00", (0 + 3999) => x"00", (0 + 4000) => x"00", (0 + 4001) => x"00", (0 + 4002) => x"00", (0 + 4003) => x"00", (0 + 4004) => x"00", (0 + 4005) => x"00", (0 + 4006) => x"00", (0 + 4007) => x"00", (0 + 4008) => x"00", (0 + 4009) => x"00", (0 + 4010) => x"00", (0 + 4011) => x"00", (0 + 4012) => x"00", (0 + 4013) => x"00", (0 + 4014) => x"00", (0 + 4015) => x"00", (0 + 4016) => x"00", (0 + 4017) => x"00", (0 + 4018) => x"00", (0 + 4019) => x"00", (0 + 4020) => x"00", (0 + 4021) => x"00", (0 + 4022) => x"00", (0 + 4023) => x"00", (0 + 4024) => x"00", (0 + 4025) => x"00", (0 + 4026) => x"00", (0 + 4027) => x"00", (0 + 4028) => x"00", (0 + 4029) => x"00", (0 + 4030) => x"00", (0 + 4031) => x"00", (0 + 4032) => x"00", (0 + 4033) => x"00", (0 + 4034) => x"00", (0 + 4035) => x"00", (0 + 4036) => x"00", (0 + 4037) => x"00", (0 + 4038) => x"00", (0 + 4039) => x"00", (0 + 4040) => x"00", (0 + 4041) => x"00", (0 + 4042) => x"00", (0 + 4043) => x"00", (0 + 4044) => x"00", (0 + 4045) => x"00", (0 + 4046) => x"00", (0 + 4047) => x"00", (0 + 4048) => x"00", (0 + 4049) => x"00", (0 + 4050) => x"00", (0 + 4051) => x"00", (0 + 4052) => x"00", (0 + 4053) => x"00", (0 + 4054) => x"00", (0 + 4055) => x"00", (0 + 4056) => x"00", (0 + 4057) => x"00", (0 + 4058) => x"00", (0 + 4059) => x"00", (0 + 4060) => x"00", (0 + 4061) => x"00", (0 + 4062) => x"00", (0 + 4063) => x"00", (0 + 4064) => x"00", (0 + 4065) => x"00", (0 + 4066) => x"00", (0 + 4067) => x"00", (0 + 4068) => x"00", (0 + 4069) => x"00", (0 + 4070) => x"00", (0 + 4071) => x"00", (0 + 4072) => x"00", (0 + 4073) => x"00", (0 + 4074) => x"00", (0 + 4075) => x"00", (0 + 4076) => x"00", (0 + 4077) => x"00", (0 + 4078) => x"00", (0 + 4079) => x"00", (0 + 4080) => x"00", (0 + 4081) => x"00", (0 + 4082) => x"00", (0 + 4083) => x"00", (0 + 4084) => x"00", (0 + 4085) => x"00", (0 + 4086) => x"00", (0 + 4087) => x"00", (0 + 4088) => x"00", (0 + 4089) => x"00", (0 + 4090) => x"00", (0 + 4091) => x"00", (0 + 4092) => x"00", (0 + 4093) => x"00", (0 + 4094) => x"00", (0 + 4095) => x"00",
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
-- Revision 0.02 - Added type definitions (store and network) for arpv2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package arp_types is
-- arp lookup types
type arp_req_req_type is
record
lookup_req : std_logic; -- set high when wanting mac adr for the requested IP
ip : std_logic_vector (31 downto 0);
end record;
type arp_req_rslt_type is
record
got_mac : std_logic; -- indicates that we got the mac
mac : std_logic_vector (47 downto 0);
got_err : std_logic; -- indicates that we got an error (prob a timeout)
end record;
type arp_entry_t is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
end record;
type arp_control_type is
record
clear_cache : std_logic;
end record;
-- arp store types
type arp_store_rslt_t is (IDLE,BUSY,SEARCHING,FOUND,NOT_FOUND);
type arp_store_rdrequest_t is
record
req : std_logic; -- request to lookup
ip : std_logic_vector(31 downto 0); -- contains ip to lookup
end record;
type arp_store_wrrequest_t is
record
req : std_logic; -- request to store
entry : arp_entry_t; -- ip,mac to store
end record;
type arp_store_result_t is
record
status : arp_store_rslt_t; -- status of the request
entry : arp_entry_t; -- contains ip,mac if found
end record;
-- arp network types
type arp_nwk_rslt_t is (IDLE,REQUESTING,RECEIVED,ERROR);
type arp_nwk_request_t is
record
req : std_logic; -- request to resolve IP addr
ip : std_logic_vector(31 downto 0); -- IP to request
end record;
type arp_nwk_result_t is
record
status : arp_nwk_rslt_t; -- status of request
entry : arp_entry_t; -- the result
end record;
end arp_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package dlx_types is
-- little-endian addresses
subtype dlx_address is std_logic_vector(31 downto 0);
subtype dlx_bv_address is bit_vector(31 downto 0);
-- big-endian data words
subtype dlx_word is std_logic_vector(0 to 31);
subtype dlx_bv_word is bit_vector(0 to 31);
type dlx_word_array is array (natural range <>) of dlx_word;
-- tristate bus driving value
constant disabled_dlx_word : dlx_word := ( others => 'Z' );
-- type for specifying data width on the data bus
subtype dlx_mem_width is std_logic_vector(1 downto 0);
constant dlx_mem_width_byte : dlx_mem_width := "01";
constant dlx_mem_width_halfword : dlx_mem_width := "10";
constant dlx_mem_width_word : dlx_mem_width := "00";
-- type for controlling trace information generated by model
type dlx_debug_control is
( none,
msg_every_100_instructions, msg_each_instruction,
trace_each_instruction, trace_each_step );
end package dlx_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package dlx_types is
-- little-endian addresses
subtype dlx_address is std_logic_vector(31 downto 0);
subtype dlx_bv_address is bit_vector(31 downto 0);
-- big-endian data words
subtype dlx_word is std_logic_vector(0 to 31);
subtype dlx_bv_word is bit_vector(0 to 31);
type dlx_word_array is array (natural range <>) of dlx_word;
-- tristate bus driving value
constant disabled_dlx_word : dlx_word := ( others => 'Z' );
-- type for specifying data width on the data bus
subtype dlx_mem_width is std_logic_vector(1 downto 0);
constant dlx_mem_width_byte : dlx_mem_width := "01";
constant dlx_mem_width_halfword : dlx_mem_width := "10";
constant dlx_mem_width_word : dlx_mem_width := "00";
-- type for controlling trace information generated by model
type dlx_debug_control is
( none,
msg_every_100_instructions, msg_each_instruction,
trace_each_instruction, trace_each_step );
end package dlx_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package dlx_types is
-- little-endian addresses
subtype dlx_address is std_logic_vector(31 downto 0);
subtype dlx_bv_address is bit_vector(31 downto 0);
-- big-endian data words
subtype dlx_word is std_logic_vector(0 to 31);
subtype dlx_bv_word is bit_vector(0 to 31);
type dlx_word_array is array (natural range <>) of dlx_word;
-- tristate bus driving value
constant disabled_dlx_word : dlx_word := ( others => 'Z' );
-- type for specifying data width on the data bus
subtype dlx_mem_width is std_logic_vector(1 downto 0);
constant dlx_mem_width_byte : dlx_mem_width := "01";
constant dlx_mem_width_halfword : dlx_mem_width := "10";
constant dlx_mem_width_word : dlx_mem_width := "00";
-- type for controlling trace information generated by model
type dlx_debug_control is
( none,
msg_every_100_instructions, msg_each_instruction,
trace_each_instruction, trace_each_step );
end package dlx_types;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNZUHKKGTG is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNZUHKKGTG is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNZUHKKGTG is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNZUHKKGTG is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNZUHKKGTG is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNZUHKKGTG is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
entity tb_test is
end tb_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test is
signal a : std_logic;
signal b : std_logic;
begin
dut: entity work.test
port map (a, b);
process
begin
wait for 1 ns;
assert b = '0' severity failure;
wait;
end process;
end behav;
|
entity r is
end;
|
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_DEBOUNCER is
Generic (
-- latency of debouncer in clock cycles, minimum value is 2,
-- value also corresponds to the number of bits compared
LATENCY : natural := 4
);
Port (
CLK : in std_logic; -- system clock
DEB_IN : in std_logic; -- input of signal from outside FPGA
DEB_OUT : out std_logic -- output of debounced (filtered) signal
);
end entity;
architecture RTL of UART_DEBOUNCER is
constant SHREG_DEPTH : natural := LATENCY-1;
signal input_shreg : std_logic_vector(SHREG_DEPTH-1 downto 0);
signal output_reg_rst : std_logic;
signal output_reg_set : std_logic;
begin
-- parameterized input shift register
input_shreg_p : process (CLK)
begin
if (rising_edge(CLK)) then
input_shreg <= input_shreg(SHREG_DEPTH-2 downto 0) & DEB_IN;
end if;
end process;
-- output register will be reset when all compared bits are low
output_reg_rst_p : process (DEB_IN, input_shreg)
variable or_var : std_logic;
begin
or_var := DEB_IN;
all_bits_or_l : for i in 0 to SHREG_DEPTH-1 loop
or_var := or_var or input_shreg(i);
end loop;
output_reg_rst <= not or_var;
end process;
-- output register will be set when all compared bits are high
output_reg_set_p : process (DEB_IN, input_shreg)
variable and_var : std_logic;
begin
and_var := DEB_IN;
all_bits_and_l : for i in 0 to SHREG_DEPTH-1 loop
and_var := and_var and input_shreg(i);
end loop;
output_reg_set <= and_var;
end process;
-- output register
output_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (output_reg_rst = '1') then
DEB_OUT <= '0';
elsif (output_reg_set = '1') then
DEB_OUT <= '1';
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_DEBOUNCER is
Generic (
-- latency of debouncer in clock cycles, minimum value is 2,
-- value also corresponds to the number of bits compared
LATENCY : natural := 4
);
Port (
CLK : in std_logic; -- system clock
DEB_IN : in std_logic; -- input of signal from outside FPGA
DEB_OUT : out std_logic -- output of debounced (filtered) signal
);
end entity;
architecture RTL of UART_DEBOUNCER is
constant SHREG_DEPTH : natural := LATENCY-1;
signal input_shreg : std_logic_vector(SHREG_DEPTH-1 downto 0);
signal output_reg_rst : std_logic;
signal output_reg_set : std_logic;
begin
-- parameterized input shift register
input_shreg_p : process (CLK)
begin
if (rising_edge(CLK)) then
input_shreg <= input_shreg(SHREG_DEPTH-2 downto 0) & DEB_IN;
end if;
end process;
-- output register will be reset when all compared bits are low
output_reg_rst_p : process (DEB_IN, input_shreg)
variable or_var : std_logic;
begin
or_var := DEB_IN;
all_bits_or_l : for i in 0 to SHREG_DEPTH-1 loop
or_var := or_var or input_shreg(i);
end loop;
output_reg_rst <= not or_var;
end process;
-- output register will be set when all compared bits are high
output_reg_set_p : process (DEB_IN, input_shreg)
variable and_var : std_logic;
begin
and_var := DEB_IN;
all_bits_and_l : for i in 0 to SHREG_DEPTH-1 loop
and_var := and_var and input_shreg(i);
end loop;
output_reg_set <= and_var;
end process;
-- output register
output_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (output_reg_rst = '1') then
DEB_OUT <= '0';
elsif (output_reg_set = '1') then
DEB_OUT <= '1';
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"E0";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"F4";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"E9";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"E6";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"DF";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"30";
when x"029" => DATA <= x"20";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"28";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"68";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8E";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"8E";
when x"061" => DATA <= x"F8";
when x"062" => DATA <= x"16";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"F9";
when x"065" => DATA <= x"33";
when x"066" => DATA <= x"BD";
when x"067" => DATA <= x"FF";
when x"068" => DATA <= x"E7";
when x"069" => DATA <= x"4F";
when x"06A" => DATA <= x"BD";
when x"06B" => DATA <= x"FF";
when x"06C" => DATA <= x"EE";
when x"06D" => DATA <= x"4F";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FA";
when x"070" => DATA <= x"30";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"CE";
when x"073" => DATA <= x"FF";
when x"074" => DATA <= x"28";
when x"075" => DATA <= x"8D";
when x"076" => DATA <= x"49";
when x"077" => DATA <= x"10";
when x"078" => DATA <= x"FE";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"8A";
when x"07B" => DATA <= x"8E";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"B9";
when x"07E" => DATA <= x"BF";
when x"07F" => DATA <= x"FF";
when x"080" => DATA <= x"90";
when x"081" => DATA <= x"1C";
when x"082" => DATA <= x"00";
when x"083" => DATA <= x"8E";
when x"084" => DATA <= x"F8";
when x"085" => DATA <= x"96";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"F9";
when x"088" => DATA <= x"33";
when x"089" => DATA <= x"BD";
when x"08A" => DATA <= x"FF";
when x"08B" => DATA <= x"F1";
when x"08C" => DATA <= x"25";
when x"08D" => DATA <= x"14";
when x"08E" => DATA <= x"8E";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"28";
when x"091" => DATA <= x"BD";
when x"092" => DATA <= x"FF";
when x"093" => DATA <= x"F7";
when x"094" => DATA <= x"20";
when x"095" => DATA <= x"ED";
when x"096" => DATA <= x"36";
when x"097" => DATA <= x"38";
when x"098" => DATA <= x"30";
when x"099" => DATA <= x"39";
when x"09A" => DATA <= x"3E";
when x"09B" => DATA <= x"2A";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"FF";
when x"09E" => DATA <= x"28";
when x"09F" => DATA <= x"57";
when x"0A0" => DATA <= x"20";
when x"0A1" => DATA <= x"FF";
when x"0A2" => DATA <= x"86";
when x"0A3" => DATA <= x"7E";
when x"0A4" => DATA <= x"BD";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"F4";
when x"0A7" => DATA <= x"3F";
when x"0A8" => DATA <= x"11";
when x"0A9" => DATA <= x"45";
when x"0AA" => DATA <= x"73";
when x"0AB" => DATA <= x"63";
when x"0AC" => DATA <= x"61";
when x"0AD" => DATA <= x"70";
when x"0AE" => DATA <= x"65";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"10";
when x"0B1" => DATA <= x"FE";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"8A";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"FF";
when x"0B6" => DATA <= x"E7";
when x"0B7" => DATA <= x"A6";
when x"0B8" => DATA <= x"80";
when x"0B9" => DATA <= x"8D";
when x"0BA" => DATA <= x"78";
when x"0BB" => DATA <= x"BD";
when x"0BC" => DATA <= x"FF";
when x"0BD" => DATA <= x"E7";
when x"0BE" => DATA <= x"20";
when x"0BF" => DATA <= x"C3";
when x"0C0" => DATA <= x"CC";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"00";
when x"0C3" => DATA <= x"FD";
when x"0C4" => DATA <= x"FF";
when x"0C5" => DATA <= x"88";
when x"0C6" => DATA <= x"CC";
when x"0C7" => DATA <= x"F8";
when x"0C8" => DATA <= x"00";
when x"0C9" => DATA <= x"FD";
when x"0CA" => DATA <= x"FF";
when x"0CB" => DATA <= x"8A";
when x"0CC" => DATA <= x"CC";
when x"0CD" => DATA <= x"F8";
when x"0CE" => DATA <= x"B0";
when x"0CF" => DATA <= x"FD";
when x"0D0" => DATA <= x"FF";
when x"0D1" => DATA <= x"FA";
when x"0D2" => DATA <= x"CC";
when x"0D3" => DATA <= x"FE";
when x"0D4" => DATA <= x"22";
when x"0D5" => DATA <= x"FD";
when x"0D6" => DATA <= x"FE";
when x"0D7" => DATA <= x"FA";
when x"0D8" => DATA <= x"8E";
when x"0D9" => DATA <= x"FF";
when x"0DA" => DATA <= x"FA";
when x"0DB" => DATA <= x"10";
when x"0DC" => DATA <= x"8E";
when x"0DD" => DATA <= x"FF";
when x"0DE" => DATA <= x"80";
when x"0DF" => DATA <= x"39";
when x"0E0" => DATA <= x"BD";
when x"0E1" => DATA <= x"FF";
when x"0E2" => DATA <= x"E0";
when x"0E3" => DATA <= x"7E";
when x"0E4" => DATA <= x"FF";
when x"0E5" => DATA <= x"EE";
when x"0E6" => DATA <= x"BD";
when x"0E7" => DATA <= x"FF";
when x"0E8" => DATA <= x"E7";
when x"0E9" => DATA <= x"A6";
when x"0EA" => DATA <= x"80";
when x"0EB" => DATA <= x"81";
when x"0EC" => DATA <= x"04";
when x"0ED" => DATA <= x"27";
when x"0EE" => DATA <= x"F0";
when x"0EF" => DATA <= x"BD";
when x"0F0" => DATA <= x"FF";
when x"0F1" => DATA <= x"EE";
when x"0F2" => DATA <= x"20";
when x"0F3" => DATA <= x"F5";
when x"0F4" => DATA <= x"34";
when x"0F5" => DATA <= x"32";
when x"0F6" => DATA <= x"86";
when x"0F7" => DATA <= x"80";
when x"0F8" => DATA <= x"8E";
when x"0F9" => DATA <= x"FF";
when x"0FA" => DATA <= x"FF";
when x"0FB" => DATA <= x"1F";
when x"0FC" => DATA <= x"12";
when x"0FD" => DATA <= x"BD";
when x"0FE" => DATA <= x"FF";
when x"0FF" => DATA <= x"F4";
when x"100" => DATA <= x"8C";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"00";
when x"103" => DATA <= x"35";
when x"104" => DATA <= x"B2";
when x"105" => DATA <= x"34";
when x"106" => DATA <= x"06";
when x"107" => DATA <= x"1F";
when x"108" => DATA <= x"10";
when x"109" => DATA <= x"8D";
when x"10A" => DATA <= x"06";
when x"10B" => DATA <= x"1F";
when x"10C" => DATA <= x"98";
when x"10D" => DATA <= x"8D";
when x"10E" => DATA <= x"02";
when x"10F" => DATA <= x"35";
when x"110" => DATA <= x"86";
when x"111" => DATA <= x"34";
when x"112" => DATA <= x"02";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"44";
when x"117" => DATA <= x"8D";
when x"118" => DATA <= x"06";
when x"119" => DATA <= x"A6";
when x"11A" => DATA <= x"E4";
when x"11B" => DATA <= x"8D";
when x"11C" => DATA <= x"02";
when x"11D" => DATA <= x"35";
when x"11E" => DATA <= x"82";
when x"11F" => DATA <= x"84";
when x"120" => DATA <= x"0F";
when x"121" => DATA <= x"81";
when x"122" => DATA <= x"0A";
when x"123" => DATA <= x"25";
when x"124" => DATA <= x"02";
when x"125" => DATA <= x"8B";
when x"126" => DATA <= x"07";
when x"127" => DATA <= x"8B";
when x"128" => DATA <= x"30";
when x"129" => DATA <= x"7E";
when x"12A" => DATA <= x"FF";
when x"12B" => DATA <= x"EE";
when x"12C" => DATA <= x"35";
when x"12D" => DATA <= x"10";
when x"12E" => DATA <= x"8D";
when x"12F" => DATA <= x"03";
when x"130" => DATA <= x"34";
when x"131" => DATA <= x"10";
when x"132" => DATA <= x"39";
when x"133" => DATA <= x"A6";
when x"134" => DATA <= x"80";
when x"135" => DATA <= x"27";
when x"136" => DATA <= x"FB";
when x"137" => DATA <= x"BD";
when x"138" => DATA <= x"FF";
when x"139" => DATA <= x"E3";
when x"13A" => DATA <= x"20";
when x"13B" => DATA <= x"F7";
when x"13C" => DATA <= x"10";
when x"13D" => DATA <= x"8E";
when x"13E" => DATA <= x"00";
when x"13F" => DATA <= x"00";
when x"140" => DATA <= x"A6";
when x"141" => DATA <= x"80";
when x"142" => DATA <= x"81";
when x"143" => DATA <= x"30";
when x"144" => DATA <= x"25";
when x"145" => DATA <= x"2B";
when x"146" => DATA <= x"81";
when x"147" => DATA <= x"3A";
when x"148" => DATA <= x"25";
when x"149" => DATA <= x"0A";
when x"14A" => DATA <= x"84";
when x"14B" => DATA <= x"DF";
when x"14C" => DATA <= x"80";
when x"14D" => DATA <= x"07";
when x"14E" => DATA <= x"25";
when x"14F" => DATA <= x"21";
when x"150" => DATA <= x"81";
when x"151" => DATA <= x"40";
when x"152" => DATA <= x"24";
when x"153" => DATA <= x"1D";
when x"154" => DATA <= x"84";
when x"155" => DATA <= x"0F";
when x"156" => DATA <= x"1E";
when x"157" => DATA <= x"02";
when x"158" => DATA <= x"58";
when x"159" => DATA <= x"49";
when x"15A" => DATA <= x"58";
when x"15B" => DATA <= x"49";
when x"15C" => DATA <= x"58";
when x"15D" => DATA <= x"49";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"1E";
when x"161" => DATA <= x"12";
when x"162" => DATA <= x"1E";
when x"163" => DATA <= x"01";
when x"164" => DATA <= x"1E";
when x"165" => DATA <= x"89";
when x"166" => DATA <= x"3A";
when x"167" => DATA <= x"1E";
when x"168" => DATA <= x"12";
when x"169" => DATA <= x"20";
when x"16A" => DATA <= x"D5";
when x"16B" => DATA <= x"A6";
when x"16C" => DATA <= x"80";
when x"16D" => DATA <= x"81";
when x"16E" => DATA <= x"20";
when x"16F" => DATA <= x"27";
when x"170" => DATA <= x"FA";
when x"171" => DATA <= x"30";
when x"172" => DATA <= x"1F";
when x"173" => DATA <= x"81";
when x"174" => DATA <= x"21";
when x"175" => DATA <= x"39";
when x"176" => DATA <= x"34";
when x"177" => DATA <= x"7C";
when x"178" => DATA <= x"11";
when x"179" => DATA <= x"8C";
when x"17A" => DATA <= x"F8";
when x"17B" => DATA <= x"00";
when x"17C" => DATA <= x"24";
when x"17D" => DATA <= x"08";
when x"17E" => DATA <= x"10";
when x"17F" => DATA <= x"FF";
when x"180" => DATA <= x"F9";
when x"181" => DATA <= x"8A";
when x"182" => DATA <= x"10";
when x"183" => DATA <= x"CE";
when x"184" => DATA <= x"FF";
when x"185" => DATA <= x"28";
when x"186" => DATA <= x"8D";
when x"187" => DATA <= x"0F";
when x"188" => DATA <= x"10";
when x"189" => DATA <= x"CE";
when x"18A" => DATA <= x"00";
when x"18B" => DATA <= x"00";
when x"18C" => DATA <= x"35";
when x"18D" => DATA <= x"FC";
when x"18E" => DATA <= x"48";
when x"18F" => DATA <= x"45";
when x"190" => DATA <= x"4C";
when x"191" => DATA <= x"50";
when x"192" => DATA <= x"80";
when x"193" => DATA <= x"47";
when x"194" => DATA <= x"4F";
when x"195" => DATA <= x"81";
when x"196" => DATA <= x"00";
when x"197" => DATA <= x"8D";
when x"198" => DATA <= x"D2";
when x"199" => DATA <= x"A6";
when x"19A" => DATA <= x"80";
when x"19B" => DATA <= x"81";
when x"19C" => DATA <= x"2A";
when x"19D" => DATA <= x"27";
when x"19E" => DATA <= x"F8";
when x"19F" => DATA <= x"30";
when x"1A0" => DATA <= x"1F";
when x"1A1" => DATA <= x"34";
when x"1A2" => DATA <= x"10";
when x"1A3" => DATA <= x"A6";
when x"1A4" => DATA <= x"80";
when x"1A5" => DATA <= x"81";
when x"1A6" => DATA <= x"21";
when x"1A7" => DATA <= x"24";
when x"1A8" => DATA <= x"FA";
when x"1A9" => DATA <= x"30";
when x"1AA" => DATA <= x"1F";
when x"1AB" => DATA <= x"8D";
when x"1AC" => DATA <= x"BE";
when x"1AD" => DATA <= x"BF";
when x"1AE" => DATA <= x"FF";
when x"1AF" => DATA <= x"86";
when x"1B0" => DATA <= x"10";
when x"1B1" => DATA <= x"8E";
when x"1B2" => DATA <= x"F9";
when x"1B3" => DATA <= x"8E";
when x"1B4" => DATA <= x"AE";
when x"1B5" => DATA <= x"E4";
when x"1B6" => DATA <= x"A6";
when x"1B7" => DATA <= x"84";
when x"1B8" => DATA <= x"81";
when x"1B9" => DATA <= x"41";
when x"1BA" => DATA <= x"25";
when x"1BB" => DATA <= x"68";
when x"1BC" => DATA <= x"A6";
when x"1BD" => DATA <= x"80";
when x"1BE" => DATA <= x"84";
when x"1BF" => DATA <= x"DF";
when x"1C0" => DATA <= x"A1";
when x"1C1" => DATA <= x"A0";
when x"1C2" => DATA <= x"27";
when x"1C3" => DATA <= x"F8";
when x"1C4" => DATA <= x"A6";
when x"1C5" => DATA <= x"A2";
when x"1C6" => DATA <= x"2B";
when x"1C7" => DATA <= x"16";
when x"1C8" => DATA <= x"A6";
when x"1C9" => DATA <= x"1F";
when x"1CA" => DATA <= x"81";
when x"1CB" => DATA <= x"2E";
when x"1CC" => DATA <= x"27";
when x"1CD" => DATA <= x"0A";
when x"1CE" => DATA <= x"A6";
when x"1CF" => DATA <= x"A0";
when x"1D0" => DATA <= x"2A";
when x"1D1" => DATA <= x"FC";
when x"1D2" => DATA <= x"A6";
when x"1D3" => DATA <= x"A4";
when x"1D4" => DATA <= x"26";
when x"1D5" => DATA <= x"DE";
when x"1D6" => DATA <= x"20";
when x"1D7" => DATA <= x"4C";
when x"1D8" => DATA <= x"A6";
when x"1D9" => DATA <= x"A0";
when x"1DA" => DATA <= x"2A";
when x"1DB" => DATA <= x"FC";
when x"1DC" => DATA <= x"20";
when x"1DD" => DATA <= x"06";
when x"1DE" => DATA <= x"E6";
when x"1DF" => DATA <= x"82";
when x"1E0" => DATA <= x"C1";
when x"1E1" => DATA <= x"21";
when x"1E2" => DATA <= x"24";
when x"1E3" => DATA <= x"40";
when x"1E4" => DATA <= x"81";
when x"1E5" => DATA <= x"80";
when x"1E6" => DATA <= x"27";
when x"1E7" => DATA <= x"2D";
when x"1E8" => DATA <= x"8D";
when x"1E9" => DATA <= x"81";
when x"1EA" => DATA <= x"10";
when x"1EB" => DATA <= x"BE";
when x"1EC" => DATA <= x"FF";
when x"1ED" => DATA <= x"90";
when x"1EE" => DATA <= x"81";
when x"1EF" => DATA <= x"0D";
when x"1F0" => DATA <= x"27";
when x"1F1" => DATA <= x"18";
when x"1F2" => DATA <= x"81";
when x"1F3" => DATA <= x"3B";
when x"1F4" => DATA <= x"27";
when x"1F5" => DATA <= x"12";
when x"1F6" => DATA <= x"BD";
when x"1F7" => DATA <= x"FF";
when x"1F8" => DATA <= x"A1";
when x"1F9" => DATA <= x"24";
when x"1FA" => DATA <= x"29";
when x"1FB" => DATA <= x"BD";
when x"1FC" => DATA <= x"F9";
when x"1FD" => DATA <= x"6B";
when x"1FE" => DATA <= x"81";
when x"1FF" => DATA <= x"3B";
when x"200" => DATA <= x"27";
when x"201" => DATA <= x"06";
when x"202" => DATA <= x"81";
when x"203" => DATA <= x"0D";
when x"204" => DATA <= x"26";
when x"205" => DATA <= x"1E";
when x"206" => DATA <= x"30";
when x"207" => DATA <= x"1F";
when x"208" => DATA <= x"30";
when x"209" => DATA <= x"01";
when x"20A" => DATA <= x"BF";
when x"20B" => DATA <= x"FF";
when x"20C" => DATA <= x"86";
when x"20D" => DATA <= x"35";
when x"20E" => DATA <= x"10";
when x"20F" => DATA <= x"1F";
when x"210" => DATA <= x"21";
when x"211" => DATA <= x"1A";
when x"212" => DATA <= x"01";
when x"213" => DATA <= x"20";
when x"214" => DATA <= x"23";
when x"215" => DATA <= x"BD";
when x"216" => DATA <= x"F9";
when x"217" => DATA <= x"6B";
when x"218" => DATA <= x"25";
when x"219" => DATA <= x"04";
when x"21A" => DATA <= x"81";
when x"21B" => DATA <= x"2E";
when x"21C" => DATA <= x"26";
when x"21D" => DATA <= x"06";
when x"21E" => DATA <= x"8E";
when x"21F" => DATA <= x"F8";
when x"220" => DATA <= x"16";
when x"221" => DATA <= x"BD";
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when x"223" => DATA <= x"33";
when x"224" => DATA <= x"35";
when x"225" => DATA <= x"10";
when x"226" => DATA <= x"86";
when x"227" => DATA <= x"02";
when x"228" => DATA <= x"BD";
when x"229" => DATA <= x"FC";
when x"22A" => DATA <= x"DE";
when x"22B" => DATA <= x"BD";
when x"22C" => DATA <= x"FC";
when x"22D" => DATA <= x"A2";
when x"22E" => DATA <= x"1A";
when x"22F" => DATA <= x"01";
when x"230" => DATA <= x"BD";
when x"231" => DATA <= x"FA";
when x"232" => DATA <= x"B4";
when x"233" => DATA <= x"2A";
when x"234" => DATA <= x"51";
when x"235" => DATA <= x"BE";
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when x"238" => DATA <= x"34";
when x"239" => DATA <= x"01";
when x"23A" => DATA <= x"1F";
when x"23B" => DATA <= x"12";
when x"23C" => DATA <= x"E6";
when x"23D" => DATA <= x"07";
when x"23E" => DATA <= x"3A";
when x"23F" => DATA <= x"CE";
when x"240" => DATA <= x"FA";
when x"241" => DATA <= x"93";
when x"242" => DATA <= x"C6";
when x"243" => DATA <= x"04";
when x"244" => DATA <= x"A6";
when x"245" => DATA <= x"80";
when x"246" => DATA <= x"A1";
when x"247" => DATA <= x"C2";
when x"248" => DATA <= x"26";
when x"249" => DATA <= x"3D";
when x"24A" => DATA <= x"5A";
when x"24B" => DATA <= x"26";
when x"24C" => DATA <= x"F7";
when x"24D" => DATA <= x"A6";
when x"24E" => DATA <= x"26";
when x"24F" => DATA <= x"48";
when x"250" => DATA <= x"2A";
when x"251" => DATA <= x"41";
when x"252" => DATA <= x"84";
when x"253" => DATA <= x"1E";
when x"254" => DATA <= x"81";
when x"255" => DATA <= x"06";
when x"256" => DATA <= x"26";
when x"257" => DATA <= x"3B";
when x"258" => DATA <= x"30";
when x"259" => DATA <= x"1C";
when x"25A" => DATA <= x"BF";
when x"25B" => DATA <= x"FF";
when x"25C" => DATA <= x"82";
when x"25D" => DATA <= x"FE";
when x"25E" => DATA <= x"FF";
when x"25F" => DATA <= x"90";
when x"260" => DATA <= x"BE";
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when x"262" => DATA <= x"8A";
when x"263" => DATA <= x"35";
when x"264" => DATA <= x"02";
when x"265" => DATA <= x"34";
when x"266" => DATA <= x"50";
when x"267" => DATA <= x"10";
when x"268" => DATA <= x"8C";
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when x"26A" => DATA <= x"00";
when x"26B" => DATA <= x"25";
when x"26C" => DATA <= x"04";
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when x"26E" => DATA <= x"BF";
when x"26F" => DATA <= x"FF";
when x"270" => DATA <= x"8A";
when x"271" => DATA <= x"46";
when x"272" => DATA <= x"10";
when x"273" => DATA <= x"BF";
when x"274" => DATA <= x"FF";
when x"275" => DATA <= x"90";
when x"276" => DATA <= x"BE";
when x"277" => DATA <= x"FF";
when x"278" => DATA <= x"86";
when x"279" => DATA <= x"86";
when x"27A" => DATA <= x"01";
when x"27B" => DATA <= x"AD";
when x"27C" => DATA <= x"A4";
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when x"27E" => DATA <= x"60";
when x"27F" => DATA <= x"10";
when x"280" => DATA <= x"BF";
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when x"282" => DATA <= x"8A";
when x"283" => DATA <= x"FF";
when x"284" => DATA <= x"FF";
when x"285" => DATA <= x"90";
when x"286" => DATA <= x"39";
when x"287" => DATA <= x"BE";
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when x"289" => DATA <= x"86";
when x"28A" => DATA <= x"4F";
when x"28B" => DATA <= x"35";
when x"28C" => DATA <= x"01";
when x"28D" => DATA <= x"6E";
when x"28E" => DATA <= x"A4";
when x"28F" => DATA <= x"29";
when x"290" => DATA <= x"43";
when x"291" => DATA <= x"28";
when x"292" => DATA <= x"00";
when x"293" => DATA <= x"35";
when x"294" => DATA <= x"01";
when x"295" => DATA <= x"10";
when x"296" => DATA <= x"24";
when x"297" => DATA <= x"05";
when x"298" => DATA <= x"20";
when x"299" => DATA <= x"BD";
when x"29A" => DATA <= x"F8";
when x"29B" => DATA <= x"CC";
when x"29C" => DATA <= x"3F";
when x"29D" => DATA <= x"F9";
when x"29E" => DATA <= x"4E";
when x"29F" => DATA <= x"6F";
when x"2A0" => DATA <= x"74";
when x"2A1" => DATA <= x"20";
when x"2A2" => DATA <= x"36";
when x"2A3" => DATA <= x"38";
when x"2A4" => DATA <= x"30";
when x"2A5" => DATA <= x"39";
when x"2A6" => DATA <= x"20";
when x"2A7" => DATA <= x"63";
when x"2A8" => DATA <= x"6F";
when x"2A9" => DATA <= x"64";
when x"2AA" => DATA <= x"65";
when x"2AB" => DATA <= x"00";
when x"2AC" => DATA <= x"4F";
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when x"2AE" => DATA <= x"FC";
when x"2AF" => DATA <= x"DE";
when x"2B0" => DATA <= x"8D";
when x"2B1" => DATA <= x"02";
when x"2B2" => DATA <= x"8B";
when x"2B3" => DATA <= x"80";
when x"2B4" => DATA <= x"B6";
when x"2B5" => DATA <= x"FE";
when x"2B6" => DATA <= x"E2";
when x"2B7" => DATA <= x"2A";
when x"2B8" => DATA <= x"FB";
when x"2B9" => DATA <= x"B6";
when x"2BA" => DATA <= x"FE";
when x"2BB" => DATA <= x"E3";
when x"2BC" => DATA <= x"39";
when x"2BD" => DATA <= x"34";
when x"2BE" => DATA <= x"06";
when x"2BF" => DATA <= x"4D";
when x"2C0" => DATA <= x"2B";
when x"2C1" => DATA <= x"23";
when x"2C2" => DATA <= x"86";
when x"2C3" => DATA <= x"04";
when x"2C4" => DATA <= x"BD";
when x"2C5" => DATA <= x"FC";
when x"2C6" => DATA <= x"DE";
when x"2C7" => DATA <= x"1F";
when x"2C8" => DATA <= x"10";
when x"2C9" => DATA <= x"BD";
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when x"2CB" => DATA <= x"DC";
when x"2CC" => DATA <= x"35";
when x"2CD" => DATA <= x"06";
when x"2CE" => DATA <= x"34";
when x"2CF" => DATA <= x"06";
when x"2D0" => DATA <= x"BD";
when x"2D1" => DATA <= x"FC";
when x"2D2" => DATA <= x"DE";
when x"2D3" => DATA <= x"8D";
when x"2D4" => DATA <= x"DF";
when x"2D5" => DATA <= x"1F";
when x"2D6" => DATA <= x"89";
when x"2D7" => DATA <= x"4F";
when x"2D8" => DATA <= x"1F";
when x"2D9" => DATA <= x"01";
when x"2DA" => DATA <= x"35";
when x"2DB" => DATA <= x"86";
when x"2DC" => DATA <= x"8E";
when x"2DD" => DATA <= x"F8";
when x"2DE" => DATA <= x"16";
when x"2DF" => DATA <= x"BF";
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when x"2E1" => DATA <= x"86";
when x"2E2" => DATA <= x"7E";
when x"2E3" => DATA <= x"FA";
when x"2E4" => DATA <= x"2E";
when x"2E5" => DATA <= x"81";
when x"2E6" => DATA <= x"82";
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when x"2E8" => DATA <= x"39";
when x"2E9" => DATA <= x"81";
when x"2EA" => DATA <= x"83";
when x"2EB" => DATA <= x"27";
when x"2EC" => DATA <= x"37";
when x"2ED" => DATA <= x"81";
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when x"2EF" => DATA <= x"27";
when x"2F0" => DATA <= x"33";
when x"2F1" => DATA <= x"86";
when x"2F2" => DATA <= x"06";
when x"2F3" => DATA <= x"BD";
when x"2F4" => DATA <= x"FC";
when x"2F5" => DATA <= x"DE";
when x"2F6" => DATA <= x"1F";
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when x"2F8" => DATA <= x"BD";
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when x"2FA" => DATA <= x"DC";
when x"2FB" => DATA <= x"BD";
when x"2FC" => DATA <= x"FC";
when x"2FD" => DATA <= x"DA";
when x"2FE" => DATA <= x"35";
when x"2FF" => DATA <= x"06";
when x"300" => DATA <= x"BD";
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when x"302" => DATA <= x"DE";
when x"303" => DATA <= x"81";
when x"304" => DATA <= x"9D";
when x"305" => DATA <= x"27";
when x"306" => DATA <= x"B5";
when x"307" => DATA <= x"81";
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when x"309" => DATA <= x"27";
when x"30A" => DATA <= x"D1";
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when x"30C" => DATA <= x"06";
when x"30D" => DATA <= x"8D";
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when x"30F" => DATA <= x"8B";
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when x"311" => DATA <= x"34";
when x"312" => DATA <= x"01";
when x"313" => DATA <= x"8D";
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when x"316" => DATA <= x"89";
when x"317" => DATA <= x"4F";
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when x"31A" => DATA <= x"8D";
when x"31B" => DATA <= x"98";
when x"31C" => DATA <= x"1E";
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when x"31E" => DATA <= x"1F";
when x"31F" => DATA <= x"01";
when x"320" => DATA <= x"35";
when x"321" => DATA <= x"87";
when x"322" => DATA <= x"86";
when x"323" => DATA <= x"85";
when x"324" => DATA <= x"48";
when x"325" => DATA <= x"8E";
when x"326" => DATA <= x"FF";
when x"327" => DATA <= x"82";
when x"328" => DATA <= x"EC";
when x"329" => DATA <= x"84";
when x"32A" => DATA <= x"1F";
when x"32B" => DATA <= x"01";
when x"32C" => DATA <= x"1F";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"4F";
when x"32F" => DATA <= x"1F";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"35";
when x"332" => DATA <= x"86";
when x"333" => DATA <= x"4D";
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when x"335" => DATA <= x"5C";
when x"336" => DATA <= x"34";
when x"337" => DATA <= x"26";
when x"338" => DATA <= x"34";
when x"339" => DATA <= x"10";
when x"33A" => DATA <= x"1F";
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when x"33C" => DATA <= x"86";
when x"33D" => DATA <= x"08";
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when x"340" => DATA <= x"DE";
when x"341" => DATA <= x"BD";
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when x"345" => DATA <= x"2A";
when x"346" => DATA <= x"04";
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when x"348" => DATA <= x"84";
when x"349" => DATA <= x"20";
when x"34A" => DATA <= x"0C";
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when x"34C" => DATA <= x"10";
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when x"34F" => DATA <= x"24";
when x"350" => DATA <= x"06";
when x"351" => DATA <= x"8E";
when x"352" => DATA <= x"FB";
when x"353" => DATA <= x"C1";
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when x"355" => DATA <= x"A6";
when x"356" => DATA <= x"84";
when x"357" => DATA <= x"35";
when x"358" => DATA <= x"10";
when x"359" => DATA <= x"BD";
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when x"35B" => DATA <= x"DE";
when x"35C" => DATA <= x"1F";
when x"35D" => DATA <= x"02";
when x"35E" => DATA <= x"1E";
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when x"360" => DATA <= x"4F";
when x"361" => DATA <= x"1E";
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when x"363" => DATA <= x"4A";
when x"364" => DATA <= x"2B";
when x"365" => DATA <= x"03";
when x"366" => DATA <= x"BD";
when x"367" => DATA <= x"FC";
when x"368" => DATA <= x"AB";
when x"369" => DATA <= x"34";
when x"36A" => DATA <= x"10";
when x"36B" => DATA <= x"5D";
when x"36C" => DATA <= x"2A";
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when x"370" => DATA <= x"20";
when x"371" => DATA <= x"0C";
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when x"373" => DATA <= x"10";
when x"374" => DATA <= x"C1";
when x"375" => DATA <= x"15";
when x"376" => DATA <= x"24";
when x"377" => DATA <= x"06";
when x"378" => DATA <= x"8E";
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when x"37A" => DATA <= x"D5";
when x"37B" => DATA <= x"3A";
when x"37C" => DATA <= x"A6";
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when x"37E" => DATA <= x"35";
when x"37F" => DATA <= x"10";
when x"380" => DATA <= x"BD";
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when x"382" => DATA <= x"DE";
when x"383" => DATA <= x"1F";
when x"384" => DATA <= x"02";
when x"385" => DATA <= x"1E";
when x"386" => DATA <= x"89";
when x"387" => DATA <= x"4F";
when x"388" => DATA <= x"1E";
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when x"38A" => DATA <= x"4A";
when x"38B" => DATA <= x"2B";
when x"38C" => DATA <= x"03";
when x"38D" => DATA <= x"BD";
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when x"38F" => DATA <= x"BB";
when x"390" => DATA <= x"35";
when x"391" => DATA <= x"A6";
when x"392" => DATA <= x"86";
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when x"394" => DATA <= x"BD";
when x"395" => DATA <= x"FC";
when x"396" => DATA <= x"DE";
when x"397" => DATA <= x"30";
when x"398" => DATA <= x"02";
when x"399" => DATA <= x"10";
when x"39A" => DATA <= x"8E";
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when x"39C" => DATA <= x"03";
when x"39D" => DATA <= x"BD";
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when x"39F" => DATA <= x"AB";
when x"3A0" => DATA <= x"30";
when x"3A1" => DATA <= x"1E";
when x"3A2" => DATA <= x"86";
when x"3A3" => DATA <= x"07";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"DE";
when x"3A7" => DATA <= x"4F";
when x"3A8" => DATA <= x"BD";
when x"3A9" => DATA <= x"FC";
when x"3AA" => DATA <= x"DE";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FA";
when x"3AD" => DATA <= x"B4";
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when x"3AF" => DATA <= x"80";
when x"3B0" => DATA <= x"25";
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when x"3B2" => DATA <= x"AE";
when x"3B3" => DATA <= x"84";
when x"3B4" => DATA <= x"BD";
when x"3B5" => DATA <= x"FA";
when x"3B6" => DATA <= x"B4";
when x"3B7" => DATA <= x"A7";
when x"3B8" => DATA <= x"80";
when x"3B9" => DATA <= x"31";
when x"3BA" => DATA <= x"21";
when x"3BB" => DATA <= x"81";
when x"3BC" => DATA <= x"0D";
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when x"3BE" => DATA <= x"F5";
when x"3BF" => DATA <= x"31";
when x"3C0" => DATA <= x"3F";
when x"3C1" => DATA <= x"39";
when x"3C2" => DATA <= x"00";
when x"3C3" => DATA <= x"05";
when x"3C4" => DATA <= x"00";
when x"3C5" => DATA <= x"05";
when x"3C6" => DATA <= x"04";
when x"3C7" => DATA <= x"05";
when x"3C8" => DATA <= x"08";
when x"3C9" => DATA <= x"0E";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"01";
when x"3CC" => DATA <= x"01";
when x"3CD" => DATA <= x"05";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"10";
when x"3D0" => DATA <= x"20";
when x"3D1" => DATA <= x"10";
when x"3D2" => DATA <= x"0D";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"04";
when x"3D5" => DATA <= x"80";
when x"3D6" => DATA <= x"05";
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when x"3D8" => DATA <= x"05";
when x"3D9" => DATA <= x"00";
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when x"3DC" => DATA <= x"00";
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when x"3DF" => DATA <= x"09";
when x"3E0" => DATA <= x"05";
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when x"3E2" => DATA <= x"08";
when x"3E3" => DATA <= x"19";
when x"3E4" => DATA <= x"00";
when x"3E5" => DATA <= x"01";
when x"3E6" => DATA <= x"0D";
when x"3E7" => DATA <= x"80";
when x"3E8" => DATA <= x"04";
when x"3E9" => DATA <= x"80";
when x"3EA" => DATA <= x"34";
when x"3EB" => DATA <= x"26";
when x"3EC" => DATA <= x"86";
when x"3ED" => DATA <= x"0C";
when x"3EE" => DATA <= x"BD";
when x"3EF" => DATA <= x"FC";
when x"3F0" => DATA <= x"DE";
when x"3F1" => DATA <= x"BD";
when x"3F2" => DATA <= x"FC";
when x"3F3" => DATA <= x"DA";
when x"3F4" => DATA <= x"10";
when x"3F5" => DATA <= x"8E";
when x"3F6" => DATA <= x"00";
when x"3F7" => DATA <= x"04";
when x"3F8" => DATA <= x"BD";
when x"3F9" => DATA <= x"FC";
when x"3FA" => DATA <= x"AB";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"06";
when x"3FD" => DATA <= x"BD";
when x"3FE" => DATA <= x"FC";
when x"3FF" => DATA <= x"DE";
when x"400" => DATA <= x"BD";
when x"401" => DATA <= x"FA";
when x"402" => DATA <= x"B4";
when x"403" => DATA <= x"34";
when x"404" => DATA <= x"02";
when x"405" => DATA <= x"10";
when x"406" => DATA <= x"8E";
when x"407" => DATA <= x"00";
when x"408" => DATA <= x"04";
when x"409" => DATA <= x"BD";
when x"40A" => DATA <= x"FC";
when x"40B" => DATA <= x"BB";
when x"40C" => DATA <= x"35";
when x"40D" => DATA <= x"A2";
when x"40E" => DATA <= x"34";
when x"40F" => DATA <= x"04";
when x"410" => DATA <= x"86";
when x"411" => DATA <= x"0E";
when x"412" => DATA <= x"BD";
when x"413" => DATA <= x"FC";
when x"414" => DATA <= x"DE";
when x"415" => DATA <= x"BD";
when x"416" => DATA <= x"FC";
when x"417" => DATA <= x"DA";
when x"418" => DATA <= x"35";
when x"419" => DATA <= x"04";
when x"41A" => DATA <= x"7E";
when x"41B" => DATA <= x"FA";
when x"41C" => DATA <= x"B0";
when x"41D" => DATA <= x"34";
when x"41E" => DATA <= x"06";
when x"41F" => DATA <= x"86";
when x"420" => DATA <= x"10";
when x"421" => DATA <= x"BD";
when x"422" => DATA <= x"FC";
when x"423" => DATA <= x"DE";
when x"424" => DATA <= x"BD";
when x"425" => DATA <= x"FC";
when x"426" => DATA <= x"DA";
when x"427" => DATA <= x"35";
when x"428" => DATA <= x"06";
when x"429" => DATA <= x"34";
when x"42A" => DATA <= x"06";
when x"42B" => DATA <= x"BD";
when x"42C" => DATA <= x"FC";
when x"42D" => DATA <= x"DE";
when x"42E" => DATA <= x"BD";
when x"42F" => DATA <= x"FA";
when x"430" => DATA <= x"B4";
when x"431" => DATA <= x"35";
when x"432" => DATA <= x"86";
when x"433" => DATA <= x"34";
when x"434" => DATA <= x"06";
when x"435" => DATA <= x"86";
when x"436" => DATA <= x"12";
when x"437" => DATA <= x"BD";
when x"438" => DATA <= x"FC";
when x"439" => DATA <= x"DE";
when x"43A" => DATA <= x"35";
when x"43B" => DATA <= x"06";
when x"43C" => DATA <= x"BD";
when x"43D" => DATA <= x"FC";
when x"43E" => DATA <= x"DE";
when x"43F" => DATA <= x"4D";
when x"440" => DATA <= x"27";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"A2";
when x"445" => DATA <= x"7E";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"B4";
when x"448" => DATA <= x"34";
when x"449" => DATA <= x"04";
when x"44A" => DATA <= x"BD";
when x"44B" => DATA <= x"FC";
when x"44C" => DATA <= x"DA";
when x"44D" => DATA <= x"BD";
when x"44E" => DATA <= x"FA";
when x"44F" => DATA <= x"B4";
when x"450" => DATA <= x"4F";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"84";
when x"453" => DATA <= x"34";
when x"454" => DATA <= x"32";
when x"455" => DATA <= x"86";
when x"456" => DATA <= x"14";
when x"457" => DATA <= x"BD";
when x"458" => DATA <= x"FC";
when x"459" => DATA <= x"DE";
when x"45A" => DATA <= x"30";
when x"45B" => DATA <= x"02";
when x"45C" => DATA <= x"10";
when x"45D" => DATA <= x"8E";
when x"45E" => DATA <= x"00";
when x"45F" => DATA <= x"10";
when x"460" => DATA <= x"BD";
when x"461" => DATA <= x"FC";
when x"462" => DATA <= x"AB";
when x"463" => DATA <= x"30";
when x"464" => DATA <= x"1E";
when x"465" => DATA <= x"AE";
when x"466" => DATA <= x"84";
when x"467" => DATA <= x"BD";
when x"468" => DATA <= x"FC";
when x"469" => DATA <= x"A2";
when x"46A" => DATA <= x"35";
when x"46B" => DATA <= x"02";
when x"46C" => DATA <= x"BD";
when x"46D" => DATA <= x"FC";
when x"46E" => DATA <= x"DE";
when x"46F" => DATA <= x"BD";
when x"470" => DATA <= x"FA";
when x"471" => DATA <= x"B4";
when x"472" => DATA <= x"35";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"34";
when x"475" => DATA <= x"02";
when x"476" => DATA <= x"30";
when x"477" => DATA <= x"02";
when x"478" => DATA <= x"10";
when x"479" => DATA <= x"8E";
when x"47A" => DATA <= x"00";
when x"47B" => DATA <= x"10";
when x"47C" => DATA <= x"BD";
when x"47D" => DATA <= x"FC";
when x"47E" => DATA <= x"BB";
when x"47F" => DATA <= x"30";
when x"480" => DATA <= x"1E";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"34";
when x"484" => DATA <= x"22";
when x"485" => DATA <= x"86";
when x"486" => DATA <= x"16";
when x"487" => DATA <= x"BD";
when x"488" => DATA <= x"FC";
when x"489" => DATA <= x"DE";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"8E";
when x"48C" => DATA <= x"00";
when x"48D" => DATA <= x"0D";
when x"48E" => DATA <= x"BD";
when x"48F" => DATA <= x"FC";
when x"490" => DATA <= x"AB";
when x"491" => DATA <= x"35";
when x"492" => DATA <= x"02";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"DE";
when x"496" => DATA <= x"10";
when x"497" => DATA <= x"8E";
when x"498" => DATA <= x"00";
when x"499" => DATA <= x"0D";
when x"49A" => DATA <= x"BD";
when x"49B" => DATA <= x"FC";
when x"49C" => DATA <= x"BB";
when x"49D" => DATA <= x"35";
when x"49E" => DATA <= x"20";
when x"49F" => DATA <= x"7E";
when x"4A0" => DATA <= x"FA";
when x"4A1" => DATA <= x"B0";
when x"4A2" => DATA <= x"A6";
when x"4A3" => DATA <= x"80";
when x"4A4" => DATA <= x"8D";
when x"4A5" => DATA <= x"38";
when x"4A6" => DATA <= x"81";
when x"4A7" => DATA <= x"0D";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"F8";
when x"4AA" => DATA <= x"39";
when x"4AB" => DATA <= x"34";
when x"4AC" => DATA <= x"04";
when x"4AD" => DATA <= x"1F";
when x"4AE" => DATA <= x"20";
when x"4AF" => DATA <= x"3A";
when x"4B0" => DATA <= x"35";
when x"4B1" => DATA <= x"04";
when x"4B2" => DATA <= x"A6";
when x"4B3" => DATA <= x"82";
when x"4B4" => DATA <= x"8D";
when x"4B5" => DATA <= x"28";
when x"4B6" => DATA <= x"31";
when x"4B7" => DATA <= x"3F";
when x"4B8" => DATA <= x"26";
when x"4B9" => DATA <= x"F8";
when x"4BA" => DATA <= x"39";
when x"4BB" => DATA <= x"34";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"1F";
when x"4BE" => DATA <= x"20";
when x"4BF" => DATA <= x"3A";
when x"4C0" => DATA <= x"35";
when x"4C1" => DATA <= x"04";
when x"4C2" => DATA <= x"BD";
when x"4C3" => DATA <= x"FA";
when x"4C4" => DATA <= x"B4";
when x"4C5" => DATA <= x"A7";
when x"4C6" => DATA <= x"82";
when x"4C7" => DATA <= x"31";
when x"4C8" => DATA <= x"3F";
when x"4C9" => DATA <= x"26";
when x"4CA" => DATA <= x"F7";
when x"4CB" => DATA <= x"39";
when x"4CC" => DATA <= x"34";
when x"4CD" => DATA <= x"02";
when x"4CE" => DATA <= x"B6";
when x"4CF" => DATA <= x"FE";
when x"4D0" => DATA <= x"E0";
when x"4D1" => DATA <= x"48";
when x"4D2" => DATA <= x"2A";
when x"4D3" => DATA <= x"FA";
when x"4D4" => DATA <= x"35";
when x"4D5" => DATA <= x"02";
when x"4D6" => DATA <= x"B7";
when x"4D7" => DATA <= x"FE";
when x"4D8" => DATA <= x"E1";
when x"4D9" => DATA <= x"39";
when x"4DA" => DATA <= x"1F";
when x"4DB" => DATA <= x"20";
when x"4DC" => DATA <= x"1F";
when x"4DD" => DATA <= x"98";
when x"4DE" => DATA <= x"34";
when x"4DF" => DATA <= x"02";
when x"4E0" => DATA <= x"B6";
when x"4E1" => DATA <= x"FE";
when x"4E2" => DATA <= x"E2";
when x"4E3" => DATA <= x"48";
when x"4E4" => DATA <= x"2A";
when x"4E5" => DATA <= x"FA";
when x"4E6" => DATA <= x"35";
when x"4E7" => DATA <= x"02";
when x"4E8" => DATA <= x"B7";
when x"4E9" => DATA <= x"FE";
when x"4EA" => DATA <= x"E3";
when x"4EB" => DATA <= x"39";
when x"4EC" => DATA <= x"34";
when x"4ED" => DATA <= x"02";
when x"4EE" => DATA <= x"B6";
when x"4EF" => DATA <= x"FE";
when x"4F0" => DATA <= x"E6";
when x"4F1" => DATA <= x"2B";
when x"4F2" => DATA <= x"51";
when x"4F3" => DATA <= x"B6";
when x"4F4" => DATA <= x"FE";
when x"4F5" => DATA <= x"E0";
when x"4F6" => DATA <= x"2B";
when x"4F7" => DATA <= x"06";
when x"4F8" => DATA <= x"35";
when x"4F9" => DATA <= x"02";
when x"4FA" => DATA <= x"6E";
when x"4FB" => DATA <= x"9F";
when x"4FC" => DATA <= x"FF";
when x"4FD" => DATA <= x"B1";
when x"4FE" => DATA <= x"B6";
when x"4FF" => DATA <= x"FE";
when x"500" => DATA <= x"E1";
when x"501" => DATA <= x"2B";
when x"502" => DATA <= x"1B";
when x"503" => DATA <= x"35";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"34";
when x"506" => DATA <= x"76";
when x"507" => DATA <= x"8D";
when x"508" => DATA <= x"1C";
when x"509" => DATA <= x"1F";
when x"50A" => DATA <= x"89";
when x"50B" => DATA <= x"4F";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"02";
when x"50E" => DATA <= x"8D";
when x"50F" => DATA <= x"15";
when x"510" => DATA <= x"1F";
when x"511" => DATA <= x"89";
when x"512" => DATA <= x"4F";
when x"513" => DATA <= x"1F";
when x"514" => DATA <= x"01";
when x"515" => DATA <= x"8D";
when x"516" => DATA <= x"0E";
when x"517" => DATA <= x"AD";
when x"518" => DATA <= x"9F";
when x"519" => DATA <= x"FF";
when x"51A" => DATA <= x"FC";
when x"51B" => DATA <= x"35";
when x"51C" => DATA <= x"76";
when x"51D" => DATA <= x"3B";
when x"51E" => DATA <= x"48";
when x"51F" => DATA <= x"B7";
when x"520" => DATA <= x"FF";
when x"521" => DATA <= x"80";
when x"522" => DATA <= x"35";
when x"523" => DATA <= x"02";
when x"524" => DATA <= x"3B";
when x"525" => DATA <= x"B6";
when x"526" => DATA <= x"FE";
when x"527" => DATA <= x"E6";
when x"528" => DATA <= x"2B";
when x"529" => DATA <= x"02";
when x"52A" => DATA <= x"8D";
when x"52B" => DATA <= x"12";
when x"52C" => DATA <= x"B6";
when x"52D" => DATA <= x"FE";
when x"52E" => DATA <= x"E0";
when x"52F" => DATA <= x"2A";
when x"530" => DATA <= x"F4";
when x"531" => DATA <= x"B6";
when x"532" => DATA <= x"FE";
when x"533" => DATA <= x"E1";
when x"534" => DATA <= x"39";
when x"535" => DATA <= x"B6";
when x"536" => DATA <= x"FE";
when x"537" => DATA <= x"E6";
when x"538" => DATA <= x"2A";
when x"539" => DATA <= x"FB";
when x"53A" => DATA <= x"B6";
when x"53B" => DATA <= x"FE";
when x"53C" => DATA <= x"E7";
when x"53D" => DATA <= x"39";
when x"53E" => DATA <= x"1C";
when x"53F" => DATA <= x"7F";
when x"540" => DATA <= x"34";
when x"541" => DATA <= x"01";
when x"542" => DATA <= x"34";
when x"543" => DATA <= x"02";
when x"544" => DATA <= x"35";
when x"545" => DATA <= x"02";
when x"546" => DATA <= x"34";
when x"547" => DATA <= x"16";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E7";
when x"54B" => DATA <= x"2A";
when x"54C" => DATA <= x"22";
when x"54D" => DATA <= x"10";
when x"54E" => DATA <= x"CE";
when x"54F" => DATA <= x"FF";
when x"550" => DATA <= x"80";
when x"551" => DATA <= x"8E";
when x"552" => DATA <= x"FF";
when x"553" => DATA <= x"00";
when x"554" => DATA <= x"BD";
when x"555" => DATA <= x"FA";
when x"556" => DATA <= x"B4";
when x"557" => DATA <= x"86";
when x"558" => DATA <= x"3F";
when x"559" => DATA <= x"A7";
when x"55A" => DATA <= x"80";
when x"55B" => DATA <= x"BD";
when x"55C" => DATA <= x"FA";
when x"55D" => DATA <= x"B4";
when x"55E" => DATA <= x"A7";
when x"55F" => DATA <= x"80";
when x"560" => DATA <= x"BD";
when x"561" => DATA <= x"FA";
when x"562" => DATA <= x"B4";
when x"563" => DATA <= x"A7";
when x"564" => DATA <= x"80";
when x"565" => DATA <= x"26";
when x"566" => DATA <= x"F9";
when x"567" => DATA <= x"8E";
when x"568" => DATA <= x"FF";
when x"569" => DATA <= x"01";
when x"56A" => DATA <= x"34";
when x"56B" => DATA <= x"10";
when x"56C" => DATA <= x"7E";
when x"56D" => DATA <= x"FF";
when x"56E" => DATA <= x"BC";
when x"56F" => DATA <= x"34";
when x"570" => DATA <= x"02";
when x"571" => DATA <= x"8D";
when x"572" => DATA <= x"C2";
when x"573" => DATA <= x"35";
when x"574" => DATA <= x"02";
when x"575" => DATA <= x"81";
when x"576" => DATA <= x"05";
when x"577" => DATA <= x"26";
when x"578" => DATA <= x"06";
when x"579" => DATA <= x"7F";
when x"57A" => DATA <= x"FF";
when x"57B" => DATA <= x"94";
when x"57C" => DATA <= x"35";
when x"57D" => DATA <= x"16";
when x"57E" => DATA <= x"3B";
when x"57F" => DATA <= x"34";
when x"580" => DATA <= x"02";
when x"581" => DATA <= x"8D";
when x"582" => DATA <= x"B2";
when x"583" => DATA <= x"B7";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"8C";
when x"586" => DATA <= x"8D";
when x"587" => DATA <= x"AD";
when x"588" => DATA <= x"B7";
when x"589" => DATA <= x"FF";
when x"58A" => DATA <= x"8D";
when x"58B" => DATA <= x"8D";
when x"58C" => DATA <= x"A8";
when x"58D" => DATA <= x"B7";
when x"58E" => DATA <= x"FF";
when x"58F" => DATA <= x"8E";
when x"590" => DATA <= x"8D";
when x"591" => DATA <= x"A3";
when x"592" => DATA <= x"B7";
when x"593" => DATA <= x"FF";
when x"594" => DATA <= x"8F";
when x"595" => DATA <= x"8D";
when x"596" => DATA <= x"9E";
when x"597" => DATA <= x"86";
when x"598" => DATA <= x"FF";
when x"599" => DATA <= x"B7";
when x"59A" => DATA <= x"FF";
when x"59B" => DATA <= x"94";
when x"59C" => DATA <= x"1C";
when x"59D" => DATA <= x"BF";
when x"59E" => DATA <= x"BE";
when x"59F" => DATA <= x"FF";
when x"5A0" => DATA <= x"8E";
when x"5A1" => DATA <= x"A6";
when x"5A2" => DATA <= x"E0";
when x"5A3" => DATA <= x"27";
when x"5A4" => DATA <= x"6C";
when x"5A5" => DATA <= x"81";
when x"5A6" => DATA <= x"02";
when x"5A7" => DATA <= x"25";
when x"5A8" => DATA <= x"5B";
when x"5A9" => DATA <= x"27";
when x"5AA" => DATA <= x"49";
when x"5AB" => DATA <= x"81";
when x"5AC" => DATA <= x"04";
when x"5AD" => DATA <= x"25";
when x"5AE" => DATA <= x"35";
when x"5AF" => DATA <= x"27";
when x"5B0" => DATA <= x"6E";
when x"5B1" => DATA <= x"5F";
when x"5B2" => DATA <= x"81";
when x"5B3" => DATA <= x"07";
when x"5B4" => DATA <= x"25";
when x"5B5" => DATA <= x"11";
when x"5B6" => DATA <= x"26";
when x"5B7" => DATA <= x"67";
when x"5B8" => DATA <= x"B6";
when x"5B9" => DATA <= x"FE";
when x"5BA" => DATA <= x"E4";
when x"5BB" => DATA <= x"2A";
when x"5BC" => DATA <= x"FB";
when x"5BD" => DATA <= x"B6";
when x"5BE" => DATA <= x"FE";
when x"5BF" => DATA <= x"E5";
when x"5C0" => DATA <= x"A7";
when x"5C1" => DATA <= x"85";
when x"5C2" => DATA <= x"5C";
when x"5C3" => DATA <= x"26";
when x"5C4" => DATA <= x"F3";
when x"5C5" => DATA <= x"20";
when x"5C6" => DATA <= x"17";
when x"5C7" => DATA <= x"B6";
when x"5C8" => DATA <= x"FE";
when x"5C9" => DATA <= x"E4";
when x"5CA" => DATA <= x"48";
when x"5CB" => DATA <= x"2A";
when x"5CC" => DATA <= x"FA";
when x"5CD" => DATA <= x"A6";
when x"5CE" => DATA <= x"85";
when x"5CF" => DATA <= x"B7";
when x"5D0" => DATA <= x"FE";
when x"5D1" => DATA <= x"E5";
when x"5D2" => DATA <= x"5C";
when x"5D3" => DATA <= x"26";
when x"5D4" => DATA <= x"F2";
when x"5D5" => DATA <= x"B6";
when x"5D6" => DATA <= x"FE";
when x"5D7" => DATA <= x"E4";
when x"5D8" => DATA <= x"48";
when x"5D9" => DATA <= x"2A";
when x"5DA" => DATA <= x"FA";
when x"5DB" => DATA <= x"B7";
when x"5DC" => DATA <= x"FE";
when x"5DD" => DATA <= x"E5";
when x"5DE" => DATA <= x"30";
when x"5DF" => DATA <= x"89";
when x"5E0" => DATA <= x"01";
when x"5E1" => DATA <= x"00";
when x"5E2" => DATA <= x"20";
when x"5E3" => DATA <= x"38";
when x"5E4" => DATA <= x"13";
when x"5E5" => DATA <= x"B6";
when x"5E6" => DATA <= x"FE";
when x"5E7" => DATA <= x"E5";
when x"5E8" => DATA <= x"F6";
when x"5E9" => DATA <= x"FE";
when x"5EA" => DATA <= x"E5";
when x"5EB" => DATA <= x"ED";
when x"5EC" => DATA <= x"81";
when x"5ED" => DATA <= x"B6";
when x"5EE" => DATA <= x"FF";
when x"5EF" => DATA <= x"94";
when x"5F0" => DATA <= x"26";
when x"5F1" => DATA <= x"F2";
when x"5F2" => DATA <= x"20";
when x"5F3" => DATA <= x"28";
when x"5F4" => DATA <= x"13";
when x"5F5" => DATA <= x"EC";
when x"5F6" => DATA <= x"81";
when x"5F7" => DATA <= x"B7";
when x"5F8" => DATA <= x"FE";
when x"5F9" => DATA <= x"E5";
when x"5FA" => DATA <= x"F7";
when x"5FB" => DATA <= x"FE";
when x"5FC" => DATA <= x"E5";
when x"5FD" => DATA <= x"B6";
when x"5FE" => DATA <= x"FF";
when x"5FF" => DATA <= x"94";
when x"600" => DATA <= x"26";
when x"601" => DATA <= x"F2";
when x"602" => DATA <= x"20";
when x"603" => DATA <= x"18";
when x"604" => DATA <= x"13";
when x"605" => DATA <= x"B6";
when x"606" => DATA <= x"FE";
when x"607" => DATA <= x"E5";
when x"608" => DATA <= x"A7";
when x"609" => DATA <= x"80";
when x"60A" => DATA <= x"B6";
when x"60B" => DATA <= x"FF";
when x"60C" => DATA <= x"94";
when x"60D" => DATA <= x"26";
when x"60E" => DATA <= x"F5";
when x"60F" => DATA <= x"20";
when x"610" => DATA <= x"0B";
when x"611" => DATA <= x"13";
when x"612" => DATA <= x"A6";
when x"613" => DATA <= x"80";
when x"614" => DATA <= x"B7";
when x"615" => DATA <= x"FE";
when x"616" => DATA <= x"E5";
when x"617" => DATA <= x"B6";
when x"618" => DATA <= x"FF";
when x"619" => DATA <= x"94";
when x"61A" => DATA <= x"26";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"BF";
when x"61D" => DATA <= x"FF";
when x"61E" => DATA <= x"8E";
when x"61F" => DATA <= x"35";
when x"620" => DATA <= x"16";
when x"621" => DATA <= x"3B";
when x"622" => DATA <= x"32";
when x"623" => DATA <= x"6A";
when x"624" => DATA <= x"35";
when x"625" => DATA <= x"10";
when x"626" => DATA <= x"BF";
when x"627" => DATA <= x"FF";
when x"628" => DATA <= x"82";
when x"629" => DATA <= x"1C";
when x"62A" => DATA <= x"00";
when x"62B" => DATA <= x"6E";
when x"62C" => DATA <= x"9F";
when x"62D" => DATA <= x"FF";
when x"62E" => DATA <= x"FA";
when x"62F" => DATA <= x"FF";
when x"630" => DATA <= x"FF";
when x"631" => DATA <= x"FF";
when x"632" => DATA <= x"FF";
when x"633" => DATA <= x"FF";
when x"634" => DATA <= x"FF";
when x"635" => DATA <= x"FF";
when x"636" => DATA <= x"FF";
when x"637" => DATA <= x"FF";
when x"638" => DATA <= x"FF";
when x"639" => DATA <= x"FF";
when x"63A" => DATA <= x"FF";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FF";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"FF";
when x"644" => DATA <= x"FF";
when x"645" => DATA <= x"FF";
when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
when x"648" => DATA <= x"FF";
when x"649" => DATA <= x"FF";
when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
when x"651" => DATA <= x"FF";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"FF";
when x"654" => DATA <= x"FF";
when x"655" => DATA <= x"FF";
when x"656" => DATA <= x"FF";
when x"657" => DATA <= x"FF";
when x"658" => DATA <= x"FF";
when x"659" => DATA <= x"FF";
when x"65A" => DATA <= x"FF";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"FF";
when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
when x"668" => DATA <= x"FF";
when x"669" => DATA <= x"FF";
when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
when x"66D" => DATA <= x"FF";
when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
when x"670" => DATA <= x"FF";
when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
when x"673" => DATA <= x"FF";
when x"674" => DATA <= x"FF";
when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
when x"678" => DATA <= x"FF";
when x"679" => DATA <= x"FF";
when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
when x"681" => DATA <= x"FF";
when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"21";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"21";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"21";
when x"6F6" => DATA <= x"FC";
when x"6F7" => DATA <= x"EC";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"21";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"22";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"21";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"B0";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"00";
when x"78D" => DATA <= x"00";
when x"78E" => DATA <= x"00";
when x"78F" => DATA <= x"00";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"FF";
when x"793" => DATA <= x"00";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"86";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"FA";
when x"79D" => DATA <= x"86";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FA";
when x"7A0" => DATA <= x"86";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"3C";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"86";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"71";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"11";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"05";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"21";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2C";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"86";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"71";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"24";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D2";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"86";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"33";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"86";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"86";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"33";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"83";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"1D";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FB";
when x"7DC" => DATA <= x"EA";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"53";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"AC";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"CC";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"33";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"BD";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"76";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"86";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
clk : in std_logic;
rst : in std_logic;
opcode : in std_logic_vector(15 downto 0);
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end alu;
architecture mux of alu is
signal ci : std_logic;
signal co : std_logic;
signal mux1, mux2: std_logic_vector(7 downto 0);
begin
process(a, b, ci, mux1, mux2)
variable sel : unsigned(2 downto 0);
begin
sel := a & b & ci;
y <= mux1(to_integer(sel));
co <= mux2(to_integer(sel));
end process;
process(clk, rst)
begin
if(rst = '0') then
ci <= '0';
mux1 <= (others => '0');
mux2 <= (others => '0');
elsif(rising_edge(clk)) then
ci <= co;
mux1 <= opcode(15 downto 8);
mux2 <= opcode(7 downto 0);
end if;
end process;
end mux;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:37)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_alap_entity;
ARCHITECTURE arf_alap_description OF arf_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := register4 + register3;
WHEN "00000011" =>
register1 := register1 + 6;
register2 := register2 + 8;
WHEN "00000100" =>
register3 := register1 * 10;
register4 := register2 * 12;
register1 := register1 * 14;
register2 := register2 * 16;
WHEN "00000101" =>
register3 := register4 + register3;
register1 := register2 + register1;
WHEN "00000110" =>
register2 := register3 * 18;
register4 := register1 * 20;
register5 := input5 * 21;
register6 := input6 * 22;
register3 := register3 * 24;
register1 := register1 * 26;
register7 := input7 * 27;
register8 := input8 * 28;
WHEN "00000111" =>
register2 := register4 + register2;
register4 := register6 + register5;
register1 := register1 + register3;
register3 := register8 + register7;
WHEN "00001000" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_alap_description; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:32:03 10/01/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/clockManagerTB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UARTClockManager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY clockManagerTB IS
END clockManagerTB;
ARCHITECTURE behavior OF clockManagerTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UARTClockManager
PORT(
CLK_IN1 : IN std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK_IN1 : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
-- Clock period definitions
constant CLK_IN1_period : time := 31.25 ns;
constant CLK_OUT1_period : time := 10 ns;
constant CLK_OUT2_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UARTClockManager PORT MAP (
CLK_IN1 => CLK_IN1,
CLK_OUT1 => CLK_OUT1,
CLK_OUT2 => CLK_OUT2,
RESET => RESET
);
-- Clock process definitions
CLK_IN1_process :process
begin
CLK_IN1 <= '0';
wait for CLK_IN1_period/2;
CLK_IN1 <= '1';
wait for CLK_IN1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_IN1_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHist:1.0
-- IP Revision: 1606202043
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHist_0_1 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_doHist_0_1;
ARCHITECTURE design_1_doHist_0_1_arch OF design_1_doHist_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHist_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT doHist IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT doHist;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHist_0_1_arch: ARCHITECTURE IS "doHist,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHist_0_1_arch : ARCHITECTURE IS "design_1_doHist_0_1,doHist,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF histo_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF histo_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF histo_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF histo_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF histo_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF histo_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF histo_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DOUT";
BEGIN
U0 : doHist
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 4,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
histo_Clk_A => histo_Clk_A,
histo_Rst_A => histo_Rst_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Addr_A => histo_Addr_A,
histo_Din_A => histo_Din_A,
histo_Dout_A => histo_Dout_A
);
END design_1_doHist_0_1_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (C) 2009-2013, Aeroflex Gaisler AB
-------------------------------------------------------------------------------
-- Entity: spw_2x_lvttl_pads
-- File: spw_2x_lvttl_pads.vhd
-- Author: Marko Isomaki, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: pads for SpW signals in router ASIC LVTTL ports
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.config.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.conv_std_logic;
entity spw_lvttl_pads is
generic (
padtech : integer := 0;
oepol : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 4;
slew : integer := 0;
input_type : integer := 0
);
port (
---------------------------------------------------------------------------
-- Signals going off-chip
---------------------------------------------------------------------------
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
---------------------------------------------------------------------------
-- Signals to core
---------------------------------------------------------------------------
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1)
);
end entity;
architecture rtl of spw_lvttl_pads is
begin
------------------------------------------------------------------------------
-- SpW port pads
------------------------------------------------------------------------------
spw_pads : for i in 0 to CFG_SPW_NUM-1 generate
spw_pad_input: if input_type <= 3 generate
spw_rxd_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxd(i),
o => lspw_rxd(i));
spw_rxs_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxs(i),
o => lspw_rxs(i));
end generate;
spw_no_pad_input: if input_type >= 4 generate
lspw_rxd(i) <= spw_rxd(i);
lspw_rxs(i) <= spw_rxs(i);
end generate;
spw_txd_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txd(i),
i => lspw_txd(i));
spw_txs_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txs(i),
i => lspw_txs(i));
end generate;
end;
|
-- $Id: simclk.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simclk - sim
-- Description: Clock generator for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP now optional port
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-10 72 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity simclk is -- test bench clock generator
generic (
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclk;
architecture sim of simclk is
begin
proc_clk: process
constant clock_halfperiod : Delay_length := PERIOD/2;
begin
CLK <= '0';
wait for OFFSET;
clk_loop: loop
CLK <= '1';
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
wait; -- endless wait, simulator will stop
end process proc_clk;
end sim;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_noise
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating noise
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_noise is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NOISE_TPYE : integer := 0
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_noise;
architecture Behavioral of hwt_noise is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component PRBS is
generic(
FPGA_FREQUENCY : integer := 100_000_000
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end component PRBS;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_noise : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_noise : std_logic_vector(0 to 31); -- noise to local ram
signal i_RAMData_noise : std_logic_vector(0 to 31); -- local ram to noise
signal o_RAMWE_noise : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal state_inner_process : std_logic;
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal noise_ce : std_logic; -- noise clock enable (like a start/stop signal)
signal noise_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NOISE_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NOISE_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_noise <= std_logic_vector(noise_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
NOISE_INST : PRBS
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ
)
port map(
clk => clk,
rst => rst,
ce => noise_ce,
signed(rand) => noise_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_noise = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_noise))) := o_RAMData_noise;
--else -- else not needed, because noise is not consuming any samples
-- i_RAMData_noise <= local_ram(conv_integer(unsigned(o_RAMAddr_noise)));
end if;
end if;
end process;
NOISE_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
noise_ce <= '0';
o_RAMWE_noise <= '0';
done := False;
elsif rising_edge(clk) then
noise_ce <= '0';
o_RAMWE_noise <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
when STATE_INIT =>
-- Init not used
state <= STATE_WAITING;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NOISE_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_PROCESS;
elsif osif_ctrl_signal = NOISE_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_noise <= '1';
noise_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_noise <= std_logic_vector(unsigned(o_RAMAddr_noise) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_noise <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MIPS_Register_TB is
end MIPS_Register_TB;
architecture Behavioral of MIPS_Register_TB is
component Register_File is
Port (
i_Clk : in std_logic;
i_Rst : in std_logic;
i_regwrite : in std_logic;
i_rt : in std_logic_vector(4 downto 0);
i_rs : in std_logic_vector(4 downto 0);
i_rd : in std_logic_vector(4 downto 0);
i_rd_data : in std_logic_vector(31 downto 0);
o_rt_data : out std_logic_vector(31 downto 0);
o_rs_data : out std_logic_vector(31 downto 0)
);
end component;
signal s_i_Clk : std_logic := '0';
signal s_i_rt : std_logic_vector(4 downto 0);
signal s_i_rs : std_logic_vector(4 downto 0);
signal s_i_rd_data : std_logic_vector(31 downto 0);
signal s_i_rd : std_logic_vector(4 downto 0);
signal s_i_RW : std_logic;
signal s_i_Rst : std_logic;
signal s_o_rt_data : std_logic_vector(31 downto 0);
signal s_o_rs_data : std_logic_vector(31 downto 0);
constant clk_period : time := 10 ns;
begin
UUT: Register_File
port map(
i_Clk => s_i_Clk,
i_Rst => s_i_Rst,
i_regwrite => s_i_RW,
i_rt => s_i_rt,
i_rs => s_i_rs,
i_rd => s_i_rd,
i_rd_data => s_i_rd_data,
o_rt_data => s_o_rt_data,
o_rs_data => s_o_rs_data
);
s_i_Clk <= not s_i_Clk after 5 ns;
Tests: process
begin
s_i_rt <= "00110";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '1';
wait for 5 ns;
s_i_rt <= "00111";
s_i_rs <= "00111";
s_i_rd_data <= X"22223333";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00111";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00110";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00110";
s_i_rd_data <= X"12345678";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00110";
s_i_rd_data <= X"FFFFEEEE";
s_i_rd <= "00101";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00101";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00101";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00111";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00101";
s_i_rd_data <= X"FEEDBEEF";
s_i_rd <= "01100";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00111";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '1';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00101";
s_i_rd_data <= X"FEEDBEEF";
s_i_rd <= "01100";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
wait;
end process;
end Behavioral;
|
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00457
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (9)
-- 7.2.4 (10)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00457(ARCH00457)
-- ENT00457_Test_Bench(ARCH00457_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES ;
use WORK.ARITHMETIC.ALL ;
entity ENT00457 is
generic (
i_phys_1 : time := c_time_1 ;
i_phys_2 : time := c_time_2 ;
i_t_phys_1 : t_phys := c_t_phys_1 ;
i_t_phys_2 : t_phys := c_t_phys_2 ;
i_st_phys_1 : st_phys := c_st_phys_1 ;
i_st_phys_2 : st_phys := c_st_phys_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00457 ;
architecture ARCH00457 of ENT00457 is
constant c2_phys_1 : integer :=
(i_phys_1 + 5 ns) / i_phys_1 + i_phys_1 / i_phys_2 +
i_phys_2 / i_phys_1 + (4 * i_phys_2) / i_phys_2 ;
constant c2_t_phys_1 : integer :=
(i_t_phys_1 + i_t_phys_1) / i_t_phys_1 + i_t_phys_1 / i_t_phys_2 +
i_t_phys_2 / i_t_phys_1 + (-6 * i_t_phys_2) / i_t_phys_2 ;
constant c2_st_phys_1 : integer :=
(i_t_phys_1) / i_st_phys_1 + i_st_phys_1 / i_t_phys_2 +
i_t_phys_2 / i_t_phys_1 + (5 * i_st_phys_2) / i_t_phys_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_phys_1 : time := i_phys_1 ;
variable v2_phys_1 : integer ;
variable v_phys_2 : time := i_phys_2 ;
variable v_t_phys_1 : t_phys := i_t_phys_1 ;
variable v2_t_phys_1 : integer ;
variable v_t_phys_2 : t_phys := i_t_phys_2 ;
variable v_st_phys_1 : st_phys := i_st_phys_1 ;
variable v2_st_phys_1 : integer ;
variable v_st_phys_2 : st_phys := i_st_phys_2 ;
--
begin
-- static expression
case bool is
when (
(c_time_1 + 5 ns) / c_time_1 + c_time_1 / c_time_2 +
c_time_2 / c_time_1 + (4 * c_time_2) / c_time_2
= 100010 and --xx and
(c_t_phys_1 + c_t_phys_1) / c_t_phys_1 + c_t_phys_1 / c_t_phys_2 +
c_t_phys_2 / c_t_phys_1 + (-6 * c_t_phys_2) / c_t_phys_2
= -170 and --xx and
(c_t_phys_1) / c_st_phys_1 + c_st_phys_1 / c_t_phys_2 +
c_t_phys_2 / c_t_phys_1 + (5 * c_st_phys_2) / c_t_phys_2
= 165 --xx
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_phys_1 = 100010 and --xx and
c2_t_phys_1 = -170 and --xx and
c2_st_phys_1 = 165 ; --xx ;
-- dynamic expression
v2_phys_1 :=
(v_phys_1 + 5 ns) / v_phys_1 + v_phys_1 / v_phys_2 +
v_phys_2 / v_phys_1 + (4 * v_phys_2) / c_time_2 ;
v2_t_phys_1 :=
(v_t_phys_1 + v_t_phys_1) / v_t_phys_1 + i_t_phys_1 / v_t_phys_2 +
v_t_phys_2 / i_t_phys_1 + (-6 * v_t_phys_2) / v_t_phys_2 ;
v2_st_phys_1 :=
(i_t_phys_1) / v_st_phys_1 + v_st_phys_1 / i_t_phys_2 +
v_t_phys_2 / v_t_phys_1 + (5 * v_st_phys_2) / v_t_phys_2 ;
dyn_correct := v2_phys_1 = 100010 and --xx and
v2_t_phys_1 = -170 and --xx and
v2_st_phys_1 = 165 ; --xx ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00457 ;
use WORK.STANDARD_TYPES.ALL ;
entity ENT00457_Test_Bench is
end ENT00457_Test_Bench ;
architecture ARCH00457_Test_Bench of ENT00457_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00457 ( ARCH00457 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00457" ,
"* predefined for phycial types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00457_Test_Bench ;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_OTHER.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_OTHER IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END FIFO_TO_OTHER;
ARCHITECTURE SYN OF fifo_to_other IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
wrusedw <= sub_wire1(9 DOWNTO 0);
rdusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=5,MAXIMUM_DEPTH=512",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 8,
lpm_widthu => 10,
lpm_widthu_r => 9,
lpm_width_r => 16,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,,MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_OTHER.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_OTHER IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END FIFO_TO_OTHER;
ARCHITECTURE SYN OF fifo_to_other IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
wrusedw <= sub_wire1(9 DOWNTO 0);
rdusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=5,MAXIMUM_DEPTH=512",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 8,
lpm_widthu => 10,
lpm_widthu_r => 9,
lpm_width_r => 16,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,,MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity enable_generator is
generic(CYCLE_COUNT: integer := 10; PASSIVE_CYCLES: integer := 0; ACTIVE_CYCLES: integer := 0);
port(
rst : in std_logic := '0';
clk: in std_logic := '0';
enable_in: in std_logic := '0';
enable_out : out std_logic := '0'
);
end entity;
architecture enable_generator_arq of enable_generator is
signal passive : integer := 0;
signal active : integer := 0;
signal counted : integer := 0;
begin
process(clk, rst)
variable passive_count : integer := 0;
variable active_count : integer := 0;
variable counted_cycles : integer := 0;
begin
if(rst = '1') then
passive_count := 0;
active_count := 0;
counted_cycles := 0;
enable_out <= '0';
elsif(enable_in = '1') then
if(rising_edge(clk)) then
if(counted_cycles = CYCLE_COUNT - 1) then
if(passive_count = PASSIVE_CYCLES - 1) then
if(active_count = ACTIVE_CYCLES) then
active_count := 0;
passive_count := 0;
else
active_count := active_count + 1;
enable_out <= '1';
end if;
else
passive_count := passive_count + 1;
enable_out <= '0';
end if;
counted_cycles := 0;
else
counted_cycles := counted_cycles + 1;
enable_out <= '0';
end if;
end if;
passive <= passive_count;
active <= active_count;
counted <= counted_cycles;
end if;
end process;
end enable_generator_arq;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLMULT_SDNF1_3_block5.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block5
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_10_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19
dout_10_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19
dout_12_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19
dout_12_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_13_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block5;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block5 IS
-- Component Declarations
COMPONENT Complex3Multiply_block8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din2_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block8
USE ENTITY work.Complex3Multiply_block8(rtl);
-- Signals
SIGNAL dout_10_re_signed : signed(18 DOWNTO 0); -- sfix19
SIGNAL din_re : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly2 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly3 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly4 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly5 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly6 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly7 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly8 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re_dly9 : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_10_im_signed : signed(18 DOWNTO 0); -- sfix19
SIGNAL din_im : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly2 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly4 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly5 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly6 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly7 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly8 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly9 : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_12_re_signed : signed(18 DOWNTO 0); -- sfix19
SIGNAL din_re_1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re_dly1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re_dly2 : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_12_im_signed : signed(18 DOWNTO 0); -- sfix19
SIGNAL din_im_1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly2 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re_dly3 : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly3 : signed(19 DOWNTO 0); -- sfix20
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_14_re_tmp : std_logic_vector(19 DOWNTO 0); -- ufix20
SIGNAL twdlXdin_14_im_tmp : std_logic_vector(19 DOWNTO 0); -- ufix20
BEGIN
u_MUL3_2 : Complex3Multiply_block8
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix20
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix20
di2_vld_dly3 => di2_vld_dly3,
twdl_3_14_re => twdl_3_14_re, -- sfix17_En15
twdl_3_14_im => twdl_3_14_im, -- sfix17_En15
softReset => softReset,
twdlXdin_14_re => twdlXdin_14_re_tmp, -- sfix20
twdlXdin_14_im => twdlXdin_14_im_tmp, -- sfix20
twdlXdin2_vld => twdlXdin_13_vld
);
dout_10_re_signed <= signed(dout_10_re);
din_re <= resize(dout_10_re_signed, 20);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_13_re <= std_logic_vector(din1_re_dly9);
dout_10_im_signed <= signed(dout_10_im);
din_im <= resize(dout_10_im_signed, 20);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_13_im <= std_logic_vector(din1_im_dly9);
dout_12_re_signed <= signed(dout_12_re);
din_re_1 <= resize(dout_12_re_signed, 20);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_12_im_signed <= signed(dout_12_im);
din_im_1 <= resize(dout_12_im_signed, 20);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_14_re <= twdlXdin_14_re_tmp;
twdlXdin_14_im <= twdlXdin_14_im_tmp;
END rtl;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_topentity_0 is
port(i : in packetprocessor_types.tup2;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
case_alt : out packetprocessor_types.tup3);
end;
architecture structural of packetprocessor_topentity_0 is
signal case_scrut : packetprocessor_types.tup3;
signal ww1 : std_logic_vector(8 downto 0);
signal ww2 : boolean;
signal ww3 : boolean;
signal x : std_logic_vector(11 downto 0);
signal y : boolean;
begin
packetprocessor_packetprocessor_case_scrut : entity packetprocessor_packetprocessor
port map
(result => case_scrut
,system1000 => system1000
,system1000_rstn => system1000_rstn
,memop => x
,en => y);
case_alt <= (tup3_sel0 => ww1
,tup3_sel1 => ww2
,tup3_sel2 => ww3);
ww1 <= case_scrut.tup3_sel0;
ww2 <= case_scrut.tup3_sel1;
ww3 <= case_scrut.tup3_sel2;
x <= i.tup2_sel0;
y <= i.tup2_sel1;
end;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_topentity_0 is
port(i : in packetprocessor_types.tup2;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
case_alt : out packetprocessor_types.tup3);
end;
architecture structural of packetprocessor_topentity_0 is
signal case_scrut : packetprocessor_types.tup3;
signal ww1 : std_logic_vector(8 downto 0);
signal ww2 : boolean;
signal ww3 : boolean;
signal x : std_logic_vector(11 downto 0);
signal y : boolean;
begin
packetprocessor_packetprocessor_case_scrut : entity packetprocessor_packetprocessor
port map
(result => case_scrut
,system1000 => system1000
,system1000_rstn => system1000_rstn
,memop => x
,en => y);
case_alt <= (tup3_sel0 => ww1
,tup3_sel1 => ww2
,tup3_sel2 => ww3);
ww1 <= case_scrut.tup3_sel0;
ww2 <= case_scrut.tup3_sel1;
ww3 <= case_scrut.tup3_sel2;
x <= i.tup2_sel0;
y <= i.tup2_sel1;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity enable_generator_tb is
end entity;
architecture enable_generator_tb_arq of enable_generator_tb is
signal enable_in : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enable_out : std_logic := '0';
component enable_generator is
generic(CYCLE_COUNT: integer := 10; PASSIVE_CYCLES: integer := 0; ACTIVE_CYCLES: integer := 0);
port(
rst : in std_logic := '0';
clk: in std_logic := '0';
enable_in: in std_logic := '0';
enable_out : out std_logic := '0'
);
end component;
begin
enable_generator_0 : enable_generator
generic map(CYCLE_COUNT => 2, PASSIVE_CYCLES => 3, ACTIVE_CYCLES => 2)
port map(
rst => rst,
enable_in => enable_in,
clk => clk,
enable_out => enable_out
);
process
begin
enable_in <= '1';
for i in 0 to 100 loop
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/21/2015 05:22:39 PM
-- Design Name:
-- Module Name: RippleCarryAdder16Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RippleCarryAdder16Bit is
Port
(
InputA : in BIT_VECTOR(15 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(15 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end RippleCarryAdder16Bit;
architecture Behavioral of RippleCarryAdder16Bit is
component FullAdder is
Port
(
A : in BIT; -- 1st bit to sum up
B : in BIT; -- 2nd bit to sum up
Cin : in BIT; -- Carry-in for sum up
S : out BIT; -- Sum of both bits
Cout : out BIT -- Carry-out for sum up
);
end component FullAdder;
signal CarryOut0 : BIT;
signal CarryOut1 : BIT;
signal CarryOut2 : BIT;
signal CarryOut3 : BIT;
signal CarryOut4 : BIT;
signal CarryOut5 : BIT;
signal CarryOut6 : BIT;
signal CarryOut7 : BIT;
signal CarryOut8 : BIT;
signal CarryOut9 : BIT;
signal CarryOut10 : BIT;
signal CarryOut11 : BIT;
signal CarryOut12 : BIT;
signal CarryOut13 : BIT;
signal CarryOut14 : BIT;
signal CarryOut15 : BIT;
begin
adder0: FullAdder port map (InputA(0), InputB(0), Cin, Output(0), CarryOut0);
adder1: FullAdder port map (InputA(1), InputB(1), CarryOut0, Output(1), CarryOut1);
adder2: FullAdder port map (InputA(2), InputB(2), CarryOut1, Output(2), CarryOut2);
adder3: FullAdder port map (InputA(3), InputB(3), CarryOut2, Output(3), CarryOut3);
adder4: FullAdder port map (InputA(4), InputB(4), CarryOut3, Output(4), CarryOut4);
adder5: FullAdder port map (InputA(5), InputB(5), CarryOut4, Output(5), CarryOut5);
adder6: FullAdder port map (InputA(6), InputB(6), CarryOut5, Output(6), CarryOut6);
adder7: FullAdder port map (InputA(7), InputB(7), CarryOut6, Output(7), CarryOut7);
adder8: FullAdder port map (InputA(8), InputB(8), CarryOut7, Output(8), CarryOut8);
adder9: FullAdder port map (InputA(9), InputB(9), CarryOut8, Output(9), CarryOut9);
adder10: FullAdder port map (InputA(10), InputB(10), CarryOut9, Output(10), CarryOut10);
adder11: FullAdder port map (InputA(11), InputB(11), CarryOut10, Output(11), CarryOut11);
adder12: FullAdder port map (InputA(12), InputB(12), CarryOut11, Output(12), CarryOut12);
adder13: FullAdder port map (InputA(13), InputB(13), CarryOut12, Output(13), CarryOut13);
adder14: FullAdder port map (InputA(14), InputB(14), CarryOut13, Output(14), CarryOut14);
adder15: FullAdder port map (InputA(15), InputB(15), CarryOut14, Output(15), CarryOut15);
Cout <= CarryOut15;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
I : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
Q2 : out std_logic_vector(3 downto 0)
);
end entity;
architecture arch of barrel is
signal Qt, Qt2 : std_logic_vector(3 downto 0):="0000";
begin
process(clk, se)
begin
if rising_edge(clk) then
if (se(0)='0' and se(1)='0') then
Qt<=I;
Qt2<=I;
elsif (se(0)='1' and se(1)='0') then
Qt<=I(3 downto 1)&"0";
Qt2<=I(3)&I(3 downto 1);
elsif (se(0)='0' and se(1)='1') then
Qt<=I(3 downto 2)&"00";
Qt2<=I(3)&I(3)&I(3 downto 2);
else
Qt<=I(3)&"000";
Qt2<=(others =>I(3));
end if;
end if;
end process;
Q<=Qt;
Q2<=Qt2;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_buttons is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- push buttons
buttons : in std_logic_vector(3 downto 0)
);
end mmio_buttons;
architecture mmio of mmio_buttons is
constant reading : std_logic := '0';
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk)
begin
if rising_edge(clk) and en = '1' and size /= "00" then
case wr is
when reading => zeroextend(data_out, buttons);
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc1_tb_top;
architecture arc of memc1_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- special, incidental, or consequential loss or damage
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-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
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-- applications related to the deployment of airbags, or any
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-- PART OF THIS FILE AT ALL TIMES.
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--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc1_tb_top;
architecture arc of memc1_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
COUNT : in STD_LOGIC_VECTOR (3 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (15 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
|
library verilog;
use verilog.vl_types.all;
entity projetoPessoal is
port(
SW : in vl_logic_vector(3 downto 0);
LEDG : out vl_logic_vector(1 downto 0);
LEDR : out vl_logic_vector(1 downto 0);
HEX0 : out vl_logic_vector(6 downto 0);
CLK : in vl_logic
);
end projetoPessoal;
|
BuzzerFa_inst : BuzzerFa PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2233.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02233ent IS
END c07s02b06x00p01n01i02233ent;
ARCHITECTURE c07s02b06x00p01n01i02233arch OF c07s02b06x00p01n01i02233ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable DISTV : DISTANCE;
variable k : integer;
BEGIN
k := DISTV mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02233 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02233arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2233.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02233ent IS
END c07s02b06x00p01n01i02233ent;
ARCHITECTURE c07s02b06x00p01n01i02233arch OF c07s02b06x00p01n01i02233ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable DISTV : DISTANCE;
variable k : integer;
BEGIN
k := DISTV mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02233 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02233arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2233.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02233ent IS
END c07s02b06x00p01n01i02233ent;
ARCHITECTURE c07s02b06x00p01n01i02233arch OF c07s02b06x00p01n01i02233ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable DISTV : DISTANCE;
variable k : integer;
BEGIN
k := DISTV mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02233 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02233arch;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: VHDL Package - ReconOS
--
-- project: ReconOS
-- author: Enno Lübbers, University of Paderborn
-- Andreas Agne, University of Paderborn
-- Christoph Rüthing, University of Paderborn
-- description: The entire ReconOS package with type definitions and
-- hardware OS services in VHDL
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reconos_pkg is
-- == Constant definitions ============================================
--
-- General constants
--
-- C_OSIF_DATA_WIDTH - width of the osif
-- C_MEMIF_DATA_WIDTH - width of the memif
--
-- C_MEMIF_CHUNK_WORDS - size of one memory request in words
-- (a request might be split up to meet this)
-- C_MEMIF_CHUNK_BYTES - chunk size in bytes
-- C_MEMIF_CHUNK_WIDTH - width of chunk (log2 C_MEMIF_CHUNK_BYTES)
-- C_MEMIF_LENGTH_WIDTH - width of the length in command word
-- C_MEMIF_OP_WIDTH - width of the operation in command word
--
constant C_OSIF_DATA_WIDTH : integer := 32;
constant C_MEMIF_DATA_WIDTH : integer := 32;
constant C_MEMIF_CHUNK_WORDS : integer := 64;
constant C_MEMIF_CHUNK_BYTES : integer := C_MEMIF_CHUNK_WORDS * 4;
constant C_MEMIF_CHUNK_WIDTH : integer := 8;
constant C_MEMIF_LENGTH_WIDTH : integer := 24;
constant C_MEMIF_OP_WIDTH : integer := 8;
--
-- "Constants" for easier handling of ranges
--
-- C_MEMIF_LENGTH_RANGE - range of the length in command word
-- C_MEMIF_OP_RANGE - range of the operation in command word
-- C_MEMIF_CHUNK_RANGE - range of chunk offset
--
subtype C_MEMIF_LENGTH_RANGE is natural range C_MEMIF_LENGTH_WIDTH - 1 downto 0;
subtype C_MEMIF_OP_RANGE is natural range C_MEMIF_DATA_WIDTH - 1 downto C_MEMIF_DATA_WIDTH - C_MEMIF_OP_WIDTH;
subtype C_MEMIF_CHUNK_RANGE is natural range C_MEMIF_CHUNK_WIDTH - 1 downto 0;
--
-- Definition of osif commands
--
-- self-describing
--
constant OSIF_CMD_THREAD_GET_INIT_DATA : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000A0";
constant OSIF_CMD_THREAD_GET_STATE_ADDR : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000A1";
constant OSIF_CMD_THREAD_EXIT : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000A2";
constant OSIF_CMD_THREAD_YIELD : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000A3";
constant OSIF_CMD_THREAD_CLEAR_SIGNAL : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000A4";
constant OSIF_CMD_SEM_POST : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000B0";
constant OSIF_CMD_SEM_WAIT : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000B1";
constant OSIF_CMD_MUTEX_LOCK : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000C0";
constant OSIF_CMD_MUTEX_UNLOCK : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000C1";
constant OSIF_CMD_MUTEX_TRYLOCK : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000C2";
constant OSIF_CMD_COND_WAIT : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000D0";
constant OSIF_CMD_COND_SIGNAL : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000D1";
constant OSIF_CMD_COND_BROADCAST : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000D2";
constant OSIF_CMD_MBOX_GET : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000F0";
constant OSIF_CMD_MBOX_PUT : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000F1";
constant OSIF_CMD_MBOX_TRYGET : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000F2";
constant OSIF_CMD_MBOX_TRYPUT : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000F3";
constant OSIF_CMD_MASK : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000FF";
constant OSIF_CMD_YIELD_MASK : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"80000000";
constant OSIF_SIGNAL_THREAD_START : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"01000000";
constant OSIF_SIGNAL_THREAD_RESUME : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"01000001";
constant OSIF_INTERRUPTED : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0) := x"000000FF";
--
-- Definition of memif commands
--
-- self-describing
--
constant MEMIF_CMD_READ : std_logic_vector(C_MEMIF_OP_WIDTH - 1 downto 0) := x"00";
constant MEMIF_CMD_WRITE : std_logic_vector(C_MEMIF_OP_WIDTH - 1 downto 0) := x"F0";
-- == Type definitions ================================================
--
-- Type definitions of i_osif_t and o_osif_t
--
-- sw2hw_/hw2sw_ - fifo signals
--
-- step - internal state of the osif
-- void - void bit free to use
--
type i_osif_t is record
sw2hw_data : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
sw2hw_empty : std_logic;
hw2sw_full : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
type o_osif_t is record
sw2hw_re : std_logic;
hw2sw_data : std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
hw2sw_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
--
-- Type definitions of i_memif_t and o_memif_t
--
-- mem2hwt_/hwt2mem_ - fifo signals
--
-- step - internal state of the osif
--
type i_memif_t is record
mem2hwt_data : std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
mem2hwt_empty : std_logic;
hwt2mem_full : std_logic;
step : integer range 0 to 15;
end record;
type o_memif_t is record
mem2hwt_re : std_logic;
hwt2mem_data : std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
hwt2mem_we : std_logic;
step : integer range 0 to 15;
end record;
--
-- Type definitions of i_ram_t and o_ram_t
--
-- ram_ - ram signals
--
-- count - byte counter of written bytes
-- mem_addr - remote address of main memory
--
type i_ram_t is record
ram_addr : unsigned(31 downto 0);
ram_data : std_logic_vector(31 downto 0);
remm : unsigned(31 downto 0);
mem_addr : unsigned(31 downto 0);
end record;
type o_ram_t is record
ram_addr : unsigned(31 downto 0);
ram_data : std_logic_vector(31 downto 0);
ram_we : std_logic;
remm : unsigned(31 downto 0);
mem_addr : unsigned(31 downto 0);
end record;
-- == Reconos functions ===============================================
--
-- Assigns signals to the osif record. This function must be called
-- asynchronously in the main entity including the os-fsm.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t_record
-- sw2hw_data - OSIF_FIFO_Sw2Hw_Data
-- sw2hw_empty - OSIF_FIFO_Sw2Hw_Empty
-- sw2hw_re - OSIF_FIFO_Sw2Hw_RE
-- hw2sw_data - OSIF_FIFO_Hw2Sw_Data
-- hw2sw_full - OSIF_FIFO_Hw2Sw_Full
-- hw2sw_we - OSIF_FIFO_Hw2Sw_WE
--
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal sw2hw_empty : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal hw2sw_full : in std_logic;
signal hw2sw_we : out std_logic
);
--
-- Resets the osif signals to a default state. This function should be called
-- on reset of the os-fsm.
--
-- o_osif - o_osif_t record
--
procedure osif_reset (
signal o_osif : out o_osif_t
);
--
-- Assigns signals to the memif record. This function must be called
-- asynchronously in the main entity including the os-fsm.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- mem2hwt_data - MEMIF_FIFO_Mem2Hwt_Data
-- mem2hwt_empty - MEMIF_FIFO_Mem2Hwt_Empty
-- mem2hwt_re - MEMIF_FIFO_Mem2Hwt_RE
-- hwt2mem_data - MEMIF_FIFO_Hwt2Mem_Data
-- hwt2mem_full - MEMIF_FIFO_Hwt2Mem_Full
-- hwt2mem_we - MEMIF_FIFO_Hwt2Mem_WE
--
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal mem2hwt_empty : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal hwt2mem_full : in std_logic;
signal hwt2mem_we : out std_logic
);
--
-- Resets the memif signals to a default state. This function should be called
-- on reset of the os-fsm.
--
-- o_memif - o_memif_t record
--
procedure memif_reset (
signal o_memif : out o_memif_t
);
--
-- Assigns signals to the memif record. This function must be called
-- asynchronously in the main entity including the os-fsm.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- ram_addr - address signal of the local ram
-- ram_i_data - input data signal of the local ram
-- ram_o_data - output data signal of the local ram
-- ram_we - write enable signal of the local ram
--
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal ram_addr : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_i_data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_o_data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_we : out std_logic
);
--
-- Resets the RAM signals to a default state. This function should be called
-- on reset of the os-fsm.
--
-- o_ram - o_ram_t record
--
procedure ram_reset (
signal o_ram : out o_ram_t
);
--
-- Reads a single word from the osif.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- word - word read from the osif
-- done - indicates when read finished
--
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Writes a single word into the osif
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- word - word to write int the osif
-- done - indicates when write finished
--
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with no arguments and a no result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- done - indicates when system call finished
--
procedure osif_call_0_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with no arguments and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- ret0 - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_0_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with one argument and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - argument of the system call
-- ret0 - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_1_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with one arguments and two results.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - argument of the system call
-- ret1 - first result of the system call
-- ret2 - second result of the system call
-- done - indicates when system call finished
--
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret1 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with two arguments and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - first argument of the system call
-- arg1 - second argument of the system call
-- ret0 - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_2_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Posts the semaphore specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Waits for the semaphore specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Locks the mutex specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Unlocks the mutex specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Tries to lock the mutex specified by handle and returns if successful or not.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Waits for the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Signals a single thread waiting on the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Signals all threads waiting on the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Puts a single word into the mbox specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word to write into the mbox
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Reads a single word from the mbox specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word read from the mbox
-- done - indicates when call finished
--
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Tries to put a single word into the mbox specified by handle but does not
-- blocks until the mbox gets populated.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word to write into the mbox
-- result - indicates if word was written into the mbox
-- done - indicates when call finished
--
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Tries to read a single word from the mbox specified by handle but does not
-- blocks until the mbox gets free.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word read from the mbox
-- result - indicates if a word was read from the mbox
-- done - indicates when call finished
--
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Gets the pointer to the initialization data of the ReconOS thread
-- specified by reconos_hwt_setinitdata.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- init - the pointer to the initialization data
-- done - indicated when call finished
--
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal init : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Terminates the current ReconOS thread.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
--
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
--
-- Writes a single word into the main memory.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- addr - address of the main memory to write
-- data - word to write into the main memory
-- done - indicates that the call finished
--
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Reads a single word from the main memory.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- addr - address of the main memory to read from
-- data - word read from the main memory
-- done - indicates that the call finished
--
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
);
--
-- Writes several words from the local ram into main memory. Therefore,
-- divides a large request into smaller ones of length at most
-- MEMIF_CHUNK_BYTES and splits request at page borders to guarantee
-- correct address translation.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- src_addr - start address to read from the local ram
-- dst_addr - start address to write into the main memory
-- len - number of bytes to transmit (bytes)
-- done - indicates that the call finished
--
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(31 downto 0);
variable done : out boolean
);
--
-- Reads several words from the main memory into the local ram. Therefore,
-- divides a large request into smaller ones of length at most
-- MEMIF_CHUNK_BYTES and splits request at page borders to guarantee
-- correct address translation.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- src_addr - start address to read from the main memory
-- dst_addr - start address to write into the local ram
-- len - number of bytes to transmit (bytes)
-- done - indicates that the call finished
--
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(31 downto 0);
variable done : out boolean
);
end package reconos_pkg;
package body reconos_pkg is
--
-- @see header
--
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal sw2hw_empty : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal hw2sw_full : in std_logic;
signal hw2sw_we : out std_logic
) is begin
i_osif.sw2hw_data <= sw2hw_data;
i_osif.sw2hw_empty <= sw2hw_empty;
sw2hw_re <= o_osif.sw2hw_re;
hw2sw_data <= o_osif.hw2sw_data;
i_osif.hw2sw_full <= hw2sw_full;
hw2sw_we <= o_osif.hw2sw_we;
i_osif.step <= o_osif.step;
i_osif.void <= o_osif.void;
end procedure osif_setup;
--
-- @see header
--
procedure osif_reset (
signal o_osif : out o_osif_t
) is begin
o_osif.sw2hw_re <= '0';
o_osif.hw2sw_data <= (others => '0');
o_osif.hw2sw_we <= '0';
o_osif.step <= 0;
o_osif.void <= '0';
end procedure osif_reset;
--
-- @see header
--
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal mem2hwt_empty : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal hwt2mem_full : in std_logic;
signal hwt2mem_we : out std_logic
) is begin
i_memif.mem2hwt_data <= mem2hwt_data;
i_memif.mem2hwt_empty <= mem2hwt_empty;
mem2hwt_re <= o_memif.mem2hwt_re;
hwt2mem_data <= o_memif.hwt2mem_data;
i_memif.hwt2mem_full <= hwt2mem_full;
hwt2mem_we <= o_memif.hwt2mem_we;
i_memif.step <= o_memif.step;
end procedure memif_setup;
--
-- @see header
--
procedure memif_reset (
signal o_memif : out o_memif_t
) is begin
o_memif.mem2hwt_re <= '0';
o_memif.hwt2mem_data <= (others => '0');
o_memif.hwt2mem_we <= '0';
o_memif.step <= 0;
end procedure memif_reset;
--
-- @see header
--
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal ram_addr : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_i_data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_o_data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
signal ram_we : out std_logic
) is begin
ram_addr <= std_logic_vector(o_ram.ram_addr);
i_ram.ram_addr <= o_ram.ram_addr;
ram_i_data <= o_ram.ram_data;
i_ram.ram_data <= ram_o_data;
ram_we <= o_ram.ram_we;
i_ram.remm <= o_ram.remm;
i_ram.mem_addr <= o_ram.mem_addr;
end procedure ram_setup;
--
-- @see header
--
procedure ram_reset (
signal o_ram : out o_ram_t
) is begin
o_ram.ram_addr <= (others => '0');
o_ram.ram_data <= (others => '0');
o_ram.ram_we <= '0';
o_ram.remm <= (others => '0');
o_ram.mem_addr <= (others => '0');
end procedure ram_reset;
--
-- @see header
--
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.sw2hw_re <= '1';
o_osif.step <= 1;
when 1 =>
if i_osif.sw2hw_empty = '0' then
word <= i_osif.sw2hw_data;
o_osif.sw2hw_re <= '0';
o_osif.step <= 2;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_read;
--
-- @see header
--
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= word;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.step <= 2;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_write;
--
-- @see header
--
procedure osif_call_0_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= call_id;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.step <= 2;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_call_0_0;
--
-- @see header
--
procedure osif_call_0_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= call_id;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.sw2hw_re <= '1';
o_osif.step <= 2;
end if;
when 2 =>
if i_osif.sw2hw_empty = '0' then
ret0 <= i_osif.sw2hw_data;
o_osif.sw2hw_re <= '0';
o_osif.step <= 3;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_call_0_1;
--
-- @see header
--
procedure osif_call_1_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= call_id;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_data <= arg0;
o_osif.step <= 2;
end if;
when 2 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.sw2hw_re <= '1';
o_osif.step <= 3;
end if;
when 3 =>
if i_osif.sw2hw_empty = '0' then
ret0 <= i_osif.sw2hw_data;
o_osif.sw2hw_re <= '0';
o_osif.step <= 4;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_call_1_1;
--
-- @see header
--
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret1 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= call_id;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_data <= arg0;
o_osif.step <= 2;
end if;
when 2 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.sw2hw_re <= '1';
o_osif.step <= 3;
end if;
when 3 =>
if i_osif.sw2hw_empty = '0' then
ret0 <= i_osif.sw2hw_data;
o_osif.step <= 4;
end if;
when 4 =>
if i_osif.sw2hw_empty = '0' then
ret1 <= i_osif.sw2hw_data;
o_osif.sw2hw_re <= '0';
o_osif.step <= 5;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_call_1_2;
--
-- @see header
--
procedure osif_call_2_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal ret0 : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= call_id;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_data <= arg0;
o_osif.step <= 2;
end if;
when 2 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_data <= arg1;
o_osif.step <= 3;
end if;
when 3 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.sw2hw_re <= '1';
o_osif.step <= 4;
end if;
when 4 =>
if i_osif.sw2hw_empty = '0' then
ret0 <= i_osif.sw2hw_data;
o_osif.sw2hw_re <= '0';
o_osif.step <= 5;
end if;
when others =>
done := True;
o_osif.step <= 0;
end case;
end procedure osif_call_2_1;
--
-- @see header
--
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_SEM_POST, handle, result, done);
end procedure osif_sem_post;
--
-- @see header
--
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_SEM_WAIT, handle, result, done);
end procedure osif_sem_wait;
--
-- @see header
--
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_MUTEX_LOCK, handle, result, done);
end procedure osif_mutex_lock;
--
-- @see header
--
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_MUTEX_UNLOCK, handle, result, done);
end procedure osif_mutex_unlock;
--
-- @see header
--
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_MUTEX_TRYLOCK, handle, result, done);
end procedure osif_mutex_trylock;
--
-- @see header
--
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2_1(i_osif, o_osif, OSIF_CMD_COND_WAIT, cond_handle, mutex_handle, result, done);
end procedure osif_cond_wait;
--
-- @see header
--
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_COND_SIGNAL, handle, result, done);
end procedure osif_cond_signal;
--
-- @see header
--
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_COND_BROADCAST, handle, result, done);
end procedure osif_cond_broadcast;
--
-- @see header
--
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2_1(i_osif, o_osif, OSIF_CMD_MBOX_PUT, handle, word, result, done);
end procedure osif_mbox_put;
--
-- @see header
--
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_1(i_osif, o_osif, OSIF_CMD_MBOX_GET, handle, word, done);
end procedure osif_mbox_get;
--
-- @see header
--
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2_1(i_osif, o_osif, OSIF_CMD_MBOX_TRYPUT, handle, word, result, done);
end procedure osif_mbox_tryput;
--
-- @see header
--
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal word : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYGET, handle, word, result, done);
end procedure osif_mbox_tryget;
--
-- @see header
--
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal init : out std_logic_vector(C_OSIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_0_1(i_osif, o_osif, OSIF_CMD_THREAD_GET_INIT_DATA, init, done);
end procedure osif_get_init_data;
--
-- @see header
--
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
case i_osif.step is
when 0 =>
o_osif.hw2sw_we <= '1';
o_osif.hw2sw_data <= OSIF_CMD_THREAD_EXIT;
o_osif.step <= 1;
when 1 =>
if i_osif.hw2sw_full = '0' then
o_osif.hw2sw_we <= '0';
o_osif.step <= 2;
end if;
when others =>
end case;
end procedure osif_thread_exit;
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_memif.step is
when 0 =>
o_memif.hwt2mem_we <= '1';
o_memif.hwt2mem_data <= MEMIF_CMD_WRITE & X"000004";
o_memif.step <= 1;
when 1 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= addr(31 downto 2) & "00";
o_memif.step <= 2;
end if;
when 2 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= data;
o_memif.step <= 3;
end if;
when 3 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_we <= '0';
o_memif.step <= 4;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write_word;
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
done := False;
case i_memif.step is
when 0 =>
o_memif.hwt2mem_we <= '1';
o_memif.hwt2mem_data <= MEMIF_CMD_READ & X"000004";
o_memif.step <= 1;
when 1 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= addr(31 downto 2) & "00";
o_memif.step <= 2;
end if;
when 2 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_we <= '0';
o_memif.mem2hwt_re <= '1';
o_memif.step <= 3;
end if;
when 3 =>
if i_memif.mem2hwt_empty = '0' then
data <= i_memif.mem2hwt_data;
o_memif.mem2hwt_re <= '0';
o_memif.step <= 4;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read_word;
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(31 downto 0);
variable done : out boolean
) is
variable to_border, to_remm : unsigned(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
done := False;
case i_memif.step is
when 0 =>
o_memif.hwt2mem_we <= '0';
o_ram.mem_addr <= unsigned(dst_addr(31 downto 2) & "00");
o_ram.remm <= unsigned(len);
o_ram.ram_addr <= unsigned(src_addr);
o_memif.step <= 1;
when 1 =>
o_memif.hwt2mem_we <= '1';
to_border := to_unsigned(C_MEMIF_CHUNK_BYTES, C_MEMIF_LENGTH_WIDTH) - i_ram.mem_addr(C_MEMIF_CHUNK_RANGE);
to_remm := i_ram.remm(C_MEMIF_LENGTH_RANGE);
if to_remm < to_border then
o_memif.hwt2mem_data <= MEMIF_CMD_WRITE & std_logic_vector(to_remm);
else
o_memif.hwt2mem_data <= MEMIF_CMD_WRITE & std_logic_vector(to_border);
end if;
o_memif.step <= 2;
when 2 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= std_logic_vector(i_ram.mem_addr);
o_memif.step <= 3;
end if;
when 3 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_we <= '0';
o_memif.step <= 4;
end if;
when 4 =>
o_ram.ram_addr <= i_ram.ram_addr + 1;
o_memif.step <= 5;
when 5 =>
o_memif.hwt2mem_we <= '1';
o_memif.hwt2mem_data <= i_ram.ram_data;
o_ram.ram_addr <= i_ram.ram_addr + 1;
o_memif.step <= 6;
when 6 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= i_ram.ram_data;
o_ram.ram_addr <= i_ram.ram_addr + 1;
o_ram.mem_addr <= i_ram.mem_addr + 4;
o_ram.remm <= i_ram.remm - 4;
if (i_ram.mem_addr + 4) mod C_MEMIF_CHUNK_BYTES = 0 then
o_memif.hwt2mem_we <= '0';
o_ram.ram_addr <= i_ram.ram_addr - 1;
o_memif.step <= 1;
end if;
if i_ram.remm - 4 = 0 then
o_memif.hwt2mem_we <= '0';
o_memif.step <= 8;
end if;
else
o_memif.hwt2mem_we <= '0';
o_ram.ram_addr <= i_ram.ram_addr - 2;
o_memif.step <= 7;
end if;
when 7 =>
if i_memif.hwt2mem_full = '0' then
o_memif.step <= 4;
end if;
when others =>
o_memif.hwt2mem_we <= '0';
o_memif.step <= 0;
done := True;
end case;
end procedure memif_write;
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(31 downto 0);
variable done : out boolean
) is
variable to_border, to_remm : unsigned(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
done := False;
case i_memif.step is
when 0 =>
o_ram.mem_addr <= unsigned(src_addr(31 downto 2) & "00");
o_ram.remm <= unsigned(len);
o_ram.ram_addr <= unsigned(dst_addr) - 1;
o_memif.step <= 1;
when 1 =>
o_ram.ram_we <= '0';
to_border := to_unsigned(C_MEMIF_CHUNK_BYTES, C_MEMIF_LENGTH_WIDTH) - i_ram.mem_addr(C_MEMIF_CHUNK_RANGE);
to_remm := i_ram.remm(C_MEMIF_LENGTH_RANGE);
if to_remm < to_border then
o_memif.hwt2mem_we <= '1';
o_memif.hwt2mem_data <= MEMIF_CMD_READ & std_logic_vector(to_remm);
else
o_memif.hwt2mem_we <= '1';
o_memif.hwt2mem_data <= MEMIF_CMD_READ & std_logic_vector(to_border);
end if;
o_memif.step <= 2;
when 2 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_data <= std_logic_vector(i_ram.mem_addr);
o_memif.step <= 3;
end if;
when 3 =>
if i_memif.hwt2mem_full = '0' then
o_memif.hwt2mem_we <= '0';
o_memif.mem2hwt_re <= '1';
o_memif.step <= 4;
end if;
when 4 =>
if i_memif.mem2hwt_empty = '0' then
o_ram.ram_we <= '1';
o_ram.ram_data <= i_memif.mem2hwt_data;
o_ram.ram_addr <= i_ram.ram_addr + 1;
o_ram.mem_addr <= i_ram.mem_addr + 4;
o_ram.remm <= i_ram.remm - 4;
if (i_ram.mem_addr + 4) mod C_MEMIF_CHUNK_BYTES = 0 then
o_memif.mem2hwt_re <= '0';
o_memif.step <= 1;
end if;
if i_ram.remm - 4 = 0 then
o_memif.mem2hwt_re <= '0';
o_memif.step <= 5;
end if;
end if;
when others =>
o_ram.ram_we <= '0';
o_memif.step <= 0;
done := true;
end case;
end procedure memif_read;
end package body reconos_pkg;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in every cycle. The bus slaves are
-- assumed to have registerd read data output with an address-in to data-out
-- latency of 1 cc. The read data muxing from bus slaves to the bus master is
-- done combinationally. Thus, at the bus master interface, there results a
-- read data latency of 1 cc.
-------------------------------------------------------------------------------
-- Note on code portability:
-------------------------------------------------------------------------------
-- The address decoding logic as implemented in process P_dec below, shows how
-- to write portable code by means of a user-defined enumaration type which is
-- used as the index range for a constant array, see mcu_pkg. This allows to
-- leave the local code (in process P_dec) unchanged when the number and/or
-- base addresses of the bus slaves in the system change. Such changes then
-- need only to be made in the global definition package.
-- To generate such portable code for the rest of the functionality (e.g. for
-- the read data mux) would require to organize all data input vectors in a
-- signal array first. This would destroy the portability of the code, since it
-- requires manual code adaption when design parameter change.
-------------------------------------------------------------------------------
-- Total # of FFs: 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity buss is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
cpu_in : in t_cpu2bus;
cpu_out : out t_bus2cpu;
-- ROM bus signals
rom_in : in t_ros2bus;
rom_out : out t_bus2ros;
-- RAM bus signals
ram_in : in t_rws2bus;
ram_out : out t_bus2rws;
-- GPIO bus signals
gpio_in : in t_rws2bus;
gpio_out : out t_bus2rws;
-- FMC TOP bus signals
fmc_top_in : in t_rws2bus;
fmc_top_out : out t_bus2rws
);
end buss;
architecture rtl of buss is
-- currently addressed bus slave
signal bus_slave, bus_slave_reg : t_bus_slave;
begin
-----------------------------------------------------------------------------
-- address decoding
-----------------------------------------------------------------------------
-- convey lower address bist from CPU to all bus slaves
rom_out.addr <= cpu_in.addr(AWL-1 downto 0);
ram_out.addr <= cpu_in.addr(AWL-1 downto 0);
gpio_out.addr <= cpu_in.addr(AWL-1 downto 0);
fmc_top_out.addr <= cpu_in.addr(AWL-1 downto 0);
-- combinational process:
-- determine addressed slave by decoding higher address bits
-----------------------------------------------------------------------------
P_dec: process(cpu_in)
begin
bus_slave <= ROM; -- default assignment
for k in t_bus_slave loop
if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then
bus_slave <= k;
end if;
end loop;
end process;
-----------------------------------------------------------------------------
-- write transfer logic
-----------------------------------------------------------------------------
-- convey write data from CPU to all bus slaves
-- rom is read-only slave
ram_out.data <= cpu_in.data;
gpio_out.data <= cpu_in.data;
fmc_top_out.data <= cpu_in.data;
-- convey write enable from CPU to addressed slave only
ram_out.wr_enb <= cpu_in.wr_enb when bus_slave = RAM else '0';
gpio_out.wr_enb <= cpu_in.wr_enb when bus_slave = GPIO else '0';
fmc_top_out.wr_enb <= cpu_in.wr_enb when bus_slave = FMC else '0';
-----------------------------------------------------------------------------
-- read transfer logic
-----------------------------------------------------------------------------
-- read data mux
with bus_slave_reg select cpu_out.data <= rom_in.data when ROM,
ram_in.data when RAM,
gpio_in.data when GPIO,
fmc_top_in.data when FMC,
(others => '-') when others;
-- convey read enable from CPU to addressed slave only
ram_out.rd_enb <= cpu_in.rd_enb when bus_slave = RAM else '0';
gpio_out.rd_enb <= cpu_in.rd_enb when bus_slave = GPIO else '0';
fmc_top_out.rd_enb <= cpu_in.rd_enb when bus_slave = FMC else '0';
-- sequential process:
-- register decode information to compensate read-latency of slaves
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
bus_slave_reg <= ROM;
elsif rising_edge(clk) then
bus_slave_reg <= bus_slave;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:29:35 08/22/2012
-- Design Name:
-- Module Name: button - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity button is
generic(
active_high:boolean := true
);
port(
clk: in std_logic;
button: in std_logic;
pulse: out std_logic
);
end button;
architecture Behavioral of button is
signal state: std_logic;
signal clean_signal: std_logic;
signal pulse_val: std_logic;
component debounce is
generic(
delay:integer := 512
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end component;
begin
pulse <= pulse_val;
db_signal:debounce
generic map (
delay => 512
)
port map(
clk => clk,
input => button,
output => clean_signal
);
button_to_pulse:process(clk)
begin
if(clk'event and clk = '1')then
if(not(clean_signal = state) )then
state <= clean_signal;
if((clean_signal = '1' and active_high) or (clean_signal = '0' and not active_high))then
pulse_val <= '1';
end if;
end if;
if(pulse_val = '1')then
pulse_val <='0';
end if;
end if;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_ctl.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-19
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controler
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-19 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
entity disp_ctl is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
-- Time of day
cur_time : in time_ty;
-- Block memory display buffer and lut
lut_addr : out std_logic_vector(11 downto 0);
lut_data : in std_logic_vector(7 downto 0);
-- Segment driver data
disp_data : out std_logic_vector(255 downto 0)
);
end disp_ctl;
architecture rtl of disp_ctl is
signal ce : std_logic;
signal cnt : std_logic_vector(5 downto 0);
signal cnt_term : std_logic;
signal char : std_logic_vector(7 downto 0);
signal dchar : std_logic_vector(7 downto 0);
SIGNAL page : std_logic_vector(7 downto 0);
signal seg : std_logic_vector(7 downto 0);
signal mask : std_logic_vector(7 downto 0);
type out_arr_t is array (natural range <>) of std_logic_vector(7 downto 0);
signal disp_sr : out_arr_t(31 downto 0);
signal rst_addr : std_logic;
signal inc_addr : std_logic;
signal disp_mem : std_logic;
signal data_val : std_logic;
signal mask_val : std_logic;
signal lut_val : std_logic;
signal out_reg : std_logic;
type ctl_t is (ctl_idle,
ctl_rd,
ctl_mux,
ctl_disp,
ctl_mask,
ctl_proc0,
ctl_proc1,
ctl_lut,
ctl_ins
);
signal curr_state : ctl_t;
signal next_state : ctl_t;
begin
-- Clock enable generator
-- Once every other clock synchronized to ms pulse.
disp_ctl_ce:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ce <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
ce <= '0';
else
ce <= not ce;
end if;
ce <= '1'; -- leave enabled for now
end if;
end process;
-- Character counter
disp_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
cnt <= (others => '0');
cnt_term <= '0';
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (rst_addr = '1') then
cnt <= (others => '0');
elsif (inc_addr = '1') then
cnt <= cnt + 1;
end if;
if (rst_addr = '1') then
cnt_term <= '0';
elsif (inc_addr = '1') then
if (cnt = 62) then
cnt_term <= '1';
else
cnt_term <= '0';
end if;
end if;
end if;
end if;
end process;
-- Display data for lookup table
disp_lut_data:
process (rst_n, clk) is
variable digit : std_logic_vector(3 downto 0);
begin
if (rst_n = '0') then
char <= (others => '0');
mask <= (others => '0');
dchar <= (others => '0');
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (data_val = '1') then
char <= lut_data;
end if;
if (mask_val = '1') then
mask <= lut_data;
end if;
case char(3 downto 0) is
when "0000" =>
digit := cur_time.t_1ms;
when "0001" =>
digit := cur_time.t_10ms;
when "0010" =>
digit := cur_time.t_100ms;
when "0011" =>
digit := cur_time.t_1s;
when "0100" =>
digit := cur_time.t_10s;
when "0101" =>
digit := cur_time.t_1m;
when "0110" =>
digit := cur_time.t_10m;
when "0111" =>
digit := cur_time.t_1h;
when "1000" =>
digit := cur_time.t_10h;
when others =>
digit := (others => '0');
end case;
if (char(7) = '1') then
dchar <= digit + x"30";
else
dchar <= '0' & char(6 downto 0);
end if;
end if;
end if;
end process;
-- Display page register, Updated every 1ms
disp_mem_page:
process (rst_n, clk) is
begin
if (rst_n = '0') then
page <= (others => '0');
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1' ) then
page <= disp_page;
end if;
end if;
end process;
-- Address mux, select character to be displayed or character genrator lut
disp_amux:
process (rst_n, clk) is
begin
if (rst_n = '0') then
lut_addr <= (others => '0');
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (disp_mem = '1') then
lut_addr <= "0" & page(4 downto 0) & cnt;
else
lut_addr <= "1000" & dchar;
end if;
end if;
end if;
end process;
-- Output register
disp_out:
process (rst_n, clk) is
begin
if (rst_n = '0') then
seg <= (others => '0');
disp_sr(0) <= x"1c";
disp_sr(1) <= x"ce";
disp_sr(2) <= x"bc";
for i in 3 to 31 loop
disp_sr(i) <= (others => '0');
end loop;
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (lut_val = '1') then
seg <= lut_data;
end if;
-- Xor in second byte of the display memory register
-- bits with the lut data
if (out_reg = '1') then
disp_sr(conv_integer(cnt(cnt'left downto 1))) <= seg xor mask;
end if;
end if;
end if;
end process;
-- Clock enable generator
-- Once every other clock synchronized to ms pulse.
disp_ctl_st:
process (rst_n, clk) is
begin
if (rst_n = '0') then
curr_state <= ctl_idle;
elsif (clk'event and clk = '1') then
if (ce = '1') then
curr_state <= next_state;
end if;
end if;
end process;
-- State diagram
-- For now just a shift register, use a state machine in case a more
-- complex sequence is needed.
disp_ctl_next:
process (curr_state, tsc_1ppms, cnt_term, disp_ena) is
begin
-- outputs
rst_addr <= '0';
inc_addr <= '0';
disp_mem <= '0';
data_val <= '0';
mask_val <= '0';
lut_val <= '0';
out_reg <= '0';
inc_addr <= '0';
case curr_state is
when ctl_idle =>
-- Start building the shift register data every ms
rst_addr <= '1';
if (tsc_1ppms = '1' and disp_ena = '1') then
next_state <= ctl_rd;
else
next_state <= ctl_idle;
end if;
when ctl_rd =>
-- Read the display memory
disp_mem <= '1';
inc_addr <= '1';
next_state <= ctl_mux;
when ctl_mux =>
-- Address mux state
disp_mem <= '1';
next_state <= ctl_disp;
when ctl_disp =>
-- Register the display memory data
data_val <= '1';
next_state <= ctl_mask;
when ctl_mask =>
-- Process char data
-- Register the display memory xor data
mask_val <= '1';
next_state <= ctl_proc0;
when ctl_proc0 =>
-- Processing
next_state <= ctl_proc1;
when ctl_proc1 =>
-- Processing
next_state <= ctl_lut;
when ctl_lut =>
-- Lookup 7 seg output
lut_val <= '1';
next_state <= ctl_ins;
when ctl_ins =>
-- Insert data into output register
-- Increment display memory address
out_reg <= '1';
inc_addr <= '1';
if (cnt_term = '1') then
next_state <= ctl_idle;
else
next_state <= ctl_rd;
end if;
when others =>
next_state <= ctl_idle;
end case;
end process;
out_map:
for i in 0 to 31 generate
disp_data(i * 8 + 7 downto i * 8) <= disp_sr(i)(7 downto 0);
end generate;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02412ent IS
END c07s03b02x00p09n01i02412ent;
ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
type T1 is array (1 to 5) of integer;
constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***PASSED TEST: c07s03b02x00p09n01i02412"
severity NOTE;
assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02412arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02412ent IS
END c07s03b02x00p09n01i02412ent;
ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
type T1 is array (1 to 5) of integer;
constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***PASSED TEST: c07s03b02x00p09n01i02412"
severity NOTE;
assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02412arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02412ent IS
END c07s03b02x00p09n01i02412ent;
ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
type T1 is array (1 to 5) of integer;
constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***PASSED TEST: c07s03b02x00p09n01i02412"
severity NOTE;
assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02412arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
igual : out STD_LOGIC);
end ALU;
architecture Behavior of ALU is
begin
process (A,B,control)
variable rAux: std_logic_vector(31 downto 0);
variable igualAux : std_logic;
begin
rAux:= (A) - (B);
if(rAux=x"00000000") then
igualAux:='1';
else
igualAux:='0';
end if;
if (control="0000") then
rAux:= (A) AND (B);
elsif(control="0001") then
rAux:= (A) OR (B);
elsif(control="0010") then
rAux:= (A) XOR (B);
elsif(control="0011") then
rAux:= (A) + (B);
elsif(control="1000") then
rAux:= (A) - (B);
elsif(control="1001") then
raux:=B(15 downto 0)&x"0000";
elsif(control="1010") then
rAux:= (A) - (B);
if(rAux(31)='1') then
rAux:=x"00000001";
else
rAux:=x"00000000";
end if;
else
rAux:=(others=>'0');
igualAux:='0';
end if;
resultado<=rAux;
igual<=igualAux;
end process;
end Behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
igual : out STD_LOGIC);
end ALU;
architecture Behavior of ALU is
begin
process (A,B,control)
variable rAux: std_logic_vector(31 downto 0);
variable igualAux : std_logic;
begin
rAux:= (A) - (B);
if(rAux=x"00000000") then
igualAux:='1';
else
igualAux:='0';
end if;
if (control="0000") then
rAux:= (A) AND (B);
elsif(control="0001") then
rAux:= (A) OR (B);
elsif(control="0010") then
rAux:= (A) XOR (B);
elsif(control="0011") then
rAux:= (A) + (B);
elsif(control="1000") then
rAux:= (A) - (B);
elsif(control="1001") then
raux:=B(15 downto 0)&x"0000";
elsif(control="1010") then
rAux:= (A) - (B);
if(rAux(31)='1') then
rAux:=x"00000001";
else
rAux:=x"00000000";
end if;
else
rAux:=(others=>'0');
igualAux:='0';
end if;
resultado<=rAux;
igual<=igualAux;
end process;
end Behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
resultado : out STD_LOGIC_VECTOR (31 downto 0);
control : in STD_LOGIC_VECTOR (3 downto 0);
igual : out STD_LOGIC);
end ALU;
architecture Behavior of ALU is
begin
process (A,B,control)
variable rAux: std_logic_vector(31 downto 0);
variable igualAux : std_logic;
begin
rAux:= (A) - (B);
if(rAux=x"00000000") then
igualAux:='1';
else
igualAux:='0';
end if;
if (control="0000") then
rAux:= (A) AND (B);
elsif(control="0001") then
rAux:= (A) OR (B);
elsif(control="0010") then
rAux:= (A) XOR (B);
elsif(control="0011") then
rAux:= (A) + (B);
elsif(control="1000") then
rAux:= (A) - (B);
elsif(control="1001") then
raux:=B(15 downto 0)&x"0000";
elsif(control="1010") then
rAux:= (A) - (B);
if(rAux(31)='1') then
rAux:=x"00000001";
else
rAux:=x"00000000";
end if;
else
rAux:=(others=>'0');
igualAux:='0';
end if;
resultado<=rAux;
igual<=igualAux;
end process;
end Behavior; |
-------------------------------------------------------------------------------
--
-- Design : CFC Unit
-- Project : Tomasulo Processor
-- Entity : CFC
-- Author : Rajat Shah
-- Company : University of Southern California
-- Last Updated : April 15th, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end cfc;
architecture cfc_arch of cfc is
--Signal declaration for 8 copies of checkpoints - Each 32 deep and 6 bit wide
type cfc_checkpoint_type is array(0 to 255) of std_logic_vector(5 downto 0);
signal Cfc_RsList, Cfc_RtList, Cfc_RdList : cfc_checkpoint_type; --3 BRAM, each containing flattened 8 tables
--Signal declaration for committed checkpoint (Retirement RAT) - 32 deep and 6 bit wide
type committed_type is array(0 to 31) of std_logic_vector(5 downto 0);
signal Committed_RsList, Committed_RtList, Committed_RdList : committed_type :=(
"000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111"); -- 3 copies of committed list initialize to 0 to 31
--Signal declaration for 8 copies of Dirty Flag Array(DFA) validating each checkpoints - Each 32 deep and 1 bit wide
type dfa_checkpoint_type is array(0 to 31) of std_logic;
type dfa_array_type is array (0 to 7) of dfa_checkpoint_type;
signal Dfa_List : dfa_array_type;
type checkpoint_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Checkpoint_TagArray: checkpoint_tag_type; --8 deep and 5 bit wide array for storing ROB tag of checkpointed branch instructions
type Frl_HeadPtrArray_type is array (0 to 7) of std_logic_vector (4 downto 0);
signal Frl_HeadPtrArray: Frl_HeadPtrArray_type;
type depth_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Depth_Array: depth_tag_type;
type Cfc_Valid_Array_type is array (0 to 7) of std_logic;
signal Cfc_ValidArray: Cfc_Valid_Array_type;
signal Full, Empty : std_logic; --flag indicating if all 8 checkpoints are used or empty
signal Head_Pointer, Tail_Pointer: std_logic_vector(2 downto 0); --Head Pointer indicates active checkpoint while tail pointer indicates oldest uncommitted branch
signal Checkpoint_MatchArray: std_logic_vector (7 downto 0); --Array indicating if the instruction on CDB matches any checkpointed branch
signal DFA_RsValid, DFA_RtValid, DFA_RdValid: std_logic;
signal Cfc_RsList_temp, Cfc_RtList_temp, Cfc_RdList_temp: std_logic_vector (5 downto 0);
signal Committed_RsList_temp, Committed_RtList_temp, Committed_RdList_temp: std_logic_vector (5 downto 0);
signal Next_Head_Pointer: std_logic_vector (2 downto 0); --Temporary Head_pointer generated during CDB Flush
begin
Depth_Array(0) <= Checkpoint_TagArray(0) - Rob_TopPtr; -- std_logic_vector is treated as unsigned because of library declaration IEEE_STD_LOGIC_UNSIGNED
Depth_Array(1) <= Checkpoint_TagArray(1) - Rob_TopPtr;
Depth_Array(2) <= Checkpoint_TagArray(2) - Rob_TopPtr;
Depth_Array(3) <= Checkpoint_TagArray(3) - Rob_TopPtr;
Depth_Array(4) <= Checkpoint_TagArray(4) - Rob_TopPtr;
Depth_Array(5) <= Checkpoint_TagArray(5) - Rob_TopPtr;
Depth_Array(6) <= Checkpoint_TagArray(6) - Rob_TopPtr;
Depth_Array(7) <= Checkpoint_TagArray(7) - Rob_TopPtr;
--Combinational assignment determining if the instruction on CDB is a frozen branch or not
Checkpoint_MatchArray(0) <= '1' when ((Checkpoint_TagArray(0) = Cdb_RobTag) and (Cfc_ValidArray(0) = '1')) else
'0';
Checkpoint_MatchArray(1) <= '1' when ((Checkpoint_TagArray(1) = Cdb_RobTag) and (Cfc_ValidArray(1) = '1')) else
'0';
Checkpoint_MatchArray(2) <= '1' when ((Checkpoint_TagArray(2) = Cdb_RobTag) and (Cfc_ValidArray(2) = '1')) else
'0';
Checkpoint_MatchArray(3) <= '1' when ((Checkpoint_TagArray(3) = Cdb_RobTag) and (Cfc_ValidArray(3) = '1')) else
'0';
Checkpoint_MatchArray(4) <= '1' when ((Checkpoint_TagArray(4) = Cdb_RobTag) and (Cfc_ValidArray(4) = '1')) else
'0';
Checkpoint_MatchArray(5) <= '1' when ((Checkpoint_TagArray(5) = Cdb_RobTag) and (Cfc_ValidArray(5) = '1')) else
'0';
Checkpoint_MatchArray(6) <= '1' when ((Checkpoint_TagArray(6) = Cdb_RobTag) and (Cfc_ValidArray(6) = '1')) else
'0';
Checkpoint_MatchArray(7) <= '1' when ((Checkpoint_TagArray(7) = Cdb_RobTag) and (Cfc_ValidArray(7) = '1')) else
'0';
Cfc_Full <= Full;
--Task 0: Complete the Full and empty conditions depending on the Head_Pointer and Tail_pointer values
Full <= '1' when (unsigned(Tail_Pointer-Head_Pointer)=1) else '0';
Empty <= '1' when (Head_Pointer = Tail_Pointer) else '0'; --Flag indicating that there is no frozen checkpoint
Cfc_FrlHeadPtr <= Frl_HeadPtrArray(conv_integer(Next_Head_Pointer));
Cfc_RobTag <= Checkpoint_Tagarray(conv_integer(Next_Head_Pointer));
CfcUpdate: process (Clk, Resetb)
begin
if(Resetb = '0') then
Head_Pointer <= "000"; --Here the Head_Pointer points to the active checkpoint and not to the empty location
Tail_Pointer <= "000";
for I in 0 to 7 loop
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
Cfc_ValidArray(I) <= '0';
end loop;
elsif (Clk'event and Clk = '1') then
--Releasing the oldest checkpoint if the branch reaches top of ROB
if ((Rob_Commit = '1') and (Rob_TopPtr = Checkpoint_TagArray(conv_integer(Tail_Pointer))) and ((Tail_Pointer - Next_Head_Pointer) /= "00")) then
Tail_Pointer <= Tail_Pointer + '1';
Cfc_ValidArray(conv_integer(Tail_Pointer)) <= '0';
for I in 0 to 31 loop
Dfa_List(conv_integer(Tail_Pointer))(I) <= '0';
end loop;
end if;
if (Cdb_Flush = '1') then
---- ADDED BY MANPREET--- need to invalidate the active rat dfa bits
for J in 0 to 31 loop
Dfa_List(conv_integer(Head_Pointer))(J) <= '0';
end loop;
-----------------------------
for I in 0 to 7 loop
-- changed by Manpreet.. shouldnt invalidate the rat corresponding to branch_tag = cdb_robtag as
-- it contains instructions before the flushed branch and will become the active rat
if (Cdb_RobDepth < Depth_Array(I)) then --Invalidating all the younger checkpoints and clearing the Dfa_List
Cfc_ValidArray(I)<='0';
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
end if;
if (Cdb_RobDepth = Depth_Array(I)) then
Cfc_ValidArray(I)<='0';
end if ;
end loop;
Head_Pointer <= Next_Head_Pointer;
else
-- Task 1: Update the DFA bit of the Active Checkpoint on dispatch of Register Writing Instruction
if (Dis_InstValid='1' and Dis_CfcRegWrite='1') then
Dfa_List(conv_integer(Head_Pointer)) (conv_integer(Dis_CfcRdAddr)) <= '1';
end if;
-- Task 2: Create a new checkpoint for dispatched branch (i.e. freeze the active checkpoint)
if ((Dis_CfcBranch = '1' or Dis_Jr31Inst = '1')and Dis_InstValid = '1' and ((Full /= '1') or ((Rob_Commit = '1') and (Full = '1') ))) then -- Task 2.1 - some conditions missing - think structural hazard - can't dispatch branch if all checkpoints are in use. But what if a branch is committing as well?
Checkpoint_TagArray (conv_integer(Head_Pointer)) <= Dis_CfcBranchTag;
Cfc_ValidArray (conv_integer(Head_Pointer)) <= '1';
Frl_HeadPtrArray(conv_integer(Head_Pointer)) <= Frl_HeadPtr;
Head_Pointer <= Head_Pointer + 1;
-- Task 2.2 - what things need to be done for a new checkpoint? Tagarray, validarray, FRL headpointer and the headpointer should be updated.
end if;
end if;
end if;
end process;
--Combinational Process to determine new head pointer during branch misprediction
CDB_Flush_Process: process (Cdb_Flush, Checkpoint_MatchArray, Frl_HeadPtrArray, Checkpoint_TagArray, Head_Pointer)
begin
Next_Head_Pointer <= Head_Pointer;
if (Cdb_Flush = '1') then
Case Checkpoint_MatchArray is --Case statement to move the head pointer on branch misprediction to corresponding frozen checkpoint
when "00000001" =>
Next_Head_Pointer <= "000";
when "00000010" =>
Next_Head_Pointer <= "001";
when "00000100" =>
Next_Head_Pointer <= "010";
when "00001000" =>
Next_Head_Pointer <= "011";
when "00010000" =>
Next_Head_Pointer <= "100";
when "00100000" =>
Next_Head_Pointer <= "101";
when "01000000" =>
Next_Head_Pointer <= "110";
when "10000000" =>
Next_Head_Pointer <= "111";
when others =>
Next_Head_Pointer <= "XXX";
end case;
end if;
end process;
--Process to find the latest value of Rs to be given to Dispatch
Dispatch_RsRead_Process: process (Clk,Resetb)
variable found_Rs1, found_Rs2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RsPointer: std_logic_vector(2 downto 0);
begin
if (Resetb = '0') then
Committed_RsList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rs1 := '1';
exit;
else
found_Rs1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rs2 := '1';
exit;
else
found_Rs2 := '0';
end if;
end if;
end loop;
-- Task 3: Use found_Rs1, found_Rs2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rspointer and Dfa_RsValid
-- Dfa_RsValid tells if the Rs register is present in any of the 8 checkpoints or not
-- BRAM_Rspointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RsValid <= found_Rs1 or found_Rs2;
if (found_Rs1 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rs2 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rspointer := (others => '0');
end if;
-- Task 4: Update Committed_Rslist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rslist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RsList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RsList_temp <= Cfc_RsList(conv_integer(BRAM_RsPointer & Dis_CfcRsAddr)); --concatenating the pointer & logical Rs address value to read BRAM
Committed_RsList_temp <= Committed_RsList(conv_integer(Dis_CfcRsAddr));
end if;
end if;
end process;
process (Dfa_RsValid, Cfc_RsList_temp, Committed_RsList_temp)--mux to select between the checkpoint value or committed value
begin
if (Dfa_RsValid = '1') then
Cfc_RsPhyAddr <= Cfc_RsList_temp;
else
Cfc_RsPhyAddr <= Committed_RsList_temp;
end if;
end process;
-- Task 5: same process as above for finding the latest value of Rt
Dispatch_RtRead_Process: process(Clk,Resetb)
variable found_Rt1, found_Rt2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RtPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RtList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rt1 := '1';
exit;
else
found_Rt1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rt2 := '1';
exit;
else
found_Rt2 := '0';
end if;
end if;
end loop;
-- Use found_Rt1, found_Rt2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rtpointer and Dfa_RtValid
-- Dfa_RtValid tells if the Rt register is present in any of the 8 checkpoints or not
-- BRAM_Rtpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RtValid <= found_Rt1 or found_Rt2;
if (found_Rt1 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rt2 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rtpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rtlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rtlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RtList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RtList_temp <= Cfc_RtList(conv_integer(BRAM_RtPointer & Dis_CfcRtAddr)); --concatenating the pointer & logical Rt address value to read BRAM
Committed_RtList_temp <= Committed_RtList(conv_integer(Dis_CfcRtAddr));
end if;
end if;
end process;
process (Dfa_RtValid, Cfc_RtList_temp, Committed_RtList_temp)
begin
if (Dfa_RtValid = '1') then
Cfc_RtPhyAddr <= Cfc_RtList_temp;
else
Cfc_RtPhyAddr <= Committed_RtList_temp;
end if;
end process;
-- Task 6: same process as above for finding the latest value of Rd
Dispatch_RdRead_Process: process(Clk,Resetb)
variable found_Rd1, found_Rd2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RdPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RdList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rd1 := '1';
exit;
else
found_Rd1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rd2 := '1';
exit;
else
found_Rd2 := '0';
end if;
end if;
end loop;
-- Use found_Rd1, found_Rd2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rdpointer and Dfa_RdValid
-- Dfa_RdValid tells if the Rd register is present in any of the 8 checkpoints or not
-- BRAM_Rdpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RdValid <= found_Rd1 or found_Rd2;
if (found_Rd1 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rd2 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rdpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rdlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rdlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RdList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RdList_temp <= Cfc_RdList(conv_integer(BRAM_RdPointer & Dis_CfcRdAddr)); --concatenating the pointer & logical Rd address value to read BRAM
Committed_RdList_temp <= Committed_RdList(conv_integer(Dis_CfcRdAddr));
end if;
end if;
end process;
process (Dfa_RdValid, Cfc_RdList_temp, Committed_RdList_temp)
begin
if (Dfa_RdValid = '1') then
Cfc_RdPhyAddr <= Cfc_RdList_temp;
else
Cfc_RdPhyAddr <= Committed_RdList_temp;
end if;
end process;
end cfc_arch;
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