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----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:19:54 10/27/2009
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-- Description: The ALU for the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.30 - File written and syntax checked
-- Revision 0.90 - Successfully simulated
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0);
cond_bits : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
main: process(A, B, sel) is
variable out_reg : STD_LOGIC_VECTOR(32 downto 0);
begin
cond_bits <= "0000";
--operations
case sel is
when "0000" => --add
out_reg := ('0' & A(31 downto 0)) + ('0' & B(31 downto 0));
when "0001" => --sub
out_reg := ('0' & A(31 downto 0)) - ('0' & B(31 downto 0));
when "0010" => --and
out_reg := '0' & (A and B);
when "0011" => --or
out_reg := '0' & (A or B);
when "0100" => --xor
out_reg := '0' & (A xor B);
when "0101" => --cp
out_reg := ('0' & A);
when "0110" => --sll
out_reg := (A(31 downto 0) & '0');
when "0111" => --srl
out_reg := ("00" & A(31 downto 1));
when "1000" => --rol
out_reg := (A(0) & A(0) & A(31 downto 1));
when "1001" => --ror
out_reg := (A(30) & A(30 downto 0) & A(31));
when others =>
out_reg := ('0' & A);
end case;
--condition bit logic
if (A > B) then
cond_bits(1) <= '1';
elsif (A = B) then
cond_bits(2) <= '1';
elsif (A < B) then
cond_bits(3) <= '1';
end if;
cond_bits(0) <= out_reg(32); --carry
result <= out_reg(31 downto 0);
end process;
end Behavioral;
|
entity tb_rec02 is
end tb_rec02;
library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;
architecture behav of tb_rec02 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec02
port map (inp => inp, o => r);
process
begin
inp.a <= 5;
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= 2;
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= 1;
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= 4;
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Fetch_tb IS
END Fetch_tb;
ARCHITECTURE behavior OF Fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*10;
RST<= '0';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Fetch_tb IS
END Fetch_tb;
ARCHITECTURE behavior OF Fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*10;
RST<= '0';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Fetch_tb IS
END Fetch_tb;
ARCHITECTURE behavior OF Fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*10;
RST<= '0';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Fetch_tb IS
END Fetch_tb;
ARCHITECTURE behavior OF Fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*10;
RST<= '0';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Fetch_tb IS
END Fetch_tb;
ARCHITECTURE behavior OF Fetch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*10;
RST<= '0';
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_DUMMY is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic
);
end IP_DUMMY;
architecture BEHAVIOURAL of IP_DUMMY is
begin
address <= conv_std_logic_vector(4, ADD_WIDTH);
data_in <= conv_std_logic_vector(666, DATA_WIDTH);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
interrupt <= '0';
end architecture BEHAVIOURAL; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_DUMMY is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic
);
end IP_DUMMY;
architecture BEHAVIOURAL of IP_DUMMY is
begin
address <= conv_std_logic_vector(4, ADD_WIDTH);
data_in <= conv_std_logic_vector(666, DATA_WIDTH);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
interrupt <= '0';
end architecture BEHAVIOURAL; |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
break_in_progress : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i, r, reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable special_reg : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
if exec_i.ctrl_wrb.reg_d = "00000" then
v.ctrl_wrb.reg_write := '0';
end if;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- In case more than just one special register needs to be supported, a multiplexer can be made here. For now, just MSR.
special_reg := (31 => reg.carry,
3 => reg.break_in_progress,
2 => reg.carry,
1 => r.interrupt_enable,
others => '0' );
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_SPR => alu_src_a := special_reg;
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
report "Invalid ALU operation" severity FAILURE;
end case;
if reg.flush_ex = '0' then
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
-- MSR operations
case exec_i.ctrl_ex.msr_op is
when MSR_SET_I =>
v.interrupt_enable := '1';
when MSR_CLR_I =>
v.interrupt_enable := '0';
when LOAD_MSR =>
v_reg.break_in_progress := dat_a(3);
v_reg.carry := dat_a(2);
v.interrupt_enable := dat_a(1);
when MSR_SET =>
v_reg.break_in_progress := exec_i.imm(3) or reg.break_in_progress;
v_reg.carry := exec_i.imm(2) or reg.carry;
v.interrupt_enable := exec_i.imm(1) or r.interrupt_enable;
when MSR_CLR =>
v_reg.break_in_progress := not exec_i.imm(3) and reg.break_in_progress;
v_reg.carry := not exec_i.imm(2) and reg.carry;
v.interrupt_enable := not exec_i.imm(1) and r.interrupt_enable;
when others =>
null;
end case;
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
-- Handle CMPU and CMP
if ( exec_i.ctrl_ex.operation = "11" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := not result_add(CFG_DMEM_WIDTH); -- unsigned = bit 32 of result
elsif ( exec_i.ctrl_ex.operation = "01" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := (result_add(CFG_DMEM_WIDTH) xor alu_src_a(CFG_DMEM_WIDTH-1) xor alu_src_b(CFG_DMEM_WIDTH-1)); -- signed
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.interrupt_enable <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.break_in_progress <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01757ent IS
END c09s05b01x00p01n01i01757ent;
ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= transport
U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= transport U after 1 ns;
elsif count = 1 then
ECLK2 <= transport D after 1 ns;
elsif count = 2 then
ECLK2 <= transport Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= transport Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= transport ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= transport DZX after 1 ns;
else
ECLK2 <= transport ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01757"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01757arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01757ent IS
END c09s05b01x00p01n01i01757ent;
ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= transport
U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= transport U after 1 ns;
elsif count = 1 then
ECLK2 <= transport D after 1 ns;
elsif count = 2 then
ECLK2 <= transport Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= transport Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= transport ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= transport DZX after 1 ns;
else
ECLK2 <= transport ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01757"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01757arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01757ent IS
END c09s05b01x00p01n01i01757ent;
ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= transport
U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= transport U after 1 ns;
elsif count = 1 then
ECLK2 <= transport D after 1 ns;
elsif count = 2 then
ECLK2 <= transport Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= transport Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= transport ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= transport DZX after 1 ns;
else
ECLK2 <= transport ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01757"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01757arch;
|
-------------------------------------------------------------------------------
-- $Id: xbic_dbeat_control.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_dbeat_control.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_dbeat_control.vhd
-- Version: v1_00_a
-- Description:
-- This VHDL design implements burst support features that are used for fixed
-- length bursts and cacheline transfers.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $5/15/2002$
--
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from plbv46_slave_burst_V1_00_a library
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.counter_f;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity xbic_dbeat_control is
generic (
-- Generics
C_NATIVE_DWIDTH : integer := 32 ;
C_FAMILY : string := "virtex5"
);
port (
-- Input ports
Bus_Rst : in std_logic ;
Bus_clk : in std_logic ;
-- Start Control
Req_Init : in std_logic ;
-- Qualifiers
Doing_Single : in std_logic ;
Doing_Cacheline : in std_logic ;
Doing_FLBurst : in std_logic ;
RNW_In : in std_logic ;
BE_In : in std_logic_vector(0 to 3);
Size_In : in std_logic_vector(0 to 3);
MSize_In : in std_logic_vector(0 to 1);
-- Count Enables
Wr_DAck : in std_logic ;
Rd_DAck : in std_logic ;
-- Special Case Output signals
Cline_Spec_1DBeat_Case : out std_logic ;
-- Done State signals
AlmostDone : out std_logic ;
Done : out std_logic
);
end entity xbic_dbeat_control;
architecture implementation of xbic_dbeat_control is
-- functions
-- none
-- Constants
--Constant COUNTER_SIZE : integer := 5;
constant DBEAT_CNTR_SIZE : integer := 4;
Constant CNTR_LD_ZEROS : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1):= (others => '0');
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant ZERO : integer := 0;
Constant ONE : integer := 1;
Constant COUNT_ZERO : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ZERO, DBEAT_CNTR_SIZE));
Constant CYCLE_CNT_ZERO : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ZERO, DBEAT_CNTR_SIZE));
Constant CYCLE_CNT_ONE : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ONE, DBEAT_CNTR_SIZE));
-- Types
-- Signals
signal req_init_reg : std_logic;
signal req_init_strt : std_logic;
signal dbeat_cnt_en : std_logic;
signal dbeat_cnt_init : std_logic;
signal dbeat_count : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_cline_value : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_flburst_value : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_comp_value_reg : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal dbeat_cnt_almst_done_raw : std_logic;
signal dbeat_cnt_almst_done : std_logic;
signal dbeat_cnt_done : std_logic;
signal mult_by_done : std_logic;
signal mult_by_almost_done : std_logic;
signal mult_by_1 : std_logic;
signal mult_by_2 : std_logic;
signal mult_by_4 : std_logic;
signal doing_multi_dbeat : std_logic;
signal mult_cnt_sreg : std_logic_vector(0 to 3);
signal Cline_special_case1 : std_logic;
signal Cline_special_case2 : std_logic;
signal Burst_special_case1 : std_logic;
signal Burst_special_case2 : std_logic;
signal Cline_special_case1_reg : std_logic;
signal Cline_special_case2_reg : std_logic;
signal Burst_special_case1_reg : std_logic;
signal Burst_special_case2_reg : std_logic;
-------------------------------------------------------------------------------
begin --(architecture implementation)
-- Misc assignments
AlmostDone <= (dbeat_cnt_almst_done and mult_by_almost_done)
When (Cline_special_case1_reg = '1')
else (dbeat_cnt_almst_done and mult_by_done);
Done <= dbeat_cnt_done and mult_by_done;
-- Detect a FLBurst of 2 data beats as a special case
Burst_special_case1 <= '1'
when (BE_In = "0001" and
Doing_FLBurst = '1')
Else '0';
-- Detect a FLBurst of 3 data beats as a special case
Burst_special_case2 <= '1'
when (BE_In = "0010" and
Doing_FLBurst = '1')
Else '0';
-- DET req_init_strt <= Req_Init and
-- DET not(req_init_reg);
req_init_strt <= Req_Init;
dbeat_cnt_init <= Bus_Rst or
req_init_strt or
--(not(mult_by_done) and
dbeat_cnt_done or
Cline_special_case1_reg or
Burst_special_case1_reg;
doing_multi_dbeat <= Doing_Cacheline or
Doing_FLBurst;
dbeat_cnt_en <= Wr_DAck or
Rd_DAck;
mult_by_done <= mult_cnt_sreg(0);
mult_by_almost_done <= mult_cnt_sreg(0) or
mult_cnt_sreg(1);
dbeat_cnt_almst_done_raw <= '1'
when (dbeat_count = almst_done_comp_value_reg)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REQ_INIT
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_REQ_INIT : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
req_init_reg <= '0';
else
req_init_reg <= Req_Init;
end if;
end if;
end process REG_REQ_INIT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SPEC_CASES
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_SPEC_CASES : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(dbeat_cnt_done = '1'and
mult_by_done = '1' and
req_init_strt = '0')) then
Cline_special_case1_reg <= '0';
Cline_special_case2_reg <= '0';
Burst_special_case1_reg <= '0';
Burst_special_case2_reg <= '0';
Cline_Spec_1DBeat_Case <= '0';
elsif (req_init_strt = '1') then
Cline_special_case1_reg <= Cline_special_case1;
Cline_special_case2_reg <= Cline_special_case2;
Burst_special_case1_reg <= Burst_special_case1;
Burst_special_case2_reg <= Burst_special_case2;
Cline_Spec_1DBeat_Case <= Cline_special_case1 and
mult_by_1;
else
null; -- hold current state
end if;
end if;
end process REG_SPEC_CASES;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_FLB_DONE_COMP_VALUE
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Fixed Length Burst Operations.
--
-------------------------------------------------------------
CALC_FLB_DONE_COMP_VALUE : process (BE_In)
begin
case BE_In is
-- when "0001" =>
-- almst_done_flburst_value <= "0000"
-- when "0010" =>
-- almst_done_flburst_value <= "0000"
when "0011" =>
almst_done_flburst_value <= "0001";
when "0100" =>
almst_done_flburst_value <= "0010";
when "0101" =>
almst_done_flburst_value <= "0011";
when "0110" =>
almst_done_flburst_value <= "0100";
when "0111" =>
almst_done_flburst_value <= "0101";
when "1000" =>
almst_done_flburst_value <= "0110";
when "1001" =>
almst_done_flburst_value <= "0111";
when "1010" =>
almst_done_flburst_value <= "1000";
when "1011" =>
almst_done_flburst_value <= "1001";
when "1100" =>
almst_done_flburst_value <= "1010";
when "1101" =>
almst_done_flburst_value <= "1011";
when "1110" =>
almst_done_flburst_value <= "1100";
when "1111" =>
almst_done_flburst_value <= "1101";
when others =>
almst_done_flburst_value <= "0000";
end case;
end process CALC_FLB_DONE_COMP_VALUE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_COMP_VALUE
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_COMP_VALUE : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(Req_Init = '1' and
Doing_Single = '1')) then
almst_done_comp_value_reg <= (others => '0');
elsif (Req_Init = '1' and
Doing_FLBurst = '1') then
almst_done_comp_value_reg <= almst_done_flburst_value;
Elsif (Req_Init = '1' and
Doing_Cacheline = '1') Then
almst_done_comp_value_reg <= almst_done_cline_value;
else
null; -- hold current value
end if;
end if;
end process REG_COMP_VALUE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DONE_FLAGS
--
-- Process Description:
-- This process implements the almost_done and done flags.
--
-------------------------------------------------------------
REG_DONE_FLAGS : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(dbeat_cnt_en = '1' and
dbeat_cnt_done = '1' and
mult_by_done = '1')) then
dbeat_cnt_almst_done <= '0';
dbeat_cnt_done <= '0';
-- Special case Singles
Elsif (req_init_strt = '1' and
Doing_Single = '1') Then
--dbeat_cnt_almst_done <= '0';
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '1';
-- Special case Cachelines (1 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_Cacheline = '1' and
Cline_special_case1 = '1') Then
--dbeat_cnt_almst_done <= '0';
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '1';
-- Special case Cachelines (2 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_Cacheline = '1' and
Cline_special_case2 = '1') Then
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '0';
-- Special case Fixed Length Burst (2 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_FLBurst = '1' and
Burst_special_case1 = '1') Then
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '0';
-- Starting a non-special case cacheline or flburst -- new DET
Elsif (req_init_strt = '1') Then -- new DET
-- new DET
dbeat_cnt_almst_done <= '0'; -- new DET
dbeat_cnt_done <= '0'; -- new DET
-- new DET
-- Normal termination case based on Dbeat Counter
elsif (dbeat_cnt_en = '1') then
dbeat_cnt_almst_done <= (dbeat_cnt_almst_done_raw and
not(dbeat_cnt_almst_done)) or
Cline_special_case1_reg;
dbeat_cnt_done <= dbeat_cnt_almst_done;
else
null; -- hold current state
end if;
end if;
end process REG_DONE_FLAGS;
----------------------------------------------------------------------------
-- Data Beat Counter Logic
-- This counter is reset at command start and counts up with every data
-- acknowledge assertion. A primary requirement for its implementation is
-- that it be ready to count a Write data acknowledge on the same clock
-- cycle that the Sl_Addrack is being asserted to the PLB.
----------------------------------------------------------------------------
-- RESP_LOAD_VALUE : process(Num_Data_Beats)
-- begin
-- if(C_MAX_DBEAT_CNT > Num_Data_Beats)then
-- resp_db_load_value <= std_logic_vector(to_unsigned(Num_Data_Beats, DBEAT_CNTR_SIZE));
-- else
-- resp_db_load_value <= std_logic_vector(to_unsigned(C_MAX_DBEAT_CNT-1,DBEAT_CNTR_SIZE));
-- end if;
-- end process RESP_LOAD_VALUE;
--
-- resp_db_cnten <= Target_DataAck and
-- not(Response_Done_i);
I_DBEAT_CNTR : entity proc_common_v3_00_a.counter_f
generic map(
C_NUM_BITS => DBEAT_CNTR_SIZE,
C_FAMILY => C_FAMILY
)
port map (
Clk => Bus_clk,
Rst => dbeat_cnt_init,
Load_In => CNTR_LD_ZEROS,
Count_Enable => dbeat_cnt_en,
Count_Load => LOGIC_LOW,
Count_Down => '0', -- count up
Count_Out => dbeat_count,
Carry_Out => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_32_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 32.
--
--
------------------------------------------------------------
BLE_32_BIT_SLAVE : if (C_NATIVE_DWIDTH = 32) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S32
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
--
-- 32-bit Slave can transfer 1 wds per data beat
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S32 : process (Size_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (4 dbeats)
almst_done_cline_value <= "0001";
when "0010" => -- Cacheline 8wrds (8 dbeats)
almst_done_cline_value <= "0101";
when "0011" => -- Cacheline 16wrds (16 dbeats)
almst_done_cline_value <= "1101";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S32;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S32
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 32.
--
-------------------------------------------------------------
GET_MULT_BY_S32 : process (Doing_FLBurst,
Doing_Cacheline,
--MSize_In,
Size_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
If (Doing_FLBurst = '1') Then
case Size_In is
-- when "1010" => -- 32-bit burst request
--
-- mult_by_1 <= '1';
--
when "1011" => -- 64-bit burst request
mult_by_1 <= '0';
mult_by_2 <= '1';
when "1100" => -- 128-bit burst request
mult_by_1 <= '0';
mult_by_4 <= '1';
when others => -- default to 32-bit
null; -- use defaults
end case;
Elsif (Doing_Cacheline = '1') Then
mult_by_1 <= '1';
-- case MSize_In is
-- when "00" => -- 32-bit master/32-bit slave
--
-- mult_by_1 <= '1';
--
-- when "01" => -- 64-bit Master/32-bit slave
--
-- mult_by_1 <= '0';
-- mult_by_2 <= '1';
--
-- when others => -- 128 bit master/32-bit slave
--
-- mult_by_1 <= '0';
-- mult_by_4 <= '1';
--
-- end case;
End if;
end process GET_MULT_BY_S32;
end generate BLE_32_BIT_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_64_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 64.
--
--
------------------------------------------------------------
BLE_64_BIT_SLAVE : if (C_NATIVE_DWIDTH = 64) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S64
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
-- 64-bit Slave can transfer 2 wds per data beat but if
-- requesting Master is 32-bits, then only 32-bits per
-- data beat.
--
-- Cline_special_case1 is asserted when the resolved dbeat
-- count is 1 data beat (only possible with 128-bit Master and
-- 128-bit Slave and 4wrd cacheline)
-- Cline_special_case12 is asserted when the resolved dbeat
-- count is 2 data beats
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S64 : process (Size_In)
--,MSize_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (2 dbeats minimum)
almst_done_cline_value <= "0001"; -- special case value
Cline_special_case1 <= '0';
Cline_special_case2 <= '1';
-- If (MSize_In = "00") Then -- 32-bit Master
-- -- requires 4 data beats
--
-- almst_done_cline_value <= "0001"; -- special case value
-- Cline_special_case1 <= '0';
-- Cline_special_case2 <= '1';
--
-- else -- 64 or 128-bit Master (only 2 data beats)
--
-- --almst_done_cline_value <= "0000";
-- almst_done_cline_value <= "0000";
-- Cline_special_case1 <= '0';
-- Cline_special_case2 <= '1';
--
--
-- End if;
when "0010" => -- Cacheline 8wrds (4 dbeats)
almst_done_cline_value <= "0001";
when "0011" => -- Cacheline 16wrds (8 dbeats)
almst_done_cline_value <= "0101";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S64;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S64
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 64.
--
-------------------------------------------------------------
GET_MULT_BY_S64 : process (Doing_FLBurst,
Doing_Cacheline,
MSize_In,
Size_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
If (Doing_FLBurst = '1') Then
case Size_In is
when "1100" => -- 128-bit burst request
mult_by_1 <= '0';
mult_by_2 <= '1';
-- when "1010" => -- 32-bit burst request
--
-- mult_by_1 <= '1';
--
-- when "1011" => -- 64-bit burst request
--
-- mult_by_1 <= '1';
when others => -- default to 32 or 64 bit burst request
null; -- use defaults
-- mult_by_1 <= '0';
-- mult_by_2 <= '1';
end case;
Elsif (Doing_Cacheline = '1') Then
case MSize_In is
when "00" => -- 32-bit master/64-bit Slave
mult_by_1 <= '0';
mult_by_2 <= '1';
-- when "01" => -- 64-bit Master/64-bit Slave
--
-- mult_by_1 <= '1';
when others => -- 128 bit master/64-bit Slave
null; -- use defaults
-- mult_by_1 <= '1';
end case;
End if;
end process GET_MULT_BY_S64;
end generate BLE_64_BIT_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_128_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 128. Will always be 1 in this case.
--
--
------------------------------------------------------------
BLE_128_BIT_SLAVE : if (C_NATIVE_DWIDTH = 128) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S128
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
-- 128-bit Slave can transfer 4 wds per data beat
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S128 : process (Size_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (1 dbeat minimum)
Cline_special_case1 <= '1';
almst_done_cline_value <= "0000";
when "0010" => -- Cacheline 8wrds (2 dbeats minimum)
Cline_special_case2 <= '1';
--almst_done_cline_value <= "0000";
almst_done_cline_value <= "0001"; -- special case
when "0011" => -- Cacheline 16wrds (4 dbeats minimum)
almst_done_cline_value <= "0001";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S128;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S128
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 128.
--
-------------------------------------------------------------
GET_MULT_BY_S128 : process (Doing_Cacheline,
MSize_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
if (Doing_Cacheline = '1') Then
case MSize_In is
when "00" => -- 32-bit master/128-bit Slave
mult_by_1 <= '0';
mult_by_4 <= '1';
when "01" => -- 64-bit Master/128-bit Slave
mult_by_1 <= '0';
mult_by_2 <= '1';
when others => -- 128 bit master/128-bit Slave
null; -- use defaults
-- mult_by_1 <= '1';
end case;
End if;
end process GET_MULT_BY_S128;
end generate BLE_128_BIT_SLAVE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: MULT_CNTR
--
-- Process Description:
-- This process implements a shift register that is set at
-- command start to the appropriate multipy value for
-- multi-data beat commands.
-- This is needed to support Burst Length Expansion, a
-- requirement when the requesting Master is wider than the
-- Slave's native data width.
--
-------------------------------------------------------------
MULT_CNTR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
mult_cnt_sreg <= (others => '0');
elsif (Req_Init = '1') then
mult_cnt_sreg(0) <= mult_by_1;
mult_cnt_sreg(1) <= mult_by_2;
mult_cnt_sreg(2) <= '0';
mult_cnt_sreg(3) <= mult_by_4;
Elsif (dbeat_cnt_en = '1' and
dbeat_cnt_done = '1') Then
-- shift the set pulse down shift register
mult_cnt_sreg(0) <= mult_cnt_sreg(1);
mult_cnt_sreg(1) <= mult_cnt_sreg(2);
mult_cnt_sreg(2) <= mult_cnt_sreg(3);
mult_cnt_sreg(3) <= '0';
else
null; -- hold current state
end if;
end if;
end process MULT_CNTR;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: ddr_phy_unisim.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclkdiffio : if phyiconf = 0 generate
ddrclocks0 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad_ds generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), '1');
end generate;
end generate;
ddrclknodiffio : if phyiconf = 1 generate
ddrclocks1 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk1_pad : outpad generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclk1b_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of FDDRRSE : component is true;
attribute syn_noprune of IFDDRRSE : component is true;
attribute syn_noprune of oddrv2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
attribute syn_noprune of oddrc3e : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; odten : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; abits: integer := 14; nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy_wo_pads is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component OBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal cbdqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_rasnr2, ddr_casnr2, ddr_wenr2 : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(nclk-1 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(ncs-1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_cbdqin, ddr_cbdqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqout : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqoen : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_adr : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_adr2 : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar2 : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr data mask
signal ddr_cbdmr : std_logic_vector (dbits/8-1 downto 0); -- ddr checkbit mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_cbdqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(ncs-1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (0 to 11) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7, ddelayb8,
ddelayb9, ddelayb10, ddelayb11);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
HMODE_dll200 : if (tech = virtex4 and MHz >= 210) or (tech = virtex5) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and MHz >= 210) or (tech = virtex5)) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1';
gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120)))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
clk180r <= not mclk;
clkout <= mclk;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clkoutret)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clkoutret) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR port map ( Q => ddr_clk(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddr_clkb(i) <= '0'; -- unused
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt(i) <= odtl(i);
end generate;
ddrbanks : for i in 0 to ncs-1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk180r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
ddr_csb(i) <= ddr_csnr(i);
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk180r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
ddr_cke(i) <= ddr_ckenr(i);
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk180r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
ddr_rasb <= ddr_rasnr;
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk180r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
ddr_casb <= ddr_casnr;
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk180r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
ddr_web <= ddr_wenr;
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clkoutret, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
end generate;
ddr_dm <= ddr_dmr;
bagen : for i in 0 to 1+eightbanks generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk180r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
end generate;
ddr_ba <= ddr_bar;
dagen : for i in 0 to abits-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk180r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
end generate;
ddr_ad <= ddr_adr;
-- DQS generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen_reg : FD port map ( Q => ddr_dqsoen_reg(i), C => clk180r, D => dqsoen);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk90r, D => ddr_dqsoen_reg(i));
end generate;
ddr_dqs_out <= ddr_dqsin;
ddr_dqs_oen <= ddr_dqsoen;
ddr_dqsoutl <= ddr_dqs_in;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clkoutret, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => clkoutret, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clkoutret, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD
generic map (INIT => '1')
port map ( Q => ddr_dqoen(i), C => clkoutret, D => oen);
end generate;
ddr_dq_out <= ddr_dqout;
ddr_dq_oen <= ddr_dqoen;
ddr_dqin_nodel <= ddr_dq_in;
end;
------------------------------------------------------------------
-- Spartan 3A DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.BUFIO;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan3a_ddr2_phy is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of spartan3a_ddr2_phy is
component DCM
generic (CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false);
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal ddr_clk_fbl, ddr_clk_fb_outl : std_ulogic;
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal rclk0b, rclk90b, rclk180b, rclk270b : std_ulogic;
signal rclk0, rclk90, rclk180, rclk270 : std_ulogic;
signal rclk0b_high, rclk90b_high, rclk270b_high : std_ulogic;
signal rclk0_high, rclk90_high, rclk270_high : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr row address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr bank address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqinl : std_logic_vector (dbits*2-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_ulogic;
signal dll1rst : std_ulogic;
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal odtl : std_logic_vector(1 downto 0);
--signals needed for alignment with DQS
signal dm_delay : std_logic_vector (dbits/8-1 downto 0);
signal dqout_delay : std_logic_vector (dbits-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= '1';
elsif rising_edge(clk) then
dll0rst <= '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM
generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64)
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
rstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2
port map (Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2
port map (Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- Generate the DDR clock to be fed back for DQ synchronization
dclkfb0r : ODDR2
port map (Q => ddr_clk_fb_outl, C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclkfb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outl);
-- The above clock fed back for DQ synchronization
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddr_clk_fbl);
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to 1 generate
csn0gen : FD
port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD
port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : FD
port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD
port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : FD
port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_web, ddr_wenr);
bagen : for i in 0 to 1+eightbanks generate
ba0 : FD
port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
addrgen : for i in 0 to 13 generate
addr0 : FD
port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dq_delay : FD
port map ( Q => dm_delay(i), C => clk0r, D => dm(i));
dm0 : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dmr(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm_delay(i), R => gnd, S => gnd);
ddr_bm_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR2
port map ( Q => ddr_dqsin(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd);
doen : FD
port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds
generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
end generate;
-- Phase shift the feedback clock and use it to latch DQ
rstphase : process (ddr_clk_fbl, rst, lockl)
begin
if rst = '0' or lockl = '0' then
dll1rst <= '1';
elsif rising_edge(ddr_clk_fbl) then
dll1rst <= '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg8 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
bufg9 : BUFG port map (I => rclk180, O => rclk180b);
read_dll : DCM
generic map (clkin_period => 8.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "VARIABLE", PHASE_SHIFT => rskew)
port map ( CLKIN => ddr_clk_fbl, CLKFB => rclk90b, DSSEN => gnd, PSCLK => mclk,
PSEN => cal_pll(0), PSINCDEC => cal_pll(1), RST => dll1rst, CLK0 => rclk90,
CLK90 => rclk180); --, CLK180 => rclk270);
-- Data bus
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map (Q0 => dqinl(i+dbits), -- 1-bit output for positive edge of C0
Q1 => dqinl(i), -- 1-bit output for negative edge of C1
C0 => rclk90b, -- 1-bit clock input
C1 => rclk270b, -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd); -- 1-bit set
dinq0 : FD
port map ( Q => dqin(i+dbits), C => rclk180b, D => dqinl(i));
dinq1 : FD
port map ( Q => dqin(i), C => rclk180b, D => dqinl(i+dbits));
dq_delay : FD
port map ( Q => dqout_delay(i), C => clk0r, D => dqout(i));
dout : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dqout(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout_delay(i), R => gnd, S => gnd);
doen : FD
port map (Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad
generic map (tech => virtex4, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
------------------------------------------------------------------
-- Spartan 6 DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM_SP;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.IODELAY2;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan6_ddr2_phy_wo_pads is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0));
end;
architecture rtl of spartan6_ddr2_phy_wo_pads is
component DCM_SP is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false );
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK2X180 : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
CLKFX : out std_ulogic;
CLKFX180 : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
STATUS : out std_logic_vector(7 downto 0);
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
DSSEN : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
RST : in std_ulogic );
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component IODELAY2 is
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75 );
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic );
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoen_reg : std_logic_vector(dbits/8-1 downto 0);
signal ddr_dq_indel : std_logic_vector(dbits-1 downto 0);
signal ckel : std_logic_vector(ncs-1 downto 0);
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal delay_cal : std_ulogic;
signal dcal_started : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mclk <= clk;
-- mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
-- Extend DCM reset signal.
dll0rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & "0";
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM_SP
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "1X", CLKIN_PERIOD => 1000.0/real(MHz) )
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM_SP
generic map ( CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64 )
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
-- Extend DCM reset signal.
dllrstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & "0";
end if;
end process;
-- Delay lock signal.
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR2
port map ( Q => ddr_clk(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd );
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to ncs-1 generate
ddr_odt(i) <= locked and odt(i);
csn0gen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_csb(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => csn(i), D1 => csn(i), R => gnd, S => gnd );
ckel(i) <= cke(i) and locked;
ckegen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_cke(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ckel(i), D1 => ckel(i), R => gnd, S => gnd );
end generate;
rasgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_rasb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => rasn, D1 => rasn, R => gnd, S => gnd );
casgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_casb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => casn, D1 => casn, R => gnd, S => gnd );
wengen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_web, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => wen, D1 => wen, R => gnd, S => gnd );
bagen : for i in 0 to 1+eightbanks generate
ba0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ba(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ba(i), D1 => ba(i), R => gnd, S => gnd );
end generate;
addrgen : for i in 0 to abits-1 generate
addr0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ad(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => addr(i), D1 => addr(i), R => gnd, S => gnd );
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dmgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dm(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm(i), R => gnd, S => gnd );
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dqsreg : FD
port map ( Q => dqsn(i), C => clk180r, D => oe );
dqsgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_out(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd );
doenreg : FD
port map ( Q => dqsoen_reg(i), C => clk180r, D => dqsoen );
doen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_oen(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsoen_reg(i), D1 => dqsoen_reg(i), R => gnd, S => gnd );
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
dqdelay : IODELAY2
generic map ( DATA_RATE => "DDR", DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO" )
port map ( BUSY => open, CAL => delay_cal, CE => cal_en(i/8), CLK => clk0r,
DATAOUT => ddr_dq_indel(i), DATAOUT2 => open, DOUT => open,
IDATAIN => ddr_dq_in(i), INC => cal_inc(i/8),
IOCLK0 => clk0r, IOCLK1 => clk180r,
ODATAIN => gnd, RST => cal_rst, T => vcc, TOUT => open );
din : IDDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( D => ddr_dq_indel(i), C0 => clk0r, C1 => clk180r, CE => vcc,
R => gnd, S => gnd, Q0 => dqin(i), Q1 => dqin(i+dbits) );
dout : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_out(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout(i), R => gnd, S => gnd );
doen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_oen(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => oen, D1 => oen, R => gnd, S => gnd );
end generate;
-- Generate IODELAY calibration command after core reset.
calcmd : process (mclk, rst)
begin
if rst = '0' then
dcal_started <= '0';
delay_cal <= '0';
elsif rising_edge(mclk) then
if mlock = '1' then
dcal_started <= '1';
delay_cal <= not dcal_started;
end if;
end if;
end process;
end architecture;
|
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
ainit: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => ainit,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
ainit: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => ainit,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2874.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02874ent IS
function "+" (I1:Bit) return bit; --- No_Failure_here
function "+" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
END c02s01b00x00p06n05i02874ent;
ARCHITECTURE c02s01b00x00p06n05i02874arch OF c02s01b00x00p06n05i02874ent IS
BEGIN
TESTING: PROCESS
variable k : bit := '0';
BEGIN
k := "+"('1');
assert NOT(k='1')
report "***PASSED TEST: c02s01b00x00p06n05i02874"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s01b00x00p06n05i02874 - Operator symbol as the function designator test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02874arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2874.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02874ent IS
function "+" (I1:Bit) return bit; --- No_Failure_here
function "+" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
END c02s01b00x00p06n05i02874ent;
ARCHITECTURE c02s01b00x00p06n05i02874arch OF c02s01b00x00p06n05i02874ent IS
BEGIN
TESTING: PROCESS
variable k : bit := '0';
BEGIN
k := "+"('1');
assert NOT(k='1')
report "***PASSED TEST: c02s01b00x00p06n05i02874"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s01b00x00p06n05i02874 - Operator symbol as the function designator test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02874arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2874.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02874ent IS
function "+" (I1:Bit) return bit; --- No_Failure_here
function "+" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
END c02s01b00x00p06n05i02874ent;
ARCHITECTURE c02s01b00x00p06n05i02874arch OF c02s01b00x00p06n05i02874ent IS
BEGIN
TESTING: PROCESS
variable k : bit := '0';
BEGIN
k := "+"('1');
assert NOT(k='1')
report "***PASSED TEST: c02s01b00x00p06n05i02874"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s01b00x00p06n05i02874 - Operator symbol as the function designator test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02874arch;
|
------------------------------------------------------------------------------
-- channel.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: channel.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 29 16:59:20 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library channel_v1_00_a;
use channel_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity channel is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Channel_Left_in : in std_logic_vector(23 downto 0);
Channel_Right_in : in std_logic_vector(23 downto 0);
Channel_Left_out : out std_logic_vector(23 downto 0);
Channel_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity channel;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of channel is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity channel_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Channel_Left_in => Channel_Left_in,
Channel_Right_in => Channel_Right_in,
Channel_Left_out => Channel_Left_out,
Channel_Right_out => Channel_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : dp_bank_sdp_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-25 2.0 pvk Updated BRAM data input pin correctly when standard SDP mode is used.
-- Lower bits mapped to DIBDI in standard SDP. In Extra wide SDP
-- configuration, higher 32 bit mapped to DIBDI.
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity dp_bank_sdp_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_SDP_WIDE : integer;
C_RD_AWIDTH : integer;
C_RD_DWIDTH : integer;
C_WR_AWIDTH : integer;
C_WR_DWIDTH : integer);
port (
rst : in std_logic;
wr_clk : in std_logic;
wr_en : in std_logic;
wr_addr : in std_logic_vector(C_WR_AWIDTH-1 downto 0);
din : in std_logic_vector(C_WR_DWIDTH-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rd_addr : in std_logic_vector(C_RD_AWIDTH-1 downto 0);
dout : out std_logic_vector(C_RD_DWIDTH-1 downto 0));
end dp_bank_sdp_v6;
architecture rtl of dp_bank_sdp_v6 is
signal bram_din : std_logic_vector(63 downto 0);
signal bram_dout : std_logic_vector(63 downto 0);
signal bram_wr_addr : std_logic_vector(15 downto 0);
signal bram_rd_addr : std_logic_vector(15 downto 0);
signal bram_we : std_logic_vector(7 downto 0);
constant USE_RAMB36E1 : boolean := ((C_WR_DWIDTH = 64 and C_RD_DWIDTH <= 64) or
(C_RD_DWIDTH = 64 and C_WR_DWIDTH <= 64));
constant USE_RAMB18E1 : boolean := ((C_WR_DWIDTH = 32 and C_RD_DWIDTH <= 32) or
(C_RD_DWIDTH = 32 and C_WR_DWIDTH <= 32));
begin
PORT_64_GEN : if USE_RAMB36E1 generate
begin
process(wr_addr)
constant ADDR_LSB : integer := log2(C_WR_DWIDTH);
constant ADDR_MSB : integer := ADDR_LSB+C_WR_AWIDTH-1;
begin
bram_wr_addr <= (others => '0');
bram_wr_addr(ADDR_MSB downto ADDR_LSB) <= wr_addr;
end process;
process(rd_addr)
constant ADDR_LSB : integer := log2(C_RD_DWIDTH);
constant ADDR_MSB : integer := ADDR_LSB+C_RD_AWIDTH-1;
begin
bram_rd_addr <= (others => '0');
bram_rd_addr(ADDR_MSB downto ADDR_LSB) <= rd_addr;
end process;
SDP_EXTRA_WIDE_GEN : if C_SDP_WIDE = 1 generate
begin
bram_din(C_WR_DWIDTH-1 downto 0) <= din;
bram_din(63 downto C_WR_DWIDTH) <= (others => '0');
end generate SDP_EXTRA_WIDE_GEN;
SDP_STD_GEN : if C_SDP_WIDE = 0 generate
begin
bram_din(32+C_WR_DWIDTH-1 downto 32) <= din;
bram_din(C_WR_DWIDTH-1 downto 0) <= din;
bram_din(31 downto C_WR_DWIDTH) <= (others => '0');
bram_din(63 downto 32+C_WR_DWIDTH) <= (others => '0');
end generate SDP_STD_GEN;
-- process(din)
-- begin
-- bram_din <= (others => '0');
-- bram_din(C_WR_DWIDTH-1 downto 0) <= din;
-- end process;
dout <= bram_dout(C_RD_DWIDTH-1 downto 0);
-- Port A: read
-- Port B: write
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP", -- "SDP" or "TDP"
READ_WIDTH_A => C_RD_DWIDTH+(C_RD_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => 0, -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => 0, -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => C_WR_DWIDTH+(C_WR_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din(31 downto 0), -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout(31 downto 0), -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_rd_addr, -- 16-bit input A port address/Read address input
CLKARDCLK => rd_clk, -- 1-bit input A port clock/Read clock input
ENARDEN => rd_en, -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => x"0", -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din(63 downto 32), -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout(63 downto 32), -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_wr_addr, -- 16-bit input B port address/Write address input
CLKBWRCLK => wr_clk, -- 1-bit input B port clock/Write clock input
ENBWREN => wr_en, -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => C_RD_DWIDTH+(C_RD_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => 0, -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => 0, -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => C_WR_DWIDTH+(C_WR_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din(31 downto 0), -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout(31 downto 0), -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_rd_addr(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => rd_clk,
ENARDEN => rd_en, -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => x"0", -- 4-bit input A port write enable input
DINBDIN => bram_din(63 downto 32), -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout(63 downto 32), -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_wr_addr(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => wr_clk,
ENBWREN => wr_en, -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => x"FF" -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate PORT_64_GEN;
end rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22688)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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bMiB5zACYbcey0JmybE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22688)
`protect data_block
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faocuh6e8Kd8s/fkZt8HeOD8ZDZ9wuUoKuNpq9U42L7njfOnNVtH0Y0ifma87dM7svaldSuHSACN
m5aJviiWWUxSVuwno1E8EQlRkRYGhFvMl5udI8yIJ8o3w7DxddgCsbw1fROZDrllskm15TkEr/Jk
tqnAnMNTs4JBRJZeG8AC0FKRKHYuGyFQVtaUfgfsaFv/C8UTp4jev7veCD4nXwF5Y0WE1j1s9UPa
Mv8=
`protect end_protected
|
-- $Id: rgbdrv_3x2mux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_3x2mux - syn
-- Description: rgbled driver: mux three 2bit inputs
--
-- Dependencies: xlib/iob_reg_o_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version (derived from rgbdrv_3x4mux)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv2; -- red data
DATG : in slv2; -- green data
DATB : in slv2; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3 -- pad-o: rgb led 1
);
end rgbdrv_3x2mux;
architecture syn of rgbdrv_3x2mux is
signal R_LED : slv4 := "0001"; -- keep 4 states to keep brightness !
signal R_COL : slv3 := "001";
signal R_DIM : slbit := '1';
signal RGB0 : slv3 := (others=>'0');
signal RGB1 : slv3 := (others=>'0');
begin
IOB_RGB0: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0);
IOB_RGB1: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_LED <= "0001";
R_COL <= "001";
R_DIM <= '1';
else
if CE_USEC = '1' then
R_DIM <= not R_DIM;
if R_DIM = '1' then
R_COL <= R_COL(1) & R_COL(0) & R_COL(2);
if R_COL(2) = '1' then
R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3);
end if;
end if;
end if;
end if;
end if;
end process proc_regs;
proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB)
begin
RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0);
RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0);
RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0);
RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1);
RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1);
RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1);
end process proc_mux;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_204;
architecture augh of cmp_204 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_204;
architecture augh of cmp_204 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_0;
ARCHITECTURE system_vga_buffer_1_0_arch OF system_vga_buffer_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_0;
ARCHITECTURE system_vga_buffer_1_0_arch OF system_vga_buffer_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_0_arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rgbfifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END rgbfifo;
ARCHITECTURE spartan6 OF rgbfifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rgbfifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END rgbfifo;
ARCHITECTURE spartan6 OF rgbfifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rgbfifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END rgbfifo;
ARCHITECTURE spartan6 OF rgbfifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
use work.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity standalone_programmer is
Port (
-- cartridge address
cart_nINFC,
cart_nINFD,
cart_ROMQA : out std_logic;
cart_A : out std_logic_vector (13 downto 0);
-- cartridge data
cart_D : inout std_logic_vector(7 downto 0);
-- cartridge clock and memory control
cart_PHI0,
cart_16MHZ,
cart_RnW,
cart_nOE,
cart_nOE2 : out std_logic;
-- avr SPI signals
avr_MOSI,
avr_SCK,
cpld_SS : in std_logic;
avr_MISO : out std_logic
--DEBUG avr_MISO2 : in std_logic
);
end standalone_programmer;
architecture Behavioural of standalone_programmer is
--DEBUG signal avr_MISO : std_logic; --DEBUG
--
signal CTL : std_logic_vector (6 downto 0);
signal A : std_logic_vector (15 downto 0);
signal D_from_SPI : std_logic_vector(7 downto 0);
signal D_from_cart : std_logic_vector (7 downto 0);
signal spi_bit_count : std_logic_vector (4 downto 0) := "00000";
signal memory_access : std_logic := '0';
signal read_nwrite : std_logic := '1';
begin
-- hackily using the AVR's SPI clock for both the PHI0 and 16MHZ lines.
cart_PHI0 <= avr_SCK;
cart_16MHZ <= avr_SCK;
-- always drive A, only drive D/nOE/nOE2 during memory access
cart_ROMQA <= A(14);
cart_A <= A(13 downto 0);
cart_RnW <= read_nwrite;
-- nINFC and nINFD for when we're accessing &FCxx or &FDxx
cart_nINFC <= '0' when (memory_access = '1' and A(15 downto 8) = x"FC" and avr_SCK = '1') else '1';
cart_nINFD <= '0' when (memory_access = '1' and A(15 downto 8) = x"FD" and avr_SCK = '1') else '1';
-- nOE for A(15:14) in "00", "01"
cart_nOE <= '0' when (memory_access = '1' and A(15) = '0' and avr_SCK = '1') else '1';
-- nOE2 for A(15:14) = "10"
cart_nOE2 <= '0' when (memory_access = '1' and A(15 downto 14) = "10" and avr_SCK = '1') else '1';
-- D driven on writes, tristated on reads
cart_D <= D_from_SPI when memory_access = '1' and read_nwrite = '0' else "ZZZZZZZZ";
-- AVR sends 0x80 for read, 0x00 for write
read_nwrite <= CTL(6);
process (avr_SCK, cpld_SS)
begin
-- SPI timing with AVR defaults: CPOL=0, CPHA=0
-- Sample on SCK rising edge, setup on SCK falling edge.
-- SS \_____________________________________________________________________________...
-- SCK ___/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__
-- MOSI x00000111111222222333333444444555555666666777777000000111111222222333333444444...
-- MISO x00000111111222222333333444444555555666666777777000000111111222222333333444444...
-- This means we get barely any time to think in between bytes -- just the high period of
-- SCK after the 8th bit. We need to set up MISO on the falling edge of avr_SCK.
if cpld_SS = '1' then
-- asynchronous reset (must not happen on an avr_SCK edge)
CTL <= "1111111";
spi_bit_count <= "00000";
A <= "0000000000000000";
D_from_SPI <= "00000000";
elsif rising_edge(avr_SCK) then
-- to read: clock in "1000000" & A15, A14-7, A6-0 & 0, 0x00, and the data byte will come out in the 4th byte
-- to write: clock in "0000000" & A15, A14-7 A6-0 & 0, D, and the byte will be written on the final clock.
-- increment the count each time
spi_bit_count <= std_logic_vector(unsigned(spi_bit_count) + 1);
-- clock in a bit, depending on spi_bit_count
if spi_bit_count(4 downto 3) = "00" then
-- reading CTL (outputting 1 on MISO) and A15
CTL <= CTL(5 downto 0) & A(15);
A(15) <= avr_MOSI;
elsif spi_bit_count(4 downto 3) = "01" or spi_bit_count(4 downto 3) = "10" then
-- reading A (outputting 0 on MISO)
if spi_bit_count /= "10111" then
A(14 downto 0) <= A(13 downto 0) & avr_MOSI;
end if;
else
-- reading or writing data; spi_bit_count(4 downto 3) = "11"
D_from_SPI <= D_from_SPI(6 downto 0) & avr_MOSI;
if spi_bit_count = "11111" then
-- we've just received the last bit of the data byte, which means we should
end if;
end if;
end if;
if cpld_SS = '1' then
avr_MISO <= '0';
D_from_cart <= "10101010";
memory_access <= '0';
elsif falling_edge(avr_SCK) then
-- We always update MISO on an avr_SCK falling edge.
-- memory_access is set to 1 on the falling edge when the avr is setting up
-- the final bit of the address, then back to 0 on the next falling edge.
-- This is so we generate a clean pulse on cart_nOE and cart_nOE2, by ANDing
-- with avr_SCK.
memory_access <= '0';
if spi_bit_count(4 downto 3) = "00" then
-- reading CTL, outputting 1
avr_MISO <= '1';
elsif spi_bit_count(4 downto 3) = "01" or spi_bit_count(4 downto 3) = "10" then
-- reading A, outputting 0
avr_MISO <= '0';
if spi_bit_count = "10110" and read_nwrite = '1' then
-- the AVR is setting up a 0 bit (it's finished sending us the address), so we set
-- memory_access = '1', and the access will occur once avr_SCK goes high again.
memory_access <= '1';
elsif spi_bit_count = "10111" and read_nwrite = '1' then
D_from_cart <= cart_D; -- actually perform the read
end if;
else
-- reading out data register (happens even when nothing is going on)
avr_MISO <= D_from_cart(7);
D_from_cart <= D_from_cart(6 downto 0) & '0';
if spi_bit_count = "11111" and read_nwrite = '0' then
-- we're about to receive the last data bit, and we're doing a write, so we need
-- to get ready to enable nOE etc.
memory_access <= '1';
end if;
end if;
end if;
end process;
end Behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3096.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03096ent IS
END c05s01b00x00p08n01i03096ent;
ARCHITECTURE c05s01b00x00p08n01i03096arch OF c05s01b00x00p08n01i03096ent IS
attribute ill1 : real;
signal s1, s2 : integer;
attribute notdesig of s1 : signal is 10.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03096 - The attribute designator does not denote an attribute."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3096.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03096ent IS
END c05s01b00x00p08n01i03096ent;
ARCHITECTURE c05s01b00x00p08n01i03096arch OF c05s01b00x00p08n01i03096ent IS
attribute ill1 : real;
signal s1, s2 : integer;
attribute notdesig of s1 : signal is 10.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03096 - The attribute designator does not denote an attribute."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3096.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03096ent IS
END c05s01b00x00p08n01i03096ent;
ARCHITECTURE c05s01b00x00p08n01i03096arch OF c05s01b00x00p08n01i03096ent IS
attribute ill1 : real;
signal s1, s2 : integer;
attribute notdesig of s1 : signal is 10.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03096 - The attribute designator does not denote an attribute."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03096arch;
|
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`protect end_protected
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF: out std_logic;
-- significant bit set flag
SBF: out std_logic
);
end DPATH;
architecture Beh of DPATH is
signal ACCUM: std_logic_vector(7 downto 0);
signal res_add: std_logic_vector(7 downto 0);
signal res_sub: std_logic_vector (7 downto 0);
signal t_zf, t_sbf: std_logic;
constant LOAD: std_logic_vector(2 downto 0) := "000";
constant ADD: std_logic_vector(2 downto 0) := "010";
constant SUB: std_logic_vector(2 downto 0) := "011";
Begin
res_add <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) + CONV_INTEGER(OP1), 8);
res_sub <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) - CONV_INTEGER(OP1), 8);
REGA: process (EN, OT, OP1, res_add, res_sub)
begin
if rising_edge(EN) then
case OT is
when LOAD => ACCUM <= OP1;
when ADD => ACCUM <= res_add;
when SUB => ACCUM <= res_sub;
when others => null;
end case;
end if;
end process;
FLAGS: process(ACCUM)
begin
if ACCUM = (ACCUM'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
if ACCUM(7) = '1' then
t_sbf <= '1';
else
t_sbf <= '0';
end if;
end process;
RES <= ACCUM;
ZF <= t_zf;
SBF <= t_sbf;
End Beh; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(3 downto 0);
mem_ras_n : out std_logic_vector(0 downto 0);
mem_cas_n : out std_logic_vector(0 downto 0);
mem_we_n : out std_logic_vector(0 downto 0);
mem_reset_n : out std_logic;
mem_dq : inout std_logic_vector(31 downto 0);
mem_dqs : inout std_logic_vector(3 downto 0);
mem_dqs_n : inout std_logic_vector(3 downto 0);
mem_odt : out std_logic_vector(0 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(127 downto 0);
avl_wdata : in std_logic_vector(127 downto 0);
avl_be : in std_logic_vector(15 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of ddr3ctrl1 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_reset_n <= '0';
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_ca : out std_logic_vector(9 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(1 downto 0);
mem_dq : inout std_logic_vector(15 downto 0);
mem_dqs : inout std_logic_vector(1 downto 0);
mem_dqs_n : inout std_logic_vector(1 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(63 downto 0);
avl_wdata : in std_logic_vector(63 downto 0);
avl_be : in std_logic_vector(7 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of lpddr2ctrl1 is
signal lafi_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_reset_n <= '0';
afi_reset_export_n <= '0';
mem_ca <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
avl_ready <= '1';
avl_rdata_valid <= '1';
avl_rdata <= (others => '0');
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
variable vclk,vhclk: std_logic := '0';
begin
lafi_clk <= vclk;
afi_half_clk <= vhclk;
wait for 4 ns;
vclk := not vclk;
if vclk='0' then vhclk:=not vhclk; end if;
end process;
rstproc: process
begin
afi_reset_n <= '0';
for x in 1 to 10 loop
wait until rising_edge(lafi_clk);
end loop;
afi_reset_n <= '1';
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_cache
-- File: mmu_cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gndv: std_logic_vector(1 downto 0);
begin
gndv <= (others => '0');
icache0 : mmu_icache
generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart,
mmuen)
port map (rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
dcache0 : mmu_dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart,
itlbnum, dtlbnum, tlb_type,
memtech, cached, mmupgsz, smp, mmuen)
port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest
)
port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
mmugen : if mmuen = 1 generate
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, 1)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi,
gndv(0), gndv(1 downto 0), open);
end generate;
nommu : if mmuen = 0 generate
mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero;
end generate;
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2,
mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end;
|
----------------------------------------
-- Datapath : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 20/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Datapath is
port (
clock, reset : in std_logic; -- clock and reset signals
ExDData, ExDAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, ExDWrite : in std_logic; -- Program / Execution mode
RF_Write : in std_logic; -- Reg File write enable
MemRead, MemWrite : in std_logic; -- Read / Write from / to the data memory
OpSel, ALUc, ALUz, Cen, Zen,ALUOp : in std_logic; -- ALU & Flag block signals
M1_Sel, M2_Sel, M5_Sel, M3_Sel : in std_logic; -- Mux select lines
M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel : in std_logic_vector(1 downto 0); -- Mux select lines
Instruction : out std_logic_vector(15 downto 0); -- Instruction to the CP
ExIWrite : in std_logic; -- Write to Instruction Mem
ExIData, ExIAddress : in std_logic_vector(15 downto 0) -- External instruction and address for programing
);
end Datapath;
architecture behave of Datapath is
--==================================== Components ====================================================--
component alu16 is -- ALU block
port (
operand1 : in std_logic_vector(15 downto 0); -- 16 std_logic input1
operand2 : in std_logic_vector(15 downto 0); -- 16 std_logic input2
op_code : in std_logic; -- 1 std_logic opcode
result : out std_logic_vector(15 downto 0); -- 16 std_logic ALU result
carry : out std_logic; -- carry flag
zero : out std_logic; -- zero flag
alu_equ : out std_logic -- comparator output
);
end component;
component incr is --increa
port (
input : in std_logic_vector(15 downto 0); -- 16 std_logic input
output : out std_logic_vector(15 downto 0) -- 16 std_logic output
);
end component;
component FlagBlock is -- FR block
port (
clock : in std_logic; -- clock signal
reset : in std_logic; -- reset signal
ALUc : in std_logic; -- conditional carry flag change
ALUz : in std_logic; -- conditional zero flag change
Cen : in std_logic; -- enable carry flag change
Zen : in std_logic; -- enable zero flag change
ALUop : in std_logic; -- unconditional ALU operation
ALUcout : in std_logic; -- the carry out from ALU
ALUzout : in std_logic; -- the zero out from ALU
ALUvalid : out std_logic; -- whether the ALU output is valid or not
FR : out std_logic_vector(1 downto 0) -- Flag register
);
end component;
component Memory is -- Memory block
port (
clock : in std_logic; -- clock
write : in std_logic; -- write to the memory
read : in std_logic; -- read from the memory
address : in std_logic_vector(15 downto 0); -- address of the memory being read
data_in : in std_logic_vector(15 downto 0); -- data input
data_out : out std_logic_vector(15 downto 0) -- data output
);
end component;
component mux2to1bit is -- 2:1 Mux (1 bit) block
port (
input0 : in std_logic;
input1 : in std_logic;
output : out std_logic;
sel : in std_logic
);
end component;
component mux2to1 is -- 2:1 Mux block
generic (
nbits : integer
);
port (
input0 : in std_logic_vector(nbits-1 downto 0);
input1 : in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel : in std_logic
);
end component;
component mux4to1 is -- 4:1 Mux block
generic (
nbits : integer
);
port (
input0, input1, input2, input3: in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel0, sel1 : in std_logic
);
end component;
component mux8to1 is -- 8:1 Mux block
generic (
nbits : integer
);
port (
input0, input1, input2, input3, input4, input5, input6, input7 : in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel0, sel1, sel2 : in std_logic
);
end component;
component reg is -- Register
generic (
nbits : integer
);
port (
reg_in : in std_logic_vector(nbits-1 downto 0); -- register input
reg_out : out std_logic_vector(nbits-1 downto 0); -- register output
clock : in std_logic; -- clock signal
write : in std_logic; -- write enable signal
reset : in std_logic -- reset signal
);
end component;
component regfile is -- Register File block
port (
clock : in std_logic;
reset : in std_logic;
InA : in std_logic_vector(2 downto 0); --address for selecting A
InB : in std_logic_vector(2 downto 0); --address for selecting B
dataA : out std_logic_vector(15 downto 0); --read the data into reg A
dataB : out std_logic_vector(15 downto 0);--read the data into reg B
dataIn : in std_logic_vector(15 downto 0);---data to be written into the register
WritEn : in std_logic; ---enable for writing
WriteAdr : in std_logic_vector(2 downto 0) --to select the destination register
);
end component;
component SE is -- Sign Extender block
generic (
initial : integer; -- number of input std_logics
final : integer -- number of output std_logics
);
port (
data_in : in std_logic_vector(initial-1 downto 0); -- data input
data_out : out std_logic_vector(final-1 downto 0) -- data output
);
end component;
component CondBlock is
port (
OpCode : in std_logic_vector(5 downto 0); -- Opcode (0-2 and 12-15) bits
ALU_val : in std_logic; -- valid signal from ALU
Curr_RFWrite : in std_logic; -- Current value of RF write
Nxt_RFWrite : out std_logic -- Next value for RF write
);
end component;
component PCImmAdd is
port (
input1 : in std_logic_vector(15 downto 0); -- 16 std_logic inputs
input2 : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0) -- 16 std_logic output
);
end component;
component FrwdBlock is
port (
clock, reset : in std_logic;
iteration : in std_logic_vector(3 downto 0);
MA_M4_Sel, WB_M4_Sel : in std_logic_vector(1 downto 0); -- M4 sel lines
MA_RFWrite, WB_RFWrite : in std_logic; -- RF write
OpCode : in std_logic_vector(5 downto 0); -- Opcode (12-15 & 0-1)
Curr_M7_Sel, Curr_M8_Sel : in std_logic_vector(1 downto 0); -- Current Mux select lines
MA_Ir911, WB_Ir911, Ir35, Ir68, Ir911 : in std_logic_vector(2 downto 0); -- Source and destination registers
MA_ALUout, MA_MemOut, WB_ALUout, WB_MemOut : in std_logic_vector(15 downto 0); -- ALUout and Data memory out
M7_In, M8_In : out std_logic_vector(15 downto 0); -- Inputs for M7 and M8
Nxt_M7_Sel, Nxt_M8_Sel : out std_logic_vector(1 downto 0) -- Updated Mux select lines
);
end component;
component LmSmBlock is
port (
clock, reset : in std_logic;
Ir0_8 : in std_logic_vector(8 downto 0);
Ir12_15 : in std_logic_vector(3 downto 0);
M1_Sel, M2_Sel, M3_Sel : in std_logic;
M4_Sel, M9_Sel, M7_Sel, M8_Sel : in std_logic_vector(1 downto 0);
PC_en, IF_en, MemRead, MemWrite, RF_Write : in std_logic;
M1_Sel_ls, M2_Sel_ls, M3_Sel_ls : out std_logic;
M4_Sel_ls, M9_Sel_ls, M7_Sel_ls, M8_Sel_ls : out std_logic_vector(1 downto 0);
PC_en_ls, IF_en_ls, MemRead_ls, MemWrite_ls, RF_Write_ls : out std_logic;
LM_reg, SM_reg : out std_logic_vector(2 downto 0);
iteration : out integer
);
end component;
--==================================== Signals ====================================================--
signal MA_in, MA_out : std_logic_vector(70 downto 0); -- Memory Access pipeline register
signal EX_in, EX_out : std_logic_vector(90 downto 0); -- Execute pipeline register
signal RR_in, RR_out : std_logic_vector(109 downto 0); -- Register Read pipeline register
signal DC_in, DC_out : std_logic_vector(64 downto 0); -- Decode pipeline register
signal IF_in, IF_out : std_logic_vector(31 downto 0); -- Fetch pipeline register
signal ZPad : std_logic_vector(15 downto 0); -- Zero padded output of WB(63-55)
signal M3_out : std_logic_vector(2 downto 0);
signal M4_out, incr_out: std_logic_vector(15 downto 0);
signal WB_PC, WB_ALUout, WB_MemOut : std_logic_vector(15 downto 0);
signal WB_M4_Sel : std_logic_vector(1 downto 0);
signal WB_M3_Sel : std_logic;
signal WB_LM_DestAdr, WB_DestAdr : std_logic_vector(2 downto 0);
signal WB_RFWrite : std_logic;
signal M9_out: std_logic_vector(15 downto 0);
signal MA_ALUout, MA_PC, MA_A, MA_B: std_logic_vector(15 downto 0);
signal DMem_Write, DMem_Read : std_logic;
signal MA_M9_Sel : std_logic_vector(1 downto 0);
signal MuxExDA_out, MuxExDD_out : std_logic_vector(15 downto 0); -- Data Memory input Muxes
signal MuxExDW_out : std_logic;
signal DMemory_out, MA_Memout : std_logic_vector(15 downto 0); -- Data Memory output
signal PC_en : std_logic; -- Enable PC updation
signal PC_out, PC_incr_out : std_logic_vector(15 downto 0); -- PC output
signal IF_en : std_logic; -- Enable IF updation
signal IF_PC : std_logic_vector(15 downto 0); -- IF stage PC
signal MuxExIW_out,IMem_Read : std_logic; -- Instruction Memory write
signal MuxExID_out, MuxExIA_out : std_logic_vector(15 downto 0); -- Instruction Memory input Muxes
signal IMemory_out : std_logic_vector(15 downto 0); -- Instruction Memory output
signal Ir12_15 : std_logic_vector(3 downto 0); -- Instruction (12 - 15) bits
signal Ir9_11 : std_logic_vector(2 downto 0); -- Instruction (9 - 11) bits
signal Ir0_8 : std_logic_vector(8 downto 0); -- Instruction (0 - 8) bits
signal DC_en : std_logic; -- Enable DC updation
signal RR_en : std_logic; -- Enable RR updation
signal RRead_SrcB1, RRead_SrcB2, RRead_SrcA1, RRead_SrcA2 : std_logic_vector(2 downto 0); -- Register Source Mux inputs
signal M1_out, M2_out : std_logic_vector(2 downto 0); -- Register Source Mux outputs
signal RR_M1_Sel, RR_M2_Sel, RR_M5_Sel : std_logic; -- Register Source Mux select lines
signal RR_PC, RR_SE6_out, RR_SE9_out, M5_out : std_logic_vector(15 downto 0); -- Sign extender outputs
signal RFoutA, RFoutB : std_logic_vector(15 downto 0); -- Register file outputs
signal JB_addr : std_logic_vector(15 downto 0); -- Jump / Branch address
signal LM_Slct : std_logic_vector(2 downto 0); -- LM select from LM/SM block
signal EX_en : std_logic; -- Enable EX updation
signal EX_B , M7_out : std_logic_vector(15 downto 0); -- M7 inputs and output
signal EX_SE6_out, EX_A, M8_out : std_logic_vector(15 downto 0); -- M8 inputs and output
signal EX_PC, PCImm, M6_out : std_logic_vector(15 downto 0); -- M6 inputs and output
signal EX_M6_Sel, EX_M7_Sel, EX_M8_Sel : std_logic_vector(1 downto 0); -- Mux select lines
signal EX_OpCode : std_logic_vector(5 downto 0); -- Opcode (0-1, 12-15) bits
signal EX_ALU_val, Curr_RFWrite, Nxt_RFWrite : std_logic; -- Enable EX updation
signal EX_OpSel, cout, zout, ALUeq : std_logic; -- ALU signals
signal EX_ALUout : std_logic_vector(15 downto 0); -- ALU output
signal EX_ALUc, EX_ALUz, EX_Cen, EX_Zen, EX_ALUop, ALU_val : std_logic; -- ALU signals
signal FR_out : std_logic_vector(1 downto 0); -- Flag Register
signal MA_en : std_logic; -- Enable MA updation
signal MA_Ir911, WB_Ir911, EX_Ir35, EX_Ir68, EX_Ir911 : std_logic_vector(2 downto 0); -- Forwarding block input
signal M7_In, M8_In : std_logic_vector(15 downto 0); -- Mux Inputs
signal Nxt_M7_Sel, Nxt_M8_Sel, MA_M4_Sel : std_logic_vector(1 downto 0); -- Mux Select lines
signal MA_RFWrite : std_logic;
signal M1_Sel_ls, M2_Sel_ls, M3_Sel_ls : std_logic;
signal M4_Sel_ls, M9_Sel_ls, M7_Sel_ls, M8_Sel_ls : std_logic_vector(1 downto 0);
signal PC_en_ls, IF_en_ls, MemRead_ls, MemWrite_ls, RF_Write_ls : std_logic;
signal LM_reg, SM_reg : std_logic_vector(2 downto 0);
signal iteration : integer range 0 to 8:= 0;
signal EX_ite : std_logic_vector(3 downto 0);
--================================================================================================--
begin -- behave
--==================================== Write back ====================================================--
ZPad <= MA_out(31 downto 23) & b"0000000";
M3 : mux2to1 generic map (3) port map (WB_DestAdr, WB_LM_DestAdr, M3_out, WB_M3_Sel);
M4 : mux4to1 generic map (16) port map (WB_MemOut, WB_ALUout, incr_out, ZPad, M4_out, WB_M4_Sel(0), WB_M4_Sel(1));
wbinc: incr port map(WB_PC, incr_out);
WB_PC <= MA_out(22 downto 7);
WB_M4_Sel <= MA_out(33 downto 32);
WB_ALUout <= MA_out(54 downto 39);
WB_MemOut <= MA_out(70 downto 55);
WB_M3_Sel <= MA_out(0);
WB_LM_DestAdr <= MA_out(6 downto 4);
WB_DestAdr <= MA_out(3 downto 1);
WB_RFWrite <= MA_out(34);
WB_Ir911 <= MA_out(3 downto 1);
--================================= Memory Access ====================================================--
reg_MA : reg generic map (71) port map (MA_in, MA_out, clock, MA_en, reset);
M9 : mux4to1 generic map (16) port map (MA_A, MA_B, MA_PC, X"0000", M9_out, MA_M9_Sel(0), MA_M9_Sel(1));
DataMem : Memory port map (clock, MuxExDW_out, DMem_Read, MuxExDA_out, MuxExDD_out, DMemory_out);
MuxExDA : mux2to1 generic map (16) port map (MA_ALUout, ExDAddress, MuxExDA_out, mode);
MuxExDD : mux2to1 generic map (16) port map (M9_out, ExDData, MuxExDD_out, mode);
MuxExDW : mux2to1bit port map (DMem_Write, ExDWrite, MuxExDW_out, mode);
MA_ALUout <= EX_out(90 downto 75);
DMem_Write <= EX_out(70);
DMem_Read <= EX_out(69);
MA_M9_Sel <= EX_out(68 downto 67);
MA_PC <= EX_out(22 downto 7);
MA_B <= EX_out(66 downto 51);
MA_A <= EX_out(50 downto 35);
MA_M4_Sel <= EX_out(33 downto 32);
MA_RFWrite <= EX_out(34);
MA_Memout <= DMemory_out;
MA_en <= '1'; -- Will be modified by LM/SM block
MA_Ir911 <= EX_out(3 downto 1);
MA_in(0) <= EX_out(0); -- M3_Sel
MA_in(3 downto 1) <= EX_out(3 downto 1); -- 9-11
MA_in(6 downto 4) <= EX_out(6 downto 4); -- LM_Sel
MA_in(22 downto 7) <= MA_PC; -- PC
MA_in(31 downto 23) <= EX_out(31 downto 23); -- 0-8
MA_in(33 downto 32) <= EX_out(33 downto 32); -- M4_Sel
MA_in(34) <= EX_out(34); -- RF_Write
MA_in(38 downto 35) <= EX_out(74 downto 71); -- OpCode
MA_in(54 downto 39) <= EX_out(90 downto 75); -- ALUout
MA_in(70 downto 55) <= DMemory_out; -- Data Memory Out
--======================================= Execution =================================================--
reg_EX : reg generic map (91) port map (EX_in, EX_out, clock, EX_en, reset);
M7 : mux4to1 generic map (16) port map (x"0000", x"0001", EX_B , M7_In, M7_out, Nxt_M7_Sel(0), Nxt_M7_Sel(1));
M8 : mux4to1 generic map (16) port map (EX_SE6_out, EX_A, M8_In, MA_ALUout, M8_out, Nxt_M8_Sel(0), Nxt_M8_Sel(1));
M6 : mux4to1 generic map (16) port map (PC_incr_out, DMemory_out, PCImm, x"0000", M6_out, EX_M6_Sel(0), EX_M6_Sel(1));
ConcBlock : CondBlock port map ( EX_OpCode, EX_ALU_val, Curr_RFWrite, Nxt_RFWrite);
EX_SE6 : SE generic map (6, 16) port map (RR_out(28 downto 23), EX_SE6_out);
-------------------------- ALU ----------------------------------------------------------------------------
ALU : alu16 port map (M7_out, M8_out, EX_OpSel, EX_ALUout, cout, zout, ALUeq);
-------------------------- FlagBlock ----------------------------------------------------------------------
FR : FlagBlock port map (clock, reset, EX_ALUc, EX_ALUz, EX_Cen, EX_Zen, EX_ALUop, cout, zout, EX_ALU_val, FR_out);
-------------------------- Forwarding Block ----------------------------------------------------------------------------
FB : FrwdBlock port map (clock, reset, EX_ite, MA_M4_Sel, WB_M4_Sel, MA_RFWrite, WB_RFWrite, EX_OpCode, EX_M7_Sel, EX_M8_Sel, MA_Ir911, WB_Ir911, EX_Ir35, EX_Ir68, EX_Ir911, MA_ALUout, MA_MemOut, WB_ALUout, WB_MemOut, M7_In, M8_In, Nxt_M7_Sel, Nxt_M8_Sel );
EX_B <= RR_out(66 downto 51);
EX_A <= RR_out(50 downto 35);
EX_M7_Sel <= RR_out(72 downto 71);
EX_M8_Sel <= RR_out(74 downto 73);
EX_M6_Sel <= RR_out(97 downto 96);
PCImm <= RR_out(95 downto 80);
EX_PC <= RR_out(22 downto 7);
Curr_RFWrite <= RR_out(34);
EX_OpSel <= RR_out(75);
EX_ALUop <= RR_out(105);
EX_ALUc <= RR_out(76);
EX_ALUz <= RR_out(77);
EX_Cen <= RR_out(78);
EX_Zen <= RR_out(79);
EX_Ir35 <= RR_out(28 downto 26);
EX_Ir68 <= RR_out(31 downto 29);
EX_Ir911<= RR_out(3 downto 1);
EX_OpCode <= RR_out(104 downto 101) & RR_out(24 downto 23);
EX_en <= '1'; -- Will be modified by LM/SM block
EX_in(0) <= RR_out(0); -- M3_Sel
EX_in(3 downto 1) <= RR_out(3 downto 1); -- 9-11
EX_in(6 downto 4) <= RR_out(6 downto 4); -- LM_Sel
EX_in(22 downto 7) <= RR_out(22 downto 7); -- PC
EX_in(31 downto 23) <= RR_out(31 downto 23); -- 0-8
EX_in(33 downto 32) <= RR_out(33 downto 32); -- M4_Sel
EX_in(34) <= Nxt_RFWrite; -- RF_Write
EX_in(50 downto 35) <= EX_A; -- RF file out A
EX_in(66 downto 51) <= EX_B; -- RF file out B
EX_in(68 downto 67) <= RR_out(68 downto 67); -- M9_Sel
EX_in(69) <= RR_out(69); -- MemRead
EX_in(70) <= RR_out(70); -- MemWrite
EX_in(74 downto 71) <= RR_out(104 downto 101); -- OpCode
EX_in(90 downto 75) <= EX_ALUout; -- ALUout
EX_ite <= RR_out(109 downto 106);
--======================================== Reg Read =================================================--
reg_RR : reg generic map (110) port map (RR_in, RR_out, clock, RR_en, reset);
M1 : mux2to1 generic map (3) port map (RRead_SrcB1, RRead_SrcB2, M1_out, RR_M1_Sel);
M2 : mux2to1 generic map (3) port map (RRead_SrcA1, RRead_SrcA2, M2_out, RR_M2_Sel);
RRead_SrcB1 <= DC_out(12 downto 10);
RRead_SrcB2 <= DC_out(60 downto 58); --from SM block
RR_M1_Sel <= DC_out(31);
RRead_SrcA1 <= DC_out(9 downto 7);
RRead_SrcA2 <= DC_out(3 downto 1);
RR_M2_Sel <= DC_out(32);
RR_PC <= DC_out(53 downto 38);
RR_SE6 : SE generic map (6, 16) port map (DC_out(9 downto 4), RR_SE6_out);
RR_SE9 : SE generic map (9, 16) port map (DC_out(12 downto 4), RR_SE9_out);
M5 : mux2to1 generic map (16) port map ( RR_SE6_out, RR_SE9_out, M5_out, RR_M5_Sel);
RR_M5_Sel <= DC_out(33);
RF : regfile port map (clock, reset, M2_out, M1_out, RFoutA, RFoutB, M4_out, WB_RFWrite, M3_out);
PCImmAdder : PCImmAdd port map(M5_out, RR_PC, JB_addr);
RR_en <= '1'; -- Will be modified by LM/SM block
RR_in(0) <= DC_out(0); -- M3 Sel
RR_in(3 downto 1) <= DC_out(3 downto 1); -- 9-11
RR_in(6 downto 4) <= LM_Slct; -- LM Sel
RR_in(22 downto 7) <= DC_out(53 downto 38); -- PC
RR_in(31 downto 23) <= DC_out(12 downto 4); -- 0-8
RR_in(33 downto 32) <= DC_out(14 downto 13); -- M4_Sel
RR_in(34) <= DC_out(15); -- RF_Write
RR_in(50 downto 35) <= RFoutA; -- RF file out A
RR_in(66 downto 51) <= RFoutB; -- RF file out B
RR_in(68 downto 67) <= DC_out(17 downto 16); -- M9_Sel
RR_in(69) <= DC_out(18); -- MemRead
RR_in(70) <= DC_out(19); -- MemWrite
RR_in(72 downto 71) <= DC_out(21 downto 20); -- M7_Sel
RR_in(74 downto 73) <= DC_out(23 downto 22); -- M8_Sel
RR_in(75) <= DC_out(24); -- ALU signals
RR_in(76) <= DC_out(25);
RR_in(77) <= DC_out(26);
RR_in(78) <= DC_out(27);
RR_in(79) <= DC_out(28);
RR_in(95 downto 80) <= JB_addr; -- PC+Imm
RR_in(97 downto 96) <= DC_out(30 downto 29); -- M6_Sel
RR_in(98) <= DC_out(31); -- M1, M2, M5 Sel
RR_in(99) <= DC_out(32);
RR_in(100) <= DC_out(33);
RR_in(104 downto 101) <= DC_out(37 downto 34); -- OpCode
RR_in (105) <= DC_out(54); --ALUOp
RR_in (109 downto 106) <= DC_out(64 downto 61);
LM_Slct <= DC_out(57 downto 55); -- From the LM Block
--=========================================== Decode ====================================================--
reg_DC : reg generic map (65) port map (DC_in, DC_out, clock, DC_en, reset);
DC_in(0) <= M3_Sel_ls;
DC_in(3 downto 1) <= Ir9_11;
DC_in(12 downto 4) <= Ir0_8;
DC_in(14 downto 13) <= M4_Sel_ls;
DC_in(15) <= RF_Write_ls;
DC_in(17 downto 16) <= M9_Sel_ls;
DC_in(18) <= MemRead_ls;
DC_in(19) <= MemWrite_ls;
DC_in(21 downto 20) <= M7_Sel_ls;
DC_in(23 downto 22) <= M8_Sel_ls;
DC_in(24) <= OpSel;
DC_in(25) <= ALUc;
DC_in(26) <= ALUz;
DC_in(27) <= Cen;
DC_in(28) <= Zen;
DC_in(30 downto 29) <= M6_Sel;
DC_in(31) <= M1_Sel_ls;
DC_in(32) <= M2_Sel_ls;
DC_in(33) <= M5_Sel;
DC_in(37 downto 34) <= Ir12_15;
DC_in(53 downto 38) <= IF_PC;
DC_in(54) <= ALUOp;
DC_in(57 downto 55) <= LM_reg;
DC_in(60 downto 58) <= SM_reg;
DC_in(64 downto 61) <= std_logic_vector(to_unsigned(iteration,4));
LM_SM : LmSmBlock port map ( clock, reset, Ir0_8, Ir12_15, M1_Sel, M2_Sel, M3_Sel, M4_Sel, M9_Sel, M7_Sel, M8_Sel, '1', '1', MemRead, MemWrite, RF_Write, M1_Sel_ls, M2_Sel_ls, M3_Sel_ls, M4_Sel_ls, M9_Sel_ls, M7_Sel_ls, M8_Sel_ls, PC_en_ls, IF_en_ls, MemRead_ls, MemWrite_ls, RF_Write_ls, LM_reg, SM_reg, iteration);
DC_en <= '1'; -- Will be modified by LM/SM block
--========================================= Fetch ===================================================--
IF_PC <= IF_out(31 downto 16); -- signals going to the next stage
Ir12_15 <= IF_out(15 downto 12);
Ir9_11 <= IF_out(11 downto 9);
Ir0_8 <= IF_out(8 downto 0);
Instruction <= IF_out(15 downto 0); --Instruction passed to the control path
IMem : Memory port map (clock, MuxExIW_out, IMem_Read, MuxExIA_out, MuxExID_out, IMemory_out);
MuxExIA : mux2to1 generic map (16) port map (PC_out, ExIAddress, MuxExIA_out, mode);
MuxExID : mux2to1 generic map (16) port map (X"0000", ExIData, MuxExID_out, mode);
MuxExIW : mux2to1bit port map ('0', ExIWrite, MuxExIW_out, mode);
reg_IF : reg generic map (32) port map (IF_in, IF_out, clock, IF_en, reset);
IF_in(15 downto 0) <= IMemory_out;
IF_in(31 downto 16)<= PC_out;
reg_PC : reg generic map (16) port map (M6_out, PC_out, clock, PC_en, reset);
Finc: incr port map(PC_out, PC_incr_out);
PC_en <= PC_en_ls; -- modified by LM/SM block
IF_en <= IF_en_ls; -- modified by LM/SM block
IMem_Read <= '1'; -- Always read from Instruction Memory
--===========================================================================================================--
end behave;
|
-- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package des_pkg is
component des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end component des;
type ip_matrix is array (0 to 63) of natural range 0 to 63;
constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7,
56, 48, 40, 32, 24, 16, 8, 0,
58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6);
constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25,
32, 0, 40, 8, 48, 16, 56, 24);
type e_matrix is array (0 to 47) of natural range 0 to 31;
constant e_table : e_matrix := (31, 0, 1, 2, 3, 4,
3, 4, 5, 6, 7, 8,
7, 8, 9, 10, 11, 12,
11, 12, 13, 14, 15, 16,
15, 16, 17, 18, 19, 20,
19, 20, 21, 22, 23, 24,
23, 24, 25, 26, 27, 28,
27, 28, 29, 30, 31, 0);
type s_matrix is array (0 to 3, 0 to 15) of integer range 0 to 15;
constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));
constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10),
1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5),
2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15),
3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9));
constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8),
1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1),
2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7),
3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12));
constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15),
1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9),
2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4),
3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14));
constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9),
1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6),
2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14),
3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3));
constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11),
1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8),
2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6),
3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13));
constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1),
1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6),
2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2),
3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12));
constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7),
1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2),
2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8),
3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11));
type pc_matrix is array (0 to 27) of natural range 0 to 63;
constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8,
0, 57, 49, 41, 33, 25, 17,
9, 1, 58, 50, 42, 34, 26,
18, 10, 2, 59, 51, 43, 35);
constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
6, 61, 53, 45, 37, 29, 21,
13, 5, 60, 52, 44, 36, 28,
20, 12, 4, 27, 19, 11, 3);
type p_matrix is array (0 to 31) of natural range 0 to 31;
constant p_table : p_matrix := (15, 6, 19, 20,
28, 11, 27, 16,
0, 14, 22, 25,
4, 17, 30, 9,
1, 7, 23, 13,
31, 26, 2, 8,
18, 12, 29, 5,
21, 10, 3, 24);
type pc2_matrix is array (0 to 47) of natural range 0 to 63;
constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4,
2, 27, 14, 5, 20, 9,
22, 18, 11, 3, 25, 7,
15, 6, 26, 19, 12, 1,
40, 51, 30, 36, 46, 54,
29, 39, 50, 44, 32, 47,
43, 48, 38, 55, 33, 52,
45, 41, 49, 35, 28, 31);
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function s (input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector;
end package des_pkg;
package body des_pkg is
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ip_table( index ) );
end loop;
return result;
end function ip;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ipn_table( index ) );
end loop;
return result;
end function ipn;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( e_table( index ) );
end loop;
return result;
end function e;
function s ( input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector is
variable int : std_logic_vector(0 to 1);
variable i : integer range 0 to 3;
variable j : integer range 0 to 15;
variable result : std_logic_vector(0 to 3);
begin
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 to 4) ) );
result := std_logic_vector( to_unsigned( s_table( i, j ), 4 ) );
return result;
end function s;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 31);
begin
for index IN 0 to 31 loop
result( index ) := input_vector( p_table( index ) );
end loop;
return result;
end function p;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector is
variable intern : std_logic_vector(0 to 47);
variable result : std_logic_vector(0 to 31);
begin
intern := e( input_r ) xor input_key;
result := p( s( intern(0 to 5), s1_table ) & s( intern(6 to 11), s2_table ) & s( intern(12 to 17), s3_table ) &
s( intern(18 to 23), s4_table ) & s( intern(24 to 29), s5_table ) & s( intern(30 to 35), s6_table ) &
s( intern(36 to 41), s7_table ) & s( intern(42 to 47), s8_table ) );
return result;
end function f;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1c_table( index ) );
end loop;
return result;
end function pc1_c;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1d_table( index ) );
end loop;
return result;
end function pc1_d;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( pc2_table( index ) );
end loop;
return result;
end function pc2;
end package body des_pkg;
|
-- a, b, c and d are the inputs
-- sel is the input selection
-- z is the output
ENTITY mux4x1 IS
PORT (a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: IN std_logic;
z: OUT std_logic;
sel: IN std_logic_vector(1 DOWNTO 0));
END mux4x1;
ARCHITECTURE rtl of mux4x1 IS
BEGIN
process(a,b,c,d,sel) begin
case sel is
when "00" => z <= a;
when "01" => z <= b;
when "10" => z <= c;
when "11" => z <= d;
end case;
end process;
END rtl;
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:10:39 PM
-- Design Name:
-- Module Name: LE - LE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LE is
Port (
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end LE;
architecture LE_Func of LE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
signal Temp3 : STD_LOGIC;
signal Temp4 : STD_LOGIC;
signal Temp5 : STD_LOGIC;
begin
Temp1 <= P3 and (not A) and (not B);
Temp2 <= P0 and A;
Temp3 <= P1 and A;
Temp4 <= (not P3) and A and B;
Temp5 <= (not P1) and P0 and B;
X <= (((Temp1 or Temp2) or Temp3) or Temp4) or Temp5;
end LE_Func;
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:10:39 PM
-- Design Name:
-- Module Name: LE - LE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LE is
Port (
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end LE;
architecture LE_Func of LE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
signal Temp3 : STD_LOGIC;
signal Temp4 : STD_LOGIC;
signal Temp5 : STD_LOGIC;
begin
Temp1 <= P3 and (not A) and (not B);
Temp2 <= P0 and A;
Temp3 <= P1 and A;
Temp4 <= (not P3) and A and B;
Temp5 <= (not P1) and P0 and B;
X <= (((Temp1 or Temp2) or Temp3) or Temp4) or Temp5;
end LE_Func;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex;
constant CFG_CLKMUL : integer := (1);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 13:29:42 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.5 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.5 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
gensig_1 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
port_mac_b : in std_ulogic_vector(3 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
gensig_1 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : out std_ulogic_vector(7 downto 0) -- Generated signals, connecting b to a
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_k1_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port_mac : out std_ulogic; -- Macro test 0 k1_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_k1_k2_e
);
end component;
-- ---------
component inst_k1_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port_mac : out std_ulogic; -- Macro test 1 k1_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 1 k1_k4
-- End of Generated Port for Entity inst_k1_k4_e
);
end component;
-- ---------
component inst_k3_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port_mac : out std_ulogic; -- Macro test 2 k3_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 2 k3_k2
-- End of Generated Port for Entity inst_k3_k2_e
);
end component;
-- ---------
component inst_k3_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port_mac : out std_ulogic; -- Macro test 3 k3_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 3 k3_k4
-- End of Generated Port for Entity inst_k3_k4_e
);
end component;
-- ---------
component inst_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_a_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_b_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_t_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal gensig_1 : std_ulogic_vector(7 downto 0);
signal gensig_10 : std_ulogic_vector(7 downto 0);
signal gensig_2 : std_ulogic_vector(7 downto 0);
signal gensig_3 : std_ulogic_vector(7 downto 0);
signal gensig_4 : std_ulogic_vector(7 downto 0);
signal gensig_5 : std_ulogic_vector(7 downto 0);
signal gensig_6 : std_ulogic_vector(7 downto 0);
signal gensig_7 : std_ulogic_vector(7 downto 0);
signal gensig_8 : std_ulogic_vector(7 downto 0);
signal gensig_9 : std_ulogic_vector(7 downto 0);
signal macro_sigc : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9, -- Generated signals, connecting b to a
port_mac_b => macro_sigc -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9 -- Generated signals, connecting b to a
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_k1_k2
inst_k1_k2: inst_k1_k2_e
port map (
port1 => macro_sig1_k1_k2, -- Macro test 0 k1_k2
port2 => macro_sig2_k1_k2, -- Macro test 0 k1_k2
port3 => macro_sign_0, -- Macro test 0 k1_k2
port_mac => macro_sigc(0), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k2 -- Macro test 0 k1_k2
);
-- End of Generated Instance Port Map for inst_k1_k2
-- Generated Instance Port Map for inst_k1_k4
inst_k1_k4: inst_k1_k4_e
port map (
port1 => macro_sig1_k1_k4, -- Macro test 1 k1_k4
port2 => macro_sig2_k1_k4, -- Macro test 1 k1_k4
port3 => macro_sign_1, -- Macro test 1 k1_k4
port_mac => macro_sigc(1), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k4 -- Macro test 1 k1_k4
);
-- End of Generated Instance Port Map for inst_k1_k4
-- Generated Instance Port Map for inst_k3_k2
inst_k3_k2: inst_k3_k2_e
port map (
port1 => macro_sig1_k3_k2, -- Macro test 2 k3_k2
port2 => macro_sig2_k3_k2, -- Macro test 2 k3_k2
port3 => macro_sign_2, -- Macro test 2 k3_k2
port_mac => macro_sigc(2), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k2 -- Macro test 2 k3_k2
);
-- End of Generated Instance Port Map for inst_k3_k2
-- Generated Instance Port Map for inst_k3_k4
inst_k3_k4: inst_k3_k4_e
port map (
port1 => macro_sig1_k3_k4, -- Macro test 3 k3_k4
port2 => macro_sig2_k3_k4, -- Macro test 3 k3_k4
port3 => macro_sign_3, -- Macro test 3 k3_k4
port_mac => macro_sigc(3), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k4 -- Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_k3_k4
-- Generated Instance Port Map for inst_ok_1
inst_ok_1: inst_ok_1_e
;
-- End of Generated Instance Port Map for inst_ok_1
-- Generated Instance Port Map for inst_ok_10
inst_ok_10: inst_ok_10_e
;
-- End of Generated Instance Port Map for inst_ok_10
-- Generated Instance Port Map for inst_ok_2
inst_ok_2: inst_ok_2_e
;
-- End of Generated Instance Port Map for inst_ok_2
-- Generated Instance Port Map for inst_ok_3
inst_ok_3: inst_ok_3_e
;
-- End of Generated Instance Port Map for inst_ok_3
-- Generated Instance Port Map for inst_ok_4
inst_ok_4: inst_ok_4_e
;
-- End of Generated Instance Port Map for inst_ok_4
-- Generated Instance Port Map for inst_ok_5
inst_ok_5: inst_ok_5_e
;
-- End of Generated Instance Port Map for inst_ok_5
-- Generated Instance Port Map for inst_ok_6
inst_ok_6: inst_ok_6_e
;
-- End of Generated Instance Port Map for inst_ok_6
-- Generated Instance Port Map for inst_ok_7
inst_ok_7: inst_ok_7_e
;
-- End of Generated Instance Port Map for inst_ok_7
-- Generated Instance Port Map for inst_ok_8
inst_ok_8: inst_ok_8_e
;
-- End of Generated Instance Port Map for inst_ok_8
-- Generated Instance Port Map for inst_ok_9
inst_ok_9: inst_ok_9_e
;
-- End of Generated Instance Port Map for inst_ok_9
-- Generated Instance Port Map for inst_shadow_1
inst_shadow_1: inst_shadow_1_e
;
-- End of Generated Instance Port Map for inst_shadow_1
-- Generated Instance Port Map for inst_shadow_10
inst_shadow_10: inst_shadow_10_e
;
-- End of Generated Instance Port Map for inst_shadow_10
-- Generated Instance Port Map for inst_shadow_2
inst_shadow_2: inst_shadow_2_e
;
-- End of Generated Instance Port Map for inst_shadow_2
-- Generated Instance Port Map for inst_shadow_3
inst_shadow_3: inst_shadow_3_e
;
-- End of Generated Instance Port Map for inst_shadow_3
-- Generated Instance Port Map for inst_shadow_4
inst_shadow_4: inst_shadow_4_e
;
-- End of Generated Instance Port Map for inst_shadow_4
-- Generated Instance Port Map for inst_shadow_5
inst_shadow_5: inst_shadow_5_e
;
-- End of Generated Instance Port Map for inst_shadow_5
-- Generated Instance Port Map for inst_shadow_6
inst_shadow_6: inst_shadow_6_e
;
-- End of Generated Instance Port Map for inst_shadow_6
-- Generated Instance Port Map for inst_shadow_7
inst_shadow_7: inst_shadow_7_e
;
-- End of Generated Instance Port Map for inst_shadow_7
-- Generated Instance Port Map for inst_shadow_8
inst_shadow_8: inst_shadow_8_e
;
-- End of Generated Instance Port Map for inst_shadow_8
-- Generated Instance Port Map for inst_shadow_9
inst_shadow_9: inst_shadow_9_e
;
-- End of Generated Instance Port Map for inst_shadow_9
-- Generated Instance Port Map for inst_shadow_a
inst_shadow_a: inst_shadow_a_e
;
-- End of Generated Instance Port Map for inst_shadow_a
-- Generated Instance Port Map for inst_shadow_b
inst_shadow_b: inst_shadow_b_e
;
-- End of Generated Instance Port Map for inst_shadow_b
-- Generated Instance Port Map for inst_shadow_k1_k2
inst_shadow_k1_k2: inst_shadow_k1_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k2
-- Generated Instance Port Map for inst_shadow_k1_k4
inst_shadow_k1_k4: inst_shadow_k1_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k4
-- Generated Instance Port Map for inst_shadow_k3_k2
inst_shadow_k3_k2: inst_shadow_k3_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k2
-- Generated Instance Port Map for inst_shadow_k3_k4
inst_shadow_k3_k4: inst_shadow_k3_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k4
-- Generated Instance Port Map for inst_shadow_ok_1
inst_shadow_ok_1: inst_shadow_ok_1_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_1
-- Generated Instance Port Map for inst_shadow_ok_10
inst_shadow_ok_10: inst_shadow_ok_10_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_10
-- Generated Instance Port Map for inst_shadow_ok_2
inst_shadow_ok_2: inst_shadow_ok_2_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_2
-- Generated Instance Port Map for inst_shadow_ok_3
inst_shadow_ok_3: inst_shadow_ok_3_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_3
-- Generated Instance Port Map for inst_shadow_ok_4
inst_shadow_ok_4: inst_shadow_ok_4_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_4
-- Generated Instance Port Map for inst_shadow_ok_5
inst_shadow_ok_5: inst_shadow_ok_5_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_5
-- Generated Instance Port Map for inst_shadow_ok_6
inst_shadow_ok_6: inst_shadow_ok_6_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_6
-- Generated Instance Port Map for inst_shadow_ok_7
inst_shadow_ok_7: inst_shadow_ok_7_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_7
-- Generated Instance Port Map for inst_shadow_ok_8
inst_shadow_ok_8: inst_shadow_ok_8_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_8
-- Generated Instance Port Map for inst_shadow_ok_9
inst_shadow_ok_9: inst_shadow_ok_9_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_9
-- Generated Instance Port Map for inst_shadow_t
inst_shadow_t: inst_shadow_t_e
;
-- End of Generated Instance Port Map for inst_shadow_t
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
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2t0+
`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2p
-- File: syncram_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
entity syncram_2p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram_2p is
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal diagin : std_logic_vector(3 downto 0);
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
diagin <= (others => '0');
inf : if tech = inferred generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech =virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram_2p generic map (abits, dbits, sepclk, wrfst)
port map (rclk, renable, raddress, dataout, wclk,
write, waddress, datain);
end generate;
vir : if tech = memvirage generate
d39 : if dbits = 39 generate
x0 : virage_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
d32 : if dbits <= 32 generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain, testin);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
ihp : if tech = ihp25 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (rclk, raddress, vgnd, dataout, renable, gnd,
wclk, waddress, datain, open, write, write);
end generate;
rh_lib18t0 : if tech = rhlib18t generate
x0 : rh_lib18t_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout, write, waddress, datain, diagin);
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
ecl : if tech = eclipse generate
x0 : eclipse_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2p
-- File: syncram_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
entity syncram_2p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram_2p is
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal diagin : std_logic_vector(3 downto 0);
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
diagin <= (others => '0');
inf : if tech = inferred generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech =virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram_2p generic map (abits, dbits, sepclk, wrfst)
port map (rclk, renable, raddress, dataout, wclk,
write, waddress, datain);
end generate;
vir : if tech = memvirage generate
d39 : if dbits = 39 generate
x0 : virage_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
d32 : if dbits <= 32 generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain, testin);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
ihp : if tech = ihp25 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (rclk, raddress, vgnd, dataout, renable, gnd,
wclk, waddress, datain, open, write, write);
end generate;
rh_lib18t0 : if tech = rhlib18t generate
x0 : rh_lib18t_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout, write, waddress, datain, diagin);
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
ecl : if tech = eclipse generate
x0 : eclipse_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity multiplexer_4x8 is
generic (
N: natural := 8; -- bits in in/out signals
M: natural := 2); -- bits in select
port (
mux_inp0: in std_logic_vector(N-1 downto 0);
mux_inp1: in std_logic_vector(N-1 downto 0);
mux_inp2: in std_logic_vector(N-1 downto 0);
mux_inp3: in std_logic_vector(N-1 downto 0);
selec: in std_logic_vector(M-1 downto 0);
mux_outp: out std_logic_vector(N-1 downto 0);
);
end entity;
------------------------------
architecture circuit of multiplexer_4x8 is
--signals and declarations
begin
mux_outp <= mux_inp0 when selec = "00" else
mux_inp1 when selec = "01" else
mux_inp2 when selec = "10" else
mux_inp3
end architecture;
------------------------------
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:10:36 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/multi_QI/multi_QI_funcsim.vhdl
-- Design : multi_QI
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \multi_QImult_gen_v12_0__parameterized0\ is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 31 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \multi_QImult_gen_v12_0__parameterized0\ : entity is "mult_gen_v12_0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of \multi_QImult_gen_v12_0__parameterized0\ : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \multi_QImult_gen_v12_0__parameterized0\ : entity is "zynq";
attribute C_HAS_CE : integer;
attribute C_HAS_CE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of \multi_QImult_gen_v12_0__parameterized0\ : entity is 7;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 16;
attribute C_A_TYPE : integer;
attribute C_A_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of \multi_QImult_gen_v12_0__parameterized0\ : entity is "10000001";
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \multi_QImult_gen_v12_0__parameterized0\ : entity is "yes";
end \multi_QImult_gen_v12_0__parameterized0\;
architecture STRUCTURE of \multi_QImult_gen_v12_0__parameterized0\ is
attribute C_A_TYPE of i_mult : label is 0;
attribute C_A_WIDTH of i_mult : label is 16;
attribute C_B_TYPE of i_mult : label is 0;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 7;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 31;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "zynq";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
attribute secure_extras : string;
attribute secure_extras of i_mult : label is "A";
begin
i_mult: entity work.\multi_QImult_gen_v12_0_viv__parameterized0\
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => CE,
CLK => CLK,
P(31 downto 0) => P(31 downto 0),
PCASC(47 downto 0) => PCASC(47 downto 0),
SCLR => SCLR,
ZERO_DETECT(1 downto 0) => ZERO_DETECT(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity multi_QI is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of multi_QI : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of multi_QI : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of multi_QI : entity is "mult_gen_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of multi_QI : entity is "multi_QI,mult_gen_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of multi_QI : entity is "multi_QI,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=7,C_A_WIDTH=16,C_A_TYPE=0,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
end multi_QI;
architecture STRUCTURE of multi_QI is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 7;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\multi_QImult_gen_v12_0__parameterized0\
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(31 downto 0) => P(31 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x16_shift_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x16_shift_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(138-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(138-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_138x16_shift_top_wrapper;
architecture xilinx of fifo_138x16_shift_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_138x16_shift_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_138x16_shift_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulitplexer IS
END tb_mulitplexer;
ARCHITECTURE behavior OF tb_mulitplexer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic := '0';
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP (
A => A,
B => B,
O => O,
s => s
);
A <= "0000111100001111", "1111111011111110" after 20 ns, "1100001011111110" after 40 ns, "1100001011111110" after 50 ns;
B <= "0000001000000000", "0001001000000000" after 20 ns, "0010010000001100" after 40 ns, "1100001011111110" after 50 ns;
--s <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 19 ns, '0' after 22 ns;
s <= 'X';
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulitplexer IS
END tb_mulitplexer;
ARCHITECTURE behavior OF tb_mulitplexer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic := '0';
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP (
A => A,
B => B,
O => O,
s => s
);
A <= "0000111100001111", "1111111011111110" after 20 ns, "1100001011111110" after 40 ns, "1100001011111110" after 50 ns;
B <= "0000001000000000", "0001001000000000" after 20 ns, "0010010000001100" after 40 ns, "1100001011111110" after 50 ns;
--s <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 19 ns, '0' after 22 ns;
s <= 'X';
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulitplexer IS
END tb_mulitplexer;
ARCHITECTURE behavior OF tb_mulitplexer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic := '0';
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP (
A => A,
B => B,
O => O,
s => s
);
A <= "0000111100001111", "1111111011111110" after 20 ns, "1100001011111110" after 40 ns, "1100001011111110" after 50 ns;
B <= "0000001000000000", "0001001000000000" after 20 ns, "0010010000001100" after 40 ns, "1100001011111110" after 50 ns;
--s <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 19 ns, '0' after 22 ns;
s <= 'X';
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulitplexer IS
END tb_mulitplexer;
ARCHITECTURE behavior OF tb_mulitplexer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic := '0';
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP (
A => A,
B => B,
O => O,
s => s
);
A <= "0000111100001111", "1111111011111110" after 20 ns, "1100001011111110" after 40 ns, "1100001011111110" after 50 ns;
B <= "0000001000000000", "0001001000000000" after 20 ns, "0010010000001100" after 40 ns, "1100001011111110" after 50 ns;
--s <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 19 ns, '0' after 22 ns;
s <= 'X';
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY Adder_TEST IS
END Adder_TEST;
ARCHITECTURE behavior OF Adder_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder
PORT(
CarryIn : IN unsigned(3 downto 0);
A : IN unsigned(3 downto 0);
B : IN unsigned(3 downto 0);
C : IN unsigned(3 downto 0);
D : IN unsigned(3 downto 0);
E : IN unsigned(3 downto 0);
Saida : OUT unsigned(3 downto 0);
CarryOut : OUT unsigned(3 downto 0)
);
END COMPONENT;
--Inputs
signal CarryIn : unsigned(3 downto 0) := (others => '0');
signal A : unsigned(3 downto 0) := (others => '0');
signal B : unsigned(3 downto 0) := (others => '0');
signal C : unsigned(3 downto 0) := (others => '0');
signal D : unsigned(3 downto 0) := (others => '0');
signal E : unsigned(3 downto 0) := (others => '0');
--Outputs
signal Saida : unsigned(3 downto 0);
signal CarryOut : unsigned(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Adder PORT MAP (
CarryIn => CarryIn,
A => A,
B => B,
C => C,
D => D,
E => E,
Saida => Saida,
CarryOut => CarryOut
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
CarryIn <= "0000";
A <= "0111";
B <= "0101";
C <= "0000";
D <= "0000";
E <= "0000";
wait;
end process;
END;
|
-- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end decoder;
architecture behv of decoder is
begin
process(op)
begin
case op is
when "0000" => result <= "0000000000000001";
when "0001" => result <= "0000000000000010";
when "0010" => result <= "0000000000000100";
when "0011" => result <= "0000000000001000";
when "0100" => result <= "0000000000010000";
when "0101" => result <= "0000000000100000";
when "0110" => result <= "0000000001000000";
-- unused
-- when "0111" => result <= "0000000010000000";
when "1000" => result <= "0000000100000000";
when "1001" => result <= "0000001000000000";
when "1010" => result <= "0000010000000000";
when "1011" => result <= "0000100000000000";
-- unused
-- when "1100" => result <= "0001000000000000";
-- when "1101" => result <= "0010000000000000";
-- when "1110" => result <= "0100000000000000";
-- when "1111" => result <= "1000000000000000";
when others =>
result <= "0000000000000000";
end case;
end process;
end behv;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity stack is
Port ( clk, reset : in STD_LOGIC;
push, pop : in STD_LOGIC;
pcin : in STD_LOGIC_VECTOR (12 downto 0);
pcout : out STD_LOGIC_VECTOR (12 downto 0));
end stack;
architecture Behavioral of stack is
signal stack : stack_type13;
begin
process(clk, reset, stack, push, pop, pcin)
variable pointer : unsigned(2 downto 0);
begin
if rising_edge(clk) then
if push = '1' then
--Write
pointer := pointer + 1;
stack(to_integer(pointer)) <= pcin;
elsif pop = '1' then
pointer := pointer - 1;
end if;
end if;
-- Set output, only readable after pop
pcout <= stack(to_integer(pointer));
if reset = '1' then
pointer := to_unsigned(0,3);
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0;
ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WID" &
"TH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity successive_approx_adc is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( terminal analog_in : electrical;
signal clock : in std_logic;
signal start : in std_logic;
signal eoc : out std_logic;
signal data_out : out std_logic_vector(0 to width - 1) );
end entity successive_approx_adc;
-- not in book
architecture struct of successive_approx_adc is
begin
end architecture struct;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity successive_approx_adc is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( terminal analog_in : electrical;
signal clock : in std_logic;
signal start : in std_logic;
signal eoc : out std_logic;
signal data_out : out std_logic_vector(0 to width - 1) );
end entity successive_approx_adc;
-- not in book
architecture struct of successive_approx_adc is
begin
end architecture struct;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity successive_approx_adc is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( terminal analog_in : electrical;
signal clock : in std_logic;
signal start : in std_logic;
signal eoc : out std_logic;
signal data_out : out std_logic_vector(0 to width - 1) );
end entity successive_approx_adc;
-- not in book
architecture struct of successive_approx_adc is
begin
end architecture struct;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:56:19 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/mips_simu.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mips
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY mips_simu IS
END mips_simu;
ARCHITECTURE behavior OF mips_simu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mips
PORT(
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mips PORT MAP (
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset<='0';
wait for 100 ns;
wait;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:56:19 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/mips_simu.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mips
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY mips_simu IS
END mips_simu;
ARCHITECTURE behavior OF mips_simu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mips
PORT(
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mips PORT MAP (
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset<='0';
wait for 100 ns;
wait;
-- insert stimulus here
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram
-- File: sram.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity sram is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(7 downto 0);
ce1 : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram is
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**Abits)-1)) of BYTE;
signal DINT,DI,DO : BYTE;
constant ahigh : integer := abits - 1;
signal wrpre : std_ulogic;
function Vpar(vec : std_logic_vector) return std_ulogic is
variable par : std_ulogic := '1';
begin
for i in vec'range loop --'
par := par xor vec(i);
end loop;
return par;
end;
begin
RAM : process(CE1,WE,DI,A,OE,D)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if FIRST then
if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
if index = 6 then
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
elsif (index = 4) or (index = 5) then
recaddr(31 downto abits+1) := (others => '0');
ai := conv_integer(recaddr)/2;
for i in 0 to 7 loop
MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7));
end loop;
else
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
end loop;
end if;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
else
if (TO_X01(not CE1) = '1') then
if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if;
dint <= mema(ai);
end if;
if (TO_X01(CE1 or WE) = '1') then
if wrpre = '1' then
mema(ai) := to_x01(std_logic_vector(DI));
end if;
end if;
end if;
wrpre <= TO_X01((not CE1) and (not WE));
DI <= D;
end process;
BUFS : process(CE1,WE,DINT,OE)
variable DRIVEB : std_logic;
begin
DRIVEB := TO_X01((not CE1) and (not OE) and WE);
case DRIVEB is
when '1' => D <= DINT after tacc * 1 ns;
when '0' => D <= "ZZZZZZZZ" after 8 ns;
when others => D <= "XXXXXXXX";
end case;
end process;
end sim;
-- pragma translate_on
|
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