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-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl is
generic (
C_S_AXI_TRACE_CNTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_TRACE_CNTRL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
A_TKEEP : IN STD_LOGIC_VECTOR (7 downto 0);
A_TSTRB : IN STD_LOGIC_VECTOR (7 downto 0);
A_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
A_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
A_TID : IN STD_LOGIC_VECTOR (4 downto 0);
A_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
B_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
B_TKEEP : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TSTRB : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
B_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
B_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
B_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_trace_cntrl_AWVALID : IN STD_LOGIC;
s_axi_trace_cntrl_AWREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_WVALID : IN STD_LOGIC;
s_axi_trace_cntrl_WREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH/8-1 downto 0);
s_axi_trace_cntrl_ARVALID : IN STD_LOGIC;
s_axi_trace_cntrl_ARREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_RVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_RREADY : IN STD_LOGIC;
s_axi_trace_cntrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_trace_cntrl_BVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_BREADY : IN STD_LOGIC;
s_axi_trace_cntrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of trace_cntrl is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"trace_cntrl,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.628000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=631,HLS_SYN_LUT=706}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp1_stg0_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st12_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal data_compare_V : STD_LOGIC_VECTOR (63 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal sample_rate : STD_LOGIC_VECTOR (31 downto 0);
signal A_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_62 : BOOLEAN;
signal ap_sig_cseq_ST_pp1_stg0_fsm_9 : STD_LOGIC;
signal ap_sig_69 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal tmp_5_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal match_phi_fu_183_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal B_TDATA_blk_n : STD_LOGIC;
signal or_cond_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal match_reg_179 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_191 : STD_LOGIC_VECTOR (30 downto 0);
signal sample_rate_read_reg_407 : STD_LOGIC_VECTOR (31 downto 0);
signal length_read_reg_413 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_419 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal total_input_samples_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_147 : BOOLEAN;
signal A_temp_data_V_reg_430 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_reg_435 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_reg_440 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_reg_445 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_reg_450 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_171 : BOOLEAN;
signal tmp_5_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_175 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_1_fu_298_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal or_cond_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_fu_362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal sample_counter_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_counter_1_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_fu_90 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_1_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal A_temp_data_V_1_fu_94 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_1_fu_98 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_1_fu_102 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_1_fu_106 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_1_fu_110 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_1_fu_114 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal tmp_1_fu_236_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_10 : STD_LOGIC;
signal ap_sig_372 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
component trace_cntrl_mul_32s_32s_32_7 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component trace_cntrl_trace_cntrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
data_compare_V : OUT STD_LOGIC_VECTOR (63 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_rate : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
trace_cntrl_trace_cntrl_s_axi_U : component trace_cntrl_trace_cntrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_TRACE_CNTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_TRACE_CNTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_trace_cntrl_AWVALID,
AWREADY => s_axi_trace_cntrl_AWREADY,
AWADDR => s_axi_trace_cntrl_AWADDR,
WVALID => s_axi_trace_cntrl_WVALID,
WREADY => s_axi_trace_cntrl_WREADY,
WDATA => s_axi_trace_cntrl_WDATA,
WSTRB => s_axi_trace_cntrl_WSTRB,
ARVALID => s_axi_trace_cntrl_ARVALID,
ARREADY => s_axi_trace_cntrl_ARREADY,
ARADDR => s_axi_trace_cntrl_ARADDR,
RVALID => s_axi_trace_cntrl_RVALID,
RREADY => s_axi_trace_cntrl_RREADY,
RDATA => s_axi_trace_cntrl_RDATA,
RRESP => s_axi_trace_cntrl_RRESP,
BVALID => s_axi_trace_cntrl_BVALID,
BREADY => s_axi_trace_cntrl_BREADY,
BRESP => s_axi_trace_cntrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
data_compare_V => data_compare_V,
length_r => length_r,
sample_rate => sample_rate);
trace_cntrl_mul_32s_32s_32_7_U0 : component trace_cntrl_mul_32s_32s_32_7
generic map (
ID => 1,
NUM_STAGE => 7,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => sample_rate,
din1 => length_r,
ce => ap_const_logic_1,
dout => grp_fu_226_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_1 = B_TREADY)))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
A_temp_data_V_1_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_data_V_1_fu_94 <= A_TDATA;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_data_V_1_fu_94 <= A_temp_data_V_reg_430;
end if;
end if;
end process;
A_temp_dest_V_1_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_dest_V_1_fu_114 <= A_TDEST;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_dest_V_1_fu_114 <= A_temp_dest_V_reg_455;
end if;
end if;
end process;
A_temp_id_V_1_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_id_V_1_fu_110 <= A_TID;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_id_V_1_fu_110 <= A_temp_id_V_reg_450;
end if;
end if;
end process;
A_temp_keep_V_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_keep_V_1_fu_98 <= A_TKEEP;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_keep_V_1_fu_98 <= A_temp_keep_V_reg_435;
end if;
end if;
end process;
A_temp_strb_V_1_fu_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_strb_V_1_fu_102 <= A_TSTRB;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_strb_V_1_fu_102 <= A_temp_strb_V_reg_440;
end if;
end if;
end process;
A_temp_user_V_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_user_V_1_fu_106 <= A_TUSER;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_user_V_1_fu_106 <= A_temp_user_V_reg_445;
end if;
end if;
end process;
i_reg_191_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
i_reg_191 <= i_1_fu_298_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
i_reg_191 <= ap_const_lv31_0;
end if;
end if;
end process;
match_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_reg_179 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
match_reg_179 <= ap_const_lv1_1;
end if;
end if;
end process;
sample_counter_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
sample_counter_fu_86 <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and (ap_const_lv1_0 = or_cond_fu_342_p2))) then
sample_counter_fu_86 <= sample_counter_1_fu_348_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
sample_counter_fu_86 <= ap_const_lv32_0;
end if;
end if;
end process;
samples_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
samples_fu_90 <= samples_1_fu_367_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
samples_fu_90 <= ap_const_lv32_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0)))) then
A_temp_data_V_reg_430 <= A_TDATA;
A_temp_dest_V_reg_455 <= A_TDEST;
A_temp_id_V_reg_450 <= A_TID;
A_temp_keep_V_reg_435 <= A_TKEEP;
A_temp_strb_V_reg_440 <= A_TSTRB;
A_temp_user_V_reg_445 <= A_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
A_temp_last_V_reg_538 <= A_temp_last_V_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
length_read_reg_413 <= length_r;
sample_rate_read_reg_407 <= sample_rate;
tmp_reg_419 <= tmp_fu_232_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
or_cond_reg_534 <= or_cond_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_4_reg_520 <= tmp_4_fu_250_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
tmp_5_reg_525 <= tmp_5_fu_293_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
total_input_samples_reg_425 <= grp_fu_226_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, A_TVALID, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY, tmp_3_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if ((not((A_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_3_fu_245_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
elsif ((not((A_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_3_fu_245_p2)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
when ap_ST_pp1_stg0_fsm_9 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_NS_fsm <= ap_ST_st12_fsm_10;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
end if;
when ap_ST_st12_fsm_10 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
A_TDATA_blk_n_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4)))) then
A_TDATA_blk_n <= A_TVALID;
else
A_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
A_TREADY_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, match_phi_fu_183_p4, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
A_temp_last_V_fu_362_p2 <= "1" when (samples_fu_90 = tmp_4_reg_520) else "0";
B_TDATA <= A_temp_data_V_1_fu_94;
B_TDATA_blk_n_assign_proc : process(B_TREADY, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, or_cond_reg_534)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)))) then
B_TDATA_blk_n <= B_TREADY;
else
B_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
B_TDEST <= A_temp_dest_V_1_fu_114;
B_TID <= A_temp_id_V_1_fu_110;
B_TKEEP <= A_temp_keep_V_1_fu_98;
B_TLAST <= A_temp_last_V_reg_538;
B_TSTRB <= A_temp_strb_V_1_fu_102;
B_TUSER <= A_temp_user_V_1_fu_106;
B_TVALID_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, or_cond_reg_534, ap_sig_175, ap_reg_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY)))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_147 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_171 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_175_assign_proc : process(A_TVALID, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
ap_sig_175 <= (not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and (A_TVALID = ap_const_logic_0));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_372 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_62_assign_proc : process(ap_CS_fsm)
begin
ap_sig_62 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_69_assign_proc : process(ap_CS_fsm)
begin
ap_sig_69 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_cseq_ST_pp1_stg0_fsm_9_assign_proc : process(ap_sig_69)
begin
if (ap_sig_69) then
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st12_fsm_10_assign_proc : process(ap_sig_372)
begin
if (ap_sig_372) then
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_147)
begin
if (ap_sig_147) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_62)
begin
if (ap_sig_62) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_171)
begin
if (ap_sig_171) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
i_1_fu_298_p2 <= std_logic_vector(unsigned(i_reg_191) + unsigned(ap_const_lv31_1));
i_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(i_reg_191),32));
match_phi_fu_183_p4_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, match_reg_179, tmp_5_reg_525)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_phi_fu_183_p4 <= ap_const_lv1_0;
else
match_phi_fu_183_p4 <= match_reg_179;
end if;
end process;
or_cond_fu_342_p2 <= (tmp_7_fu_337_p2 or match_phi_fu_183_p4);
sample_counter_1_fu_348_p2 <= std_logic_vector(unsigned(sample_counter_fu_86) + unsigned(ap_const_lv32_1));
samples_1_fu_367_p2 <= std_logic_vector(unsigned(samples_fu_90) + unsigned(ap_const_lv32_1));
tmp_1_fu_236_p1 <= A_TDATA(32 - 1 downto 0);
tmp_2_fu_240_p2 <= (tmp_reg_419 and tmp_1_fu_236_p1);
tmp_3_fu_245_p2 <= "1" when (tmp_2_fu_240_p2 = tmp_reg_419) else "0";
tmp_4_fu_250_p2 <= std_logic_vector(signed(length_read_reg_413) + signed(ap_const_lv32_FFFFFFFF));
tmp_5_fu_293_p2 <= "1" when (signed(i_cast_fu_289_p1) < signed(total_input_samples_reg_425)) else "0";
tmp_7_fu_337_p2 <= "1" when (sample_counter_fu_86 = sample_rate_read_reg_407) else "0";
tmp_fu_232_p1 <= data_compare_V(32 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl is
generic (
C_S_AXI_TRACE_CNTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_TRACE_CNTRL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
A_TKEEP : IN STD_LOGIC_VECTOR (7 downto 0);
A_TSTRB : IN STD_LOGIC_VECTOR (7 downto 0);
A_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
A_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
A_TID : IN STD_LOGIC_VECTOR (4 downto 0);
A_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
B_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
B_TKEEP : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TSTRB : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
B_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
B_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
B_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_trace_cntrl_AWVALID : IN STD_LOGIC;
s_axi_trace_cntrl_AWREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_WVALID : IN STD_LOGIC;
s_axi_trace_cntrl_WREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH/8-1 downto 0);
s_axi_trace_cntrl_ARVALID : IN STD_LOGIC;
s_axi_trace_cntrl_ARREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_RVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_RREADY : IN STD_LOGIC;
s_axi_trace_cntrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_trace_cntrl_BVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_BREADY : IN STD_LOGIC;
s_axi_trace_cntrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of trace_cntrl is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"trace_cntrl,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.628000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=631,HLS_SYN_LUT=706}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp1_stg0_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st12_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal data_compare_V : STD_LOGIC_VECTOR (63 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal sample_rate : STD_LOGIC_VECTOR (31 downto 0);
signal A_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_62 : BOOLEAN;
signal ap_sig_cseq_ST_pp1_stg0_fsm_9 : STD_LOGIC;
signal ap_sig_69 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal tmp_5_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal match_phi_fu_183_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal B_TDATA_blk_n : STD_LOGIC;
signal or_cond_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal match_reg_179 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_191 : STD_LOGIC_VECTOR (30 downto 0);
signal sample_rate_read_reg_407 : STD_LOGIC_VECTOR (31 downto 0);
signal length_read_reg_413 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_419 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal total_input_samples_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_147 : BOOLEAN;
signal A_temp_data_V_reg_430 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_reg_435 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_reg_440 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_reg_445 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_reg_450 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_171 : BOOLEAN;
signal tmp_5_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_175 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_1_fu_298_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal or_cond_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_fu_362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal sample_counter_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_counter_1_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_fu_90 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_1_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal A_temp_data_V_1_fu_94 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_1_fu_98 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_1_fu_102 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_1_fu_106 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_1_fu_110 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_1_fu_114 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal tmp_1_fu_236_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_10 : STD_LOGIC;
signal ap_sig_372 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
component trace_cntrl_mul_32s_32s_32_7 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component trace_cntrl_trace_cntrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
data_compare_V : OUT STD_LOGIC_VECTOR (63 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_rate : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
trace_cntrl_trace_cntrl_s_axi_U : component trace_cntrl_trace_cntrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_TRACE_CNTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_TRACE_CNTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_trace_cntrl_AWVALID,
AWREADY => s_axi_trace_cntrl_AWREADY,
AWADDR => s_axi_trace_cntrl_AWADDR,
WVALID => s_axi_trace_cntrl_WVALID,
WREADY => s_axi_trace_cntrl_WREADY,
WDATA => s_axi_trace_cntrl_WDATA,
WSTRB => s_axi_trace_cntrl_WSTRB,
ARVALID => s_axi_trace_cntrl_ARVALID,
ARREADY => s_axi_trace_cntrl_ARREADY,
ARADDR => s_axi_trace_cntrl_ARADDR,
RVALID => s_axi_trace_cntrl_RVALID,
RREADY => s_axi_trace_cntrl_RREADY,
RDATA => s_axi_trace_cntrl_RDATA,
RRESP => s_axi_trace_cntrl_RRESP,
BVALID => s_axi_trace_cntrl_BVALID,
BREADY => s_axi_trace_cntrl_BREADY,
BRESP => s_axi_trace_cntrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
data_compare_V => data_compare_V,
length_r => length_r,
sample_rate => sample_rate);
trace_cntrl_mul_32s_32s_32_7_U0 : component trace_cntrl_mul_32s_32s_32_7
generic map (
ID => 1,
NUM_STAGE => 7,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => sample_rate,
din1 => length_r,
ce => ap_const_logic_1,
dout => grp_fu_226_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_1 = B_TREADY)))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
A_temp_data_V_1_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_data_V_1_fu_94 <= A_TDATA;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_data_V_1_fu_94 <= A_temp_data_V_reg_430;
end if;
end if;
end process;
A_temp_dest_V_1_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_dest_V_1_fu_114 <= A_TDEST;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_dest_V_1_fu_114 <= A_temp_dest_V_reg_455;
end if;
end if;
end process;
A_temp_id_V_1_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_id_V_1_fu_110 <= A_TID;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_id_V_1_fu_110 <= A_temp_id_V_reg_450;
end if;
end if;
end process;
A_temp_keep_V_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_keep_V_1_fu_98 <= A_TKEEP;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_keep_V_1_fu_98 <= A_temp_keep_V_reg_435;
end if;
end if;
end process;
A_temp_strb_V_1_fu_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_strb_V_1_fu_102 <= A_TSTRB;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_strb_V_1_fu_102 <= A_temp_strb_V_reg_440;
end if;
end if;
end process;
A_temp_user_V_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_user_V_1_fu_106 <= A_TUSER;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_user_V_1_fu_106 <= A_temp_user_V_reg_445;
end if;
end if;
end process;
i_reg_191_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
i_reg_191 <= i_1_fu_298_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
i_reg_191 <= ap_const_lv31_0;
end if;
end if;
end process;
match_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_reg_179 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
match_reg_179 <= ap_const_lv1_1;
end if;
end if;
end process;
sample_counter_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
sample_counter_fu_86 <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and (ap_const_lv1_0 = or_cond_fu_342_p2))) then
sample_counter_fu_86 <= sample_counter_1_fu_348_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
sample_counter_fu_86 <= ap_const_lv32_0;
end if;
end if;
end process;
samples_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
samples_fu_90 <= samples_1_fu_367_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
samples_fu_90 <= ap_const_lv32_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0)))) then
A_temp_data_V_reg_430 <= A_TDATA;
A_temp_dest_V_reg_455 <= A_TDEST;
A_temp_id_V_reg_450 <= A_TID;
A_temp_keep_V_reg_435 <= A_TKEEP;
A_temp_strb_V_reg_440 <= A_TSTRB;
A_temp_user_V_reg_445 <= A_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
A_temp_last_V_reg_538 <= A_temp_last_V_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
length_read_reg_413 <= length_r;
sample_rate_read_reg_407 <= sample_rate;
tmp_reg_419 <= tmp_fu_232_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
or_cond_reg_534 <= or_cond_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_4_reg_520 <= tmp_4_fu_250_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
tmp_5_reg_525 <= tmp_5_fu_293_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
total_input_samples_reg_425 <= grp_fu_226_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, A_TVALID, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY, tmp_3_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if ((not((A_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_3_fu_245_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
elsif ((not((A_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_3_fu_245_p2)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
when ap_ST_pp1_stg0_fsm_9 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_NS_fsm <= ap_ST_st12_fsm_10;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
end if;
when ap_ST_st12_fsm_10 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
A_TDATA_blk_n_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4)))) then
A_TDATA_blk_n <= A_TVALID;
else
A_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
A_TREADY_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, match_phi_fu_183_p4, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
A_temp_last_V_fu_362_p2 <= "1" when (samples_fu_90 = tmp_4_reg_520) else "0";
B_TDATA <= A_temp_data_V_1_fu_94;
B_TDATA_blk_n_assign_proc : process(B_TREADY, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, or_cond_reg_534)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)))) then
B_TDATA_blk_n <= B_TREADY;
else
B_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
B_TDEST <= A_temp_dest_V_1_fu_114;
B_TID <= A_temp_id_V_1_fu_110;
B_TKEEP <= A_temp_keep_V_1_fu_98;
B_TLAST <= A_temp_last_V_reg_538;
B_TSTRB <= A_temp_strb_V_1_fu_102;
B_TUSER <= A_temp_user_V_1_fu_106;
B_TVALID_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, or_cond_reg_534, ap_sig_175, ap_reg_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY)))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_147 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_171 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_175_assign_proc : process(A_TVALID, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
ap_sig_175 <= (not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and (A_TVALID = ap_const_logic_0));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_372 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_62_assign_proc : process(ap_CS_fsm)
begin
ap_sig_62 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_69_assign_proc : process(ap_CS_fsm)
begin
ap_sig_69 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_cseq_ST_pp1_stg0_fsm_9_assign_proc : process(ap_sig_69)
begin
if (ap_sig_69) then
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st12_fsm_10_assign_proc : process(ap_sig_372)
begin
if (ap_sig_372) then
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_147)
begin
if (ap_sig_147) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_62)
begin
if (ap_sig_62) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_171)
begin
if (ap_sig_171) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
i_1_fu_298_p2 <= std_logic_vector(unsigned(i_reg_191) + unsigned(ap_const_lv31_1));
i_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(i_reg_191),32));
match_phi_fu_183_p4_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, match_reg_179, tmp_5_reg_525)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_phi_fu_183_p4 <= ap_const_lv1_0;
else
match_phi_fu_183_p4 <= match_reg_179;
end if;
end process;
or_cond_fu_342_p2 <= (tmp_7_fu_337_p2 or match_phi_fu_183_p4);
sample_counter_1_fu_348_p2 <= std_logic_vector(unsigned(sample_counter_fu_86) + unsigned(ap_const_lv32_1));
samples_1_fu_367_p2 <= std_logic_vector(unsigned(samples_fu_90) + unsigned(ap_const_lv32_1));
tmp_1_fu_236_p1 <= A_TDATA(32 - 1 downto 0);
tmp_2_fu_240_p2 <= (tmp_reg_419 and tmp_1_fu_236_p1);
tmp_3_fu_245_p2 <= "1" when (tmp_2_fu_240_p2 = tmp_reg_419) else "0";
tmp_4_fu_250_p2 <= std_logic_vector(signed(length_read_reg_413) + signed(ap_const_lv32_FFFFFFFF));
tmp_5_fu_293_p2 <= "1" when (signed(i_cast_fu_289_p1) < signed(total_input_samples_reg_425)) else "0";
tmp_7_fu_337_p2 <= "1" when (sample_counter_fu_86 = sample_rate_read_reg_407) else "0";
tmp_fu_232_p1 <= data_compare_V(32 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl is
generic (
C_S_AXI_TRACE_CNTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_TRACE_CNTRL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
A_TKEEP : IN STD_LOGIC_VECTOR (7 downto 0);
A_TSTRB : IN STD_LOGIC_VECTOR (7 downto 0);
A_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
A_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
A_TID : IN STD_LOGIC_VECTOR (4 downto 0);
A_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
B_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
B_TKEEP : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TSTRB : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
B_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
B_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
B_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_trace_cntrl_AWVALID : IN STD_LOGIC;
s_axi_trace_cntrl_AWREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_WVALID : IN STD_LOGIC;
s_axi_trace_cntrl_WREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH/8-1 downto 0);
s_axi_trace_cntrl_ARVALID : IN STD_LOGIC;
s_axi_trace_cntrl_ARREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_RVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_RREADY : IN STD_LOGIC;
s_axi_trace_cntrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_trace_cntrl_BVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_BREADY : IN STD_LOGIC;
s_axi_trace_cntrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of trace_cntrl is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"trace_cntrl,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.628000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=631,HLS_SYN_LUT=706}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp1_stg0_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st12_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal data_compare_V : STD_LOGIC_VECTOR (63 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal sample_rate : STD_LOGIC_VECTOR (31 downto 0);
signal A_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_62 : BOOLEAN;
signal ap_sig_cseq_ST_pp1_stg0_fsm_9 : STD_LOGIC;
signal ap_sig_69 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal tmp_5_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal match_phi_fu_183_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal B_TDATA_blk_n : STD_LOGIC;
signal or_cond_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal match_reg_179 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_191 : STD_LOGIC_VECTOR (30 downto 0);
signal sample_rate_read_reg_407 : STD_LOGIC_VECTOR (31 downto 0);
signal length_read_reg_413 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_419 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal total_input_samples_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_147 : BOOLEAN;
signal A_temp_data_V_reg_430 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_reg_435 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_reg_440 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_reg_445 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_reg_450 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_171 : BOOLEAN;
signal tmp_5_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_175 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_1_fu_298_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal or_cond_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_fu_362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal sample_counter_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_counter_1_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_fu_90 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_1_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal A_temp_data_V_1_fu_94 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_1_fu_98 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_1_fu_102 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_1_fu_106 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_1_fu_110 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_1_fu_114 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal tmp_1_fu_236_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_10 : STD_LOGIC;
signal ap_sig_372 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
component trace_cntrl_mul_32s_32s_32_7 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component trace_cntrl_trace_cntrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
data_compare_V : OUT STD_LOGIC_VECTOR (63 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_rate : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
trace_cntrl_trace_cntrl_s_axi_U : component trace_cntrl_trace_cntrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_TRACE_CNTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_TRACE_CNTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_trace_cntrl_AWVALID,
AWREADY => s_axi_trace_cntrl_AWREADY,
AWADDR => s_axi_trace_cntrl_AWADDR,
WVALID => s_axi_trace_cntrl_WVALID,
WREADY => s_axi_trace_cntrl_WREADY,
WDATA => s_axi_trace_cntrl_WDATA,
WSTRB => s_axi_trace_cntrl_WSTRB,
ARVALID => s_axi_trace_cntrl_ARVALID,
ARREADY => s_axi_trace_cntrl_ARREADY,
ARADDR => s_axi_trace_cntrl_ARADDR,
RVALID => s_axi_trace_cntrl_RVALID,
RREADY => s_axi_trace_cntrl_RREADY,
RDATA => s_axi_trace_cntrl_RDATA,
RRESP => s_axi_trace_cntrl_RRESP,
BVALID => s_axi_trace_cntrl_BVALID,
BREADY => s_axi_trace_cntrl_BREADY,
BRESP => s_axi_trace_cntrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
data_compare_V => data_compare_V,
length_r => length_r,
sample_rate => sample_rate);
trace_cntrl_mul_32s_32s_32_7_U0 : component trace_cntrl_mul_32s_32s_32_7
generic map (
ID => 1,
NUM_STAGE => 7,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => sample_rate,
din1 => length_r,
ce => ap_const_logic_1,
dout => grp_fu_226_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_1 = B_TREADY)))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
A_temp_data_V_1_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_data_V_1_fu_94 <= A_TDATA;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_data_V_1_fu_94 <= A_temp_data_V_reg_430;
end if;
end if;
end process;
A_temp_dest_V_1_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_dest_V_1_fu_114 <= A_TDEST;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_dest_V_1_fu_114 <= A_temp_dest_V_reg_455;
end if;
end if;
end process;
A_temp_id_V_1_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_id_V_1_fu_110 <= A_TID;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_id_V_1_fu_110 <= A_temp_id_V_reg_450;
end if;
end if;
end process;
A_temp_keep_V_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_keep_V_1_fu_98 <= A_TKEEP;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_keep_V_1_fu_98 <= A_temp_keep_V_reg_435;
end if;
end if;
end process;
A_temp_strb_V_1_fu_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_strb_V_1_fu_102 <= A_TSTRB;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_strb_V_1_fu_102 <= A_temp_strb_V_reg_440;
end if;
end if;
end process;
A_temp_user_V_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_user_V_1_fu_106 <= A_TUSER;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_user_V_1_fu_106 <= A_temp_user_V_reg_445;
end if;
end if;
end process;
i_reg_191_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
i_reg_191 <= i_1_fu_298_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
i_reg_191 <= ap_const_lv31_0;
end if;
end if;
end process;
match_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_reg_179 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
match_reg_179 <= ap_const_lv1_1;
end if;
end if;
end process;
sample_counter_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
sample_counter_fu_86 <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and (ap_const_lv1_0 = or_cond_fu_342_p2))) then
sample_counter_fu_86 <= sample_counter_1_fu_348_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
sample_counter_fu_86 <= ap_const_lv32_0;
end if;
end if;
end process;
samples_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
samples_fu_90 <= samples_1_fu_367_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
samples_fu_90 <= ap_const_lv32_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0)))) then
A_temp_data_V_reg_430 <= A_TDATA;
A_temp_dest_V_reg_455 <= A_TDEST;
A_temp_id_V_reg_450 <= A_TID;
A_temp_keep_V_reg_435 <= A_TKEEP;
A_temp_strb_V_reg_440 <= A_TSTRB;
A_temp_user_V_reg_445 <= A_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
A_temp_last_V_reg_538 <= A_temp_last_V_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
length_read_reg_413 <= length_r;
sample_rate_read_reg_407 <= sample_rate;
tmp_reg_419 <= tmp_fu_232_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
or_cond_reg_534 <= or_cond_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_4_reg_520 <= tmp_4_fu_250_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
tmp_5_reg_525 <= tmp_5_fu_293_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
total_input_samples_reg_425 <= grp_fu_226_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, A_TVALID, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY, tmp_3_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if ((not((A_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_3_fu_245_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
elsif ((not((A_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_3_fu_245_p2)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
when ap_ST_pp1_stg0_fsm_9 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_NS_fsm <= ap_ST_st12_fsm_10;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
end if;
when ap_ST_st12_fsm_10 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
A_TDATA_blk_n_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4)))) then
A_TDATA_blk_n <= A_TVALID;
else
A_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
A_TREADY_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, match_phi_fu_183_p4, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
A_temp_last_V_fu_362_p2 <= "1" when (samples_fu_90 = tmp_4_reg_520) else "0";
B_TDATA <= A_temp_data_V_1_fu_94;
B_TDATA_blk_n_assign_proc : process(B_TREADY, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, or_cond_reg_534)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)))) then
B_TDATA_blk_n <= B_TREADY;
else
B_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
B_TDEST <= A_temp_dest_V_1_fu_114;
B_TID <= A_temp_id_V_1_fu_110;
B_TKEEP <= A_temp_keep_V_1_fu_98;
B_TLAST <= A_temp_last_V_reg_538;
B_TSTRB <= A_temp_strb_V_1_fu_102;
B_TUSER <= A_temp_user_V_1_fu_106;
B_TVALID_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, or_cond_reg_534, ap_sig_175, ap_reg_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY)))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_147 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_171 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_175_assign_proc : process(A_TVALID, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
ap_sig_175 <= (not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and (A_TVALID = ap_const_logic_0));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_372 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_62_assign_proc : process(ap_CS_fsm)
begin
ap_sig_62 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_69_assign_proc : process(ap_CS_fsm)
begin
ap_sig_69 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_cseq_ST_pp1_stg0_fsm_9_assign_proc : process(ap_sig_69)
begin
if (ap_sig_69) then
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st12_fsm_10_assign_proc : process(ap_sig_372)
begin
if (ap_sig_372) then
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_147)
begin
if (ap_sig_147) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_62)
begin
if (ap_sig_62) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_171)
begin
if (ap_sig_171) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
i_1_fu_298_p2 <= std_logic_vector(unsigned(i_reg_191) + unsigned(ap_const_lv31_1));
i_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(i_reg_191),32));
match_phi_fu_183_p4_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, match_reg_179, tmp_5_reg_525)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_phi_fu_183_p4 <= ap_const_lv1_0;
else
match_phi_fu_183_p4 <= match_reg_179;
end if;
end process;
or_cond_fu_342_p2 <= (tmp_7_fu_337_p2 or match_phi_fu_183_p4);
sample_counter_1_fu_348_p2 <= std_logic_vector(unsigned(sample_counter_fu_86) + unsigned(ap_const_lv32_1));
samples_1_fu_367_p2 <= std_logic_vector(unsigned(samples_fu_90) + unsigned(ap_const_lv32_1));
tmp_1_fu_236_p1 <= A_TDATA(32 - 1 downto 0);
tmp_2_fu_240_p2 <= (tmp_reg_419 and tmp_1_fu_236_p1);
tmp_3_fu_245_p2 <= "1" when (tmp_2_fu_240_p2 = tmp_reg_419) else "0";
tmp_4_fu_250_p2 <= std_logic_vector(signed(length_read_reg_413) + signed(ap_const_lv32_FFFFFFFF));
tmp_5_fu_293_p2 <= "1" when (signed(i_cast_fu_289_p1) < signed(total_input_samples_reg_425)) else "0";
tmp_7_fu_337_p2 <= "1" when (sample_counter_fu_86 = sample_rate_read_reg_407) else "0";
tmp_fu_232_p1 <= data_compare_V(32 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl is
generic (
C_S_AXI_TRACE_CNTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_TRACE_CNTRL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
A_TKEEP : IN STD_LOGIC_VECTOR (7 downto 0);
A_TSTRB : IN STD_LOGIC_VECTOR (7 downto 0);
A_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
A_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
A_TID : IN STD_LOGIC_VECTOR (4 downto 0);
A_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
B_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
B_TKEEP : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TSTRB : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
B_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
B_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
B_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_trace_cntrl_AWVALID : IN STD_LOGIC;
s_axi_trace_cntrl_AWREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_WVALID : IN STD_LOGIC;
s_axi_trace_cntrl_WREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH/8-1 downto 0);
s_axi_trace_cntrl_ARVALID : IN STD_LOGIC;
s_axi_trace_cntrl_ARREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_RVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_RREADY : IN STD_LOGIC;
s_axi_trace_cntrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_trace_cntrl_BVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_BREADY : IN STD_LOGIC;
s_axi_trace_cntrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of trace_cntrl is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"trace_cntrl,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.628000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=631,HLS_SYN_LUT=706}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp1_stg0_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st12_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal data_compare_V : STD_LOGIC_VECTOR (63 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal sample_rate : STD_LOGIC_VECTOR (31 downto 0);
signal A_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_62 : BOOLEAN;
signal ap_sig_cseq_ST_pp1_stg0_fsm_9 : STD_LOGIC;
signal ap_sig_69 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal tmp_5_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal match_phi_fu_183_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal B_TDATA_blk_n : STD_LOGIC;
signal or_cond_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal match_reg_179 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_191 : STD_LOGIC_VECTOR (30 downto 0);
signal sample_rate_read_reg_407 : STD_LOGIC_VECTOR (31 downto 0);
signal length_read_reg_413 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_419 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal total_input_samples_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_147 : BOOLEAN;
signal A_temp_data_V_reg_430 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_reg_435 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_reg_440 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_reg_445 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_reg_450 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_171 : BOOLEAN;
signal tmp_5_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_175 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_1_fu_298_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal or_cond_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_fu_362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal sample_counter_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_counter_1_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_fu_90 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_1_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal A_temp_data_V_1_fu_94 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_1_fu_98 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_1_fu_102 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_1_fu_106 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_1_fu_110 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_1_fu_114 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal tmp_1_fu_236_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_10 : STD_LOGIC;
signal ap_sig_372 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
component trace_cntrl_mul_32s_32s_32_7 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component trace_cntrl_trace_cntrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
data_compare_V : OUT STD_LOGIC_VECTOR (63 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_rate : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
trace_cntrl_trace_cntrl_s_axi_U : component trace_cntrl_trace_cntrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_TRACE_CNTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_TRACE_CNTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_trace_cntrl_AWVALID,
AWREADY => s_axi_trace_cntrl_AWREADY,
AWADDR => s_axi_trace_cntrl_AWADDR,
WVALID => s_axi_trace_cntrl_WVALID,
WREADY => s_axi_trace_cntrl_WREADY,
WDATA => s_axi_trace_cntrl_WDATA,
WSTRB => s_axi_trace_cntrl_WSTRB,
ARVALID => s_axi_trace_cntrl_ARVALID,
ARREADY => s_axi_trace_cntrl_ARREADY,
ARADDR => s_axi_trace_cntrl_ARADDR,
RVALID => s_axi_trace_cntrl_RVALID,
RREADY => s_axi_trace_cntrl_RREADY,
RDATA => s_axi_trace_cntrl_RDATA,
RRESP => s_axi_trace_cntrl_RRESP,
BVALID => s_axi_trace_cntrl_BVALID,
BREADY => s_axi_trace_cntrl_BREADY,
BRESP => s_axi_trace_cntrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
data_compare_V => data_compare_V,
length_r => length_r,
sample_rate => sample_rate);
trace_cntrl_mul_32s_32s_32_7_U0 : component trace_cntrl_mul_32s_32s_32_7
generic map (
ID => 1,
NUM_STAGE => 7,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => sample_rate,
din1 => length_r,
ce => ap_const_logic_1,
dout => grp_fu_226_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_1 = B_TREADY)))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
A_temp_data_V_1_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_data_V_1_fu_94 <= A_TDATA;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_data_V_1_fu_94 <= A_temp_data_V_reg_430;
end if;
end if;
end process;
A_temp_dest_V_1_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_dest_V_1_fu_114 <= A_TDEST;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_dest_V_1_fu_114 <= A_temp_dest_V_reg_455;
end if;
end if;
end process;
A_temp_id_V_1_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_id_V_1_fu_110 <= A_TID;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_id_V_1_fu_110 <= A_temp_id_V_reg_450;
end if;
end if;
end process;
A_temp_keep_V_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_keep_V_1_fu_98 <= A_TKEEP;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_keep_V_1_fu_98 <= A_temp_keep_V_reg_435;
end if;
end if;
end process;
A_temp_strb_V_1_fu_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_strb_V_1_fu_102 <= A_TSTRB;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_strb_V_1_fu_102 <= A_temp_strb_V_reg_440;
end if;
end if;
end process;
A_temp_user_V_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_user_V_1_fu_106 <= A_TUSER;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_user_V_1_fu_106 <= A_temp_user_V_reg_445;
end if;
end if;
end process;
i_reg_191_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
i_reg_191 <= i_1_fu_298_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
i_reg_191 <= ap_const_lv31_0;
end if;
end if;
end process;
match_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_reg_179 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
match_reg_179 <= ap_const_lv1_1;
end if;
end if;
end process;
sample_counter_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
sample_counter_fu_86 <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and (ap_const_lv1_0 = or_cond_fu_342_p2))) then
sample_counter_fu_86 <= sample_counter_1_fu_348_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
sample_counter_fu_86 <= ap_const_lv32_0;
end if;
end if;
end process;
samples_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
samples_fu_90 <= samples_1_fu_367_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
samples_fu_90 <= ap_const_lv32_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0)))) then
A_temp_data_V_reg_430 <= A_TDATA;
A_temp_dest_V_reg_455 <= A_TDEST;
A_temp_id_V_reg_450 <= A_TID;
A_temp_keep_V_reg_435 <= A_TKEEP;
A_temp_strb_V_reg_440 <= A_TSTRB;
A_temp_user_V_reg_445 <= A_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
A_temp_last_V_reg_538 <= A_temp_last_V_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
length_read_reg_413 <= length_r;
sample_rate_read_reg_407 <= sample_rate;
tmp_reg_419 <= tmp_fu_232_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
or_cond_reg_534 <= or_cond_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_4_reg_520 <= tmp_4_fu_250_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
tmp_5_reg_525 <= tmp_5_fu_293_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
total_input_samples_reg_425 <= grp_fu_226_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, A_TVALID, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY, tmp_3_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if ((not((A_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_3_fu_245_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
elsif ((not((A_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_3_fu_245_p2)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
when ap_ST_pp1_stg0_fsm_9 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_NS_fsm <= ap_ST_st12_fsm_10;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
end if;
when ap_ST_st12_fsm_10 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
A_TDATA_blk_n_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4)))) then
A_TDATA_blk_n <= A_TVALID;
else
A_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
A_TREADY_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, match_phi_fu_183_p4, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
A_temp_last_V_fu_362_p2 <= "1" when (samples_fu_90 = tmp_4_reg_520) else "0";
B_TDATA <= A_temp_data_V_1_fu_94;
B_TDATA_blk_n_assign_proc : process(B_TREADY, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, or_cond_reg_534)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)))) then
B_TDATA_blk_n <= B_TREADY;
else
B_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
B_TDEST <= A_temp_dest_V_1_fu_114;
B_TID <= A_temp_id_V_1_fu_110;
B_TKEEP <= A_temp_keep_V_1_fu_98;
B_TLAST <= A_temp_last_V_reg_538;
B_TSTRB <= A_temp_strb_V_1_fu_102;
B_TUSER <= A_temp_user_V_1_fu_106;
B_TVALID_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, or_cond_reg_534, ap_sig_175, ap_reg_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY)))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_147 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_171 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_175_assign_proc : process(A_TVALID, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
ap_sig_175 <= (not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and (A_TVALID = ap_const_logic_0));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_372 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_62_assign_proc : process(ap_CS_fsm)
begin
ap_sig_62 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_69_assign_proc : process(ap_CS_fsm)
begin
ap_sig_69 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_cseq_ST_pp1_stg0_fsm_9_assign_proc : process(ap_sig_69)
begin
if (ap_sig_69) then
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st12_fsm_10_assign_proc : process(ap_sig_372)
begin
if (ap_sig_372) then
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_147)
begin
if (ap_sig_147) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_62)
begin
if (ap_sig_62) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_171)
begin
if (ap_sig_171) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
i_1_fu_298_p2 <= std_logic_vector(unsigned(i_reg_191) + unsigned(ap_const_lv31_1));
i_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(i_reg_191),32));
match_phi_fu_183_p4_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, match_reg_179, tmp_5_reg_525)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_phi_fu_183_p4 <= ap_const_lv1_0;
else
match_phi_fu_183_p4 <= match_reg_179;
end if;
end process;
or_cond_fu_342_p2 <= (tmp_7_fu_337_p2 or match_phi_fu_183_p4);
sample_counter_1_fu_348_p2 <= std_logic_vector(unsigned(sample_counter_fu_86) + unsigned(ap_const_lv32_1));
samples_1_fu_367_p2 <= std_logic_vector(unsigned(samples_fu_90) + unsigned(ap_const_lv32_1));
tmp_1_fu_236_p1 <= A_TDATA(32 - 1 downto 0);
tmp_2_fu_240_p2 <= (tmp_reg_419 and tmp_1_fu_236_p1);
tmp_3_fu_245_p2 <= "1" when (tmp_2_fu_240_p2 = tmp_reg_419) else "0";
tmp_4_fu_250_p2 <= std_logic_vector(signed(length_read_reg_413) + signed(ap_const_lv32_FFFFFFFF));
tmp_5_fu_293_p2 <= "1" when (signed(i_cast_fu_289_p1) < signed(total_input_samples_reg_425)) else "0";
tmp_7_fu_337_p2 <= "1" when (sample_counter_fu_86 = sample_rate_read_reg_407) else "0";
tmp_fu_232_p1 <= data_compare_V(32 - 1 downto 0);
end behav;
|
-- NEED RESULT: ENT00235.P00235: Associated scalar buffer ports with static subtypes passed
-- NEED RESULT: ENT00235: Associated scalar buffer ports with static subtypes passed
-- NEED RESULT: ENT00235.P00235: Associated scalar buffer ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00235
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00235(ARCH00235)
-- ENT00235_Test_Bench(ARCH00235_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00235 is
port (
toggle : buffer switch := down;
i_boolean_1, i_boolean_2 : buffer boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : buffer bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : buffer severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : buffer character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : buffer t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : buffer st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : buffer integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : buffer t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : buffer st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : buffer time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : buffer t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : buffer st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : buffer real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : buffer t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : buffer st_real1
:= c_st_real1_1
) ;
begin
end ENT00235 ;
--
architecture ARCH00235 of ENT00235 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
--
test_report ( "ENT00235" ,
"Associated scalar buffer ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
wait ;
end process ;
end ARCH00235 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00235_Test_Bench is
end ENT00235_Test_Bench ;
--
architecture ARCH00235_Test_Bench of ENT00235_Test_Bench is
begin
L1:
block
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
component UUT
port (
toggle : buffer switch ;
i_boolean_1, i_boolean_2 : buffer boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : buffer bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : buffer severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : buffer character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : buffer t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : buffer st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : buffer integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : buffer t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : buffer st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : buffer time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : buffer t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : buffer st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : buffer real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : buffer t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : buffer st_real1
:= c_st_real1_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00235 ( ARCH00235 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
P00235 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
end if ;
--
test_report ( "ENT00235.P00235" ,
"Associated scalar buffer ports with static subtypes",
correct) ;
end process P00235 ;
end block L1 ;
end ARCH00235_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: ga69kaw, Tolga Sel
--
-- Create Date: 08:38:20 11/04/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_idea.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: idea
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_idea IS
END tb_idea;
ARCHITECTURE behavior OF tb_idea IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT idea
PORT(
KEY : IN std_logic_vector(127 downto 0);
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal KEY : std_logic_vector(127 downto 0) := (others => '0');
signal X1 : std_logic_vector(15 downto 0) := (others => '0');
signal X2 : std_logic_vector(15 downto 0) := (others => '0');
signal X3 : std_logic_vector(15 downto 0) := (others => '0');
signal X4 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Y1 : std_logic_vector(15 downto 0);
signal Y2 : std_logic_vector(15 downto 0);
signal Y3 : std_logic_vector(15 downto 0);
signal Y4 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant I_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: idea PORT MAP (
KEY => KEY,
X1 => X1,
X2 => X2,
X3 => X3,
X4 => X4,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
-- Clock process definitions
test_process :process
begin
-- Test 1
X1 <= std_logic_vector(to_unsigned(1,16));
X2 <= std_logic_vector(to_unsigned(0,16));
X3 <= std_logic_vector(to_unsigned(1,16));
X4 <= std_logic_vector(to_unsigned(0,16));
KEY <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
wait for I_period/2;
-- Test 2
KEY <= "00000000000000010000000000000010000000000000001100000000000001000000000000000101000000000000011000000000000001110000000000001000";
X1 <= std_logic_vector(to_unsigned(0,16));
X2 <= std_logic_vector(to_unsigned(1,16));
X3 <= std_logic_vector(to_unsigned(2,16));
X4 <= std_logic_vector(to_unsigned(3,16));
wait for I_period/2;
-- Test 3
X1 <= std_logic_vector(to_unsigned(0,16));
X2 <= std_logic_vector(to_unsigned(1,16));
X3 <= std_logic_vector(to_unsigned(2,16));
X4 <= std_logic_vector(to_unsigned(3,16));
KEY <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
wait for I_period/2;
-- Test 4
KEY <= "00000000000000010000000000000010000000000000001100000000000001000000000000000101000000000000011000000000000001110000000000001000";
X1 <= std_logic_vector(to_unsigned(0,16));
X2 <= std_logic_vector(to_unsigned(1,16));
X3 <= std_logic_vector(to_unsigned(2,16));
X4 <= std_logic_vector(to_unsigned(3,16));
wait for I_period/2;
end process test_process;
END behavior; |
-- SKIP FIXME: Niklas remove this line, when the test succeeds
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity uart_tb is
end uart_tb;
architecture behav of uart_tb is
component uart_tx
port(
clk : in std_logic;
reset : in std_logic;
tx_start : in std_logic;
baud_tick : in std_logic;
tx_data : in std_logic_vector( 7 downto 0 );
tx_done_tick : out std_logic;
tx : out std_logic
);
end component;
component uart_rx
port (
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
baud_tick : in std_logic;
rx_done_tick : out std_logic;
rx_data : out std_logic_vector( 7 downto 0 )
);
end component;
type state_t is (idle, received, transmit);
signal rx_data: std_logic_vector(7 downto 0);
signal rx_done_tick, tx_done_tick: std_logic;
signal tx_data_next, tx_data: std_logic_vector(7 downto 0);
signal tx_start: std_logic;
signal reset, rx, tx: std_logic;
signal state_next, state: state_t;
signal clk : std_logic; -- system clock
signal baud_tick : std_logic; -- 19200
begin
tx_instance: uart_tx port map (clk, reset, tx_start, baud_tick, tx_data, tx_done_tick, tx);
rx_instance: uart_rx port map (clk, reset, rx, baud_tick, rx_done_tick, rx_data);
clk_process :process
begin
clk <= '0';
wait for 1 ns; --for 0.5 ns signal is '0'.
clk <= '1';
wait for 1 ns; --for next 0.5 ns signal is '1'.
end process;
baud_tick_process :process
begin
baud_tick <= '0';
wait for 1 ns; --for 0.5 ns signal is '0'.
baud_tick <= '1';
wait for 1 ns; --for next 0.5 ns signal is '1'.
end process;
reset_ctrl: process (clk, reset) is
begin
if reset = '1' then
tx_data <= "00000000";
elsif (clk'EVENT and (clk = '1')) then
tx_data <= tx_data_next;
end if;
end process;
test: process (state, rx_done_tick, tx_done_tick) is
begin
state_next <= state;
case(state) is
when idle =>
if(rx_done_tick = '1') then
tx_data_next <= rx_data;
tx_start <= '0';
state_next <= received;
end if;
when received =>
tx_start <= '1';
state_next <= transmit;
when transmit =>
if(tx_done_tick = '1') then
tx_start <= '0';
state_next <= idle;
end if;
end case;
end process;
end behav;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
----------------------------------------------------------------
-- uut:
-- nnlayer.vhd
-- neuron.vhd
-- fsm.vhd
-- distribuf.vhd
-- description:
-- simple test_bench to verify nnlayer behavior in normal
-- operating conditions
-- expected result:
-- neurons should be configured in weight configuration mode
-- in normal mode, neurons should input accumulation of
-- data*weights
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_nnlayer IS
END test_nnlayer;
ARCHITECTURE behavior OF test_nnlayer IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 16;
constant WWEIGHT : natural := 16;
constant WACCU : natural := 48;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 784;
constant NBNEU : natural := 10;
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WACCU : natural := WACCU;
-- Parameters for frame and number of neurons
FSIZE : natural := FSIZE;
NBNEU : natural := NBNEU
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WWEIGHT-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
-- Control signals
signal clk : std_logic := '0';
signal clear : std_logic := '0';
-- Ports for Write Enable
signal write_mode : std_logic := '0';
signal write_data : std_logic_vector(WWEIGHT-1 downto 0);
signal write_enable : std_logic := '0';
signal write_ready : std_logic := '0';
-- The user-specified frame size and number of neurons
signal user_fsize : std_logic_vector(15 downto 0);
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic := '0';
signal data_in_ready : std_logic := '0';
-- Scan chain to extract values
signal data_out : std_logic_vector(WACCU-1 downto 0);
signal data_out_valid : std_logic := '0';
-- Indicate to the parent component that we are reaching the end of the current frame
signal end_of_frame : std_logic := '0';
-- The output data enters a FIFO. This indicates the available room.
signal out_fifo_room : std_logic_vector(15 downto 0);
begin
-- Instantiate the Uni../recode.vhd:12:t Under Test (UUT)
uut: nnlayer
port map (
clk => clk,
clear => clear,
-- Ports for Write Enable
write_mode => write_mode,
write_data => write_data,
write_enable => write_enable,
write_ready => write_ready,
-- The user-specified frame size and number of neurons
user_fsize => user_fsize,
user_nbneu => user_nbneu,
-- Data input, 2 bits
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
-- Scan chain to extract values
data_out => data_out,
data_out_valid => data_out_valid,
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame => end_of_frame,
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room => out_fifo_room
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
--spy_process : process
--begin
-- init_signal_spy("/test_nnlayer/uut/fsm_gen/sensor_we_mode","sensor_we_mode",1,-1);
--end process;
-- Stimulus process
out_fifo_room_proc : process
begin
wait for clk_period;
out_fifo_room <= X"0007";
wait for clk_period;
wait for clk_period;
out_fifo_room <= X"0002";
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
wait for 3*clk_period;
clear <= '0';
write_data <= X"0001";
write_mode <= '1'; -- load weights
data_in_valid <= '1'; -- data is in FIFO
write_enable<='1';
wait for 9 * clk_period;
write_mode <= '0'; -- accu add
data_in <= X"0001";
while neurons < NBNEU loop
counter := 0;
write_data <= std_logic_vector(to_unsigned((neurons) mod 2 +1, write_data'length));
while (counter < FSIZE) loop
wait for clk_period;
ASSERT ( data_in_ready = '1')
REPORT "data_in_ready != 1";
counter := counter + 1;
wait for clk_period;
end loop;
neurons := neurons +1;
wait for 10 * clk_period;
end loop;
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_data <= X"0000";
data_in_valid <= '1'; -- data is in FIFO
counter := 0;
while (counter < FSIZE) loop
wait for clk_period;
counter := counter + 1;
wait for clk_period;
end loop;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 53
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 53
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 53
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n01i00015ent IS
END c04s02b00x00p06n01i00015ent;
ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
BEGIN
TESTING: PROCESS
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
BEGIN
assert NOT( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***PASSED TEST: c04s02b00x00p06n01i00015"
severity NOTE;
assert ( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n01i00015arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n01i00015ent IS
END c04s02b00x00p06n01i00015ent;
ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
BEGIN
TESTING: PROCESS
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
BEGIN
assert NOT( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***PASSED TEST: c04s02b00x00p06n01i00015"
severity NOTE;
assert ( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n01i00015arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n01i00015ent IS
END c04s02b00x00p06n01i00015ent;
ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
BEGIN
TESTING: PROCESS
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
BEGIN
assert NOT( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***PASSED TEST: c04s02b00x00p06n01i00015"
severity NOTE;
assert ( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n01i00015arch;
|
entity sub is
port (
result : out bit_vector(3 downto 0);
in1 : in bit_vector(3 downto 0) );
end entity;
architecture test of sub is
signal in2 : bit_vector(2 downto 0);
begin
assert in1(1 downto 0) = "00";
in2 <= "001";
result <= '0' & bit_vector(in1 and in2);
end architecture;
-------------------------------------------------------------------------------
entity partial1 is
end entity;
architecture test of partial1 is
signal result : bit_vector(3 downto 0);
signal in1 : bit_vector(1 downto 0);
begin
uut: entity work.sub
port map (
result => result,
in1(3 downto 2) => bit_vector(in1),
in1(1 downto 0) => "00" );
stim: process is
begin
in1 <= "01";
wait for 1 ns;
assert result = X"5";
wait;
end process;
end architecture;
|
entity range1 is
end entity;
architecture test of range1 is
begin
p1: process is
variable x : character;
begin
for i in 1 to 3 loop -- OK
end loop;
for i in character'range loop -- OK
end loop;
for i in character loop -- OK
end loop;
for i in x'range loop -- Error
end loop;
for i in x loop -- Error
end loop;
for i in 4 loop -- Error
end loop;
for i in integer range 1 to 3 loop -- OK
end loop;
for i in x range 'a' to 'b' loop -- Error
end loop;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgmii_rx_top_2 is
port(
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iMAC_HAL : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
iEnetRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iEnetRxDv : IN STD_LOGIC;
iEnetRxErr : IN STD_LOGIC;
-- hardware checksum check
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
--USR IF
iUDP_rx_rdy : IN STD_lOGIC;
oData_rx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oData_valid : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oEOF : OUT STD_LOGIC
);
end entity;
architecture rtl of rgmii_rx_top_2 is
COMPONENT rgmii_rx IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iRxEr : IN STD_LOGIC;
-- these signals come from wishbone clock domian, NOT synchronized
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
oEOF : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oCRCErr : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
oLenErr : OUT STD_LOGIC;
oCheckSumErr : OUT STD_LOGIC;
iMyMAC : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
oGetARP : OUT STD_LOGIC;
oGetIPv4 : BUFFER STD_LOGIC;
oGetCtrl : OUT STD_LOGIC;
oGetRaw : BUFFER STD_LOGIC;
oTaged : OUT STD_LOGIC;
oTagInfo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oStackTaged : BUFFER STD_LOGIC;
oTagInfo2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oLink : OUT STD_LOGIC;
oSpeed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
oDuplex : OUT STD_LOGIC;
oPayloadLen : BUFFER UNSIGNED(15 DOWNTO 0);
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL cSOF : STD_LOGIC;
SIGNAL cEof : STD_LOGIC;
SIGNAL cErrCrc : STD_LOGIC;
SIGNAL cErrLen : STD_LOGIC;
SIGNAL cGetArp : STD_LOGIC;
SIGNAL cErrCheckSum : STD_LOGIC;
SIGNAL cGetIPv4 : STD_LOGIC;
SIGNAL cGetCtrl : STD_LOGIC;
SIGNAL cGetRaw : STD_LOGIC;
SIGNAL cPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cRxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cRxDV : STD_LOGIC;
begin
rgmii_rx_1 : ENTITY work.rgmii_rx
PORT MAP (
iClk => iEthClk,
iRst_n => iRst_n,
iRxData => iEnetRxData,
iRxDV => iEnetRxDv,
iRxEr => iEnetRxErr,
iCheckSumIPCheck => iCheckSumIPCheck,
iCheckSumTCPCheck => iCheckSumTCPCheck,
iCheckSumUDPCheck => iCheckSumUDPCheck,
iCheckSumICMPCheck => iCheckSumICMPCheck,
oEOF => cEof,
oCRCErr => cErrCrc,
oRxErr => OPEN,
oLenErr => cErrLen,
oCheckSumErr => cErrCheckSum,
iMyMAC => iMAC_HAL,--MY_MAC,
oGetARP => cGetArp,
oGetIPv4 => cGetIPv4,
oGetCtrl => cGetCtrl,
oGetRaw => cGetRaw,
oSOF => cSOF,
oTaged => OPEN,
oTagInfo => OPEN,
oStackTaged => OPEN,
oTagInfo2 => OPEN,
oLink => OPEN,
oSpeed => OPEN,
oDuplex => OPEN,
oPayloadLen => cPayloadLen,
oRxData => cRxData,
oRxDV => cRxDV
);
-- rgmii_rx_2 : ENTITY work.rgmii_rx_2
-- PORT MAP(
-- iClk => iEthClk,
-- iRst_n => iRst_n,
--
-- iRxData => iEnetRxData,
-- iRxDV => iEnetRxDv,
-- iRxEr => iEnetRxErr,
--
-- iMAC_FPGA => iMAC_HAL,
--
-- iUdpRdy => iUDP_rx_rdy,
-- oRxData => cRxData,
-- oRxDV => cRxDV,
-- oEOF => cEof
-- );
oData_rx <= cRxData;
oData_valid <= cRxDV;
oSOF <= cSOF;
oEOF <= cEof;
end architecture; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Support package for self-checking testbenches
-- Author : Jonathan Hofman ([email protected])
-- Author : Ard Wiersma ([email protected])
-- Author : Edwin Hakkennes ([email protected])
-------------------------------------------------------------------------------
-- Description: Support package for self-checking testbenches
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_sctb_pkg is
---------------------------------------------------------------------------
-- constants for the log-level
---------------------------------------------------------------------------
constant c_log_level_error : integer := 0;
constant c_log_level_warning : integer := 1;
constant c_log_level_trace : integer := 2;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error);
procedure sctb_close_simulation(force: boolean := false);
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(region_name : string;
expected_errors : integer := 0);
procedure sctb_open_region(region_name : string;
msg : string;
expected_errors : integer := 0);
procedure sctb_close_region;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string);
procedure sctb_error(msg : string);
procedure sctb_warning(msg : string);
procedure sctb_trace(msg : string);
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string);
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string);
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string);
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string);
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string);
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to expect expected value correctness
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string);
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string);
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string);
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string);
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string);
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer);
procedure sctb_log_to_console(input : boolean := true);
---------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------
shared variable v_current_region: string(1 to 32);
end package;
package body tl_sctb_pkg is
---------------------------------------------------------------------------
-- private types, variables and constants
---------------------------------------------------------------------------
type t_string_ptr is access string;
type t_error_simulation is
record
output_file : t_string_ptr;
testcase_name : t_string_ptr;
region_active : boolean;
nr_of_regions : integer;
nr_of_failed_regions : integer;
nr_of_succeded_regions : integer;
log_level : integer;
end record;
shared variable c_error_simulation_rst : t_error_simulation := (
output_file => null,
testcase_name => null,
region_active => false,
nr_of_regions => 0,
nr_of_failed_regions => 0,
nr_of_succeded_regions => 0,
log_level => c_log_level_error);
shared variable error_simulation : t_error_simulation := c_error_simulation_rst;
type t_error_region is
record
name : t_string_ptr;
error_count : integer;
expected_errors : integer;
end record;
shared variable c_error_region_rst : t_error_region := (
name => null,
error_count => 0,
expected_errors => 0);
shared variable error_region : t_error_region;
file output_file : text;
shared variable v_log_to_console : boolean := true;
---------------------------------------------------------------------------
-- private procedures
---------------------------------------------------------------------------
-- purpose: write a line to the error log only, intended for pretty-printing
procedure write_line_log(str : string) is
variable v_line : line;
begin
if error_simulation.output_file = null then
print("[SCTB]" & str);
else
write(v_line, str);
writeline(output_file, v_line);
end if;
end procedure;
-- purpose: write a line to the error log and the console, conditionally
procedure write_line_cond (
str : string) is
begin -- write_line
if v_log_to_console then
print("[SCTB]"& str);
end if;
write_line_log(str);
end write_line_cond;
-- purpose: write a line to the error log and the console, unconditionally
procedure write_line (
str : string) is
begin -- write_line
print("[SCTB] " & time'image(now) & ": " & str);
write_line_log(str);
end write_line;
procedure write_line_of_stars is
begin -- write_line_of_stars
write_line_cond("*******************************************************************************");
end write_line_of_stars;
procedure print_header is
begin -- print_header
write_line_log("*******************************************************************************");
write_line_log("** **");
write_line_log("** (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL **");
write_line_log("** | ======= I == I = **");
write_line_log("** | I I I I **");
write_line_log("** | I === === I === I === === I I I ==== I === I === **");
write_line_log("** | I / \ I I/ I I/ I I I I I I I I I I I/ I **");
write_line_log("** | I ===== I I I I I I I I I I I I I I I I **");
write_line_log("** | I \ I I I I I I I I I /I \ I I I I I **");
write_line_log("** | I === === I I I I === === === I == I === I I **");
write_line_log("** | +---------------------------------------------------+ **");
write_line_log("** +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** | | ++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** +------------+ +++++++++++++++++++++++++| **");
write_line_log("** ++++++++++++++| **");
write_line_log("** A U T O M A T I O N T E C H N O L O G Y +++++| **");
write_line_log("** **");
write_line_log("*******************************************************************************");
end print_header;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(
testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error) is
variable testcase_name_int : string(1 to 80);
variable testcase_name_length : natural := 0;
variable v_stat : file_open_status;
begin
l_name_format : for i in 1 to 80 loop
exit l_name_format when testcase_name(i+1) = ':';
testcase_name_int(i) := testcase_name(i+1);
testcase_name_length := i;
end loop l_name_format; -- i
error_simulation := c_error_simulation_rst;
error_simulation.output_file := new string'(output_file_name);
error_simulation.testcase_name :=
new string'(testcase_name_int(1 to testcase_name_length));
file_open(v_stat, output_file, output_file_name, write_mode);
assert (v_stat = open_ok)
report "tl_sctb_pkg: Could not open file " & output_file_name & " for writing."
severity failure;
print_header;
write_line_log("");
write_line_of_stars;
write_line_cond("** Opening simulation : " &
error_simulation.testcase_name.all);
write_line_of_stars;
sctb_set_log_level(log_level);
end procedure;
procedure sctb_close_simulation(force: boolean := false) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: close active region before closing simulation!!"&
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if error_simulation.nr_of_failed_regions > 0 then
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line("** Simulation verdict : FAILURE - " &
integer'image(error_simulation.nr_of_failed_regions)
& " region(s) failed!");
write_line_of_stars;
file_close(output_file);
else
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line_cond("** Simulation verdict : SUCCESSFUL");
write_line_of_stars;
file_close(output_file);
end if;
if force then
report "simulation end forced using report failure (this does not imply a simulation error). " &
"See simulation verdict for actual simulation result!"
severity failure;
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(
region_name : string;
msg : string;
expected_errors : integer := 0) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: testbench failure - opening region """ & region_name
& """ without closing the last region first." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if msg = "" then
write_line_cond("** Opening region : " & region_name);
else
write_line_cond("** Opening region : " & region_name & " - " & msg);
end if;
write_line_cond("** Expected errors : " & integer'image(expected_errors));
write_line_log("**");
if error_region.name /= null then
deallocate(error_region.name);
end if;
error_region := c_error_region_rst;
error_region.name := new string'(region_name);
v_current_region := resize(region_name, v_current_region'length);
error_region.expected_errors := expected_errors;
error_simulation.region_active := true;
end procedure;
procedure sctb_open_region(
region_name : string;
expected_errors : integer := 0) is
begin
sctb_open_region(region_name, "", expected_errors);
end procedure;
procedure sctb_close_region is
begin
assert(error_simulation.region_active = true)
report "tl_sctb_pkg: testbench failure - closing an inactive region." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("**");
write_line_cond("** Closing region : " & error_region.name.all);
write_line_cond("** Expected errors : " & integer'image(error_region.expected_errors));
write_line_cond("** Errors : " & integer'image(error_region.error_count));
if error_region.error_count /= error_region.expected_errors then
write_line_cond("** Test verdict : FAILED");
error_simulation.nr_of_failed_regions := error_simulation.nr_of_failed_regions + 1;
else
write_line_cond("** Test verdict : SUCCEEDED");
error_simulation.nr_of_succeded_regions := error_simulation.nr_of_succeded_regions + 1;
end if;
write_line_of_stars;
error_simulation.region_active := false;
v_current_region := resize("none", v_current_region'length);
end procedure;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string) is
begin
if not condition then
sctb_error(msg);
end if;
end procedure;
procedure sctb_error(msg : string) is
begin
assert (error_simulation.region_active)
report "tl_sctb_pkg: testbench failure - Reporting an error while no error region is active." &
"Please correct your testbench and run the test again."
severity failure;
error_region.error_count := error_region.error_count + 1;
if error_region.error_count <= error_region.expected_errors then
write_line("(ERROR): " & msg);
else
write_line("[ERROR]: " & msg);
end if;
end procedure;
procedure sctb_warning(msg : string) is
begin
if error_simulation.log_level >= c_log_level_warning then
write_line("(WARNING): " & msg);
end if;
end procedure;
procedure sctb_trace(msg : string) is
begin
if error_simulation.log_level >= c_log_level_trace then
write_line("(TRACE): " & msg);
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to check expected value
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string)is
begin
sctb_expect(to_integer(expect),to_integer(got),msg);
end;
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & std_logic'image(expect)
&" Got : " & std_logic'image(got));
end;
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & integer'image(expect)
&" Got : " & integer'image(got));
end;
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & boolean'image(expect)
&" Got : " & boolean'image(got));
end;
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string)is
begin
if data_a'length <= 32 then
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : " & str(to_integer(data_a)) & " (0x" & hstr(std_logic_vector(data_a))
&") not identical to data_b : " & str(to_integer(data_b)) & " (0x" & hstr(std_logic_vector(data_b)) & ")");
else
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(std_logic_vector(data_a))
&" not identical to data_b : 0x" & hstr(std_logic_vector(data_b)));
end if;
end;
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&std_logic'image(data_a)
&" not identical to data_b : "&std_logic'image(data_b));
end;
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&integer'image(data_a)
&" not identical to data_b : "&integer'image(data_b));
end;
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&boolean'image(data_a)
&" not identical to data_b : "&boolean'image(data_b));
end;
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer) is
begin
error_simulation.log_level := log_level;
end procedure;
procedure sctb_log_to_console(input : boolean := true) is
begin
v_log_to_console := input;
end sctb_log_to_console;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Support package for self-checking testbenches
-- Author : Jonathan Hofman ([email protected])
-- Author : Ard Wiersma ([email protected])
-- Author : Edwin Hakkennes ([email protected])
-------------------------------------------------------------------------------
-- Description: Support package for self-checking testbenches
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_sctb_pkg is
---------------------------------------------------------------------------
-- constants for the log-level
---------------------------------------------------------------------------
constant c_log_level_error : integer := 0;
constant c_log_level_warning : integer := 1;
constant c_log_level_trace : integer := 2;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error);
procedure sctb_close_simulation(force: boolean := false);
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(region_name : string;
expected_errors : integer := 0);
procedure sctb_open_region(region_name : string;
msg : string;
expected_errors : integer := 0);
procedure sctb_close_region;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string);
procedure sctb_error(msg : string);
procedure sctb_warning(msg : string);
procedure sctb_trace(msg : string);
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string);
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string);
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string);
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string);
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string);
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to expect expected value correctness
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string);
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string);
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string);
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string);
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string);
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer);
procedure sctb_log_to_console(input : boolean := true);
---------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------
shared variable v_current_region: string(1 to 32);
end package;
package body tl_sctb_pkg is
---------------------------------------------------------------------------
-- private types, variables and constants
---------------------------------------------------------------------------
type t_string_ptr is access string;
type t_error_simulation is
record
output_file : t_string_ptr;
testcase_name : t_string_ptr;
region_active : boolean;
nr_of_regions : integer;
nr_of_failed_regions : integer;
nr_of_succeded_regions : integer;
log_level : integer;
end record;
shared variable c_error_simulation_rst : t_error_simulation := (
output_file => null,
testcase_name => null,
region_active => false,
nr_of_regions => 0,
nr_of_failed_regions => 0,
nr_of_succeded_regions => 0,
log_level => c_log_level_error);
shared variable error_simulation : t_error_simulation := c_error_simulation_rst;
type t_error_region is
record
name : t_string_ptr;
error_count : integer;
expected_errors : integer;
end record;
shared variable c_error_region_rst : t_error_region := (
name => null,
error_count => 0,
expected_errors => 0);
shared variable error_region : t_error_region;
file output_file : text;
shared variable v_log_to_console : boolean := true;
---------------------------------------------------------------------------
-- private procedures
---------------------------------------------------------------------------
-- purpose: write a line to the error log only, intended for pretty-printing
procedure write_line_log(str : string) is
variable v_line : line;
begin
if error_simulation.output_file = null then
print("[SCTB]" & str);
else
write(v_line, str);
writeline(output_file, v_line);
end if;
end procedure;
-- purpose: write a line to the error log and the console, conditionally
procedure write_line_cond (
str : string) is
begin -- write_line
if v_log_to_console then
print("[SCTB]"& str);
end if;
write_line_log(str);
end write_line_cond;
-- purpose: write a line to the error log and the console, unconditionally
procedure write_line (
str : string) is
begin -- write_line
print("[SCTB] " & time'image(now) & ": " & str);
write_line_log(str);
end write_line;
procedure write_line_of_stars is
begin -- write_line_of_stars
write_line_cond("*******************************************************************************");
end write_line_of_stars;
procedure print_header is
begin -- print_header
write_line_log("*******************************************************************************");
write_line_log("** **");
write_line_log("** (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL **");
write_line_log("** | ======= I == I = **");
write_line_log("** | I I I I **");
write_line_log("** | I === === I === I === === I I I ==== I === I === **");
write_line_log("** | I / \ I I/ I I/ I I I I I I I I I I I/ I **");
write_line_log("** | I ===== I I I I I I I I I I I I I I I I **");
write_line_log("** | I \ I I I I I I I I I /I \ I I I I I **");
write_line_log("** | I === === I I I I === === === I == I === I I **");
write_line_log("** | +---------------------------------------------------+ **");
write_line_log("** +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** | | ++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** +------------+ +++++++++++++++++++++++++| **");
write_line_log("** ++++++++++++++| **");
write_line_log("** A U T O M A T I O N T E C H N O L O G Y +++++| **");
write_line_log("** **");
write_line_log("*******************************************************************************");
end print_header;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(
testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error) is
variable testcase_name_int : string(1 to 80);
variable testcase_name_length : natural := 0;
variable v_stat : file_open_status;
begin
l_name_format : for i in 1 to 80 loop
exit l_name_format when testcase_name(i+1) = ':';
testcase_name_int(i) := testcase_name(i+1);
testcase_name_length := i;
end loop l_name_format; -- i
error_simulation := c_error_simulation_rst;
error_simulation.output_file := new string'(output_file_name);
error_simulation.testcase_name :=
new string'(testcase_name_int(1 to testcase_name_length));
file_open(v_stat, output_file, output_file_name, write_mode);
assert (v_stat = open_ok)
report "tl_sctb_pkg: Could not open file " & output_file_name & " for writing."
severity failure;
print_header;
write_line_log("");
write_line_of_stars;
write_line_cond("** Opening simulation : " &
error_simulation.testcase_name.all);
write_line_of_stars;
sctb_set_log_level(log_level);
end procedure;
procedure sctb_close_simulation(force: boolean := false) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: close active region before closing simulation!!"&
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if error_simulation.nr_of_failed_regions > 0 then
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line("** Simulation verdict : FAILURE - " &
integer'image(error_simulation.nr_of_failed_regions)
& " region(s) failed!");
write_line_of_stars;
file_close(output_file);
else
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line_cond("** Simulation verdict : SUCCESSFUL");
write_line_of_stars;
file_close(output_file);
end if;
if force then
report "simulation end forced using report failure (this does not imply a simulation error). " &
"See simulation verdict for actual simulation result!"
severity failure;
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(
region_name : string;
msg : string;
expected_errors : integer := 0) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: testbench failure - opening region """ & region_name
& """ without closing the last region first." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if msg = "" then
write_line_cond("** Opening region : " & region_name);
else
write_line_cond("** Opening region : " & region_name & " - " & msg);
end if;
write_line_cond("** Expected errors : " & integer'image(expected_errors));
write_line_log("**");
if error_region.name /= null then
deallocate(error_region.name);
end if;
error_region := c_error_region_rst;
error_region.name := new string'(region_name);
v_current_region := resize(region_name, v_current_region'length);
error_region.expected_errors := expected_errors;
error_simulation.region_active := true;
end procedure;
procedure sctb_open_region(
region_name : string;
expected_errors : integer := 0) is
begin
sctb_open_region(region_name, "", expected_errors);
end procedure;
procedure sctb_close_region is
begin
assert(error_simulation.region_active = true)
report "tl_sctb_pkg: testbench failure - closing an inactive region." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("**");
write_line_cond("** Closing region : " & error_region.name.all);
write_line_cond("** Expected errors : " & integer'image(error_region.expected_errors));
write_line_cond("** Errors : " & integer'image(error_region.error_count));
if error_region.error_count /= error_region.expected_errors then
write_line_cond("** Test verdict : FAILED");
error_simulation.nr_of_failed_regions := error_simulation.nr_of_failed_regions + 1;
else
write_line_cond("** Test verdict : SUCCEEDED");
error_simulation.nr_of_succeded_regions := error_simulation.nr_of_succeded_regions + 1;
end if;
write_line_of_stars;
error_simulation.region_active := false;
v_current_region := resize("none", v_current_region'length);
end procedure;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string) is
begin
if not condition then
sctb_error(msg);
end if;
end procedure;
procedure sctb_error(msg : string) is
begin
assert (error_simulation.region_active)
report "tl_sctb_pkg: testbench failure - Reporting an error while no error region is active." &
"Please correct your testbench and run the test again."
severity failure;
error_region.error_count := error_region.error_count + 1;
if error_region.error_count <= error_region.expected_errors then
write_line("(ERROR): " & msg);
else
write_line("[ERROR]: " & msg);
end if;
end procedure;
procedure sctb_warning(msg : string) is
begin
if error_simulation.log_level >= c_log_level_warning then
write_line("(WARNING): " & msg);
end if;
end procedure;
procedure sctb_trace(msg : string) is
begin
if error_simulation.log_level >= c_log_level_trace then
write_line("(TRACE): " & msg);
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to check expected value
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string)is
begin
sctb_expect(to_integer(expect),to_integer(got),msg);
end;
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & std_logic'image(expect)
&" Got : " & std_logic'image(got));
end;
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & integer'image(expect)
&" Got : " & integer'image(got));
end;
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & boolean'image(expect)
&" Got : " & boolean'image(got));
end;
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string)is
begin
if data_a'length <= 32 then
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : " & str(to_integer(data_a)) & " (0x" & hstr(std_logic_vector(data_a))
&") not identical to data_b : " & str(to_integer(data_b)) & " (0x" & hstr(std_logic_vector(data_b)) & ")");
else
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(std_logic_vector(data_a))
&" not identical to data_b : 0x" & hstr(std_logic_vector(data_b)));
end if;
end;
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&std_logic'image(data_a)
&" not identical to data_b : "&std_logic'image(data_b));
end;
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&integer'image(data_a)
&" not identical to data_b : "&integer'image(data_b));
end;
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&boolean'image(data_a)
&" not identical to data_b : "&boolean'image(data_b));
end;
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer) is
begin
error_simulation.log_level := log_level;
end procedure;
procedure sctb_log_to_console(input : boolean := true) is
begin
v_log_to_console := input;
end sctb_log_to_console;
end;
|
-- VHDL da Unidade de Controle da interface jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_interface_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
jogador : in std_logic; -- indica se o jogador é o primeiro a jogar ou o segundo
fim_impressao : in std_logic; -- indica que o tabuleiro terminou de ser impresso
fim_recepcao : in std_logic; -- indica que um caractere terminou de ser recebido
fim_transmissao : in std_logic; -- indica que um caractere terminou de ser eniado para a outra bancada
fim_jogo : in std_logic; -- indica que o jogo acabou
liga_modem : out std_logic; -- indica que a interface do modem deve ser ligada
imprime_tabuleiro : out std_logic; -- habilita a impressao do tabuleiro
envia_jogada : out std_logic; -- habilita o envio da jogada para a outra bancada
recebe_dado : out std_logic; -- habilita a recepção de um caractere do terminal
jogador_atual : out std_logic; -- indica o jogador atual do jogo da velha
dep_estados : out std_logic_vector(2 downto 0)
);
end unidade_controle_interface_jogo;
architecture comportamental of unidade_controle_interface_jogo is
type tipo_estado is (inicial, imprime_oponente, recebe_jogador, envia_caractere, imprime_jogador, recebe_oponente, imprime_final, final);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de start
if start = '1' then
if jogador='0' then
estado <= imprime_oponente;
else
estado <= imprime_jogador;
end if;
else
estado <= inicial;
end if;
when imprime_oponente => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= recebe_jogador;
else
estado <= imprime_oponente;
end if;
when recebe_jogador => -- Espera o dado ser recebido do terminal
if fim_recepcao = '1' then
estado <= envia_caractere;
elsif fim_jogo = '1' then
estado <= imprime_final;
else
estado <= recebe_jogador;
end if;
when envia_caractere =>
if fim_transmissao = '1' then
estado <= imprime_jogador;
else
estado <= envia_caractere;
end if;
when imprime_jogador => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= recebe_oponente;
else
estado <= imprime_jogador;
end if;
when recebe_oponente => -- Espera o dado ser recebido da outra bancada
if fim_recepcao = '1' then
estado <= imprime_oponente;
elsif fim_jogo = '1' then
estado <= imprime_final;
else
estado <= recebe_oponente;
end if;
when imprime_final => -- Imprime o tabuleiro no terminal
if fim_impressao = '1' then
estado <= final;
else
estado <= imprime_final;
end if;
when final =>
estado <= final;
when others => -- Default
estado <= inicial;
end case;
end if;
end process;
-- logica de saída
with estado select
imprime_tabuleiro <= '1' when imprime_oponente | imprime_jogador | imprime_final,
'0' when others;
with estado select
recebe_dado <= '1' when recebe_jogador | recebe_oponente,
'0' when others;
with estado select
envia_jogada <= '1' when envia_caractere,
'0' when others;
with estado select
jogador_atual <= '1' when imprime_oponente | recebe_oponente,
'0' when others;
with estado select
liga_modem <= '1' when envia_caractere | recebe_oponente,
'0' when others;
process (estado)
begin
case estado is
when inicial =>
dep_estados <= "000";
when imprime_oponente =>
dep_estados <= "001";
when recebe_jogador =>
dep_estados <= "010";
when envia_caractere =>
dep_estados <= "011";
when imprime_jogador =>
dep_estados <= "100";
when recebe_oponente =>
dep_estados <= "101";
when imprime_final =>
dep_estados <= "110";
when final =>
dep_estados <= "111";
when others =>
null;
end case;
end process;
end comportamental;
|
------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller is a client for the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- read - input pin, from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - input pin, from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - input pin, 8 bits, from ps2interface
-- - the byte received from the mouse.
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
-- tx_data - output pin, 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write - output pin, to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity mouse_controller is
port(
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end mouse_controller;
architecture Behavioral of mouse_controller is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(9 downto 0) := "1001111111";
-- 639
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(9 downto 0) := "0111011111";
-- 479
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(10 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max,y_max: std_logic_vector(9 downto 0) := (others => '0');
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
begin
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(9 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(9 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= '0' & value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended x_inc
inc := "111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(10) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended x_inc
inc := "000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= '0' & x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= '0' & value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended y_inc
inc := "111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(10) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended y_inc
inc := "000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > ('0' & y_max)) then
y_pos <= '0' & y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity ent is
end entity;
architecture a of ent is
constant CHECK : natural := 4;
signal last : std_logic;
signal clk: std_logic;
begin
process(clk)
variable i : natural range 0 to 127 := 0;
begin
if rising_edge(clk) then
if (((i+1) mod CHECK = 0) xor (last = '1')) then
report "Above line crashes";
end if;
i := i + 1;
end if;
end process;
end architecture;
|
--
-- OutputMemory.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity OutputMemory is
port (
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
addr : in std_logic_vector( 4 downto 0 );
wdata : in SIGNED_LI_TYPE;
rdata : out SIGNED_LI_TYPE;
addr2 : in std_logic_vector( 4 downto 0 );
rdata2 : out SIGNED_LI_TYPE
);
end entity;
architecture RTL of OutputMemory is
type SIGNED_LI_ARRAY_TYPE is array (0 to 18) of SIGNED_LI_VECTOR_TYPE;
signal data_array : SIGNED_LI_ARRAY_TYPE;
signal init_ch : integer range 0 to 18;
signal mem_wr_s : std_logic;
signal mem_addr_s : integer;
signal mem_data_s : SIGNED_LI_VECTOR_TYPE;
attribute ram_style : string;
attribute ram_style of data_array : signal is "block";
begin
mem_wr_s <= '1' when init_ch /= 18 else wr;
mem_addr_s <= init_ch when init_ch /= 18 else conv_integer(addr);
mem_data_s <= (others => '0') when init_ch /= 18 else CONV_SIGNED_LI_VECTOR(wdata);
process(clk, reset)
begin
if (reset = '1') then
init_ch <= 0;
elsif clk'event and clk='1' then
if mem_wr_s = '1' then
data_array(mem_addr_s) <= mem_data_s;
end if;
rdata <= CONV_SIGNED_LI(data_array(conv_integer(addr)));
rdata2 <= CONV_SIGNED_LI(data_array(conv_integer(addr2)));
if init_ch /= 18 then
init_ch <= init_ch + 1;
end if;
end if;
end process;
end architecture; |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of swled is
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- FIFOs implementing the channels
signal fifoCount : std_logic_vector(15 downto 0); -- MSB=writeFifo, LSB=readFifo
-- Write FIFO:
signal writeFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal writeFifoInputValid : std_logic; -- valid flag
signal writeFifoInputReady : std_logic; -- ready flag
signal writeFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal writeFifoOutputValid : std_logic; -- valid flag
signal writeFifoOutputReady : std_logic; -- ready flag
-- Read FIFO:
signal readFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal readFifoInputValid : std_logic; -- valid flag
signal readFifoInputReady : std_logic; -- ready flag
signal readFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal readFifoOutputValid : std_logic; -- valid flag
signal readFifoOutputReady : std_logic; -- ready flag
-- Counter which endlessly puts items into the read FIFO for the host to read
signal count, count_next : std_logic_vector(7 downto 0) := (others => '0');
-- Producer and consumer timers
signal producerSpeed : std_logic_vector(3 downto 0);
signal consumerSpeed : std_logic_vector(3 downto 0);
begin --BEGIN_SNIPPET(fifos)
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
count <= (others => '0');
else
count <= count_next;
end if;
end if;
end process;
-- Wire up write FIFO to channel 0 writes:
-- flags(2) driven by writeFifoOutputValid
-- writeFifoOutputReady driven by consumer_timer
-- LEDs driven by writeFifoOutputData
writeFifoInputData <=
h2fData_in;
writeFifoInputValid <=
'1' when h2fValid_in = '1' and chanAddr_in = "0000000"
else '0';
h2fReady_out <=
'0' when writeFifoInputReady = '0' and chanAddr_in = "0000000"
else '1';
-- Wire up read FIFO to channel 0 reads:
-- readFifoInputValid driven by producer_timer
-- flags(0) driven by readFifoInputReady
count_next <=
std_logic_vector(unsigned(count) + 1) when readFifoInputValid = '1'
else count;
readFifoInputData <=
count;
f2hValid_out <=
'0' when readFifoOutputValid = '0' and chanAddr_in = "0000000"
else '1';
readFifoOutputReady <=
'1' when f2hReady_in = '1' and chanAddr_in = "0000000"
else '0';
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
readFifoOutputData when "0000000", -- get from read FIFO
fifoCount(15 downto 8) when "0000001", -- get depth of write FIFO
fifoCount(7 downto 0) when "0000010", -- get depth of read FIFO
x"00" when others; --END_SNIPPET(fifos)
-- Write FIFO: written by host, read by LEDs
write_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(15 downto 8),
-- Production end
inputData_in => writeFifoInputData,
inputValid_in => writeFifoInputValid,
inputReady_out => writeFifoInputReady,
-- Consumption end
outputData_out => writeFifoOutputData,
outputValid_out => writeFifoOutputValid,
outputReady_in => writeFifoOutputReady
);
-- Read FIFO: written by counter, read by host
read_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(7 downto 0),
-- Production end
inputData_in => readFifoInputData,
inputValid_in => readFifoInputValid,
inputReady_out => readFifoInputReady,
-- Consumption end
outputData_out => readFifoOutputData,
outputValid_out => readFifoOutputValid,
outputReady_in => readFifoOutputReady
);
-- Producer timer: how fast stuff is put into the read FIFO
producerSpeed <= not(sw_in(3 downto 0));
producer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => producerSpeed,
tick_out => readFifoInputValid
);
-- Consumer timer: how fast stuff is drained from the write FIFO
consumerSpeed <= not(sw_in(7 downto 4));
consumer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => consumerSpeed,
tick_out => writeFifoOutputReady
);
-- LEDs and 7-seg display
led_out <= writeFifoOutputData;
flags <= '0' & writeFifoOutputValid & '0' & readFifoInputReady;
seven_seg : entity work.seven_seg
port map(
clk_in => clk_in,
data_in => fifoCount,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
|
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_no_default --config example/input/no_default.ini'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
constant addr_width : natural := 3;
constant data_width : natural := 32;
-- power
type power_enum is (false, -- disable
true); -- enable
function power_enum_to_sulv(v: power_enum ) return std_ulogic_vector;
function sulv_to_power_enum(v: std_ulogic_vector(1-1 downto 0)) return power_enum;
-- monkey
type monkey_enum is (chimp, -- a monkey
gorilla,
phb); -- and another monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum;
constant reg0_addr : natural := 0 ; -- 0x0
constant reg1_addr : natural := 1 ; -- 0x1
constant reg2_addr : natural := 2 ; -- 0x2
constant reg3_addr : natural := 3 ; -- 0x3
constant reg4_addr : natural := 4 ; -- 0x4
constant reg5_addr : natural := 5 ; -- 0x5
constant reg6_addr : natural := 6 ; -- 0x6
constant reg7_addr : natural := 7 ; -- 0x7
constant reg0_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
constant reg1_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg2_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg3_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width)); -- 0x00000001
constant reg4_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width)); -- 0x0000000c
constant reg7_reset_value : std_ulogic_vector(data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width)); -- 0x00000000
type reg0_record_type is record
byte3 : std_ulogic_vector(7 downto 0); -- [31:24]
byte2 : std_ulogic_vector(7 downto 0); -- [23:16]
byte1 : std_ulogic_vector(7 downto 0); -- [15:8]
byte0 : std_ulogic_vector(7 downto 0); -- [7:0]
end record;
type reg1_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg2_record_type is record
monkey2 : monkey_enum; -- [5:4]
monkey : monkey_enum; -- [3:2]
power2 : power_enum; -- [1:1]
power : power_enum; -- [0:0]
end record;
type reg3_record_type is record
field0 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg4_record_type is record
reg4 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg5_record_type is record
reg5 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg6_record_type is record
reg6 : std_ulogic_vector(31 downto 0); -- [31:0]
end record;
type reg7_record_type is record
nibble2 : std_ulogic_vector(3 downto 0); -- [19:16]
nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
end record;
type example_in_record_type is record
reg6 : reg6_record_type; -- addr 0x6
end record;
type example_out_record_type is record
reg0 : reg0_record_type; -- addr 0x0
reg1 : reg1_record_type; -- addr 0x1
reg2 : reg2_record_type; -- addr 0x2
reg3 : reg3_record_type; -- addr 0x3
reg4 : reg4_record_type; -- addr 0x4
reg5 : reg5_record_type; -- addr 0x5
reg7 : reg7_record_type; -- addr 0x7
end record;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
function reset_example return example_out_record_type;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type;
function reg0_record_type_to_sulv(v : reg0_record_type) return std_ulogic_vector;
function sulv_to_reg0_record_type(v : std_ulogic_vector) return reg0_record_type;
function reg1_record_type_to_sulv(v : reg1_record_type) return std_ulogic_vector;
function sulv_to_reg1_record_type(v : std_ulogic_vector) return reg1_record_type;
function reg2_record_type_to_sulv(v : reg2_record_type) return std_ulogic_vector;
function sulv_to_reg2_record_type(v : std_ulogic_vector) return reg2_record_type;
function reg3_record_type_to_sulv(v : reg3_record_type) return std_ulogic_vector;
function sulv_to_reg3_record_type(v : std_ulogic_vector) return reg3_record_type;
function reg4_record_type_to_sulv(v : reg4_record_type) return std_ulogic_vector;
function sulv_to_reg4_record_type(v : std_ulogic_vector) return reg4_record_type;
function reg5_record_type_to_sulv(v : reg5_record_type) return std_ulogic_vector;
function sulv_to_reg5_record_type(v : std_ulogic_vector) return reg5_record_type;
function reg6_record_type_to_sulv(v : reg6_record_type) return std_ulogic_vector;
function sulv_to_reg6_record_type(v : std_ulogic_vector) return reg6_record_type;
function reg7_record_type_to_sulv(v : reg7_record_type) return std_ulogic_vector;
function sulv_to_reg7_record_type(v : std_ulogic_vector) return reg7_record_type;
end;
package body example_vhd_pkg is
-- power
function power_enum_to_sulv(v: power_enum ) return std_ulogic_vector is
variable r : std_ulogic_vector(1-1 downto 0);
begin
case v is
when false => r:="0"; -- 0
when true => r:="1"; -- 1
end case;
return r;
end function;
function sulv_to_power_enum(v: std_ulogic_vector(1-1 downto 0)) return power_enum is
variable r : power_enum;
begin
case v is
when "0" => r:=false;
when "1" => r:=true;
when others => r:=false; -- error
end case;
return r;
end function;
-- monkey
function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector is
variable r : std_ulogic_vector(2-1 downto 0);
begin
case v is
when chimp => r:="00"; -- 0
when gorilla => r:="01"; -- 1
when phb => r:="10"; -- 2
end case;
return r;
end function;
function sulv_to_monkey_enum(v: std_ulogic_vector(2-1 downto 0)) return monkey_enum is
variable r : monkey_enum;
begin
case v is
when "00" => r:=chimp;
when "01" => r:=gorilla;
when "10" => r:=phb;
when others => r:=chimp; -- error
end case;
return r;
end function;
function reg0_record_type_to_sulv(v : reg0_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 24) := v.byte3;
r(23 downto 16) := v.byte2;
r(15 downto 8) := v.byte1;
r(7 downto 0) := v.byte0;
return r;
end function;
function sulv_to_reg0_record_type(v : std_ulogic_vector) return reg0_record_type is
variable r : reg0_record_type;
begin
r.byte3 := v(31 downto 24);
r.byte2 := v(23 downto 16);
r.byte1 := v(15 downto 8);
r.byte0 := v(7 downto 0);
return r;
end function;
function reg1_record_type_to_sulv(v : reg1_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg1_record_type(v : std_ulogic_vector) return reg1_record_type is
variable r : reg1_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg2_record_type_to_sulv(v : reg2_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(5 downto 4) := monkey_enum_to_sulv(v.monkey2);
r(3 downto 2) := monkey_enum_to_sulv(v.monkey);
r(1 downto 1) := power_enum_to_sulv(v.power2);
r(0 downto 0) := power_enum_to_sulv(v.power);
return r;
end function;
function sulv_to_reg2_record_type(v : std_ulogic_vector) return reg2_record_type is
variable r : reg2_record_type;
begin
r.monkey2 := sulv_to_monkey_enum(v(5 downto 4));
r.monkey := sulv_to_monkey_enum(v(3 downto 2));
r.power2 := sulv_to_power_enum(v(1 downto 1));
r.power := sulv_to_power_enum(v(0 downto 0));
return r;
end function;
function reg3_record_type_to_sulv(v : reg3_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.field0;
return r;
end function;
function sulv_to_reg3_record_type(v : std_ulogic_vector) return reg3_record_type is
variable r : reg3_record_type;
begin
r.field0 := v(31 downto 0);
return r;
end function;
function reg4_record_type_to_sulv(v : reg4_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg4;
return r;
end function;
function sulv_to_reg4_record_type(v : std_ulogic_vector) return reg4_record_type is
variable r : reg4_record_type;
begin
r.reg4 := v(31 downto 0);
return r;
end function;
function reg5_record_type_to_sulv(v : reg5_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg5;
return r;
end function;
function sulv_to_reg5_record_type(v : std_ulogic_vector) return reg5_record_type is
variable r : reg5_record_type;
begin
r.reg5 := v(31 downto 0);
return r;
end function;
function reg6_record_type_to_sulv(v : reg6_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(31 downto 0) := v.reg6;
return r;
end function;
function sulv_to_reg6_record_type(v : std_ulogic_vector) return reg6_record_type is
variable r : reg6_record_type;
begin
r.reg6 := v(31 downto 0);
return r;
end function;
function reg7_record_type_to_sulv(v : reg7_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
r := (others => '0');
r(19 downto 16) := v.nibble2;
r(11 downto 8) := v.nibble1;
r(3 downto 0) := v.nibble0;
return r;
end function;
function sulv_to_reg7_record_type(v : std_ulogic_vector) return reg7_record_type is
variable r : reg7_record_type;
begin
r.nibble2 := v(19 downto 16);
r.nibble1 := v(11 downto 8);
r.nibble0 := v(3 downto 0);
return r;
end function;
function read_example(registers_i : example_in_record_type;
registers_o : example_out_record_type;
address : std_ulogic_vector(addr_width-1 downto 0)
) return std_ulogic_vector is
variable r : std_ulogic_vector(data_width-1 downto 0);
begin
case to_integer(unsigned(address)) is
when reg0_addr => r:= reg0_record_type_to_sulv(registers_o.reg0);
when reg1_addr => r:= reg1_record_type_to_sulv(registers_o.reg1);
when reg2_addr => r:= reg2_record_type_to_sulv(registers_o.reg2);
when reg3_addr => r:= reg3_record_type_to_sulv(registers_o.reg3);
when reg4_addr => r:= reg4_record_type_to_sulv(registers_o.reg4);
when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
when others => r := (others => '0');
end case;
return r;
end function;
function write_example(value : std_ulogic_vector(data_width-1 downto 0);
address : std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
when others => null;
end case;
return r;
end function;
function reset_example return example_out_record_type is
variable r : example_out_record_type;
begin
r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
return r;
end function;
function reset_example(address: std_ulogic_vector(addr_width-1 downto 0);
registers_o : example_out_record_type
) return example_out_record_type is
variable r : example_out_record_type;
begin
r := registers_o;
case to_integer(unsigned(address)) is
when reg0_addr => r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
when reg1_addr => r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
when reg2_addr => r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
when reg3_addr => r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
when reg4_addr => r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
when reg7_addr => r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
when others => null;
end case;
return r;
end function;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_MRd_Transact is
port (
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
-- trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
IORd_Type : IN std_logic;
MRd_Type : IN std_logic_vector(3 downto 0);
Tlp_straddles_4KB : IN std_logic;
-- MRd Channel
pioCplD_Req : OUT std_logic;
pioCplD_RE : IN std_logic;
pioCplD_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FIFO_Data_Count : IN std_logic_vector(C_FIFO_DC_WIDTH-1 downto 0);
FIFO_Empty : IN std_logic;
FIFO_Reading : IN std_logic;
pio_FC_stop : IN std_logic;
pio_reading_status : OUT std_logic;
-- Channel reset (from MWr channel)
Channel_Rst : IN std_logic;
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
end entity rx_MRd_Transact;
architecture Behavioral of rx_MRd_Transact is
type RxMRdTrnStates is ( ST_MRd_RESET
, ST_MRd_IDLE
, ST_MRd_HEAD2
, ST_MRd_Tail
);
-- State variables
signal RxMRdTrn_NextState : RxMRdTrnStates;
signal RxMRdTrn_State : RxMRdTrnStates;
-- trn_rx stubs
signal trn_rsof_n_i : std_logic;
signal trn_reof_n_i : std_logic;
signal trn_rd_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rerrfwd_n_i : std_logic;
-- delays
signal trn_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rbar_hit_n_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- BAR encoded
signal Encoded_BAR_Index : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Reset
signal local_Reset : std_logic;
-- Output signals
-- signal trn_rdst_rdy_n_i : std_logic;
signal trn_rnp_ok_n_i : std_logic;
signal trn_rsrc_dsc_n_i : std_logic;
-- Throttle
signal trn_rx_throttle : std_logic;
signal pio_reading_status_i : std_logic;
signal pio_read_fading_cnt : std_logic_vector(8-1 downto 0);
signal MRd_Has_3DW_Header : std_logic;
signal MRd_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal Illegal_Leng_on_FIFO : std_logic;
-- Built-in single-port fifo as MRd channel buffer
component k7_sfifo_15x128
port (
clk : IN std_logic;
rst : IN std_logic;
prog_full : OUT std_logic;
-- wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : OUT std_logic;
-- rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic
);
end component;
-- Signal with MRd channel FIFO
signal pioCplD_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_RE_i : std_logic;
signal pioCplD_we : std_logic;
signal pioCplD_empty_i : std_logic;
signal pioCplD_full : std_logic;
signal pioCplD_prog_Full : std_logic;
signal pioCplD_empty_r1 : std_logic;
signal pioCplD_prog_full_r1 : std_logic;
signal pioCplD_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Request for output arbitration
signal pioCplD_Req_i : std_logic;
signal pioCplD_Leng : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
-- , REQST_Quantity
-- , REQST_FIFO_Req
);
signal FSM_REQ_pio : FSM_Request;
begin
-- positive reset and local
local_Reset <= not trn_reset_n or Channel_Rst;
-- MRd channel buffer control
-- pioCplD_RE_i <= pioCplD_RE;
pioCplD_Qout <= pioCplD_Qout_i;
pioCplD_Req <= pioCplD_Req_i; -- and not FIFO_Reading;
pio_reading_status <= pio_reading_status_i;
-- Output to the core as handshaking
trn_rsof_n_i <= trn_rsof_n;
trn_reof_n_i <= trn_reof_n;
trn_rd_i <= trn_rd;
trn_rrem_n_i <= trn_rrem_n;
trn_rerrfwd_n_i <= trn_rerrfwd_n;
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
trn_rbar_hit_n_i <= trn_rbar_hit_n;
-- Output to the core as handshaking
trn_rnp_ok_n <= trn_rnp_ok_n_i;
trn_rnp_ok_n_i <= pioCplD_prog_full_r1;
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
trn_rx_throttle <= trn_rsrc_rdy_n; -- or trn_rdst_rdy_n_i;
-- ------------------------------------------------
-- Synchronous Delay: trn_rd + trn_rbar_hit_n
--
Synch_Delay_trn_rd:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_rd_r1 <= trn_rd_i;
trn_rbar_hit_n_r1 <= trn_rbar_hit_n_i;
end if;
end process;
-- ------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
RxMRdTrn_State <= ST_MRd_RESET;
elsif trn_clk'event and trn_clk = '1' then
RxMRdTrn_State <= RxMRdTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates:
process (
RxMRdTrn_State
, MRd_Type
-- , IORd_Type
, trn_rx_throttle
, trn_rnp_ok_n_i
, trn_rsrc_dsc_n_i
, trn_rerrfwd_n_i
)
begin
case RxMRdTrn_State is
when ST_MRd_RESET =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
when ST_MRd_IDLE =>
if trn_rnp_ok_n_i='0' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when OTHERS =>
-- if IORd_Type='1' then -- Temp taking IORd as MRd3
-- RxMRdTrn_NextState <= ST_MRd3_HEAD1;
-- else
RxMRdTrn_NextState <= ST_MRd_IDLE;
-- end if;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when ST_MRd_HEAD2 =>
if trn_rx_throttle = '1' then
RxMRdTrn_NextState <= ST_MRd_HEAD2;
else
RxMRdTrn_NextState <= ST_MRd_Tail;
end if;
when ST_MRd_Tail => -- support back-to-back transactions
if trn_rnp_ok_n_i='0' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when OTHERS =>
-- if IORd_Type='1' then -- Temp taking IORd as MRd3
-- RxMRdTrn_NextState <= ST_MRd3_HEAD1;
-- else
RxMRdTrn_NextState <= ST_MRd_IDLE;
-- end if;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when OTHERS =>
RxMRdTrn_NextState <= ST_MRd_RESET;
end case;
end process;
-- ------------------------------------------------
-- Synchronous calculation: Encoded_BAR_Index
--
Syn_Calc_Encoded_BAR_Index:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
Encoded_BAR_Index <= (OTHERS=>'1');
elsif trn_clk'event and trn_clk = '1' then
if trn_rbar_hit_n(0)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(1)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(1, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(2)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(2, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(3)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(3, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(4)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(4, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(5)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(5, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(6)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(6, C_ENCODE_BAR_NUMBER);
else
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(7, C_ENCODE_BAR_NUMBER);
end if;
end if;
end process;
-- ----------------------------------------------------------------------------------
--
-- Synchronous output: MRd FIFO write port
--
-- PIO Channel Buffer (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 97 : reserved
-- 96 : Zero-length
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 68 : reserved
-- 67 ~ 65 : BAR number
-- 64 ~ 49 : Requester ID
-- 48 ~ 41 : Tag
-- 40 ~ 34 : Lower Address
-- 33 ~ 31 : Completion Status
-- 30 ~ 19 : Byte count
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
RxFSM_Output_pioCplD_WR:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
pioCplD_we <= '0';
pioCplD_din <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxMRdTrn_State is
when ST_MRd_HEAD2 =>
pioCplD_we <= '0';
if Illegal_Leng_on_FIFO='1' then -- Cpl : unsupported request
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT)
<= C_FMT3_NO_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT)
<= "001"; --------------- ############
else
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT)
<= C_FMT3_WITH_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT)
<= "000"; --------------- ############
end if;
pioCplD_din(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT)
<= trn_rd_r1(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT);
pioCplD_din(C_CHBUF_TD_BIT) <= '0';
pioCplD_din(C_CHBUF_EP_BIT) <= '0';
pioCplD_din(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT)
-- <= trn_rd_r1(C_TLP_ATTR_BIT_TOP) & C_NO_SNOOP; -- downto C_TLP_ATTR_BIT_BOT);
<= trn_rd_r1(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT);
pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
<= trn_rd_r1(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
pioCplD_din(C_CHBUF_QVALID_BIT) <= '1';
pioCplD_din(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT)
<= trn_rd_r1(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT);
pioCplD_din(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT)
<= trn_rd_r1(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT);
pioCplD_din(C_CHBUF_0LENG_BIT) <= Tlp_is_Zero_Length;
if Tlp_is_Zero_Length='1' then
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
else
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
<= Encoded_BAR_Index;
end if;
when ST_MRd_Tail =>
if MRd_Has_4DW_Header='1' then
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT downto 0);
if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "000";
elsif trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_MA_BIT_TOP-C_CHBUF_MA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
elsif trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= C_ALL_ONES(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT); --- "111" !!!
end if;
else
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT+32 downto 32);
if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "000";
elsif trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_MA_BIT_TOP-C_CHBUF_MA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
elsif trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= C_ALL_ONES(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT); --- "111" !!!
end if;
end if;
if pioCplD_din(C_CHBUF_0LENG_BIT) ='1' then -- Zero-length
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(1, C_CHBUF_CPLD_BC_BIT_TOP-C_CHBUF_CPLD_BC_BIT_BOT+1);
else
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) &"00";
end if;
-- if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0'
-- or trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0'
-- then
if trn_rbar_hit_n_r1(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0) then
pioCplD_we <= not Tlp_straddles_4KB; --'1';
else
pioCplD_we <= '0';
end if;
when OTHERS =>
pioCplD_we <= '0';
pioCplD_din <= pioCplD_din;
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MRd_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MRd_Has_4DW_Header:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
MRd_Has_3DW_Header <= '0';
MRd_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
Illegal_Leng_on_FIFO <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' then
MRd_Has_3DW_Header <= not trn_rd_i(C_TLP_FMT_BIT_BOT) and not trn_rd_i(C_TLP_FMT_BIT_BOT+1);
MRd_Has_4DW_Header <= trn_rd_i(C_TLP_FMT_BIT_BOT) and not trn_rd_i(C_TLP_FMT_BIT_BOT+1);
Tlp_is_Zero_Length <= not (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0));
if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)/=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)/=CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rbar_hit_n(CINT_FIFO_SPACE_BAR)='0'
then
Illegal_Leng_on_FIFO <= '1';
else
Illegal_Leng_on_FIFO <= '0';
end if;
else
MRd_Has_3DW_Header <= MRd_Has_3DW_Header;
MRd_Has_4DW_Header <= MRd_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
Illegal_Leng_on_FIFO <= Illegal_Leng_on_FIFO;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- syn
-- : pio_reading_status
--
Syn_PIO_Reading_EB_Status:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if trn_reof_n_i='0' then
if MRd_Has_4DW_Header='1'
and trn_rbar_hit_n(CINT_REGS_SPACE_BAR)='0'
and trn_rd_i(8-1 downto 0)=X"90" then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= X"E0";
elsif MRd_Has_3DW_Header='1'
and trn_rbar_hit_n(CINT_REGS_SPACE_BAR)='0'
and trn_rd_i(32+8-1 downto 32)=X"90" then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= X"E0";
elsif pio_read_fading_cnt(7)='1' then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= pio_read_fading_cnt + '1';
else
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
end if;
elsif pio_read_fading_cnt=X"00" then
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
else
pio_reading_status_i <= pio_reading_status_i;
pio_read_fading_cnt <= pio_read_fading_cnt + '1';
end if;
end if;
end process;
-- -------------------------------------------------
-- MRd TLP Buffer
-- -------------------------------------------------
pioCplD_Buffer:
k7_sfifo_15x128
port map (
clk => trn_clk,
rst => local_Reset,
prog_full => pioCplD_prog_Full,
-- wr_clk => trn_clk,
wr_en => pioCplD_we,
din => pioCplD_din,
full => pioCplD_full,
-- rd_clk => trn_clk,
rd_en => pioCplD_RE_i,
dout => pioCplD_Qout_wire,
prog_empty => open,
empty => pioCplD_empty_i
);
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc:
process (local_Reset, trn_clk )
begin
if local_Reset = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (OTHERS=>'0');
pioCplD_Qout_reg <= (OTHERS=>'0');
pioCplD_Leng <= (0=>'1', OTHERS=>'0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case FSM_REQ_pio is
when REQST_IDLE =>
if pioCplD_empty_i = '0' then
pioCplD_RE_i <= '1';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_1Read;
else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_IDLE;
end if;
when REQST_1Read =>
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_Decision;
when REQST_Decision =>
pioCplD_Qout_reg <= pioCplD_Qout_wire;
pioCplD_Leng <= pioCplD_Qout_wire(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
pioCplD_Qout_i <= pioCplD_Qout_i;
-- if pioCplD_Qout_wire(C_CHBUF_FMT_BIT_TOP) = '1' -- Has Payload
-- and pioCplD_Qout_wire(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- =CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
-- then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- FSM_REQ_pio <= REQST_Quantity;
-- else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
-- end if;
when REQST_nFIFO_Req =>
if pioCplD_RE = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_reg;
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
else
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
end if;
-- when REQST_Quantity =>
-- if FIFO_Empty='1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- FSM_REQ_pio <= REQST_Quantity;
-- else
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- pioCplD_Req_i <= '1';
-- FSM_REQ_pio <= REQST_FIFO_Req;
-- end if;
--
-- when REQST_FIFO_Req =>
-- if FIFO_Empty='1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- FSM_REQ_pio <= REQST_Quantity;
-- elsif pioCplD_RE = '1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_reg;
-- pioCplD_Req_i <= '0';
-- FSM_REQ_pio <= REQST_IDLE;
-- else
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- pioCplD_Req_i <= '1';
-- FSM_REQ_pio <= REQST_FIFO_Req;
-- end if;
when OTHERS =>
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (OTHERS=>'0');
pioCplD_Qout_reg <= (OTHERS=>'0');
pioCplD_Leng <= (OTHERS=>'1');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
pioCplD_empty_r1 <= pioCplD_empty_i;
pioCplD_prog_full_r1 <= pioCplD_prog_Full;
end if;
end process;
end architecture Behavioral;
|
-- ENTITY_NAME.vhd
-- -----------------------------------------------------------------------
-- brief description
-- -----------------------------------------------------------------------
-- Version : 0.0
-- Date : Jan 1999
-- Author : First Last
-- Web : http://website.com
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. point 1
-- 2. point 2
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ENTITY_NAME_inc is -- component declaration package
type ENTITY_NAME_in_t is record
en : bit;
end record;
type ENTITY_NAME_out_t is record
rdy: bit;
end record;
component ENTITY_NAME is
port(
clk : in std_logic;
reset : in std_logic;
d : in ENTITY_NAME_in_t;
q : out ENTITY_NAME_out_t);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ENTITY_NAME_inc.all;
entity ENTITY_NAME is
port(
clk : in std_logic;
reset : in std_logic;
d : in ENTITY_NAME_in_t;
q : out ENTITY_NAME_out_t);
end ENTITY_NAME;
architecture handler of ENTITY_NAME is
type not_reset_t is record
dummy : bit;
end record;
type state_t is (idle );
type reg_t is record
nr : not_reset_t;
state : state_t;
end record;
signal r, rin : reg_t;
begin --architecture
comb : process(r,d)
variable v : reg_t;
begin
--parameters
v := r;
--algorithm goes here
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.state <= idle;
elsif rising_edge(clk) then
r.state <= rin.state;
end if;
end process;
--everything in iface does not need to be reset
seq_nrst : process
begin
wait until rising_edge(clk);
r.nr <= rin.nr;
end process;
end architecture;
|
entity test is
type t is range 0 to 16#f.f#e2;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc198.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p04n01i00198ent IS
END c03s01b00x00p04n01i00198ent;
ARCHITECTURE c03s01b00x00p04n01i00198arch OF c03s01b00x00p04n01i00198ent IS
type t1 is range (1+1) to (10+2);
BEGIN
TESTING: PROCESS
variable k : t1 := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b00x00p04n01i00198"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b00x00p04n01i00198- The range must be either a range attribute name or two simple expressions combined with a direction operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p04n01i00198arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc198.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p04n01i00198ent IS
END c03s01b00x00p04n01i00198ent;
ARCHITECTURE c03s01b00x00p04n01i00198arch OF c03s01b00x00p04n01i00198ent IS
type t1 is range (1+1) to (10+2);
BEGIN
TESTING: PROCESS
variable k : t1 := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b00x00p04n01i00198"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b00x00p04n01i00198- The range must be either a range attribute name or two simple expressions combined with a direction operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p04n01i00198arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc198.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p04n01i00198ent IS
END c03s01b00x00p04n01i00198ent;
ARCHITECTURE c03s01b00x00p04n01i00198arch OF c03s01b00x00p04n01i00198ent IS
type t1 is range (1+1) to (10+2);
BEGIN
TESTING: PROCESS
variable k : t1 := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b00x00p04n01i00198"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b00x00p04n01i00198- The range must be either a range attribute name or two simple expressions combined with a direction operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p04n01i00198arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_async.vhd when simulating
-- the core, fifo_async. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_async IS
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END fifo_async;
ARCHITECTURE fifo_async_a OF fifo_async IS
-- synthesis translate_off
component wrapped_fifo_async
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_async use entity XilinxCoreLib.fifo_generator_v3_2(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_async
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synthesis translate_on
END fifo_async_a;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00186
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00186
-- PKG00186/BODY
-- E00000(ARCH00186)
-- ENT00186_Test_Bench(ARCH00186_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00186 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00186 ;
--
package body PKG00186 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00186 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00186.all ;
architecture ARCH00186 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00186" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00186 ;
--
entity ENT00186_Test_Bench is
end ENT00186_Test_Bench ;
--
architecture ARCH00186_Test_Bench of ENT00186_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00186 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00186_Test_Bench ;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity lp_filter is
generic (
g_divider : natural := 221 );
port (
clock : in std_logic;
reset : in std_logic;
signal_in : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
error_out : out std_logic;
valid_out : out std_logic );
end entity;
architecture dsvf of lp_filter is
signal filter_q : signed(signal_in'range);
signal filter_f : signed(signal_in'range);
signal input_sc : signed(signal_in'range);
signal xa : signed(signal_in'range);
signal xb : signed(signal_in'range);
signal sum_b : signed(signal_in'range);
signal sub_a : signed(signal_in'range);
signal sub_b : signed(signal_in'range);
signal x_reg : signed(signal_in'range) := (others => '0');
signal bp_reg : signed(signal_in'range);
signal hp_reg : signed(signal_in'range);
signal lp_reg : signed(signal_in'range);
signal temp_reg : signed(signal_in'range);
signal error : std_logic := '0';
signal divider : integer range 0 to g_divider-1;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
begin
-- -- Derive the actual 'f' and 'q' parameters
-- i_q_table: entity work.Q_table
-- port map (
-- Q_reg => X"6",
-- filter_q => filter_q ); -- 2.16 format
filter_q <= to_signed(65536, filter_q'length); -- 92682
filter_f <= to_signed(16384, filter_f'length);
input_sc <= signal_in; -- shift_right(signal_in, 1);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg when xb_select='0' else hp_reg;
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(17 downto 0);
variable sub_result : signed(17 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 16);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
temp_reg <= sum_result;
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
divider <= 0;
elsif divider = g_divider-1 then
divider <= 0;
else
divider <= divider + 1;
if divider < c_program'length then
instruction <= c_program(divider);
end if;
end if;
if divider = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg;
band_pass <= bp_reg;
low_pass <= lp_reg;
error_out <= error;
end dsvf;
|
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on Ben Jordon's code in this forum post:
-- http://forum.allaboutcircuits.com/showthread.php?t=23344
--
library ieee;
use ieee.std_logic_1164.all;
entity Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end Rotary;
architecture behavioral of Rotary is
signal prevA, prevB: std_logic;
signal currA, currB: std_logic;
begin
read_rotary: process(clock)
begin
if clock'event and clock = '1' then
prevA <= currA;
prevB <= currB;
currA <= A;
currB <= B;
if prevA = '0' and currA = '1' then -- a rising
if currB = '1' then
inc <= '0';
dec <= '1';
elsif currB = '0' then
inc <= '1';
dec <= '0';
end if;
elsif prevA = '1' and currA = '0' then -- a falling
if currB = '1' then
inc <= '1';
dec <= '0';
elsif currB = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '0' and currB = '1' then -- b rising
if currA = '1' then
inc <= '1';
dec <= '0';
elsif currA = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '1' and currB = '0' then -- b falling
if currA = '1' then
inc <= '0';
dec <= '1';
elsif currA = '0' then
inc <= '1';
dec <= '0';
end if;
else
inc <= '0';
dec <= '0';
end if;
end if;
end process;
end behavioral;
|
-- cb20_gpio_block_0.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 9;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000001"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_0;
architecture rtl of cb20_gpio_block_0 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 9 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000001" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_0 : component avalon_gpio_interface
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_0
|
component ledtest is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
jtag_debug_master_reset_reset : out std_logic; -- reset
led_array_io_export : out std_logic_vector(7 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
switch_array_io_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component ledtest;
u0 : component ledtest
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
jtag_debug_master_reset_reset => CONNECTED_TO_jtag_debug_master_reset_reset, -- jtag_debug_master_reset.reset
led_array_io_export => CONNECTED_TO_led_array_io_export, -- led_array_io.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
switch_array_io_export => CONNECTED_TO_switch_array_io_export -- switch_array_io.export
);
|
-------------------------------------------------------------------------------
-- Title : Vectoring-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_vectoring_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-13
-- Last update: 2014-09-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a top-block for vectoring mode using concordic,
-- constrained standard_logic_vector version.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-13 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity cordic_vectoring_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32
);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic
);
end entity cordic_vectoring_slv;
-------------------------------------------------------------------------------
architecture str of cordic_vectoring_slv is
signal adjusted_x : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_y : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_z : signed(g_width-1 downto 0) := (others => '0');
signal mag_temp : signed(g_width-1 downto 0) := (others => '0');
signal phase_temp : signed(g_width-1 downto 0) := (others => '0');
signal y_temp : signed(g_width-1 downto 0) := (others => '0');
signal valid_temp : std_logic := '0';
component inversion_stage is
generic (
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component inversion_stage;
component cordic_core is
generic (
g_stages : natural;
g_mode : string;
g_bit_growth : natural);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component cordic_core;
begin -- architecture str
cmp_inversion : inversion_stage
generic map (
g_mode => "rect_to_polar")
port map (
x_i => signed(x_i),
y_i => signed(y_i),
z_i => (g_width-1 downto 0 => '0'),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
x_o => adjusted_x,
y_o => adjusted_y,
z_o => adjusted_z,
valid_o => valid_temp);
cmp_core : cordic_core
generic map (
g_stages => g_stages,
g_mode => "rect_to_polar",
g_bit_growth => natural(ceil(log2(real(g_stages)))))
port map (
x_i => adjusted_x,
y_i => adjusted_y,
z_i => adjusted_z,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_temp,
x_o => mag_temp,
y_o => y_temp,
z_o => phase_temp,
valid_o => valid_o);
mag_o <= std_logic_vector(mag_temp);
phase_o <= std_logic_vector(phase_temp);
end architecture str;
-------------------------------------------------------------------------------
|
entity FIFO is
end entity fifo;
entity FIFO is
end entity FIFO;
entity FIFO is
end entity Fifo;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 09 02:07:22 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl
-- Design : system_xlconstant_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_0 : entity is "yes";
end system_xlconstant_0_0;
architecture STRUCTURE of system_xlconstant_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
dout(0) <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- Title : SPI Slave Package Definition
-- Project :
-------------------------------------------------------------------------------
-- File : spislave_pkg.vhd
-- Author : [email protected]
-- Company :
-- Created : 2011-08-27
-- Platform :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
package spislave_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component spi_slave
port (
miso_p : out std_logic;
mosi_p : in std_logic;
sck_p : in std_logic;
csn_p : in std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic);
end component;
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
end spislave_pkg;
-------------------------------------------------------------------------------
package body spislave_pkg is
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31 downto 16) := std_logic_vector(to_unsigned(addr, 16));
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31) := '1'; -- MSB = '1' <=> write
d(30 downto 16) := addr(14 downto 0);
d(15 downto 0) := data;
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
end package body spislave_pkg;
|
-------------------------------------------------------------------------------
-- Title : SPI Slave Package Definition
-- Project :
-------------------------------------------------------------------------------
-- File : spislave_pkg.vhd
-- Author : [email protected]
-- Company :
-- Created : 2011-08-27
-- Platform :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
package spislave_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component spi_slave
port (
miso_p : out std_logic;
mosi_p : in std_logic;
sck_p : in std_logic;
csn_p : in std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic);
end component;
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
end spislave_pkg;
-------------------------------------------------------------------------------
package body spislave_pkg is
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31 downto 16) := std_logic_vector(to_unsigned(addr, 16));
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31) := '1'; -- MSB = '1' <=> write
d(30 downto 16) := addr(14 downto 0);
d(15 downto 0) := data;
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
end package body spislave_pkg;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02300_bad.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of clock name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02300_bad is
port (
i_Clk : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02300_bad;
architecture Behavioral of CNE_02300_bad is
signal Clock_tmp : std_logic;
begin
Clock_tmp <= i_Clk;
DFF1:DFlipFlop
port map (
i_Clock => Clock_tmp,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Apr 4 05:28:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../hier.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1 2006/04/11 13:36:52 wig Exp $
-- $Date: 2006/04/11 13:36:52 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.1 2006/04/11 13:36:52 wig
-- Updated testcases: left constant/* and verilog/uamn open.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
port_a : out std_logic; -- auto_a from a to b
port_b : in std_ulogic_vector(7 downto 0); -- auto_b from c to a and b
port_c : in std_ulogic_vector(15 downto 0); -- auto_c is I
port_d : out std_ulogic_vector(31 downto 0); -- auto_d is O bus
port_e : out std_ulogic_vector(23 downto 0) -- auto_e is O bus with internal in to other module
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:11 10/03/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_ALU_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_ALU_TB IS
END TestCPU1_ALU_TB;
ARCHITECTURE behavior OF TestCPU1_ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_ALU
PORT(
operation : IN std_logic;
to_bus_e : IN std_logic;
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
result : OUT std_logic_vector(15 downto 0);
z_flag : OUT std_logic
);
END COMPONENT;
--Inputs
signal operation : std_logic := '0';
signal to_bus_e : std_logic := '0';
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal result : std_logic_vector(15 downto 0);
signal z_flag : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_ALU PORT MAP (
operation => operation,
to_bus_e => to_bus_e,
A => A,
B => B,
result => result,
z_flag => z_flag
);
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
A <= x"0003";
B <= x"0001";
operation <= '1';
to_bus_e <= '1';
wait for 10 ns;
operation <= '0';
wait for 10 ns;
B <= x"0003";
operation <= '1';
wait for 10 ns;
to_bus_e <= '0';
wait;
end process;
END;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:22 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_pointer_basic_0_1 -prefix
-- design_1_pointer_basic_0_1_ design_1_pointer_basic_0_1_sim_netlist.vhdl
-- Design : design_1_pointer_basic_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\d_read_reg_52_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt : out STD_LOGIC;
\ap_CS_fsm_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
ap_rst_n : in STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC
);
end design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi;
architecture STRUCTURE of design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi is
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ap_idle : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal \^d_read_reg_52_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal int_ap_done : STD_LOGIC;
signal int_ap_done_i_1_n_0 : STD_LOGIC;
signal int_ap_done_i_2_n_0 : STD_LOGIC;
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_start_i_1_n_0 : STD_LOGIC;
signal int_ap_start_i_2_n_0 : STD_LOGIC;
signal int_ap_start_i_3_n_0 : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_auto_restart_i_1_n_0 : STD_LOGIC;
signal \int_d_i[0]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[10]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[11]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[12]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[13]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[14]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[15]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[16]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[17]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[18]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[19]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[1]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[20]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[21]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[22]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[23]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[24]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[25]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[26]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[27]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[28]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[29]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[2]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[30]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_2_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_3_n_0\ : STD_LOGIC;
signal \int_d_i[3]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[4]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[5]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[6]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[7]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[8]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[9]_i_1_n_0\ : STD_LOGIC;
signal int_d_o : STD_LOGIC_VECTOR ( 31 downto 0 );
signal int_d_o_ap_vld : STD_LOGIC;
signal int_d_o_ap_vld_i_1_n_0 : STD_LOGIC;
signal int_gie_i_1_n_0 : STD_LOGIC;
signal int_gie_reg_n_0 : STD_LOGIC;
signal \int_ier[0]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_2_n_0\ : STD_LOGIC;
signal \int_ier_reg_n_0_[0]\ : STD_LOGIC;
signal \int_ier_reg_n_0_[1]\ : STD_LOGIC;
signal int_isr : STD_LOGIC;
signal int_isr7_out : STD_LOGIC;
signal \int_isr[0]_i_1_n_0\ : STD_LOGIC;
signal \int_isr[1]_i_1_n_0\ : STD_LOGIC;
signal \int_isr_reg_n_0_[0]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_1_in : STD_LOGIC;
signal rdata : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[0]_i_3_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[16]_i_1_n_0\ : STD_LOGIC;
signal \rdata[17]_i_1_n_0\ : STD_LOGIC;
signal \rdata[18]_i_1_n_0\ : STD_LOGIC;
signal \rdata[19]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_2_n_0\ : STD_LOGIC;
signal \rdata[1]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_4_n_0\ : STD_LOGIC;
signal \rdata[20]_i_1_n_0\ : STD_LOGIC;
signal \rdata[21]_i_1_n_0\ : STD_LOGIC;
signal \rdata[22]_i_1_n_0\ : STD_LOGIC;
signal \rdata[23]_i_1_n_0\ : STD_LOGIC;
signal \rdata[24]_i_1_n_0\ : STD_LOGIC;
signal \rdata[25]_i_1_n_0\ : STD_LOGIC;
signal \rdata[26]_i_1_n_0\ : STD_LOGIC;
signal \rdata[27]_i_1_n_0\ : STD_LOGIC;
signal \rdata[28]_i_1_n_0\ : STD_LOGIC;
signal \rdata[29]_i_1_n_0\ : STD_LOGIC;
signal \rdata[30]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_3_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_2_n_0\ : STD_LOGIC;
signal \rdata[7]_i_3_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_pointer_basic_io_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_pointer_basic_io_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \d_read_reg_52[31]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair33";
attribute SOFT_HLUTNM of int_ap_start_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_d_i[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \int_d_i[10]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_d_i[11]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_d_i[12]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[13]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[14]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[15]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[16]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[17]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[18]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[19]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[20]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_d_i[21]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_d_i[22]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[23]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[24]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[25]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[26]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[27]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[28]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[29]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[30]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[31]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \int_d_i[4]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_d_i[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_d_i[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[8]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_d_i[9]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_ier[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_isr[1]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdata[10]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[11]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[12]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[13]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \rdata[15]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[16]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[17]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \rdata[18]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[19]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[1]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[20]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[21]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[22]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[23]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[24]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[25]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[26]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[27]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[28]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[29]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[30]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[31]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[5]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \rdata[6]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \rdata[7]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdata[8]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \rdata[9]_i_1\ : label is "soft_lutpair31";
begin
SR(0) <= \^sr\(0);
\d_read_reg_52_reg[31]\(31 downto 0) <= \^d_read_reg_52_reg[31]\(31 downto 0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_pointer_basic_io_RVALID(1 downto 0) <= \^s_axi_pointer_basic_io_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BFB"
)
port map (
I0 => s_axi_pointer_basic_io_RREADY,
I1 => \^s_axi_pointer_basic_io_rvalid\(1),
I2 => \^s_axi_pointer_basic_io_rvalid\(0),
I3 => s_axi_pointer_basic_io_ARVALID,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_ARVALID,
I1 => \^s_axi_pointer_basic_io_rvalid\(0),
I2 => s_axi_pointer_basic_io_RREADY,
I3 => \^s_axi_pointer_basic_io_rvalid\(1),
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF272227"
)
port map (
I0 => \^out\(0),
I1 => s_axi_pointer_basic_io_AWVALID,
I2 => \^out\(1),
I3 => \^out\(2),
I4 => s_axi_pointer_basic_io_BREADY,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_AWVALID,
I1 => \^out\(0),
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_WVALID,
I1 => \^out\(1),
I2 => s_axi_pointer_basic_io_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_2_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_2_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => ap_start,
I3 => Q(2),
O => \ap_CS_fsm_reg[1]\(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => Q(0),
I1 => ap_start,
I2 => Q(2),
I3 => Q(1),
O => \ap_CS_fsm_reg[1]\(1)
);
\d_read_reg_52[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ap_start,
I1 => Q(0),
O => E(0)
);
int_ap_done_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFAAAAAAAA"
)
port map (
I0 => Q(2),
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => s_axi_pointer_basic_io_ARADDR(2),
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_done_i_2_n_0,
I5 => int_ap_done,
O => int_ap_done_i_1_n_0
);
int_ap_done_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_pointer_basic_io_ARVALID,
I1 => \^s_axi_pointer_basic_io_rvalid\(0),
I2 => s_axi_pointer_basic_io_ARADDR(0),
I3 => s_axi_pointer_basic_io_ARADDR(1),
O => int_ap_done_i_2_n_0
);
int_ap_done_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_done_i_1_n_0,
Q => int_ap_done,
R => \^sr\(0)
);
int_ap_idle_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => ap_idle
);
int_ap_idle_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_idle,
Q => int_ap_idle,
R => \^sr\(0)
);
int_ap_ready_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => Q(2),
Q => int_ap_ready,
R => \^sr\(0)
);
int_ap_start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBBBBBF8888888"
)
port map (
I0 => int_auto_restart,
I1 => Q(2),
I2 => int_ap_start_i_2_n_0,
I3 => int_ap_start_i_3_n_0,
I4 => s_axi_pointer_basic_io_WDATA(0),
I5 => ap_start,
O => int_ap_start_i_1_n_0
);
int_ap_start_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_pointer_basic_io_WSTRB(0),
I1 => \waddr_reg_n_0_[2]\,
O => int_ap_start_i_2_n_0
);
int_ap_start_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[1]\,
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \^out\(1),
I4 => \waddr_reg_n_0_[3]\,
I5 => \waddr_reg_n_0_[4]\,
O => int_ap_start_i_3_n_0
);
int_ap_start_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_start_i_1_n_0,
Q => ap_start,
R => \^sr\(0)
);
int_auto_restart_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(7),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => int_ap_start_i_3_n_0,
I4 => int_auto_restart,
O => int_auto_restart_i_1_n_0
);
int_auto_restart_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_auto_restart_i_1_n_0,
Q => int_auto_restart,
R => \^sr\(0)
);
\int_d_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(0),
O => \int_d_i[0]_i_1_n_0\
);
\int_d_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(10),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(10),
O => \int_d_i[10]_i_1_n_0\
);
\int_d_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(11),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(11),
O => \int_d_i[11]_i_1_n_0\
);
\int_d_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(12),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(12),
O => \int_d_i[12]_i_1_n_0\
);
\int_d_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(13),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(13),
O => \int_d_i[13]_i_1_n_0\
);
\int_d_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(14),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(14),
O => \int_d_i[14]_i_1_n_0\
);
\int_d_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(15),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(15),
O => \int_d_i[15]_i_1_n_0\
);
\int_d_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(16),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(16),
O => \int_d_i[16]_i_1_n_0\
);
\int_d_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(17),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(17),
O => \int_d_i[17]_i_1_n_0\
);
\int_d_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(18),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(18),
O => \int_d_i[18]_i_1_n_0\
);
\int_d_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(19),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(19),
O => \int_d_i[19]_i_1_n_0\
);
\int_d_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(1),
O => \int_d_i[1]_i_1_n_0\
);
\int_d_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(20),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(20),
O => \int_d_i[20]_i_1_n_0\
);
\int_d_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(21),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(21),
O => \int_d_i[21]_i_1_n_0\
);
\int_d_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(22),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(22),
O => \int_d_i[22]_i_1_n_0\
);
\int_d_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(23),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(23),
O => \int_d_i[23]_i_1_n_0\
);
\int_d_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(24),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(24),
O => \int_d_i[24]_i_1_n_0\
);
\int_d_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(25),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(25),
O => \int_d_i[25]_i_1_n_0\
);
\int_d_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(26),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(26),
O => \int_d_i[26]_i_1_n_0\
);
\int_d_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(27),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(27),
O => \int_d_i[27]_i_1_n_0\
);
\int_d_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(28),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(28),
O => \int_d_i[28]_i_1_n_0\
);
\int_d_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(29),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(29),
O => \int_d_i[29]_i_1_n_0\
);
\int_d_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(2),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(2),
O => \int_d_i[2]_i_1_n_0\
);
\int_d_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(30),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(30),
O => \int_d_i[30]_i_1_n_0\
);
\int_d_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \int_d_i[31]_i_3_n_0\,
I1 => \waddr_reg_n_0_[4]\,
I2 => \waddr_reg_n_0_[2]\,
O => \int_d_i[31]_i_1_n_0\
);
\int_d_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(31),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(31),
O => \int_d_i[31]_i_2_n_0\
);
\int_d_i[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => \waddr_reg_n_0_[3]\,
I1 => \^out\(1),
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \waddr_reg_n_0_[1]\,
I4 => \waddr_reg_n_0_[0]\,
O => \int_d_i[31]_i_3_n_0\
);
\int_d_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(3),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(3),
O => \int_d_i[3]_i_1_n_0\
);
\int_d_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(4),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(4),
O => \int_d_i[4]_i_1_n_0\
);
\int_d_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(5),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(5),
O => \int_d_i[5]_i_1_n_0\
);
\int_d_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(6),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(6),
O => \int_d_i[6]_i_1_n_0\
);
\int_d_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(7),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(7),
O => \int_d_i[7]_i_1_n_0\
);
\int_d_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(8),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(8),
O => \int_d_i[8]_i_1_n_0\
);
\int_d_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(9),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(9),
O => \int_d_i[9]_i_1_n_0\
);
\int_d_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[0]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(0),
R => \^sr\(0)
);
\int_d_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[10]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(10),
R => \^sr\(0)
);
\int_d_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[11]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(11),
R => \^sr\(0)
);
\int_d_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[12]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(12),
R => \^sr\(0)
);
\int_d_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[13]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(13),
R => \^sr\(0)
);
\int_d_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[14]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(14),
R => \^sr\(0)
);
\int_d_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[15]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(15),
R => \^sr\(0)
);
\int_d_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[16]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(16),
R => \^sr\(0)
);
\int_d_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[17]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(17),
R => \^sr\(0)
);
\int_d_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[18]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(18),
R => \^sr\(0)
);
\int_d_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[19]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(19),
R => \^sr\(0)
);
\int_d_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[1]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(1),
R => \^sr\(0)
);
\int_d_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[20]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(20),
R => \^sr\(0)
);
\int_d_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[21]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(21),
R => \^sr\(0)
);
\int_d_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[22]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(22),
R => \^sr\(0)
);
\int_d_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[23]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(23),
R => \^sr\(0)
);
\int_d_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[24]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(24),
R => \^sr\(0)
);
\int_d_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[25]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(25),
R => \^sr\(0)
);
\int_d_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[26]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(26),
R => \^sr\(0)
);
\int_d_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[27]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(27),
R => \^sr\(0)
);
\int_d_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[28]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(28),
R => \^sr\(0)
);
\int_d_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[29]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(29),
R => \^sr\(0)
);
\int_d_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[2]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(2),
R => \^sr\(0)
);
\int_d_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[30]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(30),
R => \^sr\(0)
);
\int_d_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[31]_i_2_n_0\,
Q => \^d_read_reg_52_reg[31]\(31),
R => \^sr\(0)
);
\int_d_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[3]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(3),
R => \^sr\(0)
);
\int_d_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[4]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(4),
R => \^sr\(0)
);
\int_d_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[5]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(5),
R => \^sr\(0)
);
\int_d_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[6]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(6),
R => \^sr\(0)
);
\int_d_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[7]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(7),
R => \^sr\(0)
);
\int_d_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[8]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(8),
R => \^sr\(0)
);
\int_d_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[9]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(9),
R => \^sr\(0)
);
int_d_o_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFAAAAAAAA"
)
port map (
I0 => Q(2),
I1 => s_axi_pointer_basic_io_ARADDR(2),
I2 => s_axi_pointer_basic_io_ARADDR(4),
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_done_i_2_n_0,
I5 => int_d_o_ap_vld,
O => int_d_o_ap_vld_i_1_n_0
);
int_d_o_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_d_o_ap_vld_i_1_n_0,
Q => int_d_o_ap_vld,
R => \^sr\(0)
);
\int_d_o_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(0),
Q => int_d_o(0),
R => \^sr\(0)
);
\int_d_o_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(10),
Q => int_d_o(10),
R => \^sr\(0)
);
\int_d_o_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(11),
Q => int_d_o(11),
R => \^sr\(0)
);
\int_d_o_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(12),
Q => int_d_o(12),
R => \^sr\(0)
);
\int_d_o_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(13),
Q => int_d_o(13),
R => \^sr\(0)
);
\int_d_o_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(14),
Q => int_d_o(14),
R => \^sr\(0)
);
\int_d_o_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(15),
Q => int_d_o(15),
R => \^sr\(0)
);
\int_d_o_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(16),
Q => int_d_o(16),
R => \^sr\(0)
);
\int_d_o_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(17),
Q => int_d_o(17),
R => \^sr\(0)
);
\int_d_o_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(18),
Q => int_d_o(18),
R => \^sr\(0)
);
\int_d_o_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(19),
Q => int_d_o(19),
R => \^sr\(0)
);
\int_d_o_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(1),
Q => int_d_o(1),
R => \^sr\(0)
);
\int_d_o_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(20),
Q => int_d_o(20),
R => \^sr\(0)
);
\int_d_o_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(21),
Q => int_d_o(21),
R => \^sr\(0)
);
\int_d_o_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(22),
Q => int_d_o(22),
R => \^sr\(0)
);
\int_d_o_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(23),
Q => int_d_o(23),
R => \^sr\(0)
);
\int_d_o_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(24),
Q => int_d_o(24),
R => \^sr\(0)
);
\int_d_o_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(25),
Q => int_d_o(25),
R => \^sr\(0)
);
\int_d_o_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(26),
Q => int_d_o(26),
R => \^sr\(0)
);
\int_d_o_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(27),
Q => int_d_o(27),
R => \^sr\(0)
);
\int_d_o_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(28),
Q => int_d_o(28),
R => \^sr\(0)
);
\int_d_o_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(29),
Q => int_d_o(29),
R => \^sr\(0)
);
\int_d_o_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(2),
Q => int_d_o(2),
R => \^sr\(0)
);
\int_d_o_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(30),
Q => int_d_o(30),
R => \^sr\(0)
);
\int_d_o_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(31),
Q => int_d_o(31),
R => \^sr\(0)
);
\int_d_o_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(3),
Q => int_d_o(3),
R => \^sr\(0)
);
\int_d_o_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(4),
Q => int_d_o(4),
R => \^sr\(0)
);
\int_d_o_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(5),
Q => int_d_o(5),
R => \^sr\(0)
);
\int_d_o_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(6),
Q => int_d_o(6),
R => \^sr\(0)
);
\int_d_o_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(7),
Q => int_d_o(7),
R => \^sr\(0)
);
\int_d_o_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(8),
Q => int_d_o(8),
R => \^sr\(0)
);
\int_d_o_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(9),
Q => int_d_o(9),
R => \^sr\(0)
);
int_gie_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF8000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => int_ap_start_i_3_n_0,
I2 => \waddr_reg_n_0_[2]\,
I3 => s_axi_pointer_basic_io_WSTRB(0),
I4 => int_gie_reg_n_0,
O => int_gie_i_1_n_0
);
int_gie_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_gie_i_1_n_0,
Q => int_gie_reg_n_0,
R => \^sr\(0)
);
\int_ier[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \int_ier[1]_i_2_n_0\,
I4 => \int_ier_reg_n_0_[0]\,
O => \int_ier[0]_i_1_n_0\
);
\int_ier[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \int_ier[1]_i_2_n_0\,
I4 => \int_ier_reg_n_0_[1]\,
O => \int_ier[1]_i_1_n_0\
);
\int_ier[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF7FFFF"
)
port map (
I0 => \^out\(1),
I1 => s_axi_pointer_basic_io_WVALID,
I2 => \waddr_reg_n_0_[1]\,
I3 => \waddr_reg_n_0_[0]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \waddr_reg_n_0_[4]\,
O => \int_ier[1]_i_2_n_0\
);
\int_ier_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[0]_i_1_n_0\,
Q => \int_ier_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_ier_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[1]_i_1_n_0\,
Q => \int_ier_reg_n_0_[1]\,
R => \^sr\(0)
);
\int_isr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFFFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => \int_ier[1]_i_2_n_0\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \waddr_reg_n_0_[2]\,
I4 => int_isr7_out,
I5 => \int_isr_reg_n_0_[0]\,
O => \int_isr[0]_i_1_n_0\
);
\int_isr[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(2),
I1 => \int_ier_reg_n_0_[0]\,
O => int_isr7_out
);
\int_isr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFFFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => \int_ier[1]_i_2_n_0\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \waddr_reg_n_0_[2]\,
I4 => int_isr,
I5 => p_1_in,
O => \int_isr[1]_i_1_n_0\
);
\int_isr[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(2),
I1 => \int_ier_reg_n_0_[1]\,
O => int_isr
);
\int_isr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[0]_i_1_n_0\,
Q => \int_isr_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_isr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[1]_i_1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
interrupt_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => int_gie_reg_n_0,
I1 => p_1_in,
I2 => \int_isr_reg_n_0_[0]\,
O => interrupt
);
\rdata[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000B8"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => \rdata[0]_i_3_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(0),
I4 => s_axi_pointer_basic_io_ARADDR(1),
O => rdata(0)
);
\rdata[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0A0CFC0"
)
port map (
I0 => int_d_o_ap_vld,
I1 => int_d_o(0),
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => \^d_read_reg_52_reg[31]\(0),
I4 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[0]_i_2_n_0\
);
\rdata[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \int_isr_reg_n_0_[0]\,
I1 => \int_ier_reg_n_0_[0]\,
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => int_gie_reg_n_0,
I4 => s_axi_pointer_basic_io_ARADDR(2),
I5 => ap_start,
O => \rdata[0]_i_3_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(10),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(11),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(12),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(13),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(14),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(15),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(15),
O => \rdata[15]_i_1_n_0\
);
\rdata[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(16),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(16),
O => \rdata[16]_i_1_n_0\
);
\rdata[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(17),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(17),
O => \rdata[17]_i_1_n_0\
);
\rdata[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(18),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(18),
O => \rdata[18]_i_1_n_0\
);
\rdata[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(19),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(19),
O => \rdata[19]_i_1_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0E0E0EE"
)
port map (
I0 => \rdata[1]_i_2_n_0\,
I1 => \rdata[1]_i_3_n_0\,
I2 => \rdata[1]_i_4_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(4),
I4 => s_axi_pointer_basic_io_ARADDR(0),
I5 => s_axi_pointer_basic_io_ARADDR(1),
O => rdata(1)
);
\rdata[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F2F2F2F2F2F2FFF2"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(4),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(1),
I3 => int_ap_done,
I4 => s_axi_pointer_basic_io_ARADDR(3),
I5 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[1]_i_2_n_0\
);
\rdata[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(3),
I1 => \int_ier_reg_n_0_[1]\,
I2 => s_axi_pointer_basic_io_ARADDR(2),
I3 => p_1_in,
O => \rdata[1]_i_3_n_0\
);
\rdata[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000E2"
)
port map (
I0 => \^d_read_reg_52_reg[31]\(1),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => int_d_o(1),
I3 => s_axi_pointer_basic_io_ARADDR(1),
I4 => s_axi_pointer_basic_io_ARADDR(0),
I5 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[1]_i_4_n_0\
);
\rdata[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(20),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(20),
O => \rdata[20]_i_1_n_0\
);
\rdata[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(21),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(21),
O => \rdata[21]_i_1_n_0\
);
\rdata[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(22),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(22),
O => \rdata[22]_i_1_n_0\
);
\rdata[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(23),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(23),
O => \rdata[23]_i_1_n_0\
);
\rdata[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(24),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(24),
O => \rdata[24]_i_1_n_0\
);
\rdata[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(25),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(25),
O => \rdata[25]_i_1_n_0\
);
\rdata[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(26),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(26),
O => \rdata[26]_i_1_n_0\
);
\rdata[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(27),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(27),
O => \rdata[27]_i_1_n_0\
);
\rdata[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(28),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(28),
O => \rdata[28]_i_1_n_0\
);
\rdata[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(29),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(29),
O => \rdata[29]_i_1_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(2),
I1 => \^d_read_reg_52_reg[31]\(2),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_idle,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(2)
);
\rdata[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(30),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(30),
O => \rdata[30]_i_1_n_0\
);
\rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFD000000000000"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(4),
I1 => s_axi_pointer_basic_io_ARADDR(2),
I2 => s_axi_pointer_basic_io_ARADDR(0),
I3 => s_axi_pointer_basic_io_ARADDR(1),
I4 => s_axi_pointer_basic_io_ARVALID,
I5 => \^s_axi_pointer_basic_io_rvalid\(0),
O => \rdata[31]_i_1_n_0\
);
\rdata[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_pointer_basic_io_rvalid\(0),
I1 => s_axi_pointer_basic_io_ARVALID,
O => ar_hs
);
\rdata[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(31),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(31),
O => \rdata[31]_i_3_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(3),
I1 => \^d_read_reg_52_reg[31]\(3),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_ready,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(3)
);
\rdata[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(4),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(5),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(6),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(7),
I1 => \^d_read_reg_52_reg[31]\(7),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_auto_restart,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(7)
);
\rdata[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(1),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(4),
O => \rdata[7]_i_2_n_0\
);
\rdata[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(2),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(1),
O => \rdata[7]_i_3_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(8),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(9),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(0),
Q => s_axi_pointer_basic_io_RDATA(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(10),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(11),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(12),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(13),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(14),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(15),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[16]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(16),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[17]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(17),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[18]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(18),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[19]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(19),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(1),
Q => s_axi_pointer_basic_io_RDATA(1),
R => '0'
);
\rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[20]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(20),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[21]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(21),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[22]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(22),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[23]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(23),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[24]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(24),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[25]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(25),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[26]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(26),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[27]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(27),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[28]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(28),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[29]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(29),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(2),
Q => s_axi_pointer_basic_io_RDATA(2),
R => '0'
);
\rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[30]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(30),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[31]_i_3_n_0\,
Q => s_axi_pointer_basic_io_RDATA(31),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(3),
Q => s_axi_pointer_basic_io_RDATA(3),
R => '0'
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(4),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(5),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(6),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(7),
Q => s_axi_pointer_basic_io_RDATA(7),
R => '0'
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(8),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(9),
R => \rdata[31]_i_1_n_0\
);
\waddr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^out\(0),
I1 => s_axi_pointer_basic_io_AWVALID,
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1_pointer_basic is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt : out STD_LOGIC
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b100";
attribute hls_module : string;
attribute hls_module of design_1_pointer_basic_0_1_pointer_basic : entity is "yes";
end design_1_pointer_basic_0_1_pointer_basic;
architecture STRUCTURE of design_1_pointer_basic_0_1_pointer_basic is
signal \<const0>\ : STD_LOGIC;
signal \acc[0]_i_2_n_0\ : STD_LOGIC;
signal \acc[0]_i_3_n_0\ : STD_LOGIC;
signal \acc[0]_i_4_n_0\ : STD_LOGIC;
signal \acc[0]_i_5_n_0\ : STD_LOGIC;
signal \acc[12]_i_2_n_0\ : STD_LOGIC;
signal \acc[12]_i_3_n_0\ : STD_LOGIC;
signal \acc[12]_i_4_n_0\ : STD_LOGIC;
signal \acc[12]_i_5_n_0\ : STD_LOGIC;
signal \acc[16]_i_2_n_0\ : STD_LOGIC;
signal \acc[16]_i_3_n_0\ : STD_LOGIC;
signal \acc[16]_i_4_n_0\ : STD_LOGIC;
signal \acc[16]_i_5_n_0\ : STD_LOGIC;
signal \acc[20]_i_2_n_0\ : STD_LOGIC;
signal \acc[20]_i_3_n_0\ : STD_LOGIC;
signal \acc[20]_i_4_n_0\ : STD_LOGIC;
signal \acc[20]_i_5_n_0\ : STD_LOGIC;
signal \acc[24]_i_2_n_0\ : STD_LOGIC;
signal \acc[24]_i_3_n_0\ : STD_LOGIC;
signal \acc[24]_i_4_n_0\ : STD_LOGIC;
signal \acc[24]_i_5_n_0\ : STD_LOGIC;
signal \acc[28]_i_2_n_0\ : STD_LOGIC;
signal \acc[28]_i_3_n_0\ : STD_LOGIC;
signal \acc[28]_i_4_n_0\ : STD_LOGIC;
signal \acc[28]_i_5_n_0\ : STD_LOGIC;
signal \acc[4]_i_2_n_0\ : STD_LOGIC;
signal \acc[4]_i_3_n_0\ : STD_LOGIC;
signal \acc[4]_i_4_n_0\ : STD_LOGIC;
signal \acc[4]_i_5_n_0\ : STD_LOGIC;
signal \acc[8]_i_2_n_0\ : STD_LOGIC;
signal \acc[8]_i_3_n_0\ : STD_LOGIC;
signal \acc[8]_i_4_n_0\ : STD_LOGIC;
signal \acc[8]_i_5_n_0\ : STD_LOGIC;
signal acc_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \acc_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal d_i : STD_LOGIC_VECTOR ( 31 downto 0 );
signal d_read_reg_52 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
begin
s_axi_pointer_basic_io_BRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_BRESP(0) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\acc[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(3),
I1 => acc_reg(3),
O => \acc[0]_i_2_n_0\
);
\acc[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(2),
I1 => acc_reg(2),
O => \acc[0]_i_3_n_0\
);
\acc[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(1),
I1 => acc_reg(1),
O => \acc[0]_i_4_n_0\
);
\acc[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(0),
I1 => acc_reg(0),
O => \acc[0]_i_5_n_0\
);
\acc[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(15),
I1 => acc_reg(15),
O => \acc[12]_i_2_n_0\
);
\acc[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(14),
I1 => acc_reg(14),
O => \acc[12]_i_3_n_0\
);
\acc[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(13),
I1 => acc_reg(13),
O => \acc[12]_i_4_n_0\
);
\acc[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(12),
I1 => acc_reg(12),
O => \acc[12]_i_5_n_0\
);
\acc[16]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(19),
I1 => acc_reg(19),
O => \acc[16]_i_2_n_0\
);
\acc[16]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(18),
I1 => acc_reg(18),
O => \acc[16]_i_3_n_0\
);
\acc[16]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(17),
I1 => acc_reg(17),
O => \acc[16]_i_4_n_0\
);
\acc[16]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(16),
I1 => acc_reg(16),
O => \acc[16]_i_5_n_0\
);
\acc[20]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(23),
I1 => acc_reg(23),
O => \acc[20]_i_2_n_0\
);
\acc[20]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(22),
I1 => acc_reg(22),
O => \acc[20]_i_3_n_0\
);
\acc[20]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(21),
I1 => acc_reg(21),
O => \acc[20]_i_4_n_0\
);
\acc[20]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(20),
I1 => acc_reg(20),
O => \acc[20]_i_5_n_0\
);
\acc[24]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(27),
I1 => acc_reg(27),
O => \acc[24]_i_2_n_0\
);
\acc[24]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(26),
I1 => acc_reg(26),
O => \acc[24]_i_3_n_0\
);
\acc[24]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(25),
I1 => acc_reg(25),
O => \acc[24]_i_4_n_0\
);
\acc[24]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(24),
I1 => acc_reg(24),
O => \acc[24]_i_5_n_0\
);
\acc[28]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => acc_reg(31),
I1 => d_read_reg_52(31),
O => \acc[28]_i_2_n_0\
);
\acc[28]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(30),
I1 => acc_reg(30),
O => \acc[28]_i_3_n_0\
);
\acc[28]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(29),
I1 => acc_reg(29),
O => \acc[28]_i_4_n_0\
);
\acc[28]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(28),
I1 => acc_reg(28),
O => \acc[28]_i_5_n_0\
);
\acc[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(7),
I1 => acc_reg(7),
O => \acc[4]_i_2_n_0\
);
\acc[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(6),
I1 => acc_reg(6),
O => \acc[4]_i_3_n_0\
);
\acc[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(5),
I1 => acc_reg(5),
O => \acc[4]_i_4_n_0\
);
\acc[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(4),
I1 => acc_reg(4),
O => \acc[4]_i_5_n_0\
);
\acc[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(11),
I1 => acc_reg(11),
O => \acc[8]_i_2_n_0\
);
\acc[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(10),
I1 => acc_reg(10),
O => \acc[8]_i_3_n_0\
);
\acc[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(9),
I1 => acc_reg(9),
O => \acc[8]_i_4_n_0\
);
\acc[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(8),
I1 => acc_reg(8),
O => \acc[8]_i_5_n_0\
);
\acc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_7\,
Q => acc_reg(0),
R => '0'
);
\acc_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \acc_reg[0]_i_1_n_0\,
CO(2) => \acc_reg[0]_i_1_n_1\,
CO(1) => \acc_reg[0]_i_1_n_2\,
CO(0) => \acc_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(3 downto 0),
O(3) => \acc_reg[0]_i_1_n_4\,
O(2) => \acc_reg[0]_i_1_n_5\,
O(1) => \acc_reg[0]_i_1_n_6\,
O(0) => \acc_reg[0]_i_1_n_7\,
S(3) => \acc[0]_i_2_n_0\,
S(2) => \acc[0]_i_3_n_0\,
S(1) => \acc[0]_i_4_n_0\,
S(0) => \acc[0]_i_5_n_0\
);
\acc_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_5\,
Q => acc_reg(10),
R => '0'
);
\acc_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_4\,
Q => acc_reg(11),
R => '0'
);
\acc_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_7\,
Q => acc_reg(12),
R => '0'
);
\acc_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[8]_i_1_n_0\,
CO(3) => \acc_reg[12]_i_1_n_0\,
CO(2) => \acc_reg[12]_i_1_n_1\,
CO(1) => \acc_reg[12]_i_1_n_2\,
CO(0) => \acc_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(15 downto 12),
O(3) => \acc_reg[12]_i_1_n_4\,
O(2) => \acc_reg[12]_i_1_n_5\,
O(1) => \acc_reg[12]_i_1_n_6\,
O(0) => \acc_reg[12]_i_1_n_7\,
S(3) => \acc[12]_i_2_n_0\,
S(2) => \acc[12]_i_3_n_0\,
S(1) => \acc[12]_i_4_n_0\,
S(0) => \acc[12]_i_5_n_0\
);
\acc_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_6\,
Q => acc_reg(13),
R => '0'
);
\acc_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_5\,
Q => acc_reg(14),
R => '0'
);
\acc_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_4\,
Q => acc_reg(15),
R => '0'
);
\acc_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_7\,
Q => acc_reg(16),
R => '0'
);
\acc_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[12]_i_1_n_0\,
CO(3) => \acc_reg[16]_i_1_n_0\,
CO(2) => \acc_reg[16]_i_1_n_1\,
CO(1) => \acc_reg[16]_i_1_n_2\,
CO(0) => \acc_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(19 downto 16),
O(3) => \acc_reg[16]_i_1_n_4\,
O(2) => \acc_reg[16]_i_1_n_5\,
O(1) => \acc_reg[16]_i_1_n_6\,
O(0) => \acc_reg[16]_i_1_n_7\,
S(3) => \acc[16]_i_2_n_0\,
S(2) => \acc[16]_i_3_n_0\,
S(1) => \acc[16]_i_4_n_0\,
S(0) => \acc[16]_i_5_n_0\
);
\acc_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_6\,
Q => acc_reg(17),
R => '0'
);
\acc_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_5\,
Q => acc_reg(18),
R => '0'
);
\acc_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_4\,
Q => acc_reg(19),
R => '0'
);
\acc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_6\,
Q => acc_reg(1),
R => '0'
);
\acc_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_7\,
Q => acc_reg(20),
R => '0'
);
\acc_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[16]_i_1_n_0\,
CO(3) => \acc_reg[20]_i_1_n_0\,
CO(2) => \acc_reg[20]_i_1_n_1\,
CO(1) => \acc_reg[20]_i_1_n_2\,
CO(0) => \acc_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(23 downto 20),
O(3) => \acc_reg[20]_i_1_n_4\,
O(2) => \acc_reg[20]_i_1_n_5\,
O(1) => \acc_reg[20]_i_1_n_6\,
O(0) => \acc_reg[20]_i_1_n_7\,
S(3) => \acc[20]_i_2_n_0\,
S(2) => \acc[20]_i_3_n_0\,
S(1) => \acc[20]_i_4_n_0\,
S(0) => \acc[20]_i_5_n_0\
);
\acc_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_6\,
Q => acc_reg(21),
R => '0'
);
\acc_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_5\,
Q => acc_reg(22),
R => '0'
);
\acc_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_4\,
Q => acc_reg(23),
R => '0'
);
\acc_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_7\,
Q => acc_reg(24),
R => '0'
);
\acc_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[20]_i_1_n_0\,
CO(3) => \acc_reg[24]_i_1_n_0\,
CO(2) => \acc_reg[24]_i_1_n_1\,
CO(1) => \acc_reg[24]_i_1_n_2\,
CO(0) => \acc_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(27 downto 24),
O(3) => \acc_reg[24]_i_1_n_4\,
O(2) => \acc_reg[24]_i_1_n_5\,
O(1) => \acc_reg[24]_i_1_n_6\,
O(0) => \acc_reg[24]_i_1_n_7\,
S(3) => \acc[24]_i_2_n_0\,
S(2) => \acc[24]_i_3_n_0\,
S(1) => \acc[24]_i_4_n_0\,
S(0) => \acc[24]_i_5_n_0\
);
\acc_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_6\,
Q => acc_reg(25),
R => '0'
);
\acc_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_5\,
Q => acc_reg(26),
R => '0'
);
\acc_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_4\,
Q => acc_reg(27),
R => '0'
);
\acc_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_7\,
Q => acc_reg(28),
R => '0'
);
\acc_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[24]_i_1_n_0\,
CO(3) => \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \acc_reg[28]_i_1_n_1\,
CO(1) => \acc_reg[28]_i_1_n_2\,
CO(0) => \acc_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => d_read_reg_52(30 downto 28),
O(3) => \acc_reg[28]_i_1_n_4\,
O(2) => \acc_reg[28]_i_1_n_5\,
O(1) => \acc_reg[28]_i_1_n_6\,
O(0) => \acc_reg[28]_i_1_n_7\,
S(3) => \acc[28]_i_2_n_0\,
S(2) => \acc[28]_i_3_n_0\,
S(1) => \acc[28]_i_4_n_0\,
S(0) => \acc[28]_i_5_n_0\
);
\acc_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_6\,
Q => acc_reg(29),
R => '0'
);
\acc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_5\,
Q => acc_reg(2),
R => '0'
);
\acc_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_5\,
Q => acc_reg(30),
R => '0'
);
\acc_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_4\,
Q => acc_reg(31),
R => '0'
);
\acc_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_4\,
Q => acc_reg(3),
R => '0'
);
\acc_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_7\,
Q => acc_reg(4),
R => '0'
);
\acc_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[0]_i_1_n_0\,
CO(3) => \acc_reg[4]_i_1_n_0\,
CO(2) => \acc_reg[4]_i_1_n_1\,
CO(1) => \acc_reg[4]_i_1_n_2\,
CO(0) => \acc_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(7 downto 4),
O(3) => \acc_reg[4]_i_1_n_4\,
O(2) => \acc_reg[4]_i_1_n_5\,
O(1) => \acc_reg[4]_i_1_n_6\,
O(0) => \acc_reg[4]_i_1_n_7\,
S(3) => \acc[4]_i_2_n_0\,
S(2) => \acc[4]_i_3_n_0\,
S(1) => \acc[4]_i_4_n_0\,
S(0) => \acc[4]_i_5_n_0\
);
\acc_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_6\,
Q => acc_reg(5),
R => '0'
);
\acc_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_5\,
Q => acc_reg(6),
R => '0'
);
\acc_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_4\,
Q => acc_reg(7),
R => '0'
);
\acc_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_7\,
Q => acc_reg(8),
R => '0'
);
\acc_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[4]_i_1_n_0\,
CO(3) => \acc_reg[8]_i_1_n_0\,
CO(2) => \acc_reg[8]_i_1_n_1\,
CO(1) => \acc_reg[8]_i_1_n_2\,
CO(0) => \acc_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(11 downto 8),
O(3) => \acc_reg[8]_i_1_n_4\,
O(2) => \acc_reg[8]_i_1_n_5\,
O(1) => \acc_reg[8]_i_1_n_6\,
O(0) => \acc_reg[8]_i_1_n_7\,
S(3) => \acc[8]_i_2_n_0\,
S(2) => \acc[8]_i_3_n_0\,
S(1) => \acc[8]_i_4_n_0\,
S(0) => \acc[8]_i_5_n_0\
);
\acc_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_6\,
Q => acc_reg(9),
R => '0'
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_CS_fsm_state2,
Q => ap_CS_fsm_state3,
R => ap_rst_n_inv
);
\d_read_reg_52_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(0),
Q => d_read_reg_52(0),
R => '0'
);
\d_read_reg_52_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(10),
Q => d_read_reg_52(10),
R => '0'
);
\d_read_reg_52_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(11),
Q => d_read_reg_52(11),
R => '0'
);
\d_read_reg_52_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(12),
Q => d_read_reg_52(12),
R => '0'
);
\d_read_reg_52_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(13),
Q => d_read_reg_52(13),
R => '0'
);
\d_read_reg_52_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(14),
Q => d_read_reg_52(14),
R => '0'
);
\d_read_reg_52_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(15),
Q => d_read_reg_52(15),
R => '0'
);
\d_read_reg_52_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(16),
Q => d_read_reg_52(16),
R => '0'
);
\d_read_reg_52_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(17),
Q => d_read_reg_52(17),
R => '0'
);
\d_read_reg_52_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(18),
Q => d_read_reg_52(18),
R => '0'
);
\d_read_reg_52_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(19),
Q => d_read_reg_52(19),
R => '0'
);
\d_read_reg_52_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(1),
Q => d_read_reg_52(1),
R => '0'
);
\d_read_reg_52_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(20),
Q => d_read_reg_52(20),
R => '0'
);
\d_read_reg_52_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(21),
Q => d_read_reg_52(21),
R => '0'
);
\d_read_reg_52_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(22),
Q => d_read_reg_52(22),
R => '0'
);
\d_read_reg_52_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(23),
Q => d_read_reg_52(23),
R => '0'
);
\d_read_reg_52_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(24),
Q => d_read_reg_52(24),
R => '0'
);
\d_read_reg_52_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(25),
Q => d_read_reg_52(25),
R => '0'
);
\d_read_reg_52_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(26),
Q => d_read_reg_52(26),
R => '0'
);
\d_read_reg_52_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(27),
Q => d_read_reg_52(27),
R => '0'
);
\d_read_reg_52_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(28),
Q => d_read_reg_52(28),
R => '0'
);
\d_read_reg_52_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(29),
Q => d_read_reg_52(29),
R => '0'
);
\d_read_reg_52_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(2),
Q => d_read_reg_52(2),
R => '0'
);
\d_read_reg_52_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(30),
Q => d_read_reg_52(30),
R => '0'
);
\d_read_reg_52_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(31),
Q => d_read_reg_52(31),
R => '0'
);
\d_read_reg_52_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(3),
Q => d_read_reg_52(3),
R => '0'
);
\d_read_reg_52_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(4),
Q => d_read_reg_52(4),
R => '0'
);
\d_read_reg_52_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(5),
Q => d_read_reg_52(5),
R => '0'
);
\d_read_reg_52_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(6),
Q => d_read_reg_52(6),
R => '0'
);
\d_read_reg_52_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(7),
Q => d_read_reg_52(7),
R => '0'
);
\d_read_reg_52_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(8),
Q => d_read_reg_52(8),
R => '0'
);
\d_read_reg_52_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(9),
Q => d_read_reg_52(9),
R => '0'
);
pointer_basic_pointer_basic_io_s_axi_U: entity work.design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi
port map (
D(31 downto 0) => acc_reg(31 downto 0),
E(0) => ap_NS_fsm1,
Q(2) => ap_CS_fsm_state3,
Q(1) => ap_CS_fsm_state2,
Q(0) => \ap_CS_fsm_reg_n_0_[0]\,
SR(0) => ap_rst_n_inv,
\ap_CS_fsm_reg[1]\(1 downto 0) => ap_NS_fsm(1 downto 0),
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\d_read_reg_52_reg[31]\(31 downto 0) => d_i(31 downto 0),
interrupt => interrupt,
\out\(2) => s_axi_pointer_basic_io_BVALID,
\out\(1) => s_axi_pointer_basic_io_WREADY,
\out\(0) => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RVALID(1) => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RVALID(0) => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1 is
port (
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_pointer_basic_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_pointer_basic_0_1 : entity is "design_1_pointer_basic_0_1,pointer_basic,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of design_1_pointer_basic_0_1 : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of design_1_pointer_basic_0_1 : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of design_1_pointer_basic_0_1 : entity is "pointer_basic,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of design_1_pointer_basic_0_1 : entity is "yes";
end design_1_pointer_basic_0_1;
architecture STRUCTURE of design_1_pointer_basic_0_1 is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of inst : label is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "3'b100";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_pointer_basic_io_RREADY : signal is "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB";
begin
inst: entity work.design_1_pointer_basic_0_1_pointer_basic
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARREADY => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWREADY => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP(1 downto 0) => s_axi_pointer_basic_io_BRESP(1 downto 0),
s_axi_pointer_basic_io_BVALID => s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RRESP(1 downto 0) => s_axi_pointer_basic_io_RRESP(1 downto 0),
s_axi_pointer_basic_io_RVALID => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WREADY => s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:22 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_pointer_basic_0_1 -prefix
-- design_1_pointer_basic_0_1_ design_1_pointer_basic_0_1_sim_netlist.vhdl
-- Design : design_1_pointer_basic_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\d_read_reg_52_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt : out STD_LOGIC;
\ap_CS_fsm_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
ap_rst_n : in STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC
);
end design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi;
architecture STRUCTURE of design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi is
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ap_idle : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal \^d_read_reg_52_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal int_ap_done : STD_LOGIC;
signal int_ap_done_i_1_n_0 : STD_LOGIC;
signal int_ap_done_i_2_n_0 : STD_LOGIC;
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_start_i_1_n_0 : STD_LOGIC;
signal int_ap_start_i_2_n_0 : STD_LOGIC;
signal int_ap_start_i_3_n_0 : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_auto_restart_i_1_n_0 : STD_LOGIC;
signal \int_d_i[0]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[10]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[11]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[12]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[13]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[14]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[15]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[16]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[17]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[18]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[19]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[1]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[20]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[21]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[22]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[23]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[24]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[25]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[26]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[27]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[28]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[29]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[2]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[30]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_2_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_3_n_0\ : STD_LOGIC;
signal \int_d_i[3]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[4]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[5]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[6]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[7]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[8]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[9]_i_1_n_0\ : STD_LOGIC;
signal int_d_o : STD_LOGIC_VECTOR ( 31 downto 0 );
signal int_d_o_ap_vld : STD_LOGIC;
signal int_d_o_ap_vld_i_1_n_0 : STD_LOGIC;
signal int_gie_i_1_n_0 : STD_LOGIC;
signal int_gie_reg_n_0 : STD_LOGIC;
signal \int_ier[0]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_2_n_0\ : STD_LOGIC;
signal \int_ier_reg_n_0_[0]\ : STD_LOGIC;
signal \int_ier_reg_n_0_[1]\ : STD_LOGIC;
signal int_isr : STD_LOGIC;
signal int_isr7_out : STD_LOGIC;
signal \int_isr[0]_i_1_n_0\ : STD_LOGIC;
signal \int_isr[1]_i_1_n_0\ : STD_LOGIC;
signal \int_isr_reg_n_0_[0]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_1_in : STD_LOGIC;
signal rdata : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[0]_i_3_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[16]_i_1_n_0\ : STD_LOGIC;
signal \rdata[17]_i_1_n_0\ : STD_LOGIC;
signal \rdata[18]_i_1_n_0\ : STD_LOGIC;
signal \rdata[19]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_2_n_0\ : STD_LOGIC;
signal \rdata[1]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_4_n_0\ : STD_LOGIC;
signal \rdata[20]_i_1_n_0\ : STD_LOGIC;
signal \rdata[21]_i_1_n_0\ : STD_LOGIC;
signal \rdata[22]_i_1_n_0\ : STD_LOGIC;
signal \rdata[23]_i_1_n_0\ : STD_LOGIC;
signal \rdata[24]_i_1_n_0\ : STD_LOGIC;
signal \rdata[25]_i_1_n_0\ : STD_LOGIC;
signal \rdata[26]_i_1_n_0\ : STD_LOGIC;
signal \rdata[27]_i_1_n_0\ : STD_LOGIC;
signal \rdata[28]_i_1_n_0\ : STD_LOGIC;
signal \rdata[29]_i_1_n_0\ : STD_LOGIC;
signal \rdata[30]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_3_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_2_n_0\ : STD_LOGIC;
signal \rdata[7]_i_3_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_pointer_basic_io_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_pointer_basic_io_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \d_read_reg_52[31]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair33";
attribute SOFT_HLUTNM of int_ap_start_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_d_i[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \int_d_i[10]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_d_i[11]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_d_i[12]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[13]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[14]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[15]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[16]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[17]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[18]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[19]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[20]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_d_i[21]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_d_i[22]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[23]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[24]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[25]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[26]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[27]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[28]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[29]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[30]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[31]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \int_d_i[4]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_d_i[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_d_i[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[8]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_d_i[9]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_ier[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_isr[1]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdata[10]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[11]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[12]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[13]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \rdata[15]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[16]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[17]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \rdata[18]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[19]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[1]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdata[20]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[21]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[22]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[23]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[24]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[25]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[26]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[27]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[28]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[29]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[30]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[31]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[5]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \rdata[6]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \rdata[7]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdata[8]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \rdata[9]_i_1\ : label is "soft_lutpair31";
begin
SR(0) <= \^sr\(0);
\d_read_reg_52_reg[31]\(31 downto 0) <= \^d_read_reg_52_reg[31]\(31 downto 0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_pointer_basic_io_RVALID(1 downto 0) <= \^s_axi_pointer_basic_io_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BFB"
)
port map (
I0 => s_axi_pointer_basic_io_RREADY,
I1 => \^s_axi_pointer_basic_io_rvalid\(1),
I2 => \^s_axi_pointer_basic_io_rvalid\(0),
I3 => s_axi_pointer_basic_io_ARVALID,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_ARVALID,
I1 => \^s_axi_pointer_basic_io_rvalid\(0),
I2 => s_axi_pointer_basic_io_RREADY,
I3 => \^s_axi_pointer_basic_io_rvalid\(1),
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF272227"
)
port map (
I0 => \^out\(0),
I1 => s_axi_pointer_basic_io_AWVALID,
I2 => \^out\(1),
I3 => \^out\(2),
I4 => s_axi_pointer_basic_io_BREADY,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_AWVALID,
I1 => \^out\(0),
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_WVALID,
I1 => \^out\(1),
I2 => s_axi_pointer_basic_io_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_2_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_2_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => ap_start,
I3 => Q(2),
O => \ap_CS_fsm_reg[1]\(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => Q(0),
I1 => ap_start,
I2 => Q(2),
I3 => Q(1),
O => \ap_CS_fsm_reg[1]\(1)
);
\d_read_reg_52[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ap_start,
I1 => Q(0),
O => E(0)
);
int_ap_done_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFAAAAAAAA"
)
port map (
I0 => Q(2),
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => s_axi_pointer_basic_io_ARADDR(2),
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_done_i_2_n_0,
I5 => int_ap_done,
O => int_ap_done_i_1_n_0
);
int_ap_done_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_pointer_basic_io_ARVALID,
I1 => \^s_axi_pointer_basic_io_rvalid\(0),
I2 => s_axi_pointer_basic_io_ARADDR(0),
I3 => s_axi_pointer_basic_io_ARADDR(1),
O => int_ap_done_i_2_n_0
);
int_ap_done_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_done_i_1_n_0,
Q => int_ap_done,
R => \^sr\(0)
);
int_ap_idle_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => ap_idle
);
int_ap_idle_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_idle,
Q => int_ap_idle,
R => \^sr\(0)
);
int_ap_ready_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => Q(2),
Q => int_ap_ready,
R => \^sr\(0)
);
int_ap_start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBBBBBF8888888"
)
port map (
I0 => int_auto_restart,
I1 => Q(2),
I2 => int_ap_start_i_2_n_0,
I3 => int_ap_start_i_3_n_0,
I4 => s_axi_pointer_basic_io_WDATA(0),
I5 => ap_start,
O => int_ap_start_i_1_n_0
);
int_ap_start_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_pointer_basic_io_WSTRB(0),
I1 => \waddr_reg_n_0_[2]\,
O => int_ap_start_i_2_n_0
);
int_ap_start_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[1]\,
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \^out\(1),
I4 => \waddr_reg_n_0_[3]\,
I5 => \waddr_reg_n_0_[4]\,
O => int_ap_start_i_3_n_0
);
int_ap_start_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_start_i_1_n_0,
Q => ap_start,
R => \^sr\(0)
);
int_auto_restart_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(7),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => int_ap_start_i_3_n_0,
I4 => int_auto_restart,
O => int_auto_restart_i_1_n_0
);
int_auto_restart_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_auto_restart_i_1_n_0,
Q => int_auto_restart,
R => \^sr\(0)
);
\int_d_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(0),
O => \int_d_i[0]_i_1_n_0\
);
\int_d_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(10),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(10),
O => \int_d_i[10]_i_1_n_0\
);
\int_d_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(11),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(11),
O => \int_d_i[11]_i_1_n_0\
);
\int_d_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(12),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(12),
O => \int_d_i[12]_i_1_n_0\
);
\int_d_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(13),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(13),
O => \int_d_i[13]_i_1_n_0\
);
\int_d_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(14),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(14),
O => \int_d_i[14]_i_1_n_0\
);
\int_d_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(15),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(15),
O => \int_d_i[15]_i_1_n_0\
);
\int_d_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(16),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(16),
O => \int_d_i[16]_i_1_n_0\
);
\int_d_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(17),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(17),
O => \int_d_i[17]_i_1_n_0\
);
\int_d_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(18),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(18),
O => \int_d_i[18]_i_1_n_0\
);
\int_d_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(19),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(19),
O => \int_d_i[19]_i_1_n_0\
);
\int_d_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(1),
O => \int_d_i[1]_i_1_n_0\
);
\int_d_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(20),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(20),
O => \int_d_i[20]_i_1_n_0\
);
\int_d_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(21),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(21),
O => \int_d_i[21]_i_1_n_0\
);
\int_d_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(22),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(22),
O => \int_d_i[22]_i_1_n_0\
);
\int_d_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(23),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^d_read_reg_52_reg[31]\(23),
O => \int_d_i[23]_i_1_n_0\
);
\int_d_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(24),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(24),
O => \int_d_i[24]_i_1_n_0\
);
\int_d_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(25),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(25),
O => \int_d_i[25]_i_1_n_0\
);
\int_d_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(26),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(26),
O => \int_d_i[26]_i_1_n_0\
);
\int_d_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(27),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(27),
O => \int_d_i[27]_i_1_n_0\
);
\int_d_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(28),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(28),
O => \int_d_i[28]_i_1_n_0\
);
\int_d_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(29),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(29),
O => \int_d_i[29]_i_1_n_0\
);
\int_d_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(2),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(2),
O => \int_d_i[2]_i_1_n_0\
);
\int_d_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(30),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(30),
O => \int_d_i[30]_i_1_n_0\
);
\int_d_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \int_d_i[31]_i_3_n_0\,
I1 => \waddr_reg_n_0_[4]\,
I2 => \waddr_reg_n_0_[2]\,
O => \int_d_i[31]_i_1_n_0\
);
\int_d_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(31),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^d_read_reg_52_reg[31]\(31),
O => \int_d_i[31]_i_2_n_0\
);
\int_d_i[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => \waddr_reg_n_0_[3]\,
I1 => \^out\(1),
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \waddr_reg_n_0_[1]\,
I4 => \waddr_reg_n_0_[0]\,
O => \int_d_i[31]_i_3_n_0\
);
\int_d_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(3),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(3),
O => \int_d_i[3]_i_1_n_0\
);
\int_d_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(4),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(4),
O => \int_d_i[4]_i_1_n_0\
);
\int_d_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(5),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(5),
O => \int_d_i[5]_i_1_n_0\
);
\int_d_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(6),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(6),
O => \int_d_i[6]_i_1_n_0\
);
\int_d_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(7),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^d_read_reg_52_reg[31]\(7),
O => \int_d_i[7]_i_1_n_0\
);
\int_d_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(8),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(8),
O => \int_d_i[8]_i_1_n_0\
);
\int_d_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(9),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^d_read_reg_52_reg[31]\(9),
O => \int_d_i[9]_i_1_n_0\
);
\int_d_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[0]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(0),
R => \^sr\(0)
);
\int_d_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[10]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(10),
R => \^sr\(0)
);
\int_d_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[11]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(11),
R => \^sr\(0)
);
\int_d_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[12]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(12),
R => \^sr\(0)
);
\int_d_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[13]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(13),
R => \^sr\(0)
);
\int_d_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[14]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(14),
R => \^sr\(0)
);
\int_d_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[15]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(15),
R => \^sr\(0)
);
\int_d_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[16]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(16),
R => \^sr\(0)
);
\int_d_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[17]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(17),
R => \^sr\(0)
);
\int_d_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[18]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(18),
R => \^sr\(0)
);
\int_d_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[19]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(19),
R => \^sr\(0)
);
\int_d_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[1]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(1),
R => \^sr\(0)
);
\int_d_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[20]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(20),
R => \^sr\(0)
);
\int_d_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[21]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(21),
R => \^sr\(0)
);
\int_d_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[22]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(22),
R => \^sr\(0)
);
\int_d_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[23]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(23),
R => \^sr\(0)
);
\int_d_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[24]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(24),
R => \^sr\(0)
);
\int_d_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[25]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(25),
R => \^sr\(0)
);
\int_d_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[26]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(26),
R => \^sr\(0)
);
\int_d_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[27]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(27),
R => \^sr\(0)
);
\int_d_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[28]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(28),
R => \^sr\(0)
);
\int_d_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[29]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(29),
R => \^sr\(0)
);
\int_d_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[2]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(2),
R => \^sr\(0)
);
\int_d_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[30]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(30),
R => \^sr\(0)
);
\int_d_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[31]_i_2_n_0\,
Q => \^d_read_reg_52_reg[31]\(31),
R => \^sr\(0)
);
\int_d_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[3]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(3),
R => \^sr\(0)
);
\int_d_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[4]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(4),
R => \^sr\(0)
);
\int_d_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[5]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(5),
R => \^sr\(0)
);
\int_d_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[6]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(6),
R => \^sr\(0)
);
\int_d_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[7]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(7),
R => \^sr\(0)
);
\int_d_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[8]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(8),
R => \^sr\(0)
);
\int_d_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_d_i[31]_i_1_n_0\,
D => \int_d_i[9]_i_1_n_0\,
Q => \^d_read_reg_52_reg[31]\(9),
R => \^sr\(0)
);
int_d_o_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFAAAAAAAA"
)
port map (
I0 => Q(2),
I1 => s_axi_pointer_basic_io_ARADDR(2),
I2 => s_axi_pointer_basic_io_ARADDR(4),
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_done_i_2_n_0,
I5 => int_d_o_ap_vld,
O => int_d_o_ap_vld_i_1_n_0
);
int_d_o_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_d_o_ap_vld_i_1_n_0,
Q => int_d_o_ap_vld,
R => \^sr\(0)
);
\int_d_o_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(0),
Q => int_d_o(0),
R => \^sr\(0)
);
\int_d_o_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(10),
Q => int_d_o(10),
R => \^sr\(0)
);
\int_d_o_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(11),
Q => int_d_o(11),
R => \^sr\(0)
);
\int_d_o_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(12),
Q => int_d_o(12),
R => \^sr\(0)
);
\int_d_o_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(13),
Q => int_d_o(13),
R => \^sr\(0)
);
\int_d_o_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(14),
Q => int_d_o(14),
R => \^sr\(0)
);
\int_d_o_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(15),
Q => int_d_o(15),
R => \^sr\(0)
);
\int_d_o_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(16),
Q => int_d_o(16),
R => \^sr\(0)
);
\int_d_o_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(17),
Q => int_d_o(17),
R => \^sr\(0)
);
\int_d_o_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(18),
Q => int_d_o(18),
R => \^sr\(0)
);
\int_d_o_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(19),
Q => int_d_o(19),
R => \^sr\(0)
);
\int_d_o_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(1),
Q => int_d_o(1),
R => \^sr\(0)
);
\int_d_o_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(20),
Q => int_d_o(20),
R => \^sr\(0)
);
\int_d_o_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(21),
Q => int_d_o(21),
R => \^sr\(0)
);
\int_d_o_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(22),
Q => int_d_o(22),
R => \^sr\(0)
);
\int_d_o_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(23),
Q => int_d_o(23),
R => \^sr\(0)
);
\int_d_o_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(24),
Q => int_d_o(24),
R => \^sr\(0)
);
\int_d_o_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(25),
Q => int_d_o(25),
R => \^sr\(0)
);
\int_d_o_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(26),
Q => int_d_o(26),
R => \^sr\(0)
);
\int_d_o_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(27),
Q => int_d_o(27),
R => \^sr\(0)
);
\int_d_o_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(28),
Q => int_d_o(28),
R => \^sr\(0)
);
\int_d_o_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(29),
Q => int_d_o(29),
R => \^sr\(0)
);
\int_d_o_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(2),
Q => int_d_o(2),
R => \^sr\(0)
);
\int_d_o_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(30),
Q => int_d_o(30),
R => \^sr\(0)
);
\int_d_o_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(31),
Q => int_d_o(31),
R => \^sr\(0)
);
\int_d_o_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(3),
Q => int_d_o(3),
R => \^sr\(0)
);
\int_d_o_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(4),
Q => int_d_o(4),
R => \^sr\(0)
);
\int_d_o_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(5),
Q => int_d_o(5),
R => \^sr\(0)
);
\int_d_o_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(6),
Q => int_d_o(6),
R => \^sr\(0)
);
\int_d_o_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(7),
Q => int_d_o(7),
R => \^sr\(0)
);
\int_d_o_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(8),
Q => int_d_o(8),
R => \^sr\(0)
);
\int_d_o_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => Q(2),
D => D(9),
Q => int_d_o(9),
R => \^sr\(0)
);
int_gie_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF8000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => int_ap_start_i_3_n_0,
I2 => \waddr_reg_n_0_[2]\,
I3 => s_axi_pointer_basic_io_WSTRB(0),
I4 => int_gie_reg_n_0,
O => int_gie_i_1_n_0
);
int_gie_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_gie_i_1_n_0,
Q => int_gie_reg_n_0,
R => \^sr\(0)
);
\int_ier[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \int_ier[1]_i_2_n_0\,
I4 => \int_ier_reg_n_0_[0]\,
O => \int_ier[0]_i_1_n_0\
);
\int_ier[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => \waddr_reg_n_0_[2]\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \int_ier[1]_i_2_n_0\,
I4 => \int_ier_reg_n_0_[1]\,
O => \int_ier[1]_i_1_n_0\
);
\int_ier[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF7FFFF"
)
port map (
I0 => \^out\(1),
I1 => s_axi_pointer_basic_io_WVALID,
I2 => \waddr_reg_n_0_[1]\,
I3 => \waddr_reg_n_0_[0]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \waddr_reg_n_0_[4]\,
O => \int_ier[1]_i_2_n_0\
);
\int_ier_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[0]_i_1_n_0\,
Q => \int_ier_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_ier_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[1]_i_1_n_0\,
Q => \int_ier_reg_n_0_[1]\,
R => \^sr\(0)
);
\int_isr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFFFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => \int_ier[1]_i_2_n_0\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \waddr_reg_n_0_[2]\,
I4 => int_isr7_out,
I5 => \int_isr_reg_n_0_[0]\,
O => \int_isr[0]_i_1_n_0\
);
\int_isr[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(2),
I1 => \int_ier_reg_n_0_[0]\,
O => int_isr7_out
);
\int_isr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFFFFFFF2000"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => \int_ier[1]_i_2_n_0\,
I2 => s_axi_pointer_basic_io_WSTRB(0),
I3 => \waddr_reg_n_0_[2]\,
I4 => int_isr,
I5 => p_1_in,
O => \int_isr[1]_i_1_n_0\
);
\int_isr[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(2),
I1 => \int_ier_reg_n_0_[1]\,
O => int_isr
);
\int_isr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[0]_i_1_n_0\,
Q => \int_isr_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_isr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[1]_i_1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
interrupt_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => int_gie_reg_n_0,
I1 => p_1_in,
I2 => \int_isr_reg_n_0_[0]\,
O => interrupt
);
\rdata[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000B8"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => \rdata[0]_i_3_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(0),
I4 => s_axi_pointer_basic_io_ARADDR(1),
O => rdata(0)
);
\rdata[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0A0CFC0"
)
port map (
I0 => int_d_o_ap_vld,
I1 => int_d_o(0),
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => \^d_read_reg_52_reg[31]\(0),
I4 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[0]_i_2_n_0\
);
\rdata[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \int_isr_reg_n_0_[0]\,
I1 => \int_ier_reg_n_0_[0]\,
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => int_gie_reg_n_0,
I4 => s_axi_pointer_basic_io_ARADDR(2),
I5 => ap_start,
O => \rdata[0]_i_3_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(10),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(11),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(12),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(13),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(14),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(15),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(15),
O => \rdata[15]_i_1_n_0\
);
\rdata[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(16),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(16),
O => \rdata[16]_i_1_n_0\
);
\rdata[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(17),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(17),
O => \rdata[17]_i_1_n_0\
);
\rdata[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(18),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(18),
O => \rdata[18]_i_1_n_0\
);
\rdata[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(19),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(19),
O => \rdata[19]_i_1_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0E0E0EE"
)
port map (
I0 => \rdata[1]_i_2_n_0\,
I1 => \rdata[1]_i_3_n_0\,
I2 => \rdata[1]_i_4_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(4),
I4 => s_axi_pointer_basic_io_ARADDR(0),
I5 => s_axi_pointer_basic_io_ARADDR(1),
O => rdata(1)
);
\rdata[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F2F2F2F2F2F2FFF2"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(4),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(1),
I3 => int_ap_done,
I4 => s_axi_pointer_basic_io_ARADDR(3),
I5 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[1]_i_2_n_0\
);
\rdata[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(3),
I1 => \int_ier_reg_n_0_[1]\,
I2 => s_axi_pointer_basic_io_ARADDR(2),
I3 => p_1_in,
O => \rdata[1]_i_3_n_0\
);
\rdata[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000E2"
)
port map (
I0 => \^d_read_reg_52_reg[31]\(1),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => int_d_o(1),
I3 => s_axi_pointer_basic_io_ARADDR(1),
I4 => s_axi_pointer_basic_io_ARADDR(0),
I5 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[1]_i_4_n_0\
);
\rdata[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(20),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(20),
O => \rdata[20]_i_1_n_0\
);
\rdata[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(21),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(21),
O => \rdata[21]_i_1_n_0\
);
\rdata[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(22),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(22),
O => \rdata[22]_i_1_n_0\
);
\rdata[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(23),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(23),
O => \rdata[23]_i_1_n_0\
);
\rdata[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(24),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(24),
O => \rdata[24]_i_1_n_0\
);
\rdata[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(25),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(25),
O => \rdata[25]_i_1_n_0\
);
\rdata[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(26),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(26),
O => \rdata[26]_i_1_n_0\
);
\rdata[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(27),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(27),
O => \rdata[27]_i_1_n_0\
);
\rdata[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(28),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(28),
O => \rdata[28]_i_1_n_0\
);
\rdata[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(29),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(29),
O => \rdata[29]_i_1_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(2),
I1 => \^d_read_reg_52_reg[31]\(2),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_idle,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(2)
);
\rdata[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(30),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(30),
O => \rdata[30]_i_1_n_0\
);
\rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFD000000000000"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(4),
I1 => s_axi_pointer_basic_io_ARADDR(2),
I2 => s_axi_pointer_basic_io_ARADDR(0),
I3 => s_axi_pointer_basic_io_ARADDR(1),
I4 => s_axi_pointer_basic_io_ARVALID,
I5 => \^s_axi_pointer_basic_io_rvalid\(0),
O => \rdata[31]_i_1_n_0\
);
\rdata[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_pointer_basic_io_rvalid\(0),
I1 => s_axi_pointer_basic_io_ARVALID,
O => ar_hs
);
\rdata[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(31),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(31),
O => \rdata[31]_i_3_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(3),
I1 => \^d_read_reg_52_reg[31]\(3),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_ap_ready,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(3)
);
\rdata[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(4),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(5),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(6),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000AFC0A0C"
)
port map (
I0 => int_d_o(7),
I1 => \^d_read_reg_52_reg[31]\(7),
I2 => \rdata[7]_i_2_n_0\,
I3 => s_axi_pointer_basic_io_ARADDR(3),
I4 => int_auto_restart,
I5 => \rdata[7]_i_3_n_0\,
O => rdata(7)
);
\rdata[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(1),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(4),
O => \rdata[7]_i_2_n_0\
);
\rdata[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(2),
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(1),
O => \rdata[7]_i_3_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(8),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(9),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^d_read_reg_52_reg[31]\(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(0),
Q => s_axi_pointer_basic_io_RDATA(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(10),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(11),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(12),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(13),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(14),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(15),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[16]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(16),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[17]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(17),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[18]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(18),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[19]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(19),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(1),
Q => s_axi_pointer_basic_io_RDATA(1),
R => '0'
);
\rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[20]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(20),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[21]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(21),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[22]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(22),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[23]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(23),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[24]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(24),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[25]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(25),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[26]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(26),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[27]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(27),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[28]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(28),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[29]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(29),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(2),
Q => s_axi_pointer_basic_io_RDATA(2),
R => '0'
);
\rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[30]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(30),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[31]_i_3_n_0\,
Q => s_axi_pointer_basic_io_RDATA(31),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(3),
Q => s_axi_pointer_basic_io_RDATA(3),
R => '0'
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(4),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(5),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(6),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => rdata(7),
Q => s_axi_pointer_basic_io_RDATA(7),
R => '0'
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(8),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => s_axi_pointer_basic_io_RDATA(9),
R => \rdata[31]_i_1_n_0\
);
\waddr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^out\(0),
I1 => s_axi_pointer_basic_io_AWVALID,
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1_pointer_basic is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt : out STD_LOGIC
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of design_1_pointer_basic_0_1_pointer_basic : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of design_1_pointer_basic_0_1_pointer_basic : entity is "3'b100";
attribute hls_module : string;
attribute hls_module of design_1_pointer_basic_0_1_pointer_basic : entity is "yes";
end design_1_pointer_basic_0_1_pointer_basic;
architecture STRUCTURE of design_1_pointer_basic_0_1_pointer_basic is
signal \<const0>\ : STD_LOGIC;
signal \acc[0]_i_2_n_0\ : STD_LOGIC;
signal \acc[0]_i_3_n_0\ : STD_LOGIC;
signal \acc[0]_i_4_n_0\ : STD_LOGIC;
signal \acc[0]_i_5_n_0\ : STD_LOGIC;
signal \acc[12]_i_2_n_0\ : STD_LOGIC;
signal \acc[12]_i_3_n_0\ : STD_LOGIC;
signal \acc[12]_i_4_n_0\ : STD_LOGIC;
signal \acc[12]_i_5_n_0\ : STD_LOGIC;
signal \acc[16]_i_2_n_0\ : STD_LOGIC;
signal \acc[16]_i_3_n_0\ : STD_LOGIC;
signal \acc[16]_i_4_n_0\ : STD_LOGIC;
signal \acc[16]_i_5_n_0\ : STD_LOGIC;
signal \acc[20]_i_2_n_0\ : STD_LOGIC;
signal \acc[20]_i_3_n_0\ : STD_LOGIC;
signal \acc[20]_i_4_n_0\ : STD_LOGIC;
signal \acc[20]_i_5_n_0\ : STD_LOGIC;
signal \acc[24]_i_2_n_0\ : STD_LOGIC;
signal \acc[24]_i_3_n_0\ : STD_LOGIC;
signal \acc[24]_i_4_n_0\ : STD_LOGIC;
signal \acc[24]_i_5_n_0\ : STD_LOGIC;
signal \acc[28]_i_2_n_0\ : STD_LOGIC;
signal \acc[28]_i_3_n_0\ : STD_LOGIC;
signal \acc[28]_i_4_n_0\ : STD_LOGIC;
signal \acc[28]_i_5_n_0\ : STD_LOGIC;
signal \acc[4]_i_2_n_0\ : STD_LOGIC;
signal \acc[4]_i_3_n_0\ : STD_LOGIC;
signal \acc[4]_i_4_n_0\ : STD_LOGIC;
signal \acc[4]_i_5_n_0\ : STD_LOGIC;
signal \acc[8]_i_2_n_0\ : STD_LOGIC;
signal \acc[8]_i_3_n_0\ : STD_LOGIC;
signal \acc[8]_i_4_n_0\ : STD_LOGIC;
signal \acc[8]_i_5_n_0\ : STD_LOGIC;
signal acc_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \acc_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal d_i : STD_LOGIC_VECTOR ( 31 downto 0 );
signal d_read_reg_52 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
begin
s_axi_pointer_basic_io_BRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_BRESP(0) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\acc[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(3),
I1 => acc_reg(3),
O => \acc[0]_i_2_n_0\
);
\acc[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(2),
I1 => acc_reg(2),
O => \acc[0]_i_3_n_0\
);
\acc[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(1),
I1 => acc_reg(1),
O => \acc[0]_i_4_n_0\
);
\acc[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(0),
I1 => acc_reg(0),
O => \acc[0]_i_5_n_0\
);
\acc[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(15),
I1 => acc_reg(15),
O => \acc[12]_i_2_n_0\
);
\acc[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(14),
I1 => acc_reg(14),
O => \acc[12]_i_3_n_0\
);
\acc[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(13),
I1 => acc_reg(13),
O => \acc[12]_i_4_n_0\
);
\acc[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(12),
I1 => acc_reg(12),
O => \acc[12]_i_5_n_0\
);
\acc[16]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(19),
I1 => acc_reg(19),
O => \acc[16]_i_2_n_0\
);
\acc[16]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(18),
I1 => acc_reg(18),
O => \acc[16]_i_3_n_0\
);
\acc[16]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(17),
I1 => acc_reg(17),
O => \acc[16]_i_4_n_0\
);
\acc[16]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(16),
I1 => acc_reg(16),
O => \acc[16]_i_5_n_0\
);
\acc[20]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(23),
I1 => acc_reg(23),
O => \acc[20]_i_2_n_0\
);
\acc[20]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(22),
I1 => acc_reg(22),
O => \acc[20]_i_3_n_0\
);
\acc[20]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(21),
I1 => acc_reg(21),
O => \acc[20]_i_4_n_0\
);
\acc[20]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(20),
I1 => acc_reg(20),
O => \acc[20]_i_5_n_0\
);
\acc[24]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(27),
I1 => acc_reg(27),
O => \acc[24]_i_2_n_0\
);
\acc[24]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(26),
I1 => acc_reg(26),
O => \acc[24]_i_3_n_0\
);
\acc[24]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(25),
I1 => acc_reg(25),
O => \acc[24]_i_4_n_0\
);
\acc[24]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(24),
I1 => acc_reg(24),
O => \acc[24]_i_5_n_0\
);
\acc[28]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => acc_reg(31),
I1 => d_read_reg_52(31),
O => \acc[28]_i_2_n_0\
);
\acc[28]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(30),
I1 => acc_reg(30),
O => \acc[28]_i_3_n_0\
);
\acc[28]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(29),
I1 => acc_reg(29),
O => \acc[28]_i_4_n_0\
);
\acc[28]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(28),
I1 => acc_reg(28),
O => \acc[28]_i_5_n_0\
);
\acc[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(7),
I1 => acc_reg(7),
O => \acc[4]_i_2_n_0\
);
\acc[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(6),
I1 => acc_reg(6),
O => \acc[4]_i_3_n_0\
);
\acc[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(5),
I1 => acc_reg(5),
O => \acc[4]_i_4_n_0\
);
\acc[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(4),
I1 => acc_reg(4),
O => \acc[4]_i_5_n_0\
);
\acc[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(11),
I1 => acc_reg(11),
O => \acc[8]_i_2_n_0\
);
\acc[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(10),
I1 => acc_reg(10),
O => \acc[8]_i_3_n_0\
);
\acc[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(9),
I1 => acc_reg(9),
O => \acc[8]_i_4_n_0\
);
\acc[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(8),
I1 => acc_reg(8),
O => \acc[8]_i_5_n_0\
);
\acc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_7\,
Q => acc_reg(0),
R => '0'
);
\acc_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \acc_reg[0]_i_1_n_0\,
CO(2) => \acc_reg[0]_i_1_n_1\,
CO(1) => \acc_reg[0]_i_1_n_2\,
CO(0) => \acc_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(3 downto 0),
O(3) => \acc_reg[0]_i_1_n_4\,
O(2) => \acc_reg[0]_i_1_n_5\,
O(1) => \acc_reg[0]_i_1_n_6\,
O(0) => \acc_reg[0]_i_1_n_7\,
S(3) => \acc[0]_i_2_n_0\,
S(2) => \acc[0]_i_3_n_0\,
S(1) => \acc[0]_i_4_n_0\,
S(0) => \acc[0]_i_5_n_0\
);
\acc_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_5\,
Q => acc_reg(10),
R => '0'
);
\acc_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_4\,
Q => acc_reg(11),
R => '0'
);
\acc_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_7\,
Q => acc_reg(12),
R => '0'
);
\acc_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[8]_i_1_n_0\,
CO(3) => \acc_reg[12]_i_1_n_0\,
CO(2) => \acc_reg[12]_i_1_n_1\,
CO(1) => \acc_reg[12]_i_1_n_2\,
CO(0) => \acc_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(15 downto 12),
O(3) => \acc_reg[12]_i_1_n_4\,
O(2) => \acc_reg[12]_i_1_n_5\,
O(1) => \acc_reg[12]_i_1_n_6\,
O(0) => \acc_reg[12]_i_1_n_7\,
S(3) => \acc[12]_i_2_n_0\,
S(2) => \acc[12]_i_3_n_0\,
S(1) => \acc[12]_i_4_n_0\,
S(0) => \acc[12]_i_5_n_0\
);
\acc_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_6\,
Q => acc_reg(13),
R => '0'
);
\acc_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_5\,
Q => acc_reg(14),
R => '0'
);
\acc_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_4\,
Q => acc_reg(15),
R => '0'
);
\acc_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_7\,
Q => acc_reg(16),
R => '0'
);
\acc_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[12]_i_1_n_0\,
CO(3) => \acc_reg[16]_i_1_n_0\,
CO(2) => \acc_reg[16]_i_1_n_1\,
CO(1) => \acc_reg[16]_i_1_n_2\,
CO(0) => \acc_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(19 downto 16),
O(3) => \acc_reg[16]_i_1_n_4\,
O(2) => \acc_reg[16]_i_1_n_5\,
O(1) => \acc_reg[16]_i_1_n_6\,
O(0) => \acc_reg[16]_i_1_n_7\,
S(3) => \acc[16]_i_2_n_0\,
S(2) => \acc[16]_i_3_n_0\,
S(1) => \acc[16]_i_4_n_0\,
S(0) => \acc[16]_i_5_n_0\
);
\acc_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_6\,
Q => acc_reg(17),
R => '0'
);
\acc_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_5\,
Q => acc_reg(18),
R => '0'
);
\acc_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_4\,
Q => acc_reg(19),
R => '0'
);
\acc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_6\,
Q => acc_reg(1),
R => '0'
);
\acc_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_7\,
Q => acc_reg(20),
R => '0'
);
\acc_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[16]_i_1_n_0\,
CO(3) => \acc_reg[20]_i_1_n_0\,
CO(2) => \acc_reg[20]_i_1_n_1\,
CO(1) => \acc_reg[20]_i_1_n_2\,
CO(0) => \acc_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(23 downto 20),
O(3) => \acc_reg[20]_i_1_n_4\,
O(2) => \acc_reg[20]_i_1_n_5\,
O(1) => \acc_reg[20]_i_1_n_6\,
O(0) => \acc_reg[20]_i_1_n_7\,
S(3) => \acc[20]_i_2_n_0\,
S(2) => \acc[20]_i_3_n_0\,
S(1) => \acc[20]_i_4_n_0\,
S(0) => \acc[20]_i_5_n_0\
);
\acc_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_6\,
Q => acc_reg(21),
R => '0'
);
\acc_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_5\,
Q => acc_reg(22),
R => '0'
);
\acc_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_4\,
Q => acc_reg(23),
R => '0'
);
\acc_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_7\,
Q => acc_reg(24),
R => '0'
);
\acc_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[20]_i_1_n_0\,
CO(3) => \acc_reg[24]_i_1_n_0\,
CO(2) => \acc_reg[24]_i_1_n_1\,
CO(1) => \acc_reg[24]_i_1_n_2\,
CO(0) => \acc_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(27 downto 24),
O(3) => \acc_reg[24]_i_1_n_4\,
O(2) => \acc_reg[24]_i_1_n_5\,
O(1) => \acc_reg[24]_i_1_n_6\,
O(0) => \acc_reg[24]_i_1_n_7\,
S(3) => \acc[24]_i_2_n_0\,
S(2) => \acc[24]_i_3_n_0\,
S(1) => \acc[24]_i_4_n_0\,
S(0) => \acc[24]_i_5_n_0\
);
\acc_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_6\,
Q => acc_reg(25),
R => '0'
);
\acc_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_5\,
Q => acc_reg(26),
R => '0'
);
\acc_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_4\,
Q => acc_reg(27),
R => '0'
);
\acc_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_7\,
Q => acc_reg(28),
R => '0'
);
\acc_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[24]_i_1_n_0\,
CO(3) => \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \acc_reg[28]_i_1_n_1\,
CO(1) => \acc_reg[28]_i_1_n_2\,
CO(0) => \acc_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => d_read_reg_52(30 downto 28),
O(3) => \acc_reg[28]_i_1_n_4\,
O(2) => \acc_reg[28]_i_1_n_5\,
O(1) => \acc_reg[28]_i_1_n_6\,
O(0) => \acc_reg[28]_i_1_n_7\,
S(3) => \acc[28]_i_2_n_0\,
S(2) => \acc[28]_i_3_n_0\,
S(1) => \acc[28]_i_4_n_0\,
S(0) => \acc[28]_i_5_n_0\
);
\acc_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_6\,
Q => acc_reg(29),
R => '0'
);
\acc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_5\,
Q => acc_reg(2),
R => '0'
);
\acc_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_5\,
Q => acc_reg(30),
R => '0'
);
\acc_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_4\,
Q => acc_reg(31),
R => '0'
);
\acc_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_4\,
Q => acc_reg(3),
R => '0'
);
\acc_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_7\,
Q => acc_reg(4),
R => '0'
);
\acc_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[0]_i_1_n_0\,
CO(3) => \acc_reg[4]_i_1_n_0\,
CO(2) => \acc_reg[4]_i_1_n_1\,
CO(1) => \acc_reg[4]_i_1_n_2\,
CO(0) => \acc_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(7 downto 4),
O(3) => \acc_reg[4]_i_1_n_4\,
O(2) => \acc_reg[4]_i_1_n_5\,
O(1) => \acc_reg[4]_i_1_n_6\,
O(0) => \acc_reg[4]_i_1_n_7\,
S(3) => \acc[4]_i_2_n_0\,
S(2) => \acc[4]_i_3_n_0\,
S(1) => \acc[4]_i_4_n_0\,
S(0) => \acc[4]_i_5_n_0\
);
\acc_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_6\,
Q => acc_reg(5),
R => '0'
);
\acc_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_5\,
Q => acc_reg(6),
R => '0'
);
\acc_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_4\,
Q => acc_reg(7),
R => '0'
);
\acc_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_7\,
Q => acc_reg(8),
R => '0'
);
\acc_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[4]_i_1_n_0\,
CO(3) => \acc_reg[8]_i_1_n_0\,
CO(2) => \acc_reg[8]_i_1_n_1\,
CO(1) => \acc_reg[8]_i_1_n_2\,
CO(0) => \acc_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(11 downto 8),
O(3) => \acc_reg[8]_i_1_n_4\,
O(2) => \acc_reg[8]_i_1_n_5\,
O(1) => \acc_reg[8]_i_1_n_6\,
O(0) => \acc_reg[8]_i_1_n_7\,
S(3) => \acc[8]_i_2_n_0\,
S(2) => \acc[8]_i_3_n_0\,
S(1) => \acc[8]_i_4_n_0\,
S(0) => \acc[8]_i_5_n_0\
);
\acc_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_6\,
Q => acc_reg(9),
R => '0'
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_CS_fsm_state2,
Q => ap_CS_fsm_state3,
R => ap_rst_n_inv
);
\d_read_reg_52_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(0),
Q => d_read_reg_52(0),
R => '0'
);
\d_read_reg_52_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(10),
Q => d_read_reg_52(10),
R => '0'
);
\d_read_reg_52_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(11),
Q => d_read_reg_52(11),
R => '0'
);
\d_read_reg_52_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(12),
Q => d_read_reg_52(12),
R => '0'
);
\d_read_reg_52_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(13),
Q => d_read_reg_52(13),
R => '0'
);
\d_read_reg_52_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(14),
Q => d_read_reg_52(14),
R => '0'
);
\d_read_reg_52_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(15),
Q => d_read_reg_52(15),
R => '0'
);
\d_read_reg_52_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(16),
Q => d_read_reg_52(16),
R => '0'
);
\d_read_reg_52_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(17),
Q => d_read_reg_52(17),
R => '0'
);
\d_read_reg_52_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(18),
Q => d_read_reg_52(18),
R => '0'
);
\d_read_reg_52_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(19),
Q => d_read_reg_52(19),
R => '0'
);
\d_read_reg_52_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(1),
Q => d_read_reg_52(1),
R => '0'
);
\d_read_reg_52_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(20),
Q => d_read_reg_52(20),
R => '0'
);
\d_read_reg_52_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(21),
Q => d_read_reg_52(21),
R => '0'
);
\d_read_reg_52_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(22),
Q => d_read_reg_52(22),
R => '0'
);
\d_read_reg_52_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(23),
Q => d_read_reg_52(23),
R => '0'
);
\d_read_reg_52_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(24),
Q => d_read_reg_52(24),
R => '0'
);
\d_read_reg_52_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(25),
Q => d_read_reg_52(25),
R => '0'
);
\d_read_reg_52_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(26),
Q => d_read_reg_52(26),
R => '0'
);
\d_read_reg_52_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(27),
Q => d_read_reg_52(27),
R => '0'
);
\d_read_reg_52_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(28),
Q => d_read_reg_52(28),
R => '0'
);
\d_read_reg_52_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(29),
Q => d_read_reg_52(29),
R => '0'
);
\d_read_reg_52_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(2),
Q => d_read_reg_52(2),
R => '0'
);
\d_read_reg_52_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(30),
Q => d_read_reg_52(30),
R => '0'
);
\d_read_reg_52_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(31),
Q => d_read_reg_52(31),
R => '0'
);
\d_read_reg_52_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(3),
Q => d_read_reg_52(3),
R => '0'
);
\d_read_reg_52_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(4),
Q => d_read_reg_52(4),
R => '0'
);
\d_read_reg_52_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(5),
Q => d_read_reg_52(5),
R => '0'
);
\d_read_reg_52_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(6),
Q => d_read_reg_52(6),
R => '0'
);
\d_read_reg_52_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(7),
Q => d_read_reg_52(7),
R => '0'
);
\d_read_reg_52_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(8),
Q => d_read_reg_52(8),
R => '0'
);
\d_read_reg_52_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(9),
Q => d_read_reg_52(9),
R => '0'
);
pointer_basic_pointer_basic_io_s_axi_U: entity work.design_1_pointer_basic_0_1_pointer_basic_pointer_basic_io_s_axi
port map (
D(31 downto 0) => acc_reg(31 downto 0),
E(0) => ap_NS_fsm1,
Q(2) => ap_CS_fsm_state3,
Q(1) => ap_CS_fsm_state2,
Q(0) => \ap_CS_fsm_reg_n_0_[0]\,
SR(0) => ap_rst_n_inv,
\ap_CS_fsm_reg[1]\(1 downto 0) => ap_NS_fsm(1 downto 0),
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\d_read_reg_52_reg[31]\(31 downto 0) => d_i(31 downto 0),
interrupt => interrupt,
\out\(2) => s_axi_pointer_basic_io_BVALID,
\out\(1) => s_axi_pointer_basic_io_WREADY,
\out\(0) => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RVALID(1) => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RVALID(0) => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_pointer_basic_0_1 is
port (
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_pointer_basic_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_pointer_basic_0_1 : entity is "design_1_pointer_basic_0_1,pointer_basic,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of design_1_pointer_basic_0_1 : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of design_1_pointer_basic_0_1 : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of design_1_pointer_basic_0_1 : entity is "pointer_basic,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of design_1_pointer_basic_0_1 : entity is "yes";
end design_1_pointer_basic_0_1;
architecture STRUCTURE of design_1_pointer_basic_0_1 is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of inst : label is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "3'b100";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_pointer_basic_io_RREADY : signal is "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB";
begin
inst: entity work.design_1_pointer_basic_0_1_pointer_basic
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARREADY => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWREADY => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP(1 downto 0) => s_axi_pointer_basic_io_BRESP(1 downto 0),
s_axi_pointer_basic_io_BVALID => s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RRESP(1 downto 0) => s_axi_pointer_basic_io_RRESP(1 downto 0),
s_axi_pointer_basic_io_RVALID => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WREADY => s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal lock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal prom32 : std_ulogic;
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal i2c_scl : std_ulogic;
signal i2c_sda : std_ulogic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_sck : std_logic;
signal spi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal trst,tck,tms,tdi,tdo: std_ulogic;
signal gtx_clk : std_ulogic := '0';
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal emdint : std_ulogic;
signal emdio : std_logic;
signal emdc : std_ulogic;
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1', '0' after 1500 ns;
dsubre <= '1' when (testen = 1) and (scanen = 1) else
-- '0' when (testen = 1) and (scanen = 0) else '1';
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after ct * 1 ns;
gtx_clk <= not gtx_clk after 8 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "HHL";
-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
gpio(15 downto 11) <= "HLLHH"; --19
gpio(10 downto 8) <= "HLL"; --4
gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxd <= spw_txd; spw_rxs <= spw_txs;
roen <= '0';
promedac <= '0';
prom32 <= '1';
rxd2 <= txd2;
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
rst, clksel, clk, lock, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
i2c_scl, i2c_sda,
spi_miso, spi_mosi, spi_sck, spi_slvsel,
prom32,
spw_clksel, spw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
gtx_clk, erx_clk, erxd, erx_dv, etx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdio, emdc ,
test, trst, tck, tms, tdi, tdo);
-- optional sdram
sdcke <= "11";
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
emdint <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 0,
base1000_x_hd => 0,
base1000_t_fd => 0,
base1000_t_hd => 0,
rmii => 0,
rgmii => 0
)
port map(rst, emdio, etx_clk, erx_clk, erxd,
erx_dv, erx_er, erx_col, erx_crs, etxd,
etx_en, etx_er, emdc, gtx_clk);
end generate;
spimem0: if (CFG_SPICTRL_ENABLE = 1) generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0)
port map (spi_sck, spi_mosi, spi_miso, spi_slvsel(0));
end generate spimem0;
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
bst0: process
begin
trst <= '0';
tck <= '0';
tms <= '1';
tdi <= '0';
wait for 2500 ns;
trst <= '1';
if to_x01(error) = '1' then wait on error; end if;
if CFG_BOUNDSCAN_EN /= 0 then bscantest(tdo,tck,tms,tdi,10); end if;
assert false
report "*** IU in error mode, simulation halted ***"
severity failure ;
wait;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
cb <= buskeep(cb) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev42 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev42 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal tmpxx: std_logic_vector(19 downto 0);
signal tmpyy: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDMD2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
--constant LDIX : std_logic_vector(5 downto 0) := "000110";
--constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant STMD : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : std_logic_vector(31 downto 0);
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal dvect : WORD_VECTOR(0 to 7);
signal wout: std_logic_vector(63 downto 0);
signal lcount: std_logic_vector(31 downto 0);
signal scount: std_logic_vector(31 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2=LDMD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3=LDMD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3 = STMD) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when ((Opcode4=SYS or Opcode4=STMD) and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2=STM or Opcode2=STR or Opcode2=WPAD or Opcode2 = LDMD or Opcode2 = STMD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=LDMD or Opcode3 = STMD or Opcode3 = WPAD) else
true when(Opcode4=SYS or Opcode4=RETI or Opcode4 = STMD) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= x"00000000";
lcount <= x"00000000";
scount <= x"00000000";
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
t1_val <= X"0000000000000000";
t2_val <= X"0000000000000000";
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM or Opcode2 = LDMD) then
MAR <= x"000" & M2;
tmpxx <= std_logic_vector((unsigned(M2) + 1));
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STMD) then
dvect(0) <= std_logic_vector(unsigned(wva) + unsigned(h0));
dvect(1) <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dvect(2) <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dvect(3) <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dvect(4) <= std_logic_vector(unsigned(wve) + unsigned(h4));
dvect(5) <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dvect(6) <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dvect(7) <= std_logic_vector(unsigned(wvh) + unsigned(h7));
MAR <= x"000" & M2;
MDR_out <= dvect(to_integer(unsigned(scount)))(63 downto 32);
tmpyy <= x"000" & std_logic_vector(unsigned(M2) + 1);
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2 = LDMD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR) then
null;
elsif(Opcode2=STMD) then
register_file(to_integer(unsigned(RX3))) <= MAR;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDMD) then
mvect(to_integer(unsigned(lcount)))(63 downto 32) <= MDR_in;
MAR <= x"000" & tmpxx;
register_file(to_integer(unsigned(RX3))) <= std_logic_vector(lcount);
elsif (Opcode3=STM or Opcode3=STR) then
null;
elsif (Opcode3 = STMD) then
register_file(to_integer(unsigned(RY3))) <= tmpyy;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDMD) then
MDR_in <= MEM_in;
elsif(Opcode3 = STMD) then
MAR <= tmpyy;
MDR_out <= dvect(to_integer(unsigned(scount)))(31 downto 0);
elsif (Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
mvect(to_integer(unsigned(lcount)))(31 downto 0) <= MDR_in;
elsif (Opcode4 = STMD) then
null;
elsif (Opcode4 = WPAD) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
lcount <= std_logic_vector(unsigned(lcount)+1);
elsif (Opcode4 = STMD) then
if (to_integer(unsigned(scount)) = 7) then
scount <= x"00000000";
else
scount <= std_logic_vector(unsigned(scount) + 1);
end if;
elsif(Opcode4 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
|
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
|
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
|
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Wing_Pinout is
port (
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WingType_miso_AH: inout std_logic_vector(7 downto 0);
WingType_mosi_AH: inout std_logic_vector(7 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WingType_miso_AL: inout std_logic_vector(7 downto 0);
WingType_mosi_AL: inout std_logic_vector(7 downto 0);
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WingType_miso_BH: inout std_logic_vector(7 downto 0);
WingType_mosi_BH: inout std_logic_vector(7 downto 0);
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WingType_miso_BL: inout std_logic_vector(7 downto 0);
WingType_mosi_BL: inout std_logic_vector(7 downto 0);
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WingType_miso_CH: inout std_logic_vector(7 downto 0);
WingType_mosi_CH: inout std_logic_vector(7 downto 0);
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WingType_miso_CL: inout std_logic_vector(7 downto 0);
WingType_mosi_CL: inout std_logic_vector(7 downto 0);
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Wing_Pinout;
architecture BEHAVIORAL of Papilio_Default_Wing_Pinout is
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WingType_mosi_AL(0) );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WingType_mosi_AL(1) );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WingType_mosi_AL(2) );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WingType_mosi_AL(3) );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WingType_mosi_AL(4) );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WingType_mosi_AL(5) );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WingType_mosi_AL(6) );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WingType_mosi_AL(7) );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WingType_mosi_AH(0) );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WingType_mosi_AH(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WingType_mosi_AH(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WingType_mosi_AH(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WingType_mosi_AH(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WingType_mosi_AH(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WingType_mosi_AH(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WingType_mosi_AH(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WingType_mosi_BL(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WingType_mosi_BL(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WingType_mosi_BL(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WingType_mosi_BL(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WingType_mosi_BL(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WingType_mosi_BL(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WingType_mosi_BL(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WingType_mosi_BL(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WingType_mosi_BH(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WingType_mosi_BH(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WingType_mosi_BH(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WingType_mosi_BH(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WingType_mosi_BH(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WingType_mosi_BH(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WingType_mosi_BH(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WingType_mosi_BH(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WingType_mosi_CL(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WingType_mosi_CL(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WingType_mosi_CL(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WingType_mosi_CL(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WingType_mosi_CL(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WingType_mosi_CL(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WingType_mosi_CL(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WingType_mosi_CL(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WingType_mosi_CH(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WingType_mosi_CH(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WingType_mosi_CH(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WingType_mosi_CH(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WingType_mosi_CH(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WingType_mosi_CH(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WingType_mosi_CH(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WingType_mosi_CH(7) );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
WING_AL0 <= WingType_miso_AL(0);
WING_AL1 <= WingType_miso_AL(1);
WING_AL2 <= WingType_miso_AL(2);
WING_AL3 <= WingType_miso_AL(3);
WING_AL4 <= WingType_miso_AL(4);
WING_AL5 <= WingType_miso_AL(5);
WING_AL6 <= WingType_miso_AL(6);
WING_AL7 <= WingType_miso_AL(7);
WING_AH0 <= WingType_miso_AH(0);
WING_AH1 <= WingType_miso_AH(1);
WING_AH2 <= WingType_miso_AH(2);
WING_AH3 <= WingType_miso_AH(3);
WING_AH4 <= WingType_miso_AH(4);
WING_AH5 <= WingType_miso_AH(5);
WING_AH6 <= WingType_miso_AH(6);
WING_AH7 <= WingType_miso_AH(7);
WING_BL0 <= WingType_miso_BL(0);
WING_BL1 <= WingType_miso_BL(1);
WING_BL2 <= WingType_miso_BL(2);
WING_BL3 <= WingType_miso_BL(3);
WING_BL4 <= WingType_miso_BL(4);
WING_BL5 <= WingType_miso_BL(5);
WING_BL6 <= WingType_miso_BL(6);
WING_BL7 <= WingType_miso_BL(7);
WING_BH0 <= WingType_miso_BH(0);
WING_BH1 <= WingType_miso_BH(1);
WING_BH2 <= WingType_miso_BH(2);
WING_BH3 <= WingType_miso_BH(3);
WING_BH4 <= WingType_miso_BH(4);
WING_BH5 <= WingType_miso_BH(5);
WING_BH6 <= WingType_miso_BH(6);
WING_BH7 <= WingType_miso_BH(7);
WING_CL0 <= WingType_miso_CL(0);
WING_CL1 <= WingType_miso_CL(1);
WING_CL2 <= WingType_miso_CL(2);
WING_CL3 <= WingType_miso_CL(3);
WING_CL4 <= WingType_miso_CL(4);
WING_CL5 <= WingType_miso_CL(5);
WING_CL6 <= WingType_miso_CL(6);
WING_CL7 <= WingType_miso_CL(7);
WING_CH0 <= WingType_miso_CH(0);
WING_CH1 <= WingType_miso_CH(1);
WING_CH2 <= WingType_miso_CH(2);
WING_CH3 <= WingType_miso_CH(3);
WING_CH4 <= WingType_miso_CH(4);
WING_CH5 <= WingType_miso_CH(5);
WING_CH6 <= WingType_miso_CH(6);
WING_CH7 <= WingType_miso_CH(7);
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
|
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2012 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_bin2gray.vhd
--
-- -----------------------------------------------------------------------
--
-- Convert binary to gray-code
--
-- -----------------------------------------------------------------------
-- d - binary input
-- q - gray-code output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_bin2gray is
generic (
bits : integer := 4
);
port (
d : in unsigned(bits-1 downto 0) := (others => '0');
q : out unsigned(bits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_bin2gray is
begin
process(d)
begin
for i in 0 to bits-1 loop
if i = (bits-1) then
q(i) <= d(i);
else
q(i) <= d(i) xor d(i+1);
end if;
end loop;
end process;
end architecture;
|
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3151.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03151ent_a IS
END c05s02b02x00p08n01i03151ent_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_a OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_a;
ARCHITECTURE c05s02b02x00p08n01i03151arch_c OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_c;
ARCHITECTURE c05s02b02x00p08n01i03151arch_b OF c05s02b02x00p08n01i03151ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03151"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03151arch_b;
--
ENTITY c05s02b02x00p08n01i03151ent IS
END c05s02b02x00p08n01i03151ent;
ARCHITECTURE c05s02b02x00p08n01i03151arch OF c05s02b02x00p08n01i03151ent IS
component c05s02b02x00p08n01i03151ent_a
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03151ent_a;
END c05s02b02x00p08n01i03151arch;
configuration c05s02b02x00p08n01i03151cfg of c05s02b02x00p08n01i03151ent is
for c05s02b02x00p08n01i03151arch
end for;
end c05s02b02x00p08n01i03151cfg;
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