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-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity spi_master is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5); -- for a 100MHz sclk_i, yields a 10MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0) -- parallel output (clocked on rising spi_clk after last bit)
);
end spi_master;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert PREFETCH >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert SPI_2X_CLK_DIV > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
begin
if sclk_i'event and sclk_i = '1' then
if clk_cnt = SPI_2X_CLK_DIV-1 then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_ce_gen_proc;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
core_clock_gen_proc : process (sclk_i) is
begin
if sclk_i'event and sclk_i = '1' then
if spi_2x_ce = '1' then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process core_clock_gen_proc;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc: if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc: if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc: if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc: if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc: if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc: if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
end process rx_bit_proc;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D ) is
begin
if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
begin
-- registered data input, input register with clock enable
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if sclk_i'event and sclk_i = '1' then
if rst_i = '1' then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if sclk_i'event and sclk_i = '1' then
if sck_ena_ce = '1' then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy' and stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_i
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
do_o_proc: do_o <= do_buffer_reg; -- parallel data out
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if sck_ena_reg = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
end architecture rtl;
|
entity FIFO is
end entity FIFO;
entity --Comment
--Comment
--Comment
FIFO is
end entity
FIFO;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_strb_gen2;
use axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_11.axi_datamover_fifo;
use axi_datamover_v5_1_11.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_11.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_11.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shifter is
port(
ib : in std_logic_vector(31 downto 0);
shdir : in std_logic;
shamt : in std_logic_vector(4 downto 0);
q : out std_logic_vector(31 downto 0)
);
end shifter;
architecture behv of shifter is
--function to do the shifting
function barrel_shift(
in_data: in std_logic_vector(31 downto 0);
dir: in std_logic;
count: in std_logic_vector(4 downto 0)) return std_logic_vector is
begin
if (dir = '1') then
return std_logic_vector((shr(unsigned(in_data), unsigned(count))));
else
return std_logic_vector((SHL(unsigned(in_data), unsigned(count))));
end if;
end barrel_shift;
begin
process(ib,shdir,shamt)
begin
q <= barrel_shift(ib, shdir, shamt);
end process;
end behv; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:42:50 01/12/2014
-- Design Name:
-- Module Name: peripherics - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity peripherics is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
TX : out STD_LOGIC;
RX : in STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Address : inout STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : inout STD_LOGIC;
WriteEnable : inout STD_LOGIC;
OutputEnable : inout STD_LOGIC;
Send : in STD_LOGIC;
Ready : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0)
);
end peripherics;
architecture Behavioral of peripherics is
COMPONENT RS232top
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
Data_in : IN std_logic_vector(7 downto 0);
Valid_D : IN std_logic;
RD : IN std_logic;
Data_read : IN std_logic;
Ack_in : OUT std_logic;
TX_RDY : OUT std_logic;
TD : OUT std_logic;
Data_out : OUT std_logic_vector(7 downto 0);
Full : OUT std_logic;
Empty : OUT std_logic
);
END COMPONENT;
COMPONENT dma
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Send : IN std_logic;
DMA_ACK : IN std_logic;
Ack_out : IN std_logic;
TX_RDY : IN std_logic;
RCVD_data : IN std_logic_vector(7 downto 0);
RX_Full : IN std_logic;
RX_empty : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
TX_data : OUT std_logic_vector(7 downto 0);
Valid_D : OUT std_logic;
Data_read : OUT std_logic
);
END COMPONENT;
COMPONENT ram
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
WriteEnable : IN std_logic;
OutputEnable : IN std_logic;
ChipSelect : IN std_logic;
Address : IN std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0);
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_h : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
signal data_in_i, data_out_i :std_logic_vector(7 downto 0);
signal valid_i, ack_i, txready_i, dataread_i : std_logic;
signal empty_i, full_i : std_logic;
begin
RS232: RS232top PORT MAP(
Reset => Reset,
Clk => Clk,
Data_in => data_in_i,
Valid_D => valid_i,
Ack_in => ack_i,
TX_RDY => txready_i,
TD => TX,
RD => RX,
Data_out => data_out_i,
Data_read => dataread_i,
Full => full_i,
Empty => empty_i
);
DMA0: dma PORT MAP(
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
TX_data => data_in_i,
Valid_D => valid_i,
Ack_out => ack_i,
TX_RDY => txready_i,
RCVD_data => data_out_i,
Data_read => dataread_i,
RX_Full => full_i,
RX_empty => empty_i
);
RAM0: ram PORT MAP(
Clk => Clk,
Reset => Reset,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
ChipSelect => ChipSelect,
Address => Address,
Databus => Databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
end Behavioral;
|
-- tb.vhd : FPGA top level testbench
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity testbench is
end entity testbench;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of testbench is
signal smclk : std_logic := '1';
signal ledf : std_logic;
signal p3m : std_logic_vector(7 downto 0) := (others=>'Z');
signal afbus : std_logic_vector(11 downto 0) :=(others =>'Z');
signal xbus : std_logic_vector(45 downto 0) :=(others =>'Z');
signal rdbus : std_logic_vector(7 downto 0) :=(others =>'Z');
signal ldbus : std_logic_vector(7 downto 0) :=(others =>'Z');
signal lrs, lrw, le : std_logic;
signal ispi_clk : std_logic:='1';
signal ispi_cs : std_logic:='1';
signal ispi_di : std_logic:='0';
signal ispi_do : std_logic:='0';
begin
-- ==========================================
-- Top-level entita reprezentujici cele FPGA
-- ==========================================
uut: entity work.fpga
port map(
SMCLK => smclk,
ACLK => '0',
FCLK => '0',
LEDF => ledf,
SPI_CLK => ispi_clk,
SPI_CS => '1',
SPI_FPGA_CS => ispi_cs,
SPI_DI => ispi_di,
SPI_DO => ispi_do,
KIN => open,
KOUT => (others => '0'),
LE => le,
LRW => lrw,
LRS => lrs,
LD => ldbus,
RA => open,
RD => rdbus,
RDQM => open,
RCS => open,
RRAS => open,
RCAS => open,
RWE => open,
RCKE => open,
RCLK => open,
P3M => p3m,
AFBUS => afbus,
X => xbus
);
-- ==========================================
-- LCD display model
-- ==========================================
lcd: entity work.lcd
port map(
LRS => lrs,
LRW => lrw,
LE => le,
LD => ldbus
);
-- ==========================================================================
-- Clock generator 7.4MHz
-- ==========================================================================
smclk <= not smclk after 67.5 ns;
-- ==========================================================================
-- Reset generator
-- ==========================================================================
p3m(0) <= '1', '0' after 500 ns;
-- ==========================================================================
-- SPI clock generator (SMCLK/4)
-- ==========================================================================
ispi_clk <= not ispi_clk after 4*67.5 ns;
end architecture behavioral;
|
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.nexys4_pack.all;
use work.plasoc_interconnect_crossbar_wrap_pack.plasoc_interconnect_crossbar_wrap;
use work.plasoc_interconnect_crossbar_wrap_pack.clogb2;
use work.plasoc_cpu_0_crossbar_wrap_pack.plasoc_cpu_0_crossbar_wrap;
use work.plasoc_cpu_1_crossbar_wrap_pack.plasoc_cpu_1_crossbar_wrap;
use work.plasoc_cpu_2_crossbar_wrap_pack.plasoc_cpu_2_crossbar_wrap;
use work.plasoc_cpu_pack.plasoc_cpu;
use work.plasoc_int_pack.plasoc_int;
use work.plasoc_int_pack.default_interrupt_total;
use work.plasoc_timer_pack.plasoc_timer;
use work.plasoc_gpio_pack.plasoc_gpio;
use work.plasoc_uart_pack.plasoc_uart;
use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite;
use work.koc_lock_pack.koc_lock;
use work.koc_signal_pack.koc_signal;
entity koc_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "none";
upper_ext : boolean := true);
port (
sys_clk_i : in std_logic;
sys_rst : in std_logic;
gpio_output : out std_logic_vector(data_out_width-1 downto 0);
gpio_input : in std_logic_vector(data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end koc_wrapper;
architecture Behavioral of koc_wrapper is
----------------------------
-- Component Declarations --
----------------------------
component bd_wrapper is
port (
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
aclk : out STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_i : in STD_LOGIC;
sys_rst : in STD_LOGIC);
end component;
component bram is
generic (
select_app : string := "none"; -- jump, boot, main
address_width : integer := 18;
data_width : integer := 32;
bram_depth : integer := 65536);
port(
bram_rst_a : in std_logic;
bram_clk_a : in std_logic;
bram_en_a : in std_logic;
bram_we_a : in std_logic_vector(data_width/8-1 downto 0);
bram_addr_a : in std_logic_vector(address_width-1 downto 0);
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0);
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0'));
end component;
component axi_bram_ctrl_0 IS
port (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component clk_wiz_0
port (
aclk : out std_logic;
resetn : in std_logic;
locked : out std_logic;
sys_clk_i : in std_logic);
end component;
component proc_sys_reset_0 is
port (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
end component;
constant axi_cpu_bus_slave_amount : integer := 1;
constant axi_cpu_bus_slave_id_width : integer := 0;
constant axi_cpu_bus_master_id_width : integer := clogb2(axi_cpu_bus_slave_amount)+axi_cpu_bus_slave_id_width;
constant axi_slave_amount : integer := 3;
constant axi_slave_id_width : integer := axi_cpu_bus_master_id_width;
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
constant axi_address_width : integer := 32;
constant axi_address_periph_width : integer := 16;
constant axi_data_width : integer := 32;
constant bram_address_width : integer := 16;
constant bram_data_width : integer := axi_data_width;
constant bram_bram_depth : integer := 16384;
signal aclk : std_logic;
signal interconnect_aresetn : std_logic_vector(0 downto 0);
signal peripheral_aresetn : std_logic_vector(0 downto 0);
signal dcm_locked : std_logic;
signal ram_bram_rst_a : std_logic;
signal ram_bram_clk_a : std_logic;
signal ram_bram_en_a : std_logic;
signal ram_bram_we_a : std_logic_vector(3 downto 0);
signal ram_bram_addr_a : std_logic_vector(15 downto 0);
signal ram_bram_wrdata_a : std_logic_vector(31 downto 0);
signal ram_bram_rddata_a : std_logic_vector(31 downto 0);
signal boot_bram_rst_a : std_logic;
signal boot_bram_clk_a : std_logic;
signal boot_bram_en_a : std_logic;
signal boot_bram_we_a : std_logic_vector(3 downto 0);
signal boot_bram_addr_a : std_logic_vector(15 downto 0);
signal boot_bram_wrdata_a : std_logic_vector(31 downto 0);
signal boot_bram_rddata_a : std_logic_vector(31 downto 0);
-------------------------------
-- Main Interconnect Signals --
-------------------------------
signal cpu_0_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_0_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_0_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_awlock : std_logic;
signal cpu_0_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awvalid : std_logic;
signal cpu_0_axi_full_awready : std_logic;
signal cpu_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_0_axi_full_wlast : std_logic;
signal cpu_0_axi_full_wvalid : std_logic;
signal cpu_0_axi_full_wready : std_logic;
signal cpu_0_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_bvalid : std_logic;
signal cpu_0_axi_full_bready : std_logic;
signal cpu_0_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_0_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_0_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_arlock : std_logic;
signal cpu_0_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arvalid : std_logic;
signal cpu_0_axi_full_arready : std_logic;
signal cpu_0_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_0_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_rlast : std_logic;
signal cpu_0_axi_full_rvalid : std_logic;
signal cpu_0_axi_full_rready : std_logic;
signal cpu_1_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_1_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_1_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_awlock : std_logic;
signal cpu_1_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awvalid : std_logic;
signal cpu_1_axi_full_awready : std_logic;
signal cpu_1_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_1_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_1_axi_full_wlast : std_logic;
signal cpu_1_axi_full_wvalid : std_logic;
signal cpu_1_axi_full_wready : std_logic;
signal cpu_1_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_bvalid : std_logic;
signal cpu_1_axi_full_bready : std_logic;
signal cpu_1_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_1_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_1_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_arlock : std_logic;
signal cpu_1_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arvalid : std_logic;
signal cpu_1_axi_full_arready : std_logic;
signal cpu_1_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_1_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_rlast : std_logic;
signal cpu_1_axi_full_rvalid : std_logic;
signal cpu_1_axi_full_rready : std_logic;
signal cpu_2_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_2_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_2_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_awlock : std_logic;
signal cpu_2_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awvalid : std_logic;
signal cpu_2_axi_full_awready : std_logic;
signal cpu_2_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_2_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_2_axi_full_wlast : std_logic;
signal cpu_2_axi_full_wvalid : std_logic;
signal cpu_2_axi_full_wready : std_logic;
signal cpu_2_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_bvalid : std_logic;
signal cpu_2_axi_full_bready : std_logic;
signal cpu_2_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_2_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_2_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_arlock : std_logic;
signal cpu_2_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arvalid : std_logic;
signal cpu_2_axi_full_arready : std_logic;
signal cpu_2_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_2_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_rlast : std_logic;
signal cpu_2_axi_full_rvalid : std_logic;
signal cpu_2_axi_full_rready : std_logic;
signal boot_bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal boot_bram_axi_full_awlen : std_logic_vector(7 downto 0);
signal boot_bram_axi_full_awsize : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_awburst : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_awlock : std_logic;
signal boot_bram_axi_full_awcache : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awprot : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_awqos : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awregion : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awvalid : std_logic;
signal boot_bram_axi_full_awready : std_logic;
signal boot_bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal boot_bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal boot_bram_axi_full_wlast : std_logic;
signal boot_bram_axi_full_wvalid : std_logic;
signal boot_bram_axi_full_wready : std_logic;
signal boot_bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_bresp : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_bvalid : std_logic;
signal boot_bram_axi_full_bready : std_logic;
signal boot_bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal boot_bram_axi_full_arlen : std_logic_vector(7 downto 0);
signal boot_bram_axi_full_arsize : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_arburst : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_arlock : std_logic;
signal boot_bram_axi_full_arcache : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arprot : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_arqos : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arregion : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arvalid : std_logic;
signal boot_bram_axi_full_arready : std_logic;
signal boot_bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal boot_bram_axi_full_rresp : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_rlast : std_logic;
signal boot_bram_axi_full_rvalid : std_logic;
signal boot_bram_axi_full_rready : std_logic;
signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_awid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
signal ram_axi_full_awlen : std_logic_vector(7 downto 0);
signal ram_axi_full_awsize : std_logic_vector(2 downto 0);
signal ram_axi_full_awburst : std_logic_vector(1 downto 0);
signal ram_axi_full_awlock : std_logic;
signal ram_axi_full_awlock_slv : std_logic_vector(0 downto 0);
signal ram_axi_full_awcache : std_logic_vector(3 downto 0);
signal ram_axi_full_awprot : std_logic_vector(2 downto 0);
signal ram_axi_full_awqos : std_logic_vector(3 downto 0);
signal ram_axi_full_awregion : std_logic_vector(3 downto 0);
signal ram_axi_full_awvalid : std_logic;
signal ram_axi_full_awready : std_logic;
signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_axi_full_wlast : std_logic;
signal ram_axi_full_wvalid : std_logic;
signal ram_axi_full_wready : std_logic;
signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_bid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_bresp : std_logic_vector(1 downto 0);
signal ram_axi_full_bvalid : std_logic;
signal ram_axi_full_bready : std_logic;
signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_arid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
signal ram_axi_full_arlen : std_logic_vector(7 downto 0);
signal ram_axi_full_arsize : std_logic_vector(2 downto 0);
signal ram_axi_full_arburst : std_logic_vector(1 downto 0);
signal ram_axi_full_arlock : std_logic;
signal ram_axi_full_arlock_slv : std_logic_vector(0 downto 0);
signal ram_axi_full_arcache : std_logic_vector(3 downto 0);
signal ram_axi_full_arprot : std_logic_vector(2 downto 0);
signal ram_axi_full_arqos : std_logic_vector(3 downto 0);
signal ram_axi_full_arregion : std_logic_vector(3 downto 0);
signal ram_axi_full_arvalid : std_logic;
signal ram_axi_full_arready : std_logic;
signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_rid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_rresp : std_logic_vector(1 downto 0);
signal ram_axi_full_rlast : std_logic;
signal ram_axi_full_rvalid : std_logic;
signal ram_axi_full_rready : std_logic;
signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_awlen : std_logic_vector(7 downto 0);
signal int_axi_full_awsize : std_logic_vector(2 downto 0);
signal int_axi_full_awburst : std_logic_vector(1 downto 0);
signal int_axi_full_awlock : std_logic;
signal int_axi_full_awcache : std_logic_vector(3 downto 0);
signal int_axi_full_awprot : std_logic_vector(2 downto 0);
signal int_axi_full_awqos : std_logic_vector(3 downto 0);
signal int_axi_full_awregion : std_logic_vector(3 downto 0);
signal int_axi_full_awvalid : std_logic;
signal int_axi_full_awready : std_logic;
signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_full_wlast : std_logic;
signal int_axi_full_wvalid : std_logic;
signal int_axi_full_wready : std_logic;
signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_bresp : std_logic_vector(1 downto 0);
signal int_axi_full_bvalid : std_logic;
signal int_axi_full_bready : std_logic;
signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_arlen : std_logic_vector(7 downto 0);
signal int_axi_full_arsize : std_logic_vector(2 downto 0);
signal int_axi_full_arburst : std_logic_vector(1 downto 0);
signal int_axi_full_arlock : std_logic;
signal int_axi_full_arcache : std_logic_vector(3 downto 0);
signal int_axi_full_arprot : std_logic_vector(2 downto 0);
signal int_axi_full_arqos : std_logic_vector(3 downto 0);
signal int_axi_full_arregion : std_logic_vector(3 downto 0);
signal int_axi_full_arvalid : std_logic;
signal int_axi_full_arready : std_logic;
signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_rresp : std_logic_vector(1 downto 0);
signal int_axi_full_rlast : std_logic;
signal int_axi_full_rvalid : std_logic;
signal int_axi_full_rready : std_logic;
signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_axi_full_awlock : std_logic;
signal timer_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_axi_full_awvalid : std_logic;
signal timer_axi_full_awready : std_logic;
signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_full_wlast : std_logic;
signal timer_axi_full_wvalid : std_logic;
signal timer_axi_full_wready : std_logic;
signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_axi_full_bvalid : std_logic;
signal timer_axi_full_bready : std_logic;
signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_axi_full_arlock : std_logic;
signal timer_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_axi_full_arvalid : std_logic;
signal timer_axi_full_arready : std_logic;
signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_axi_full_rlast : std_logic;
signal timer_axi_full_rvalid : std_logic;
signal timer_axi_full_rready : std_logic;
signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_awlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_awsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_awburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_awlock : std_logic;
signal gpio_axi_full_awcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_awqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_awregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_awvalid : std_logic;
signal gpio_axi_full_awready : std_logic;
signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_full_wlast : std_logic;
signal gpio_axi_full_wvalid : std_logic;
signal gpio_axi_full_wready : std_logic;
signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_bvalid : std_logic;
signal gpio_axi_full_bready : std_logic;
signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_arlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_arsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_arburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_arlock : std_logic;
signal gpio_axi_full_arcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_arqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_arregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_arvalid : std_logic;
signal gpio_axi_full_arready : std_logic;
signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_rlast : std_logic;
signal gpio_axi_full_rvalid : std_logic;
signal gpio_axi_full_rready : std_logic;
signal uart_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_awlen : std_logic_vector(7 downto 0);
signal uart_axi_full_awsize : std_logic_vector(2 downto 0);
signal uart_axi_full_awburst : std_logic_vector(1 downto 0);
signal uart_axi_full_awlock : std_logic;
signal uart_axi_full_awcache : std_logic_vector(3 downto 0);
signal uart_axi_full_awprot : std_logic_vector(2 downto 0);
signal uart_axi_full_awqos : std_logic_vector(3 downto 0);
signal uart_axi_full_awregion : std_logic_vector(3 downto 0);
signal uart_axi_full_awvalid : std_logic;
signal uart_axi_full_awready : std_logic;
signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_full_wlast : std_logic;
signal uart_axi_full_wvalid : std_logic;
signal uart_axi_full_wready : std_logic;
signal uart_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_bresp : std_logic_vector(1 downto 0);
signal uart_axi_full_bvalid : std_logic;
signal uart_axi_full_bready : std_logic;
signal uart_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_arlen : std_logic_vector(7 downto 0);
signal uart_axi_full_arsize : std_logic_vector(2 downto 0);
signal uart_axi_full_arburst : std_logic_vector(1 downto 0);
signal uart_axi_full_arlock : std_logic;
signal uart_axi_full_arcache : std_logic_vector(3 downto 0);
signal uart_axi_full_arprot : std_logic_vector(2 downto 0);
signal uart_axi_full_arqos : std_logic_vector(3 downto 0);
signal uart_axi_full_arregion : std_logic_vector(3 downto 0);
signal uart_axi_full_arvalid : std_logic;
signal uart_axi_full_arready : std_logic;
signal uart_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_rresp : std_logic_vector(1 downto 0);
signal uart_axi_full_rlast : std_logic;
signal uart_axi_full_rvalid : std_logic;
signal uart_axi_full_rready : std_logic;
signal lock_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_full_awlen : std_logic_vector(7 downto 0);
signal lock_axi_full_awsize : std_logic_vector(2 downto 0);
signal lock_axi_full_awburst : std_logic_vector(1 downto 0);
signal lock_axi_full_awlock : std_logic;
signal lock_axi_full_awcache : std_logic_vector(3 downto 0);
signal lock_axi_full_awprot : std_logic_vector(2 downto 0);
signal lock_axi_full_awqos : std_logic_vector(3 downto 0);
signal lock_axi_full_awregion : std_logic_vector(3 downto 0);
signal lock_axi_full_awvalid : std_logic;
signal lock_axi_full_awready : std_logic;
signal lock_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal lock_axi_full_wlast : std_logic;
signal lock_axi_full_wvalid : std_logic;
signal lock_axi_full_wready : std_logic;
signal lock_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_bresp : std_logic_vector(1 downto 0);
signal lock_axi_full_bvalid : std_logic;
signal lock_axi_full_bready : std_logic;
signal lock_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_full_arlen : std_logic_vector(7 downto 0);
signal lock_axi_full_arsize : std_logic_vector(2 downto 0);
signal lock_axi_full_arburst : std_logic_vector(1 downto 0);
signal lock_axi_full_arlock : std_logic;
signal lock_axi_full_arcache : std_logic_vector(3 downto 0);
signal lock_axi_full_arprot : std_logic_vector(2 downto 0);
signal lock_axi_full_arqos : std_logic_vector(3 downto 0);
signal lock_axi_full_arregion : std_logic_vector(3 downto 0);
signal lock_axi_full_arvalid : std_logic;
signal lock_axi_full_arready : std_logic;
signal lock_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_full_rresp : std_logic_vector(1 downto 0);
signal lock_axi_full_rlast : std_logic;
signal lock_axi_full_rvalid : std_logic;
signal lock_axi_full_rready : std_logic;
---------------------
-- CPU Bus Signals --
---------------------
signal cpu_bus_0_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_awlock : std_logic;
signal cpu_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awvalid : std_logic;
signal cpu_bus_0_full_awready : std_logic;
signal cpu_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_0_full_wlast : std_logic;
signal cpu_bus_0_full_wvalid : std_logic;
signal cpu_bus_0_full_wready : std_logic;
signal cpu_bus_0_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_bvalid : std_logic;
signal cpu_bus_0_full_bready : std_logic;
signal cpu_bus_0_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_arlock : std_logic;
signal cpu_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arvalid : std_logic;
signal cpu_bus_0_full_arready : std_logic;
signal cpu_bus_0_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_rlast : std_logic;
signal cpu_bus_0_full_rvalid : std_logic;
signal cpu_bus_0_full_rready : std_logic;
signal cpuid_gpio_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_awlock : std_logic;
signal cpuid_gpio_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awvalid : std_logic;
signal cpuid_gpio_bus_0_full_awready : std_logic;
signal cpuid_gpio_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_0_full_wlast : std_logic;
signal cpuid_gpio_bus_0_full_wvalid : std_logic;
signal cpuid_gpio_bus_0_full_wready : std_logic;
signal cpuid_gpio_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_bvalid : std_logic;
signal cpuid_gpio_bus_0_full_bready : std_logic;
signal cpuid_gpio_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_arlock : std_logic;
signal cpuid_gpio_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arvalid : std_logic;
signal cpuid_gpio_bus_0_full_arready : std_logic;
signal cpuid_gpio_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_rlast : std_logic;
signal cpuid_gpio_bus_0_full_rvalid : std_logic;
signal cpuid_gpio_bus_0_full_rready : std_logic;
signal int_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_0_full_awlock : std_logic;
signal int_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_0_full_awvalid : std_logic;
signal int_bus_0_full_awready : std_logic;
signal int_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_0_full_wlast : std_logic;
signal int_bus_0_full_wvalid : std_logic;
signal int_bus_0_full_wready : std_logic;
signal int_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_0_full_bvalid : std_logic;
signal int_bus_0_full_bready : std_logic;
signal int_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_0_full_arlock : std_logic;
signal int_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_0_full_arvalid : std_logic;
signal int_bus_0_full_arready : std_logic;
signal int_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_0_full_rlast : std_logic;
signal int_bus_0_full_rvalid : std_logic;
signal int_bus_0_full_rready : std_logic;
signal signal_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_0_full_awlock : std_logic;
signal signal_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awvalid : std_logic;
signal signal_bus_0_full_awready : std_logic;
signal signal_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_0_full_wlast : std_logic;
signal signal_bus_0_full_wvalid : std_logic;
signal signal_bus_0_full_wready : std_logic;
signal signal_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_0_full_bvalid : std_logic;
signal signal_bus_0_full_bready : std_logic;
signal signal_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_0_full_arlock : std_logic;
signal signal_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arvalid : std_logic;
signal signal_bus_0_full_arready : std_logic;
signal signal_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_0_full_rlast : std_logic;
signal signal_bus_0_full_rvalid : std_logic;
signal signal_bus_0_full_rready : std_logic;
signal timer_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_0_full_awlock : std_logic;
signal timer_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awvalid : std_logic;
signal timer_bus_0_full_awready : std_logic;
signal timer_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_0_full_wlast : std_logic;
signal timer_bus_0_full_wvalid : std_logic;
signal timer_bus_0_full_wready : std_logic;
signal timer_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_0_full_bvalid : std_logic;
signal timer_bus_0_full_bready : std_logic;
signal timer_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_0_full_arlock : std_logic;
signal timer_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arvalid : std_logic;
signal timer_bus_0_full_arready : std_logic;
signal timer_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_0_full_rlast : std_logic;
signal timer_bus_0_full_rvalid : std_logic;
signal timer_bus_0_full_rready : std_logic;
signal cpu_bus_1_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_awlock : std_logic;
signal cpu_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awvalid : std_logic;
signal cpu_bus_1_full_awready : std_logic;
signal cpu_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_1_full_wlast : std_logic;
signal cpu_bus_1_full_wvalid : std_logic;
signal cpu_bus_1_full_wready : std_logic;
signal cpu_bus_1_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_bvalid : std_logic;
signal cpu_bus_1_full_bready : std_logic;
signal cpu_bus_1_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_arlock : std_logic;
signal cpu_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arvalid : std_logic;
signal cpu_bus_1_full_arready : std_logic;
signal cpu_bus_1_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_rlast : std_logic;
signal cpu_bus_1_full_rvalid : std_logic;
signal cpu_bus_1_full_rready : std_logic;
signal cpuid_gpio_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_awlock : std_logic;
signal cpuid_gpio_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awvalid : std_logic;
signal cpuid_gpio_bus_1_full_awready : std_logic;
signal cpuid_gpio_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_1_full_wlast : std_logic;
signal cpuid_gpio_bus_1_full_wvalid : std_logic;
signal cpuid_gpio_bus_1_full_wready : std_logic;
signal cpuid_gpio_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_bvalid : std_logic;
signal cpuid_gpio_bus_1_full_bready : std_logic;
signal cpuid_gpio_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_arlock : std_logic;
signal cpuid_gpio_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arvalid : std_logic;
signal cpuid_gpio_bus_1_full_arready : std_logic;
signal cpuid_gpio_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_rlast : std_logic;
signal cpuid_gpio_bus_1_full_rvalid : std_logic;
signal cpuid_gpio_bus_1_full_rready : std_logic;
signal int_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_1_full_awlock : std_logic;
signal int_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_1_full_awvalid : std_logic;
signal int_bus_1_full_awready : std_logic;
signal int_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_1_full_wlast : std_logic;
signal int_bus_1_full_wvalid : std_logic;
signal int_bus_1_full_wready : std_logic;
signal int_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_1_full_bvalid : std_logic;
signal int_bus_1_full_bready : std_logic;
signal int_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_1_full_arlock : std_logic;
signal int_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_1_full_arvalid : std_logic;
signal int_bus_1_full_arready : std_logic;
signal int_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_1_full_rlast : std_logic;
signal int_bus_1_full_rvalid : std_logic;
signal int_bus_1_full_rready : std_logic;
signal signal_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_1_full_awlock : std_logic;
signal signal_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awvalid : std_logic;
signal signal_bus_1_full_awready : std_logic;
signal signal_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_1_full_wlast : std_logic;
signal signal_bus_1_full_wvalid : std_logic;
signal signal_bus_1_full_wready : std_logic;
signal signal_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_1_full_bvalid : std_logic;
signal signal_bus_1_full_bready : std_logic;
signal signal_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_1_full_arlock : std_logic;
signal signal_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arvalid : std_logic;
signal signal_bus_1_full_arready : std_logic;
signal signal_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_1_full_rlast : std_logic;
signal signal_bus_1_full_rvalid : std_logic;
signal signal_bus_1_full_rready : std_logic;
signal timer_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_1_full_awlock : std_logic;
signal timer_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awvalid : std_logic;
signal timer_bus_1_full_awready : std_logic;
signal timer_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_1_full_wlast : std_logic;
signal timer_bus_1_full_wvalid : std_logic;
signal timer_bus_1_full_wready : std_logic;
signal timer_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_1_full_bvalid : std_logic;
signal timer_bus_1_full_bready : std_logic;
signal timer_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_1_full_arlock : std_logic;
signal timer_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arvalid : std_logic;
signal timer_bus_1_full_arready : std_logic;
signal timer_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_1_full_rlast : std_logic;
signal timer_bus_1_full_rvalid : std_logic;
signal timer_bus_1_full_rready : std_logic;
signal cpu_bus_2_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_awlock : std_logic;
signal cpu_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awvalid : std_logic;
signal cpu_bus_2_full_awready : std_logic;
signal cpu_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_2_full_wlast : std_logic;
signal cpu_bus_2_full_wvalid : std_logic;
signal cpu_bus_2_full_wready : std_logic;
signal cpu_bus_2_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_bvalid : std_logic;
signal cpu_bus_2_full_bready : std_logic;
signal cpu_bus_2_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_arlock : std_logic;
signal cpu_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arvalid : std_logic;
signal cpu_bus_2_full_arready : std_logic;
signal cpu_bus_2_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_rlast : std_logic;
signal cpu_bus_2_full_rvalid : std_logic;
signal cpu_bus_2_full_rready : std_logic;
signal cpuid_gpio_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_awlock : std_logic;
signal cpuid_gpio_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awvalid : std_logic;
signal cpuid_gpio_bus_2_full_awready : std_logic;
signal cpuid_gpio_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_2_full_wlast : std_logic;
signal cpuid_gpio_bus_2_full_wvalid : std_logic;
signal cpuid_gpio_bus_2_full_wready : std_logic;
signal cpuid_gpio_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_bvalid : std_logic;
signal cpuid_gpio_bus_2_full_bready : std_logic;
signal cpuid_gpio_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_arlock : std_logic;
signal cpuid_gpio_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arvalid : std_logic;
signal cpuid_gpio_bus_2_full_arready : std_logic;
signal cpuid_gpio_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_rlast : std_logic;
signal cpuid_gpio_bus_2_full_rvalid : std_logic;
signal cpuid_gpio_bus_2_full_rready : std_logic;
signal int_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_2_full_awlock : std_logic;
signal int_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_2_full_awvalid : std_logic;
signal int_bus_2_full_awready : std_logic;
signal int_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_2_full_wlast : std_logic;
signal int_bus_2_full_wvalid : std_logic;
signal int_bus_2_full_wready : std_logic;
signal int_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_2_full_bvalid : std_logic;
signal int_bus_2_full_bready : std_logic;
signal int_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_2_full_arlock : std_logic;
signal int_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_2_full_arvalid : std_logic;
signal int_bus_2_full_arready : std_logic;
signal int_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_2_full_rlast : std_logic;
signal int_bus_2_full_rvalid : std_logic;
signal int_bus_2_full_rready : std_logic;
signal signal_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_2_full_awlock : std_logic;
signal signal_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awvalid : std_logic;
signal signal_bus_2_full_awready : std_logic;
signal signal_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_2_full_wlast : std_logic;
signal signal_bus_2_full_wvalid : std_logic;
signal signal_bus_2_full_wready : std_logic;
signal signal_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_2_full_bvalid : std_logic;
signal signal_bus_2_full_bready : std_logic;
signal signal_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_2_full_arlock : std_logic;
signal signal_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arvalid : std_logic;
signal signal_bus_2_full_arready : std_logic;
signal signal_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_2_full_rlast : std_logic;
signal signal_bus_2_full_rvalid : std_logic;
signal signal_bus_2_full_rready : std_logic;
signal timer_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_2_full_awlock : std_logic;
signal timer_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awvalid : std_logic;
signal timer_bus_2_full_awready : std_logic;
signal timer_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_2_full_wlast : std_logic;
signal timer_bus_2_full_wvalid : std_logic;
signal timer_bus_2_full_wready : std_logic;
signal timer_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_2_full_bvalid : std_logic;
signal timer_bus_2_full_bready : std_logic;
signal timer_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_2_full_arlock : std_logic;
signal timer_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arvalid : std_logic;
signal timer_bus_2_full_arready : std_logic;
signal timer_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_2_full_rlast : std_logic;
signal timer_bus_2_full_rvalid : std_logic;
signal timer_bus_2_full_rready : std_logic;
--------------------------------------
-- CPUID GPIO AXI Full2Lite Signals --
--------------------------------------
signal cpuid_gpio_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_lite_awvalid : std_logic;
signal cpuid_gpio_bus_0_lite_awready : std_logic;
signal cpuid_gpio_bus_0_lite_wvalid : std_logic;
signal cpuid_gpio_bus_0_lite_wready : std_logic;
signal cpuid_gpio_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_0_lite_bvalid : std_logic;
signal cpuid_gpio_bus_0_lite_bready : std_logic;
signal cpuid_gpio_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_lite_arvalid : std_logic;
signal cpuid_gpio_bus_0_lite_arready : std_logic;
signal cpuid_gpio_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_rvalid : std_logic;
signal cpuid_gpio_bus_0_lite_rready : std_logic;
signal cpuid_gpio_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_lite_awvalid : std_logic;
signal cpuid_gpio_bus_1_lite_awready : std_logic;
signal cpuid_gpio_bus_1_lite_wvalid : std_logic;
signal cpuid_gpio_bus_1_lite_wready : std_logic;
signal cpuid_gpio_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_1_lite_bvalid : std_logic;
signal cpuid_gpio_bus_1_lite_bready : std_logic;
signal cpuid_gpio_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_lite_arvalid : std_logic;
signal cpuid_gpio_bus_1_lite_arready : std_logic;
signal cpuid_gpio_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_rvalid : std_logic;
signal cpuid_gpio_bus_1_lite_rready : std_logic;
signal cpuid_gpio_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_lite_awvalid : std_logic;
signal cpuid_gpio_bus_2_lite_awready : std_logic;
signal cpuid_gpio_bus_2_lite_wvalid : std_logic;
signal cpuid_gpio_bus_2_lite_wready : std_logic;
signal cpuid_gpio_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_2_lite_bvalid : std_logic;
signal cpuid_gpio_bus_2_lite_bready : std_logic;
signal cpuid_gpio_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_lite_arvalid : std_logic;
signal cpuid_gpio_bus_2_lite_arready : std_logic;
signal cpuid_gpio_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_rvalid : std_logic;
signal cpuid_gpio_bus_2_lite_rready : std_logic;
signal cpuid_gpio_bus_2_lite_rresp : std_logic_vector(1 downto 0);
-----------------------------------
-- CPU INT AXI Full2Lite Signals --
-----------------------------------
signal int_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_0_lite_awvalid : std_logic;
signal int_bus_0_lite_awready : std_logic;
signal int_bus_0_lite_wvalid : std_logic;
signal int_bus_0_lite_wready : std_logic;
signal int_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_0_lite_bvalid : std_logic;
signal int_bus_0_lite_bready : std_logic;
signal int_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_0_lite_arvalid : std_logic;
signal int_bus_0_lite_arready : std_logic;
signal int_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_lite_rvalid : std_logic;
signal int_bus_0_lite_rready : std_logic;
signal int_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal int_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_1_lite_awvalid : std_logic;
signal int_bus_1_lite_awready : std_logic;
signal int_bus_1_lite_wvalid : std_logic;
signal int_bus_1_lite_wready : std_logic;
signal int_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_1_lite_bvalid : std_logic;
signal int_bus_1_lite_bready : std_logic;
signal int_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_1_lite_arvalid : std_logic;
signal int_bus_1_lite_arready : std_logic;
signal int_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_lite_rvalid : std_logic;
signal int_bus_1_lite_rready : std_logic;
signal int_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal int_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_2_lite_awvalid : std_logic;
signal int_bus_2_lite_awready : std_logic;
signal int_bus_2_lite_wvalid : std_logic;
signal int_bus_2_lite_wready : std_logic;
signal int_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_2_lite_bvalid : std_logic;
signal int_bus_2_lite_bready : std_logic;
signal int_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_2_lite_arvalid : std_logic;
signal int_bus_2_lite_arready : std_logic;
signal int_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_lite_rvalid : std_logic;
signal int_bus_2_lite_rready : std_logic;
signal int_bus_2_lite_rresp : std_logic_vector(1 downto 0);
--------------------------------------
-- CPU Signal AXI Full2Lite Signals --
--------------------------------------
signal signal_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_0_lite_awvalid : std_logic;
signal signal_bus_0_lite_awready : std_logic;
signal signal_bus_0_lite_wvalid : std_logic;
signal signal_bus_0_lite_wready : std_logic;
signal signal_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_0_lite_bvalid : std_logic;
signal signal_bus_0_lite_bready : std_logic;
signal signal_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_0_lite_arvalid : std_logic;
signal signal_bus_0_lite_arready : std_logic;
signal signal_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_lite_rvalid : std_logic;
signal signal_bus_0_lite_rready : std_logic;
signal signal_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal signal_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_1_lite_awvalid : std_logic;
signal signal_bus_1_lite_awready : std_logic;
signal signal_bus_1_lite_wvalid : std_logic;
signal signal_bus_1_lite_wready : std_logic;
signal signal_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_1_lite_bvalid : std_logic;
signal signal_bus_1_lite_bready : std_logic;
signal signal_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_1_lite_arvalid : std_logic;
signal signal_bus_1_lite_arready : std_logic;
signal signal_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_lite_rvalid : std_logic;
signal signal_bus_1_lite_rready : std_logic;
signal signal_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal signal_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_2_lite_awvalid : std_logic;
signal signal_bus_2_lite_awready : std_logic;
signal signal_bus_2_lite_wvalid : std_logic;
signal signal_bus_2_lite_wready : std_logic;
signal signal_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_2_lite_bvalid : std_logic;
signal signal_bus_2_lite_bready : std_logic;
signal signal_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_2_lite_arvalid : std_logic;
signal signal_bus_2_lite_arready : std_logic;
signal signal_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_lite_rvalid : std_logic;
signal signal_bus_2_lite_rready : std_logic;
signal signal_bus_2_lite_rresp : std_logic_vector(1 downto 0);
-------------------------------------
-- CPU Timer AXI Full2Lite Signals --
-------------------------------------
signal timer_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_0_lite_awvalid : std_logic;
signal timer_bus_0_lite_awready : std_logic;
signal timer_bus_0_lite_wvalid : std_logic;
signal timer_bus_0_lite_wready : std_logic;
signal timer_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_0_lite_bvalid : std_logic;
signal timer_bus_0_lite_bready : std_logic;
signal timer_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_0_lite_arvalid : std_logic;
signal timer_bus_0_lite_arready : std_logic;
signal timer_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_lite_rvalid : std_logic;
signal timer_bus_0_lite_rready : std_logic;
signal timer_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal timer_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_1_lite_awvalid : std_logic;
signal timer_bus_1_lite_awready : std_logic;
signal timer_bus_1_lite_wvalid : std_logic;
signal timer_bus_1_lite_wready : std_logic;
signal timer_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_1_lite_bvalid : std_logic;
signal timer_bus_1_lite_bready : std_logic;
signal timer_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_1_lite_arvalid : std_logic;
signal timer_bus_1_lite_arready : std_logic;
signal timer_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_lite_rvalid : std_logic;
signal timer_bus_1_lite_rready : std_logic;
signal timer_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal timer_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_2_lite_awvalid : std_logic;
signal timer_bus_2_lite_awready : std_logic;
signal timer_bus_2_lite_wvalid : std_logic;
signal timer_bus_2_lite_wready : std_logic;
signal timer_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_2_lite_bvalid : std_logic;
signal timer_bus_2_lite_bready : std_logic;
signal timer_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_2_lite_arvalid : std_logic;
signal timer_bus_2_lite_arready : std_logic;
signal timer_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_lite_rvalid : std_logic;
signal timer_bus_2_lite_rready : std_logic;
signal timer_bus_2_lite_rresp : std_logic_vector(1 downto 0);
---------------------------------------------
-- Main Interconnect AXI Full2Lite Signals --
---------------------------------------------
signal int_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_lite_awprot : std_logic_vector(2 downto 0);
signal int_axi_lite_awvalid : std_logic;
signal int_axi_lite_awready : std_logic;
signal int_axi_lite_wvalid : std_logic;
signal int_axi_lite_wready : std_logic;
signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_lite_bvalid : std_logic;
signal int_axi_lite_bready : std_logic;
signal int_axi_lite_bresp : std_logic_vector(1 downto 0);
signal int_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_lite_arprot : std_logic_vector(2 downto 0);
signal int_axi_lite_arvalid : std_logic;
signal int_axi_lite_arready : std_logic;
signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_rvalid : std_logic;
signal int_axi_lite_rready : std_logic;
signal int_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_awvalid : std_logic;
signal timer_axi_lite_awready : std_logic;
signal timer_axi_lite_wvalid : std_logic;
signal timer_axi_lite_wready : std_logic;
signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_lite_bvalid : std_logic;
signal timer_axi_lite_bready : std_logic;
signal timer_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_arvalid : std_logic;
signal timer_axi_lite_arready : std_logic;
signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_rvalid : std_logic;
signal timer_axi_lite_rready : std_logic;
signal timer_axi_lite_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_awvalid : std_logic;
signal gpio_axi_lite_awready : std_logic;
signal gpio_axi_lite_wvalid : std_logic;
signal gpio_axi_lite_wready : std_logic;
signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_lite_bvalid : std_logic;
signal gpio_axi_lite_bready : std_logic;
signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_arvalid : std_logic;
signal gpio_axi_lite_arready : std_logic;
signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_rvalid : std_logic;
signal gpio_axi_lite_rready : std_logic;
signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_lite_awprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_awvalid : std_logic;
signal uart_axi_lite_awready : std_logic;
signal uart_axi_lite_wvalid : std_logic;
signal uart_axi_lite_wready : std_logic;
signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_lite_bvalid : std_logic;
signal uart_axi_lite_bready : std_logic;
signal uart_axi_lite_bresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_lite_arprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_arvalid : std_logic;
signal uart_axi_lite_arready : std_logic;
signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_rvalid : std_logic;
signal uart_axi_lite_rready : std_logic;
signal uart_axi_lite_rresp : std_logic_vector(1 downto 0);
signal lock_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_lite_awprot : std_logic_vector(2 downto 0);
signal lock_axi_lite_awvalid : std_logic;
signal lock_axi_lite_awready : std_logic;
signal lock_axi_lite_wvalid : std_logic;
signal lock_axi_lite_wready : std_logic;
signal lock_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal lock_axi_lite_bvalid : std_logic;
signal lock_axi_lite_bready : std_logic;
signal lock_axi_lite_bresp : std_logic_vector(1 downto 0);
signal lock_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_lite_arprot : std_logic_vector(2 downto 0);
signal lock_axi_lite_arvalid : std_logic;
signal lock_axi_lite_arready : std_logic;
signal lock_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_lite_rvalid : std_logic;
signal lock_axi_lite_rready : std_logic;
signal lock_axi_lite_rresp : std_logic_vector(1 downto 0);
------------------------
-- Peripheral Signals --
------------------------
signal cpu_int : std_logic;
signal dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_0_int : std_logic;
signal dev_0_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_1_int : std_logic;
signal dev_1_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_2_int : std_logic;
signal dev_2_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal sig_0_1 : std_logic;
signal sig_1_2 : std_logic;
begin
ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock;
ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock;
ram_axi_full_awid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_awid;
ram_axi_full_bid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_bid;
ram_axi_full_arid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_arid;
ram_axi_full_rid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_rid;
-----------------
-- ID samplers --
-----------------
process (aclk)
begin
if rising_edge (aclk) then
if boot_bram_axi_full_awvalid='1' and boot_bram_axi_full_awready='1' then
boot_bram_axi_full_bid <= boot_bram_axi_full_awid;
end if;
if boot_bram_axi_full_arvalid='1' and boot_bram_axi_full_arready='1' then
boot_bram_axi_full_rid <= boot_bram_axi_full_arid;
end if;
if upper_ext=false then
if ram_axi_full_awvalid='1'and ram_axi_full_awready='1' then
ram_axi_full_bid <= ram_axi_full_awid;
end if;
if ram_axi_full_arvalid='1' and ram_axi_full_arready='1' then
ram_axi_full_rid <= ram_axi_full_arid;
end if;
end if;
end if;
end process;
------------------------------
-- Boot Bram Instantiations --
------------------------------
boot_bram_axi_bram_ctrl_0_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => peripheral_aresetn(0),
s_axi_awaddr => boot_bram_axi_full_awaddr(bram_address_width-1 downto 0),
s_axi_awlen => boot_bram_axi_full_awlen,
s_axi_awsize => boot_bram_axi_full_awsize,
s_axi_awburst => boot_bram_axi_full_awburst,
s_axi_awlock => boot_bram_axi_full_awlock,
s_axi_awcache => boot_bram_axi_full_awcache,
s_axi_awprot => boot_bram_axi_full_awprot,
s_axi_awvalid => boot_bram_axi_full_awvalid,
s_axi_awready => boot_bram_axi_full_awready,
s_axi_wdata => boot_bram_axi_full_wdata,
s_axi_wstrb => boot_bram_axi_full_wstrb,
s_axi_wlast => boot_bram_axi_full_wlast,
s_axi_wvalid => boot_bram_axi_full_wvalid,
s_axi_wready => boot_bram_axi_full_wready,
s_axi_bresp => boot_bram_axi_full_bresp,
s_axi_bvalid => boot_bram_axi_full_bvalid,
s_axi_bready => boot_bram_axi_full_bready,
s_axi_araddr => boot_bram_axi_full_araddr(bram_address_width-1 downto 0),
s_axi_arlen => boot_bram_axi_full_arlen,
s_axi_arsize => boot_bram_axi_full_arsize,
s_axi_arburst => boot_bram_axi_full_arburst,
s_axi_arlock => boot_bram_axi_full_arlock,
s_axi_arcache => boot_bram_axi_full_arcache,
s_axi_arprot => boot_bram_axi_full_arprot,
s_axi_arvalid => boot_bram_axi_full_arvalid,
s_axi_arready => boot_bram_axi_full_arready,
s_axi_rdata => boot_bram_axi_full_rdata,
s_axi_rresp => boot_bram_axi_full_rresp,
s_axi_rlast => boot_bram_axi_full_rlast,
s_axi_rvalid => boot_bram_axi_full_rvalid,
s_axi_rready => boot_bram_axi_full_rready,
bram_rst_a => boot_bram_rst_a,
bram_clk_a => boot_bram_clk_a,
bram_en_a => boot_bram_en_a,
bram_we_a => boot_bram_we_a,
bram_addr_a => boot_bram_addr_a,
bram_wrdata_a => boot_bram_wrdata_a,
bram_rddata_a => boot_bram_rddata_a);
boot_bram_inst : bram
generic map (
select_app => lower_app,
address_width => bram_address_width,
data_width => bram_data_width,
bram_depth => bram_bram_depth)
port map (
bram_rst_a => boot_bram_rst_a,
bram_clk_a => boot_bram_clk_a,
bram_en_a => boot_bram_en_a,
bram_we_a => boot_bram_we_a,
bram_addr_a => boot_bram_addr_a,
bram_wrdata_a => boot_bram_wrdata_a,
bram_rddata_a => boot_bram_rddata_a);
-------------------------------------
-- Main Memory and Synchronization --
-------------------------------------
gen_ext_mm :
if upper_ext=true generate
bd_wrapper_inst : bd_wrapper
port map (
DDR2_addr => DDR2_addr,
DDR2_ba => DDR2_ba,
DDR2_cas_n => DDR2_cas_n,
DDR2_ck_n => DDR2_ck_n,
DDR2_ck_p => DDR2_ck_p,
DDR2_cke => DDR2_cke,
DDR2_cs_n => DDR2_cs_n,
DDR2_dm => DDR2_dm,
DDR2_dq => DDR2_dq,
DDR2_dqs_n => DDR2_dqs_n,
DDR2_dqs_p => DDR2_dqs_p,
DDR2_odt => DDR2_odt,
DDR2_ras_n => DDR2_ras_n,
DDR2_we_n => DDR2_we_n,
S00_AXI_araddr => ram_axi_full_araddr,
S00_AXI_arburst => ram_axi_full_arburst,
S00_AXI_arcache => ram_axi_full_arcache,
S00_AXI_arid => ram_axi_full_arid_ext,
S00_AXI_arlen => ram_axi_full_arlen,
S00_AXI_arlock => ram_axi_full_arlock_slv,
S00_AXI_arprot => ram_axi_full_arprot,
S00_AXI_arqos => ram_axi_full_arqos,
S00_AXI_arready => ram_axi_full_arready,
S00_AXI_arregion => ram_axi_full_arregion,
S00_AXI_arsize => ram_axi_full_arsize,
S00_AXI_arvalid => ram_axi_full_arvalid,
S00_AXI_awaddr => ram_axi_full_awaddr,
S00_AXI_awburst => ram_axi_full_awburst,
S00_AXI_awcache => ram_axi_full_awcache,
S00_AXI_awid => ram_axi_full_awid_ext,
S00_AXI_awlen => ram_axi_full_awlen,
S00_AXI_awlock => ram_axi_full_awlock_slv,
S00_AXI_awprot => ram_axi_full_awprot,
S00_AXI_awqos => ram_axi_full_awqos,
S00_AXI_awready => ram_axi_full_awready,
S00_AXI_awregion => ram_axi_full_awregion,
S00_AXI_awsize => ram_axi_full_awsize,
S00_AXI_awvalid => ram_axi_full_awvalid,
S00_AXI_bid => ram_axi_full_bid_ext,
S00_AXI_bready => ram_axi_full_bready,
S00_AXI_bresp => ram_axi_full_bresp,
S00_AXI_bvalid => ram_axi_full_bvalid,
S00_AXI_rdata => ram_axi_full_rdata,
S00_AXI_rid => ram_axi_full_rid_ext,
S00_AXI_rlast => ram_axi_full_rlast,
S00_AXI_rready => ram_axi_full_rready,
S00_AXI_rresp => ram_axi_full_rresp,
S00_AXI_rvalid => ram_axi_full_rvalid,
S00_AXI_wdata => ram_axi_full_wdata,
S00_AXI_wlast => ram_axi_full_wlast,
S00_AXI_wready => ram_axi_full_wready,
S00_AXI_wstrb => ram_axi_full_wstrb,
S00_AXI_wvalid => ram_axi_full_wvalid,
aclk => aclk,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn,
sys_clk_i => sys_clk_i,
sys_rst => sys_rst);
end generate;
gen_int_mm :
if upper_ext=false generate
bd_axi_bram_ctrl_0_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => peripheral_aresetn(0),
s_axi_awaddr => ram_axi_full_awaddr(bram_address_width-1 downto 0),
s_axi_awlen => ram_axi_full_awlen,
s_axi_awsize => ram_axi_full_awsize,
s_axi_awburst => ram_axi_full_awburst,
s_axi_awlock => ram_axi_full_awlock,
s_axi_awcache => ram_axi_full_awcache,
s_axi_awprot => ram_axi_full_awprot,
s_axi_awvalid => ram_axi_full_awvalid,
s_axi_awready => ram_axi_full_awready,
s_axi_wdata => ram_axi_full_wdata,
s_axi_wstrb => ram_axi_full_wstrb,
s_axi_wlast => ram_axi_full_wlast,
s_axi_wvalid => ram_axi_full_wvalid,
s_axi_wready => ram_axi_full_wready,
s_axi_bresp => ram_axi_full_bresp,
s_axi_bvalid => ram_axi_full_bvalid,
s_axi_bready => ram_axi_full_bready,
s_axi_araddr => ram_axi_full_araddr(bram_address_width-1 downto 0),
s_axi_arlen => ram_axi_full_arlen,
s_axi_arsize => ram_axi_full_arsize,
s_axi_arburst => ram_axi_full_arburst,
s_axi_arlock => ram_axi_full_arlock,
s_axi_arcache => ram_axi_full_arcache,
s_axi_arprot => ram_axi_full_arprot,
s_axi_arvalid => ram_axi_full_arvalid,
s_axi_arready => ram_axi_full_arready,
s_axi_rdata => ram_axi_full_rdata,
s_axi_rresp => ram_axi_full_rresp,
s_axi_rlast => ram_axi_full_rlast,
s_axi_rvalid => ram_axi_full_rvalid,
s_axi_rready => ram_axi_full_rready,
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
bd_bram_inst : bram
generic map (
select_app => upper_app,
address_width => bram_address_width,
data_width => bram_data_width,
bram_depth => bram_bram_depth)
port map (
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
bd_clk_wiz_inst : clk_wiz_0
port map (
aclk => aclk,
resetn => sys_rst,
locked => dcm_locked,
sys_clk_i => sys_clk_i);
bd_proc_sys_reset_inst : proc_sys_reset_0
port map (
slowest_sync_clk => aclk,
ext_reset_in => sys_clk_i,
aux_reset_in => '0',
mb_debug_sys_rst => '0',
dcm_locked => dcm_locked,
mb_reset => open,
bus_struct_reset => open,
peripheral_reset => open,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn);
end generate;
-----------------------
-- Main Interconnect --
-----------------------
plasoc_interconnect_crossbar_wrap_inst : plasoc_interconnect_crossbar_wrap
port map (
cpu_0_s_axi_awid => cpu_0_axi_full_awid,
cpu_0_s_axi_awaddr => cpu_0_axi_full_awaddr,
cpu_0_s_axi_awlen => cpu_0_axi_full_awlen,
cpu_0_s_axi_awsize => cpu_0_axi_full_awsize,
cpu_0_s_axi_awburst => cpu_0_axi_full_awburst,
cpu_0_s_axi_awlock => cpu_0_axi_full_awlock,
cpu_0_s_axi_awcache => cpu_0_axi_full_awcache,
cpu_0_s_axi_awprot => cpu_0_axi_full_awprot,
cpu_0_s_axi_awqos => cpu_0_axi_full_awqos,
cpu_0_s_axi_awregion => cpu_0_axi_full_awregion,
cpu_0_s_axi_awvalid => cpu_0_axi_full_awvalid,
cpu_0_s_axi_awready => cpu_0_axi_full_awready,
cpu_0_s_axi_wdata => cpu_0_axi_full_wdata,
cpu_0_s_axi_wstrb => cpu_0_axi_full_wstrb,
cpu_0_s_axi_wlast => cpu_0_axi_full_wlast,
cpu_0_s_axi_wvalid => cpu_0_axi_full_wvalid,
cpu_0_s_axi_wready => cpu_0_axi_full_wready,
cpu_0_s_axi_bid => cpu_0_axi_full_bid,
cpu_0_s_axi_bresp => cpu_0_axi_full_bresp,
cpu_0_s_axi_bvalid => cpu_0_axi_full_bvalid,
cpu_0_s_axi_bready => cpu_0_axi_full_bready,
cpu_0_s_axi_arid => cpu_0_axi_full_arid,
cpu_0_s_axi_araddr => cpu_0_axi_full_araddr,
cpu_0_s_axi_arlen => cpu_0_axi_full_arlen,
cpu_0_s_axi_arsize => cpu_0_axi_full_arsize,
cpu_0_s_axi_arburst => cpu_0_axi_full_arburst,
cpu_0_s_axi_arlock => cpu_0_axi_full_arlock,
cpu_0_s_axi_arcache => cpu_0_axi_full_arcache,
cpu_0_s_axi_arprot => cpu_0_axi_full_arprot,
cpu_0_s_axi_arqos => cpu_0_axi_full_arqos,
cpu_0_s_axi_arregion => cpu_0_axi_full_arregion,
cpu_0_s_axi_arvalid => cpu_0_axi_full_arvalid,
cpu_0_s_axi_arready => cpu_0_axi_full_arready,
cpu_0_s_axi_rid => cpu_0_axi_full_rid,
cpu_0_s_axi_rdata => cpu_0_axi_full_rdata,
cpu_0_s_axi_rresp => cpu_0_axi_full_rresp,
cpu_0_s_axi_rlast => cpu_0_axi_full_rlast,
cpu_0_s_axi_rvalid => cpu_0_axi_full_rvalid,
cpu_0_s_axi_rready => cpu_0_axi_full_rready,
cpu_1_s_axi_awid => cpu_1_axi_full_awid,
cpu_1_s_axi_awaddr => cpu_1_axi_full_awaddr,
cpu_1_s_axi_awlen => cpu_1_axi_full_awlen,
cpu_1_s_axi_awsize => cpu_1_axi_full_awsize,
cpu_1_s_axi_awburst => cpu_1_axi_full_awburst,
cpu_1_s_axi_awlock => cpu_1_axi_full_awlock,
cpu_1_s_axi_awcache => cpu_1_axi_full_awcache,
cpu_1_s_axi_awprot => cpu_1_axi_full_awprot,
cpu_1_s_axi_awqos => cpu_1_axi_full_awqos,
cpu_1_s_axi_awregion => cpu_1_axi_full_awregion,
cpu_1_s_axi_awvalid => cpu_1_axi_full_awvalid,
cpu_1_s_axi_awready => cpu_1_axi_full_awready,
cpu_1_s_axi_wdata => cpu_1_axi_full_wdata,
cpu_1_s_axi_wstrb => cpu_1_axi_full_wstrb,
cpu_1_s_axi_wlast => cpu_1_axi_full_wlast,
cpu_1_s_axi_wvalid => cpu_1_axi_full_wvalid,
cpu_1_s_axi_wready => cpu_1_axi_full_wready,
cpu_1_s_axi_bid => cpu_1_axi_full_bid,
cpu_1_s_axi_bresp => cpu_1_axi_full_bresp,
cpu_1_s_axi_bvalid => cpu_1_axi_full_bvalid,
cpu_1_s_axi_bready => cpu_1_axi_full_bready,
cpu_1_s_axi_arid => cpu_1_axi_full_arid,
cpu_1_s_axi_araddr => cpu_1_axi_full_araddr,
cpu_1_s_axi_arlen => cpu_1_axi_full_arlen,
cpu_1_s_axi_arsize => cpu_1_axi_full_arsize,
cpu_1_s_axi_arburst => cpu_1_axi_full_arburst,
cpu_1_s_axi_arlock => cpu_1_axi_full_arlock,
cpu_1_s_axi_arcache => cpu_1_axi_full_arcache,
cpu_1_s_axi_arprot => cpu_1_axi_full_arprot,
cpu_1_s_axi_arqos => cpu_1_axi_full_arqos,
cpu_1_s_axi_arregion => cpu_1_axi_full_arregion,
cpu_1_s_axi_arvalid => cpu_1_axi_full_arvalid,
cpu_1_s_axi_arready => cpu_1_axi_full_arready,
cpu_1_s_axi_rid => cpu_1_axi_full_rid,
cpu_1_s_axi_rdata => cpu_1_axi_full_rdata,
cpu_1_s_axi_rresp => cpu_1_axi_full_rresp,
cpu_1_s_axi_rlast => cpu_1_axi_full_rlast,
cpu_1_s_axi_rvalid => cpu_1_axi_full_rvalid,
cpu_1_s_axi_rready => cpu_1_axi_full_rready,
cpu_2_s_axi_awid => cpu_2_axi_full_awid,
cpu_2_s_axi_awaddr => cpu_2_axi_full_awaddr,
cpu_2_s_axi_awlen => cpu_2_axi_full_awlen,
cpu_2_s_axi_awsize => cpu_2_axi_full_awsize,
cpu_2_s_axi_awburst => cpu_2_axi_full_awburst,
cpu_2_s_axi_awlock => cpu_2_axi_full_awlock,
cpu_2_s_axi_awcache => cpu_2_axi_full_awcache,
cpu_2_s_axi_awprot => cpu_2_axi_full_awprot,
cpu_2_s_axi_awqos => cpu_2_axi_full_awqos,
cpu_2_s_axi_awregion => cpu_2_axi_full_awregion,
cpu_2_s_axi_awvalid => cpu_2_axi_full_awvalid,
cpu_2_s_axi_awready => cpu_2_axi_full_awready,
cpu_2_s_axi_wdata => cpu_2_axi_full_wdata,
cpu_2_s_axi_wstrb => cpu_2_axi_full_wstrb,
cpu_2_s_axi_wlast => cpu_2_axi_full_wlast,
cpu_2_s_axi_wvalid => cpu_2_axi_full_wvalid,
cpu_2_s_axi_wready => cpu_2_axi_full_wready,
cpu_2_s_axi_bid => cpu_2_axi_full_bid,
cpu_2_s_axi_bresp => cpu_2_axi_full_bresp,
cpu_2_s_axi_bvalid => cpu_2_axi_full_bvalid,
cpu_2_s_axi_bready => cpu_2_axi_full_bready,
cpu_2_s_axi_arid => cpu_2_axi_full_arid,
cpu_2_s_axi_araddr => cpu_2_axi_full_araddr,
cpu_2_s_axi_arlen => cpu_2_axi_full_arlen,
cpu_2_s_axi_arsize => cpu_2_axi_full_arsize,
cpu_2_s_axi_arburst => cpu_2_axi_full_arburst,
cpu_2_s_axi_arlock => cpu_2_axi_full_arlock,
cpu_2_s_axi_arcache => cpu_2_axi_full_arcache,
cpu_2_s_axi_arprot => cpu_2_axi_full_arprot,
cpu_2_s_axi_arqos => cpu_2_axi_full_arqos,
cpu_2_s_axi_arregion => cpu_2_axi_full_arregion,
cpu_2_s_axi_arvalid => cpu_2_axi_full_arvalid,
cpu_2_s_axi_arready => cpu_2_axi_full_arready,
cpu_2_s_axi_rid => cpu_2_axi_full_rid,
cpu_2_s_axi_rdata => cpu_2_axi_full_rdata,
cpu_2_s_axi_rresp => cpu_2_axi_full_rresp,
cpu_2_s_axi_rlast => cpu_2_axi_full_rlast,
cpu_2_s_axi_rvalid => cpu_2_axi_full_rvalid,
cpu_2_s_axi_rready => cpu_2_axi_full_rready,
boot_bram_m_axi_awid => boot_bram_axi_full_awid,
boot_bram_m_axi_awaddr => boot_bram_axi_full_awaddr,
boot_bram_m_axi_awlen => boot_bram_axi_full_awlen,
boot_bram_m_axi_awsize => boot_bram_axi_full_awsize,
boot_bram_m_axi_awburst => boot_bram_axi_full_awburst,
boot_bram_m_axi_awlock => boot_bram_axi_full_awlock,
boot_bram_m_axi_awcache => boot_bram_axi_full_awcache,
boot_bram_m_axi_awprot => boot_bram_axi_full_awprot,
boot_bram_m_axi_awqos => boot_bram_axi_full_awqos,
boot_bram_m_axi_awregion => boot_bram_axi_full_awregion,
boot_bram_m_axi_awvalid => boot_bram_axi_full_awvalid,
boot_bram_m_axi_awready => boot_bram_axi_full_awready,
boot_bram_m_axi_wdata => boot_bram_axi_full_wdata,
boot_bram_m_axi_wstrb => boot_bram_axi_full_wstrb,
boot_bram_m_axi_wlast => boot_bram_axi_full_wlast,
boot_bram_m_axi_wvalid => boot_bram_axi_full_wvalid,
boot_bram_m_axi_wready => boot_bram_axi_full_wready,
boot_bram_m_axi_bid => boot_bram_axi_full_bid,
boot_bram_m_axi_bresp => boot_bram_axi_full_bresp,
boot_bram_m_axi_bvalid => boot_bram_axi_full_bvalid,
boot_bram_m_axi_bready => boot_bram_axi_full_bready,
boot_bram_m_axi_arid => boot_bram_axi_full_arid,
boot_bram_m_axi_araddr => boot_bram_axi_full_araddr,
boot_bram_m_axi_arlen => boot_bram_axi_full_arlen,
boot_bram_m_axi_arsize => boot_bram_axi_full_arsize,
boot_bram_m_axi_arburst => boot_bram_axi_full_arburst,
boot_bram_m_axi_arlock => boot_bram_axi_full_arlock,
boot_bram_m_axi_arcache => boot_bram_axi_full_arcache,
boot_bram_m_axi_arprot => boot_bram_axi_full_arprot,
boot_bram_m_axi_arqos => boot_bram_axi_full_arqos,
boot_bram_m_axi_arregion => boot_bram_axi_full_arregion,
boot_bram_m_axi_arvalid => boot_bram_axi_full_arvalid,
boot_bram_m_axi_arready => boot_bram_axi_full_arready,
boot_bram_m_axi_rid => boot_bram_axi_full_rid,
boot_bram_m_axi_rdata => boot_bram_axi_full_rdata,
boot_bram_m_axi_rresp => boot_bram_axi_full_rresp,
boot_bram_m_axi_rlast => boot_bram_axi_full_rlast,
boot_bram_m_axi_rvalid => boot_bram_axi_full_rvalid,
boot_bram_m_axi_rready => boot_bram_axi_full_rready,
ram_m_axi_awid => ram_axi_full_awid,
ram_m_axi_awaddr => ram_axi_full_awaddr,
ram_m_axi_awlen => ram_axi_full_awlen,
ram_m_axi_awsize => ram_axi_full_awsize,
ram_m_axi_awburst => ram_axi_full_awburst,
ram_m_axi_awlock => ram_axi_full_awlock,
ram_m_axi_awcache => ram_axi_full_awcache,
ram_m_axi_awprot => ram_axi_full_awprot,
ram_m_axi_awqos => ram_axi_full_awqos,
ram_m_axi_awregion => ram_axi_full_awregion,
ram_m_axi_awvalid => ram_axi_full_awvalid,
ram_m_axi_awready => ram_axi_full_awready,
ram_m_axi_wdata => ram_axi_full_wdata,
ram_m_axi_wstrb => ram_axi_full_wstrb,
ram_m_axi_wlast => ram_axi_full_wlast,
ram_m_axi_wvalid => ram_axi_full_wvalid,
ram_m_axi_wready => ram_axi_full_wready,
ram_m_axi_bid => ram_axi_full_bid,
ram_m_axi_bresp => ram_axi_full_bresp,
ram_m_axi_bvalid => ram_axi_full_bvalid,
ram_m_axi_bready => ram_axi_full_bready,
ram_m_axi_arid => ram_axi_full_arid,
ram_m_axi_araddr => ram_axi_full_araddr,
ram_m_axi_arlen => ram_axi_full_arlen,
ram_m_axi_arsize => ram_axi_full_arsize,
ram_m_axi_arburst => ram_axi_full_arburst,
ram_m_axi_arlock => ram_axi_full_arlock,
ram_m_axi_arcache => ram_axi_full_arcache,
ram_m_axi_arprot => ram_axi_full_arprot,
ram_m_axi_arqos => ram_axi_full_arqos,
ram_m_axi_arregion => ram_axi_full_arregion,
ram_m_axi_arvalid => ram_axi_full_arvalid,
ram_m_axi_arready => ram_axi_full_arready,
ram_m_axi_rid => ram_axi_full_rid,
ram_m_axi_rdata => ram_axi_full_rdata,
ram_m_axi_rresp => ram_axi_full_rresp,
ram_m_axi_rlast => ram_axi_full_rlast,
ram_m_axi_rvalid => ram_axi_full_rvalid,
ram_m_axi_rready => ram_axi_full_rready,
int_m_axi_awid => int_axi_full_awid,
int_m_axi_awaddr => int_axi_full_awaddr,
int_m_axi_awlen => int_axi_full_awlen,
int_m_axi_awsize => int_axi_full_awsize,
int_m_axi_awburst => int_axi_full_awburst,
int_m_axi_awlock => int_axi_full_awlock,
int_m_axi_awcache => int_axi_full_awcache,
int_m_axi_awprot => int_axi_full_awprot,
int_m_axi_awqos => int_axi_full_awqos,
int_m_axi_awregion => int_axi_full_awregion,
int_m_axi_awvalid => int_axi_full_awvalid,
int_m_axi_awready => int_axi_full_awready,
int_m_axi_wdata => int_axi_full_wdata,
int_m_axi_wstrb => int_axi_full_wstrb,
int_m_axi_wlast => int_axi_full_wlast,
int_m_axi_wvalid => int_axi_full_wvalid,
int_m_axi_wready => int_axi_full_wready,
int_m_axi_bid => int_axi_full_bid,
int_m_axi_bresp => int_axi_full_bresp,
int_m_axi_bvalid => int_axi_full_bvalid,
int_m_axi_bready => int_axi_full_bready,
int_m_axi_arid => int_axi_full_arid,
int_m_axi_araddr => int_axi_full_araddr,
int_m_axi_arlen => int_axi_full_arlen,
int_m_axi_arsize => int_axi_full_arsize,
int_m_axi_arburst => int_axi_full_arburst,
int_m_axi_arlock => int_axi_full_arlock,
int_m_axi_arcache => int_axi_full_arcache,
int_m_axi_arprot => int_axi_full_arprot,
int_m_axi_arqos => int_axi_full_arqos,
int_m_axi_arregion => int_axi_full_arregion,
int_m_axi_arvalid => int_axi_full_arvalid,
int_m_axi_arready => int_axi_full_arready,
int_m_axi_rid => int_axi_full_rid,
int_m_axi_rdata => int_axi_full_rdata,
int_m_axi_rresp => int_axi_full_rresp,
int_m_axi_rlast => int_axi_full_rlast,
int_m_axi_rvalid => int_axi_full_rvalid,
int_m_axi_rready => int_axi_full_rready,
timer_m_axi_awid => timer_axi_full_awid,
timer_m_axi_awaddr => timer_axi_full_awaddr,
timer_m_axi_awlen => timer_axi_full_awlen,
timer_m_axi_awsize => timer_axi_full_awsize,
timer_m_axi_awburst => timer_axi_full_awburst,
timer_m_axi_awlock => timer_axi_full_awlock,
timer_m_axi_awcache => timer_axi_full_awcache,
timer_m_axi_awprot => timer_axi_full_awprot,
timer_m_axi_awqos => timer_axi_full_awqos,
timer_m_axi_awregion => timer_axi_full_awregion,
timer_m_axi_awvalid => timer_axi_full_awvalid,
timer_m_axi_awready => timer_axi_full_awready,
timer_m_axi_wdata => timer_axi_full_wdata,
timer_m_axi_wstrb => timer_axi_full_wstrb,
timer_m_axi_wlast => timer_axi_full_wlast,
timer_m_axi_wvalid => timer_axi_full_wvalid,
timer_m_axi_wready => timer_axi_full_wready,
timer_m_axi_bid => timer_axi_full_bid,
timer_m_axi_bresp => timer_axi_full_bresp,
timer_m_axi_bvalid => timer_axi_full_bvalid,
timer_m_axi_bready => timer_axi_full_bready,
timer_m_axi_arid => timer_axi_full_arid,
timer_m_axi_araddr => timer_axi_full_araddr,
timer_m_axi_arlen => timer_axi_full_arlen,
timer_m_axi_arsize => timer_axi_full_arsize,
timer_m_axi_arburst => timer_axi_full_arburst,
timer_m_axi_arlock => timer_axi_full_arlock,
timer_m_axi_arcache => timer_axi_full_arcache,
timer_m_axi_arprot => timer_axi_full_arprot,
timer_m_axi_arqos => timer_axi_full_arqos,
timer_m_axi_arregion => timer_axi_full_arregion,
timer_m_axi_arvalid => timer_axi_full_arvalid,
timer_m_axi_arready => timer_axi_full_arready,
timer_m_axi_rid => timer_axi_full_rid,
timer_m_axi_rdata => timer_axi_full_rdata,
timer_m_axi_rresp => timer_axi_full_rresp,
timer_m_axi_rlast => timer_axi_full_rlast,
timer_m_axi_rvalid => timer_axi_full_rvalid,
timer_m_axi_rready => timer_axi_full_rready,
gpio_m_axi_awid => gpio_axi_full_awid,
gpio_m_axi_awaddr => gpio_axi_full_awaddr,
gpio_m_axi_awlen => gpio_axi_full_awlen,
gpio_m_axi_awsize => gpio_axi_full_awsize,
gpio_m_axi_awburst => gpio_axi_full_awburst,
gpio_m_axi_awlock => gpio_axi_full_awlock,
gpio_m_axi_awcache => gpio_axi_full_awcache,
gpio_m_axi_awprot => gpio_axi_full_awprot,
gpio_m_axi_awqos => gpio_axi_full_awqos,
gpio_m_axi_awregion => gpio_axi_full_awregion,
gpio_m_axi_awvalid => gpio_axi_full_awvalid,
gpio_m_axi_awready => gpio_axi_full_awready,
gpio_m_axi_wdata => gpio_axi_full_wdata,
gpio_m_axi_wstrb => gpio_axi_full_wstrb,
gpio_m_axi_wlast => gpio_axi_full_wlast,
gpio_m_axi_wvalid => gpio_axi_full_wvalid,
gpio_m_axi_wready => gpio_axi_full_wready,
gpio_m_axi_bid => gpio_axi_full_bid,
gpio_m_axi_bresp => gpio_axi_full_bresp,
gpio_m_axi_bvalid => gpio_axi_full_bvalid,
gpio_m_axi_bready => gpio_axi_full_bready,
gpio_m_axi_arid => gpio_axi_full_arid,
gpio_m_axi_araddr => gpio_axi_full_araddr,
gpio_m_axi_arlen => gpio_axi_full_arlen,
gpio_m_axi_arsize => gpio_axi_full_arsize,
gpio_m_axi_arburst => gpio_axi_full_arburst,
gpio_m_axi_arlock => gpio_axi_full_arlock,
gpio_m_axi_arcache => gpio_axi_full_arcache,
gpio_m_axi_arprot => gpio_axi_full_arprot,
gpio_m_axi_arqos => gpio_axi_full_arqos,
gpio_m_axi_arregion => gpio_axi_full_arregion,
gpio_m_axi_arvalid => gpio_axi_full_arvalid,
gpio_m_axi_arready => gpio_axi_full_arready,
gpio_m_axi_rid => gpio_axi_full_rid,
gpio_m_axi_rdata => gpio_axi_full_rdata,
gpio_m_axi_rresp => gpio_axi_full_rresp,
gpio_m_axi_rlast => gpio_axi_full_rlast,
gpio_m_axi_rvalid => gpio_axi_full_rvalid,
gpio_m_axi_rready => gpio_axi_full_rready,
uart_m_axi_awid => uart_axi_full_awid,
uart_m_axi_awaddr => uart_axi_full_awaddr,
uart_m_axi_awlen => uart_axi_full_awlen,
uart_m_axi_awsize => uart_axi_full_awsize,
uart_m_axi_awburst => uart_axi_full_awburst,
uart_m_axi_awlock => uart_axi_full_awlock,
uart_m_axi_awcache => uart_axi_full_awcache,
uart_m_axi_awprot => uart_axi_full_awprot,
uart_m_axi_awqos => uart_axi_full_awqos,
uart_m_axi_awregion => uart_axi_full_awregion,
uart_m_axi_awvalid => uart_axi_full_awvalid,
uart_m_axi_awready => uart_axi_full_awready,
uart_m_axi_wdata => uart_axi_full_wdata,
uart_m_axi_wstrb => uart_axi_full_wstrb,
uart_m_axi_wlast => uart_axi_full_wlast,
uart_m_axi_wvalid => uart_axi_full_wvalid,
uart_m_axi_wready => uart_axi_full_wready,
uart_m_axi_bid => uart_axi_full_bid,
uart_m_axi_bresp => uart_axi_full_bresp,
uart_m_axi_bvalid => uart_axi_full_bvalid,
uart_m_axi_bready => uart_axi_full_bready,
uart_m_axi_arid => uart_axi_full_arid,
uart_m_axi_araddr => uart_axi_full_araddr,
uart_m_axi_arlen => uart_axi_full_arlen,
uart_m_axi_arsize => uart_axi_full_arsize,
uart_m_axi_arburst => uart_axi_full_arburst,
uart_m_axi_arlock => uart_axi_full_arlock,
uart_m_axi_arcache => uart_axi_full_arcache,
uart_m_axi_arprot => uart_axi_full_arprot,
uart_m_axi_arqos => uart_axi_full_arqos,
uart_m_axi_arregion => uart_axi_full_arregion,
uart_m_axi_arvalid => uart_axi_full_arvalid,
uart_m_axi_arready => uart_axi_full_arready,
uart_m_axi_rid => uart_axi_full_rid,
uart_m_axi_rdata => uart_axi_full_rdata,
uart_m_axi_rresp => uart_axi_full_rresp,
uart_m_axi_rlast => uart_axi_full_rlast,
uart_m_axi_rvalid => uart_axi_full_rvalid,
uart_m_axi_rready => uart_axi_full_rready,
lock_m_axi_awid => lock_axi_full_awid,
lock_m_axi_awaddr => lock_axi_full_awaddr,
lock_m_axi_awlen => lock_axi_full_awlen,
lock_m_axi_awsize => lock_axi_full_awsize,
lock_m_axi_awburst => lock_axi_full_awburst,
lock_m_axi_awlock => lock_axi_full_awlock,
lock_m_axi_awcache => lock_axi_full_awcache,
lock_m_axi_awprot => lock_axi_full_awprot,
lock_m_axi_awqos => lock_axi_full_awqos,
lock_m_axi_awregion => lock_axi_full_awregion,
lock_m_axi_awvalid => lock_axi_full_awvalid,
lock_m_axi_awready => lock_axi_full_awready,
lock_m_axi_wdata => lock_axi_full_wdata,
lock_m_axi_wstrb => lock_axi_full_wstrb,
lock_m_axi_wlast => lock_axi_full_wlast,
lock_m_axi_wvalid => lock_axi_full_wvalid,
lock_m_axi_wready => lock_axi_full_wready,
lock_m_axi_bid => lock_axi_full_bid,
lock_m_axi_bresp => lock_axi_full_bresp,
lock_m_axi_bvalid => lock_axi_full_bvalid,
lock_m_axi_bready => lock_axi_full_bready,
lock_m_axi_arid => lock_axi_full_arid,
lock_m_axi_araddr => lock_axi_full_araddr,
lock_m_axi_arlen => lock_axi_full_arlen,
lock_m_axi_arsize => lock_axi_full_arsize,
lock_m_axi_arburst => lock_axi_full_arburst,
lock_m_axi_arlock => lock_axi_full_arlock,
lock_m_axi_arcache => lock_axi_full_arcache,
lock_m_axi_arprot => lock_axi_full_arprot,
lock_m_axi_arqos => lock_axi_full_arqos,
lock_m_axi_arregion => lock_axi_full_arregion,
lock_m_axi_arvalid => lock_axi_full_arvalid,
lock_m_axi_arready => lock_axi_full_arready,
lock_m_axi_rid => lock_axi_full_rid,
lock_m_axi_rdata => lock_axi_full_rdata,
lock_m_axi_rresp => lock_axi_full_rresp,
lock_m_axi_rlast => lock_axi_full_rlast,
lock_m_axi_rvalid => lock_axi_full_rvalid,
lock_m_axi_rready => lock_axi_full_rready,
aclk => aclk, aresetn => interconnect_aresetn(0));
---------------
-- CPU Buses --
---------------
cpu_0_bus_inst : plasoc_cpu_0_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_0_full_awid,
cpu_s_axi_awaddr => cpu_bus_0_full_awaddr,
cpu_s_axi_awlen => cpu_bus_0_full_awlen,
cpu_s_axi_awsize => cpu_bus_0_full_awsize,
cpu_s_axi_awburst => cpu_bus_0_full_awburst,
cpu_s_axi_awlock => cpu_bus_0_full_awlock,
cpu_s_axi_awcache => cpu_bus_0_full_awcache,
cpu_s_axi_awprot => cpu_bus_0_full_awprot,
cpu_s_axi_awqos => cpu_bus_0_full_awqos,
cpu_s_axi_awregion => cpu_bus_0_full_awregion,
cpu_s_axi_awvalid => cpu_bus_0_full_awvalid,
cpu_s_axi_awready => cpu_bus_0_full_awready,
cpu_s_axi_wdata => cpu_bus_0_full_wdata,
cpu_s_axi_wstrb => cpu_bus_0_full_wstrb,
cpu_s_axi_wlast => cpu_bus_0_full_wlast,
cpu_s_axi_wvalid => cpu_bus_0_full_wvalid,
cpu_s_axi_wready => cpu_bus_0_full_wready,
cpu_s_axi_bid => cpu_bus_0_full_bid,
cpu_s_axi_bresp => cpu_bus_0_full_bresp,
cpu_s_axi_bvalid => cpu_bus_0_full_bvalid,
cpu_s_axi_bready => cpu_bus_0_full_bready,
cpu_s_axi_arid => cpu_bus_0_full_arid,
cpu_s_axi_araddr => cpu_bus_0_full_araddr,
cpu_s_axi_arlen => cpu_bus_0_full_arlen,
cpu_s_axi_arsize => cpu_bus_0_full_arsize,
cpu_s_axi_arburst => cpu_bus_0_full_arburst,
cpu_s_axi_arlock => cpu_bus_0_full_arlock,
cpu_s_axi_arcache => cpu_bus_0_full_arcache,
cpu_s_axi_arprot => cpu_bus_0_full_arprot,
cpu_s_axi_arqos => cpu_bus_0_full_arqos,
cpu_s_axi_arregion => cpu_bus_0_full_arregion,
cpu_s_axi_arvalid => cpu_bus_0_full_arvalid,
cpu_s_axi_arready => cpu_bus_0_full_arready,
cpu_s_axi_rid => cpu_bus_0_full_rid,
cpu_s_axi_rdata => cpu_bus_0_full_rdata,
cpu_s_axi_rresp => cpu_bus_0_full_rresp,
cpu_s_axi_rlast => cpu_bus_0_full_rlast,
cpu_s_axi_rvalid => cpu_bus_0_full_rvalid,
cpu_s_axi_rready => cpu_bus_0_full_rready,
ip_m_axi_awid => cpu_0_axi_full_awid,
ip_m_axi_awaddr => cpu_0_axi_full_awaddr,
ip_m_axi_awlen => cpu_0_axi_full_awlen,
ip_m_axi_awsize => cpu_0_axi_full_awsize,
ip_m_axi_awburst => cpu_0_axi_full_awburst,
ip_m_axi_awlock => cpu_0_axi_full_awlock,
ip_m_axi_awcache => cpu_0_axi_full_awcache,
ip_m_axi_awprot => cpu_0_axi_full_awprot,
ip_m_axi_awqos => cpu_0_axi_full_awqos,
ip_m_axi_awregion => cpu_0_axi_full_awregion,
ip_m_axi_awvalid => cpu_0_axi_full_awvalid,
ip_m_axi_awready => cpu_0_axi_full_awready,
ip_m_axi_wdata => cpu_0_axi_full_wdata,
ip_m_axi_wstrb => cpu_0_axi_full_wstrb,
ip_m_axi_wlast => cpu_0_axi_full_wlast,
ip_m_axi_wvalid => cpu_0_axi_full_wvalid,
ip_m_axi_wready => cpu_0_axi_full_wready,
ip_m_axi_bid => cpu_0_axi_full_bid,
ip_m_axi_bresp => cpu_0_axi_full_bresp,
ip_m_axi_bvalid => cpu_0_axi_full_bvalid,
ip_m_axi_bready => cpu_0_axi_full_bready,
ip_m_axi_arid => cpu_0_axi_full_arid,
ip_m_axi_araddr => cpu_0_axi_full_araddr,
ip_m_axi_arlen => cpu_0_axi_full_arlen,
ip_m_axi_arsize => cpu_0_axi_full_arsize,
ip_m_axi_arburst => cpu_0_axi_full_arburst,
ip_m_axi_arlock => cpu_0_axi_full_arlock,
ip_m_axi_arcache => cpu_0_axi_full_arcache,
ip_m_axi_arprot => cpu_0_axi_full_arprot,
ip_m_axi_arqos => cpu_0_axi_full_arqos,
ip_m_axi_arregion => cpu_0_axi_full_arregion,
ip_m_axi_arvalid => cpu_0_axi_full_arvalid,
ip_m_axi_arready => cpu_0_axi_full_arready,
ip_m_axi_rid => cpu_0_axi_full_rid,
ip_m_axi_rdata => cpu_0_axi_full_rdata,
ip_m_axi_rresp => cpu_0_axi_full_rresp,
ip_m_axi_rlast => cpu_0_axi_full_rlast,
ip_m_axi_rvalid => cpu_0_axi_full_rvalid,
ip_m_axi_rready => cpu_0_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_0_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_0_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_0_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_0_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_0_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_0_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_0_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_0_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_0_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_0_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_0_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_0_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_0_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_0_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_0_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_0_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_0_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_0_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_0_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_0_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_0_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_0_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_0_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_0_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_0_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_0_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_0_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_0_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_0_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_0_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_0_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_0_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_0_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_0_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_0_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_0_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_0_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_0_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_0_full_rready,
int_m_axi_awid => int_bus_0_full_awid,
int_m_axi_awaddr => int_bus_0_full_awaddr,
int_m_axi_awlen => int_bus_0_full_awlen,
int_m_axi_awsize => int_bus_0_full_awsize,
int_m_axi_awburst => int_bus_0_full_awburst,
int_m_axi_awlock => int_bus_0_full_awlock,
int_m_axi_awcache => int_bus_0_full_awcache,
int_m_axi_awprot => int_bus_0_full_awprot,
int_m_axi_awqos => int_bus_0_full_awqos,
int_m_axi_awregion => int_bus_0_full_awregion,
int_m_axi_awvalid => int_bus_0_full_awvalid,
int_m_axi_awready => int_bus_0_full_awready,
int_m_axi_wdata => int_bus_0_full_wdata,
int_m_axi_wstrb => int_bus_0_full_wstrb,
int_m_axi_wlast => int_bus_0_full_wlast,
int_m_axi_wvalid => int_bus_0_full_wvalid,
int_m_axi_wready => int_bus_0_full_wready,
int_m_axi_bid => int_bus_0_full_bid,
int_m_axi_bresp => int_bus_0_full_bresp,
int_m_axi_bvalid => int_bus_0_full_bvalid,
int_m_axi_bready => int_bus_0_full_bready,
int_m_axi_arid => int_bus_0_full_arid,
int_m_axi_araddr => int_bus_0_full_araddr,
int_m_axi_arlen => int_bus_0_full_arlen,
int_m_axi_arsize => int_bus_0_full_arsize,
int_m_axi_arburst => int_bus_0_full_arburst,
int_m_axi_arlock => int_bus_0_full_arlock,
int_m_axi_arcache => int_bus_0_full_arcache,
int_m_axi_arprot => int_bus_0_full_arprot,
int_m_axi_arqos => int_bus_0_full_arqos,
int_m_axi_arregion => int_bus_0_full_arregion,
int_m_axi_arvalid => int_bus_0_full_arvalid,
int_m_axi_arready => int_bus_0_full_arready,
int_m_axi_rid => int_bus_0_full_rid,
int_m_axi_rdata => int_bus_0_full_rdata,
int_m_axi_rresp => int_bus_0_full_rresp,
int_m_axi_rlast => int_bus_0_full_rlast,
int_m_axi_rvalid => int_bus_0_full_rvalid,
int_m_axi_rready => int_bus_0_full_rready,
signal_m_axi_awid => signal_bus_0_full_awid,
signal_m_axi_awaddr => signal_bus_0_full_awaddr,
signal_m_axi_awlen => signal_bus_0_full_awlen,
signal_m_axi_awsize => signal_bus_0_full_awsize,
signal_m_axi_awburst => signal_bus_0_full_awburst,
signal_m_axi_awlock => signal_bus_0_full_awlock,
signal_m_axi_awcache => signal_bus_0_full_awcache,
signal_m_axi_awprot => signal_bus_0_full_awprot,
signal_m_axi_awqos => signal_bus_0_full_awqos,
signal_m_axi_awregion => signal_bus_0_full_awregion,
signal_m_axi_awvalid => signal_bus_0_full_awvalid,
signal_m_axi_awready => signal_bus_0_full_awready,
signal_m_axi_wdata => signal_bus_0_full_wdata,
signal_m_axi_wstrb => signal_bus_0_full_wstrb,
signal_m_axi_wlast => signal_bus_0_full_wlast,
signal_m_axi_wvalid => signal_bus_0_full_wvalid,
signal_m_axi_wready => signal_bus_0_full_wready,
signal_m_axi_bid => signal_bus_0_full_bid,
signal_m_axi_bresp => signal_bus_0_full_bresp,
signal_m_axi_bvalid => signal_bus_0_full_bvalid,
signal_m_axi_bready => signal_bus_0_full_bready,
signal_m_axi_arid => signal_bus_0_full_arid,
signal_m_axi_araddr => signal_bus_0_full_araddr,
signal_m_axi_arlen => signal_bus_0_full_arlen,
signal_m_axi_arsize => signal_bus_0_full_arsize,
signal_m_axi_arburst => signal_bus_0_full_arburst,
signal_m_axi_arlock => signal_bus_0_full_arlock,
signal_m_axi_arcache => signal_bus_0_full_arcache,
signal_m_axi_arprot => signal_bus_0_full_arprot,
signal_m_axi_arqos => signal_bus_0_full_arqos,
signal_m_axi_arregion => signal_bus_0_full_arregion,
signal_m_axi_arvalid => signal_bus_0_full_arvalid,
signal_m_axi_arready => signal_bus_0_full_arready,
signal_m_axi_rid => signal_bus_0_full_rid,
signal_m_axi_rdata => signal_bus_0_full_rdata,
signal_m_axi_rresp => signal_bus_0_full_rresp,
signal_m_axi_rlast => signal_bus_0_full_rlast,
signal_m_axi_rvalid => signal_bus_0_full_rvalid,
timer_m_axi_awid => timer_bus_0_full_awid,
timer_m_axi_awaddr => timer_bus_0_full_awaddr,
timer_m_axi_awlen => timer_bus_0_full_awlen,
timer_m_axi_awsize => timer_bus_0_full_awsize,
timer_m_axi_awburst => timer_bus_0_full_awburst,
timer_m_axi_awlock => timer_bus_0_full_awlock,
timer_m_axi_awcache => timer_bus_0_full_awcache,
timer_m_axi_awprot => timer_bus_0_full_awprot,
timer_m_axi_awqos => timer_bus_0_full_awqos,
timer_m_axi_awregion => timer_bus_0_full_awregion,
timer_m_axi_awvalid => timer_bus_0_full_awvalid,
timer_m_axi_awready => timer_bus_0_full_awready,
timer_m_axi_wdata => timer_bus_0_full_wdata,
timer_m_axi_wstrb => timer_bus_0_full_wstrb,
timer_m_axi_wlast => timer_bus_0_full_wlast,
timer_m_axi_wvalid => timer_bus_0_full_wvalid,
timer_m_axi_wready => timer_bus_0_full_wready,
timer_m_axi_bid => timer_bus_0_full_bid,
timer_m_axi_bresp => timer_bus_0_full_bresp,
timer_m_axi_bvalid => timer_bus_0_full_bvalid,
timer_m_axi_bready => timer_bus_0_full_bready,
timer_m_axi_arid => timer_bus_0_full_arid,
timer_m_axi_araddr => timer_bus_0_full_araddr,
timer_m_axi_arlen => timer_bus_0_full_arlen,
timer_m_axi_arsize => timer_bus_0_full_arsize,
timer_m_axi_arburst => timer_bus_0_full_arburst,
timer_m_axi_arlock => timer_bus_0_full_arlock,
timer_m_axi_arcache => timer_bus_0_full_arcache,
timer_m_axi_arprot => timer_bus_0_full_arprot,
timer_m_axi_arqos => timer_bus_0_full_arqos,
timer_m_axi_arregion => timer_bus_0_full_arregion,
timer_m_axi_arvalid => timer_bus_0_full_arvalid,
timer_m_axi_arready => timer_bus_0_full_arready,
timer_m_axi_rid => timer_bus_0_full_rid,
timer_m_axi_rdata => timer_bus_0_full_rdata,
timer_m_axi_rresp => timer_bus_0_full_rresp,
timer_m_axi_rlast => timer_bus_0_full_rlast,
timer_m_axi_rvalid => timer_bus_0_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
cpu_1_bus_inst : plasoc_cpu_1_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_1_full_awid,
cpu_s_axi_awaddr => cpu_bus_1_full_awaddr,
cpu_s_axi_awlen => cpu_bus_1_full_awlen,
cpu_s_axi_awsize => cpu_bus_1_full_awsize,
cpu_s_axi_awburst => cpu_bus_1_full_awburst,
cpu_s_axi_awlock => cpu_bus_1_full_awlock,
cpu_s_axi_awcache => cpu_bus_1_full_awcache,
cpu_s_axi_awprot => cpu_bus_1_full_awprot,
cpu_s_axi_awqos => cpu_bus_1_full_awqos,
cpu_s_axi_awregion => cpu_bus_1_full_awregion,
cpu_s_axi_awvalid => cpu_bus_1_full_awvalid,
cpu_s_axi_awready => cpu_bus_1_full_awready,
cpu_s_axi_wdata => cpu_bus_1_full_wdata,
cpu_s_axi_wstrb => cpu_bus_1_full_wstrb,
cpu_s_axi_wlast => cpu_bus_1_full_wlast,
cpu_s_axi_wvalid => cpu_bus_1_full_wvalid,
cpu_s_axi_wready => cpu_bus_1_full_wready,
cpu_s_axi_bid => cpu_bus_1_full_bid,
cpu_s_axi_bresp => cpu_bus_1_full_bresp,
cpu_s_axi_bvalid => cpu_bus_1_full_bvalid,
cpu_s_axi_bready => cpu_bus_1_full_bready,
cpu_s_axi_arid => cpu_bus_1_full_arid,
cpu_s_axi_araddr => cpu_bus_1_full_araddr,
cpu_s_axi_arlen => cpu_bus_1_full_arlen,
cpu_s_axi_arsize => cpu_bus_1_full_arsize,
cpu_s_axi_arburst => cpu_bus_1_full_arburst,
cpu_s_axi_arlock => cpu_bus_1_full_arlock,
cpu_s_axi_arcache => cpu_bus_1_full_arcache,
cpu_s_axi_arprot => cpu_bus_1_full_arprot,
cpu_s_axi_arqos => cpu_bus_1_full_arqos,
cpu_s_axi_arregion => cpu_bus_1_full_arregion,
cpu_s_axi_arvalid => cpu_bus_1_full_arvalid,
cpu_s_axi_arready => cpu_bus_1_full_arready,
cpu_s_axi_rid => cpu_bus_1_full_rid,
cpu_s_axi_rdata => cpu_bus_1_full_rdata,
cpu_s_axi_rresp => cpu_bus_1_full_rresp,
cpu_s_axi_rlast => cpu_bus_1_full_rlast,
cpu_s_axi_rvalid => cpu_bus_1_full_rvalid,
cpu_s_axi_rready => cpu_bus_1_full_rready,
ip_m_axi_awid => cpu_1_axi_full_awid,
ip_m_axi_awaddr => cpu_1_axi_full_awaddr,
ip_m_axi_awlen => cpu_1_axi_full_awlen,
ip_m_axi_awsize => cpu_1_axi_full_awsize,
ip_m_axi_awburst => cpu_1_axi_full_awburst,
ip_m_axi_awlock => cpu_1_axi_full_awlock,
ip_m_axi_awcache => cpu_1_axi_full_awcache,
ip_m_axi_awprot => cpu_1_axi_full_awprot,
ip_m_axi_awqos => cpu_1_axi_full_awqos,
ip_m_axi_awregion => cpu_1_axi_full_awregion,
ip_m_axi_awvalid => cpu_1_axi_full_awvalid,
ip_m_axi_awready => cpu_1_axi_full_awready,
ip_m_axi_wdata => cpu_1_axi_full_wdata,
ip_m_axi_wstrb => cpu_1_axi_full_wstrb,
ip_m_axi_wlast => cpu_1_axi_full_wlast,
ip_m_axi_wvalid => cpu_1_axi_full_wvalid,
ip_m_axi_wready => cpu_1_axi_full_wready,
ip_m_axi_bid => cpu_1_axi_full_bid,
ip_m_axi_bresp => cpu_1_axi_full_bresp,
ip_m_axi_bvalid => cpu_1_axi_full_bvalid,
ip_m_axi_bready => cpu_1_axi_full_bready,
ip_m_axi_arid => cpu_1_axi_full_arid,
ip_m_axi_araddr => cpu_1_axi_full_araddr,
ip_m_axi_arlen => cpu_1_axi_full_arlen,
ip_m_axi_arsize => cpu_1_axi_full_arsize,
ip_m_axi_arburst => cpu_1_axi_full_arburst,
ip_m_axi_arlock => cpu_1_axi_full_arlock,
ip_m_axi_arcache => cpu_1_axi_full_arcache,
ip_m_axi_arprot => cpu_1_axi_full_arprot,
ip_m_axi_arqos => cpu_1_axi_full_arqos,
ip_m_axi_arregion => cpu_1_axi_full_arregion,
ip_m_axi_arvalid => cpu_1_axi_full_arvalid,
ip_m_axi_arready => cpu_1_axi_full_arready,
ip_m_axi_rid => cpu_1_axi_full_rid,
ip_m_axi_rdata => cpu_1_axi_full_rdata,
ip_m_axi_rresp => cpu_1_axi_full_rresp,
ip_m_axi_rlast => cpu_1_axi_full_rlast,
ip_m_axi_rvalid => cpu_1_axi_full_rvalid,
ip_m_axi_rready => cpu_1_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_1_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_1_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_1_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_1_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_1_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_1_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_1_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_1_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_1_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_1_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_1_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_1_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_1_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_1_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_1_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_1_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_1_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_1_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_1_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_1_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_1_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_1_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_1_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_1_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_1_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_1_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_1_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_1_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_1_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_1_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_1_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_1_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_1_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_1_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_1_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_1_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_1_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_1_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_1_full_rready,
int_m_axi_awid => int_bus_1_full_awid,
int_m_axi_awaddr => int_bus_1_full_awaddr,
int_m_axi_awlen => int_bus_1_full_awlen,
int_m_axi_awsize => int_bus_1_full_awsize,
int_m_axi_awburst => int_bus_1_full_awburst,
int_m_axi_awlock => int_bus_1_full_awlock,
int_m_axi_awcache => int_bus_1_full_awcache,
int_m_axi_awprot => int_bus_1_full_awprot,
int_m_axi_awqos => int_bus_1_full_awqos,
int_m_axi_awregion => int_bus_1_full_awregion,
int_m_axi_awvalid => int_bus_1_full_awvalid,
int_m_axi_awready => int_bus_1_full_awready,
int_m_axi_wdata => int_bus_1_full_wdata,
int_m_axi_wstrb => int_bus_1_full_wstrb,
int_m_axi_wlast => int_bus_1_full_wlast,
int_m_axi_wvalid => int_bus_1_full_wvalid,
int_m_axi_wready => int_bus_1_full_wready,
int_m_axi_bid => int_bus_1_full_bid,
int_m_axi_bresp => int_bus_1_full_bresp,
int_m_axi_bvalid => int_bus_1_full_bvalid,
int_m_axi_bready => int_bus_1_full_bready,
int_m_axi_arid => int_bus_1_full_arid,
int_m_axi_araddr => int_bus_1_full_araddr,
int_m_axi_arlen => int_bus_1_full_arlen,
int_m_axi_arsize => int_bus_1_full_arsize,
int_m_axi_arburst => int_bus_1_full_arburst,
int_m_axi_arlock => int_bus_1_full_arlock,
int_m_axi_arcache => int_bus_1_full_arcache,
int_m_axi_arprot => int_bus_1_full_arprot,
int_m_axi_arqos => int_bus_1_full_arqos,
int_m_axi_arregion => int_bus_1_full_arregion,
int_m_axi_arvalid => int_bus_1_full_arvalid,
int_m_axi_arready => int_bus_1_full_arready,
int_m_axi_rid => int_bus_1_full_rid,
int_m_axi_rdata => int_bus_1_full_rdata,
int_m_axi_rresp => int_bus_1_full_rresp,
int_m_axi_rlast => int_bus_1_full_rlast,
int_m_axi_rvalid => int_bus_1_full_rvalid,
int_m_axi_rready => int_bus_1_full_rready,
signal_m_axi_awid => signal_bus_1_full_awid,
signal_m_axi_awaddr => signal_bus_1_full_awaddr,
signal_m_axi_awlen => signal_bus_1_full_awlen,
signal_m_axi_awsize => signal_bus_1_full_awsize,
signal_m_axi_awburst => signal_bus_1_full_awburst,
signal_m_axi_awlock => signal_bus_1_full_awlock,
signal_m_axi_awcache => signal_bus_1_full_awcache,
signal_m_axi_awprot => signal_bus_1_full_awprot,
signal_m_axi_awqos => signal_bus_1_full_awqos,
signal_m_axi_awregion => signal_bus_1_full_awregion,
signal_m_axi_awvalid => signal_bus_1_full_awvalid,
signal_m_axi_awready => signal_bus_1_full_awready,
signal_m_axi_wdata => signal_bus_1_full_wdata,
signal_m_axi_wstrb => signal_bus_1_full_wstrb,
signal_m_axi_wlast => signal_bus_1_full_wlast,
signal_m_axi_wvalid => signal_bus_1_full_wvalid,
signal_m_axi_wready => signal_bus_1_full_wready,
signal_m_axi_bid => signal_bus_1_full_bid,
signal_m_axi_bresp => signal_bus_1_full_bresp,
signal_m_axi_bvalid => signal_bus_1_full_bvalid,
signal_m_axi_bready => signal_bus_1_full_bready,
signal_m_axi_arid => signal_bus_1_full_arid,
signal_m_axi_araddr => signal_bus_1_full_araddr,
signal_m_axi_arlen => signal_bus_1_full_arlen,
signal_m_axi_arsize => signal_bus_1_full_arsize,
signal_m_axi_arburst => signal_bus_1_full_arburst,
signal_m_axi_arlock => signal_bus_1_full_arlock,
signal_m_axi_arcache => signal_bus_1_full_arcache,
signal_m_axi_arprot => signal_bus_1_full_arprot,
signal_m_axi_arqos => signal_bus_1_full_arqos,
signal_m_axi_arregion => signal_bus_1_full_arregion,
signal_m_axi_arvalid => signal_bus_1_full_arvalid,
signal_m_axi_arready => signal_bus_1_full_arready,
signal_m_axi_rid => signal_bus_1_full_rid,
signal_m_axi_rdata => signal_bus_1_full_rdata,
signal_m_axi_rresp => signal_bus_1_full_rresp,
signal_m_axi_rlast => signal_bus_1_full_rlast,
signal_m_axi_rvalid => signal_bus_1_full_rvalid,
timer_m_axi_awid => timer_bus_1_full_awid,
timer_m_axi_awaddr => timer_bus_1_full_awaddr,
timer_m_axi_awlen => timer_bus_1_full_awlen,
timer_m_axi_awsize => timer_bus_1_full_awsize,
timer_m_axi_awburst => timer_bus_1_full_awburst,
timer_m_axi_awlock => timer_bus_1_full_awlock,
timer_m_axi_awcache => timer_bus_1_full_awcache,
timer_m_axi_awprot => timer_bus_1_full_awprot,
timer_m_axi_awqos => timer_bus_1_full_awqos,
timer_m_axi_awregion => timer_bus_1_full_awregion,
timer_m_axi_awvalid => timer_bus_1_full_awvalid,
timer_m_axi_awready => timer_bus_1_full_awready,
timer_m_axi_wdata => timer_bus_1_full_wdata,
timer_m_axi_wstrb => timer_bus_1_full_wstrb,
timer_m_axi_wlast => timer_bus_1_full_wlast,
timer_m_axi_wvalid => timer_bus_1_full_wvalid,
timer_m_axi_wready => timer_bus_1_full_wready,
timer_m_axi_bid => timer_bus_1_full_bid,
timer_m_axi_bresp => timer_bus_1_full_bresp,
timer_m_axi_bvalid => timer_bus_1_full_bvalid,
timer_m_axi_bready => timer_bus_1_full_bready,
timer_m_axi_arid => timer_bus_1_full_arid,
timer_m_axi_araddr => timer_bus_1_full_araddr,
timer_m_axi_arlen => timer_bus_1_full_arlen,
timer_m_axi_arsize => timer_bus_1_full_arsize,
timer_m_axi_arburst => timer_bus_1_full_arburst,
timer_m_axi_arlock => timer_bus_1_full_arlock,
timer_m_axi_arcache => timer_bus_1_full_arcache,
timer_m_axi_arprot => timer_bus_1_full_arprot,
timer_m_axi_arqos => timer_bus_1_full_arqos,
timer_m_axi_arregion => timer_bus_1_full_arregion,
timer_m_axi_arvalid => timer_bus_1_full_arvalid,
timer_m_axi_arready => timer_bus_1_full_arready,
timer_m_axi_rid => timer_bus_1_full_rid,
timer_m_axi_rdata => timer_bus_1_full_rdata,
timer_m_axi_rresp => timer_bus_1_full_rresp,
timer_m_axi_rlast => timer_bus_1_full_rlast,
timer_m_axi_rvalid => timer_bus_1_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
cpu_2_bus_inst : plasoc_cpu_2_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_2_full_awid,
cpu_s_axi_awaddr => cpu_bus_2_full_awaddr,
cpu_s_axi_awlen => cpu_bus_2_full_awlen,
cpu_s_axi_awsize => cpu_bus_2_full_awsize,
cpu_s_axi_awburst => cpu_bus_2_full_awburst,
cpu_s_axi_awlock => cpu_bus_2_full_awlock,
cpu_s_axi_awcache => cpu_bus_2_full_awcache,
cpu_s_axi_awprot => cpu_bus_2_full_awprot,
cpu_s_axi_awqos => cpu_bus_2_full_awqos,
cpu_s_axi_awregion => cpu_bus_2_full_awregion,
cpu_s_axi_awvalid => cpu_bus_2_full_awvalid,
cpu_s_axi_awready => cpu_bus_2_full_awready,
cpu_s_axi_wdata => cpu_bus_2_full_wdata,
cpu_s_axi_wstrb => cpu_bus_2_full_wstrb,
cpu_s_axi_wlast => cpu_bus_2_full_wlast,
cpu_s_axi_wvalid => cpu_bus_2_full_wvalid,
cpu_s_axi_wready => cpu_bus_2_full_wready,
cpu_s_axi_bid => cpu_bus_2_full_bid,
cpu_s_axi_bresp => cpu_bus_2_full_bresp,
cpu_s_axi_bvalid => cpu_bus_2_full_bvalid,
cpu_s_axi_bready => cpu_bus_2_full_bready,
cpu_s_axi_arid => cpu_bus_2_full_arid,
cpu_s_axi_araddr => cpu_bus_2_full_araddr,
cpu_s_axi_arlen => cpu_bus_2_full_arlen,
cpu_s_axi_arsize => cpu_bus_2_full_arsize,
cpu_s_axi_arburst => cpu_bus_2_full_arburst,
cpu_s_axi_arlock => cpu_bus_2_full_arlock,
cpu_s_axi_arcache => cpu_bus_2_full_arcache,
cpu_s_axi_arprot => cpu_bus_2_full_arprot,
cpu_s_axi_arqos => cpu_bus_2_full_arqos,
cpu_s_axi_arregion => cpu_bus_2_full_arregion,
cpu_s_axi_arvalid => cpu_bus_2_full_arvalid,
cpu_s_axi_arready => cpu_bus_2_full_arready,
cpu_s_axi_rid => cpu_bus_2_full_rid,
cpu_s_axi_rdata => cpu_bus_2_full_rdata,
cpu_s_axi_rresp => cpu_bus_2_full_rresp,
cpu_s_axi_rlast => cpu_bus_2_full_rlast,
cpu_s_axi_rvalid => cpu_bus_2_full_rvalid,
cpu_s_axi_rready => cpu_bus_2_full_rready,
ip_m_axi_awid => cpu_2_axi_full_awid,
ip_m_axi_awaddr => cpu_2_axi_full_awaddr,
ip_m_axi_awlen => cpu_2_axi_full_awlen,
ip_m_axi_awsize => cpu_2_axi_full_awsize,
ip_m_axi_awburst => cpu_2_axi_full_awburst,
ip_m_axi_awlock => cpu_2_axi_full_awlock,
ip_m_axi_awcache => cpu_2_axi_full_awcache,
ip_m_axi_awprot => cpu_2_axi_full_awprot,
ip_m_axi_awqos => cpu_2_axi_full_awqos,
ip_m_axi_awregion => cpu_2_axi_full_awregion,
ip_m_axi_awvalid => cpu_2_axi_full_awvalid,
ip_m_axi_awready => cpu_2_axi_full_awready,
ip_m_axi_wdata => cpu_2_axi_full_wdata,
ip_m_axi_wstrb => cpu_2_axi_full_wstrb,
ip_m_axi_wlast => cpu_2_axi_full_wlast,
ip_m_axi_wvalid => cpu_2_axi_full_wvalid,
ip_m_axi_wready => cpu_2_axi_full_wready,
ip_m_axi_bid => cpu_2_axi_full_bid,
ip_m_axi_bresp => cpu_2_axi_full_bresp,
ip_m_axi_bvalid => cpu_2_axi_full_bvalid,
ip_m_axi_bready => cpu_2_axi_full_bready,
ip_m_axi_arid => cpu_2_axi_full_arid,
ip_m_axi_araddr => cpu_2_axi_full_araddr,
ip_m_axi_arlen => cpu_2_axi_full_arlen,
ip_m_axi_arsize => cpu_2_axi_full_arsize,
ip_m_axi_arburst => cpu_2_axi_full_arburst,
ip_m_axi_arlock => cpu_2_axi_full_arlock,
ip_m_axi_arcache => cpu_2_axi_full_arcache,
ip_m_axi_arprot => cpu_2_axi_full_arprot,
ip_m_axi_arqos => cpu_2_axi_full_arqos,
ip_m_axi_arregion => cpu_2_axi_full_arregion,
ip_m_axi_arvalid => cpu_2_axi_full_arvalid,
ip_m_axi_arready => cpu_2_axi_full_arready,
ip_m_axi_rid => cpu_2_axi_full_rid,
ip_m_axi_rdata => cpu_2_axi_full_rdata,
ip_m_axi_rresp => cpu_2_axi_full_rresp,
ip_m_axi_rlast => cpu_2_axi_full_rlast,
ip_m_axi_rvalid => cpu_2_axi_full_rvalid,
ip_m_axi_rready => cpu_2_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_2_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_2_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_2_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_2_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_2_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_2_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_2_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_2_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_2_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_2_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_2_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_2_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_2_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_2_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_2_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_2_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_2_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_2_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_2_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_2_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_2_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_2_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_2_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_2_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_2_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_2_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_2_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_2_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_2_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_2_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_2_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_2_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_2_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_2_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_2_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_2_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_2_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_2_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_2_full_rready,
int_m_axi_awid => int_bus_2_full_awid,
int_m_axi_awaddr => int_bus_2_full_awaddr,
int_m_axi_awlen => int_bus_2_full_awlen,
int_m_axi_awsize => int_bus_2_full_awsize,
int_m_axi_awburst => int_bus_2_full_awburst,
int_m_axi_awlock => int_bus_2_full_awlock,
int_m_axi_awcache => int_bus_2_full_awcache,
int_m_axi_awprot => int_bus_2_full_awprot,
int_m_axi_awqos => int_bus_2_full_awqos,
int_m_axi_awregion => int_bus_2_full_awregion,
int_m_axi_awvalid => int_bus_2_full_awvalid,
int_m_axi_awready => int_bus_2_full_awready,
int_m_axi_wdata => int_bus_2_full_wdata,
int_m_axi_wstrb => int_bus_2_full_wstrb,
int_m_axi_wlast => int_bus_2_full_wlast,
int_m_axi_wvalid => int_bus_2_full_wvalid,
int_m_axi_wready => int_bus_2_full_wready,
int_m_axi_bid => int_bus_2_full_bid,
int_m_axi_bresp => int_bus_2_full_bresp,
int_m_axi_bvalid => int_bus_2_full_bvalid,
int_m_axi_bready => int_bus_2_full_bready,
int_m_axi_arid => int_bus_2_full_arid,
int_m_axi_araddr => int_bus_2_full_araddr,
int_m_axi_arlen => int_bus_2_full_arlen,
int_m_axi_arsize => int_bus_2_full_arsize,
int_m_axi_arburst => int_bus_2_full_arburst,
int_m_axi_arlock => int_bus_2_full_arlock,
int_m_axi_arcache => int_bus_2_full_arcache,
int_m_axi_arprot => int_bus_2_full_arprot,
int_m_axi_arqos => int_bus_2_full_arqos,
int_m_axi_arregion => int_bus_2_full_arregion,
int_m_axi_arvalid => int_bus_2_full_arvalid,
int_m_axi_arready => int_bus_2_full_arready,
int_m_axi_rid => int_bus_2_full_rid,
int_m_axi_rdata => int_bus_2_full_rdata,
int_m_axi_rresp => int_bus_2_full_rresp,
int_m_axi_rlast => int_bus_2_full_rlast,
int_m_axi_rvalid => int_bus_2_full_rvalid,
int_m_axi_rready => int_bus_2_full_rready,
signal_m_axi_awid => signal_bus_2_full_awid,
signal_m_axi_awaddr => signal_bus_2_full_awaddr,
signal_m_axi_awlen => signal_bus_2_full_awlen,
signal_m_axi_awsize => signal_bus_2_full_awsize,
signal_m_axi_awburst => signal_bus_2_full_awburst,
signal_m_axi_awlock => signal_bus_2_full_awlock,
signal_m_axi_awcache => signal_bus_2_full_awcache,
signal_m_axi_awprot => signal_bus_2_full_awprot,
signal_m_axi_awqos => signal_bus_2_full_awqos,
signal_m_axi_awregion => signal_bus_2_full_awregion,
signal_m_axi_awvalid => signal_bus_2_full_awvalid,
signal_m_axi_awready => signal_bus_2_full_awready,
signal_m_axi_wdata => signal_bus_2_full_wdata,
signal_m_axi_wstrb => signal_bus_2_full_wstrb,
signal_m_axi_wlast => signal_bus_2_full_wlast,
signal_m_axi_wvalid => signal_bus_2_full_wvalid,
signal_m_axi_wready => signal_bus_2_full_wready,
signal_m_axi_bid => signal_bus_2_full_bid,
signal_m_axi_bresp => signal_bus_2_full_bresp,
signal_m_axi_bvalid => signal_bus_2_full_bvalid,
signal_m_axi_bready => signal_bus_2_full_bready,
signal_m_axi_arid => signal_bus_2_full_arid,
signal_m_axi_araddr => signal_bus_2_full_araddr,
signal_m_axi_arlen => signal_bus_2_full_arlen,
signal_m_axi_arsize => signal_bus_2_full_arsize,
signal_m_axi_arburst => signal_bus_2_full_arburst,
signal_m_axi_arlock => signal_bus_2_full_arlock,
signal_m_axi_arcache => signal_bus_2_full_arcache,
signal_m_axi_arprot => signal_bus_2_full_arprot,
signal_m_axi_arqos => signal_bus_2_full_arqos,
signal_m_axi_arregion => signal_bus_2_full_arregion,
signal_m_axi_arvalid => signal_bus_2_full_arvalid,
signal_m_axi_arready => signal_bus_2_full_arready,
signal_m_axi_rid => signal_bus_2_full_rid,
signal_m_axi_rdata => signal_bus_2_full_rdata,
signal_m_axi_rresp => signal_bus_2_full_rresp,
signal_m_axi_rlast => signal_bus_2_full_rlast,
signal_m_axi_rvalid => signal_bus_2_full_rvalid,
timer_m_axi_awid => timer_bus_2_full_awid,
timer_m_axi_awaddr => timer_bus_2_full_awaddr,
timer_m_axi_awlen => timer_bus_2_full_awlen,
timer_m_axi_awsize => timer_bus_2_full_awsize,
timer_m_axi_awburst => timer_bus_2_full_awburst,
timer_m_axi_awlock => timer_bus_2_full_awlock,
timer_m_axi_awcache => timer_bus_2_full_awcache,
timer_m_axi_awprot => timer_bus_2_full_awprot,
timer_m_axi_awqos => timer_bus_2_full_awqos,
timer_m_axi_awregion => timer_bus_2_full_awregion,
timer_m_axi_awvalid => timer_bus_2_full_awvalid,
timer_m_axi_awready => timer_bus_2_full_awready,
timer_m_axi_wdata => timer_bus_2_full_wdata,
timer_m_axi_wstrb => timer_bus_2_full_wstrb,
timer_m_axi_wlast => timer_bus_2_full_wlast,
timer_m_axi_wvalid => timer_bus_2_full_wvalid,
timer_m_axi_wready => timer_bus_2_full_wready,
timer_m_axi_bid => timer_bus_2_full_bid,
timer_m_axi_bresp => timer_bus_2_full_bresp,
timer_m_axi_bvalid => timer_bus_2_full_bvalid,
timer_m_axi_bready => timer_bus_2_full_bready,
timer_m_axi_arid => timer_bus_2_full_arid,
timer_m_axi_araddr => timer_bus_2_full_araddr,
timer_m_axi_arlen => timer_bus_2_full_arlen,
timer_m_axi_arsize => timer_bus_2_full_arsize,
timer_m_axi_arburst => timer_bus_2_full_arburst,
timer_m_axi_arlock => timer_bus_2_full_arlock,
timer_m_axi_arcache => timer_bus_2_full_arcache,
timer_m_axi_arprot => timer_bus_2_full_arprot,
timer_m_axi_arqos => timer_bus_2_full_arqos,
timer_m_axi_arregion => timer_bus_2_full_arregion,
timer_m_axi_arvalid => timer_bus_2_full_arvalid,
timer_m_axi_arready => timer_bus_2_full_arready,
timer_m_axi_rid => timer_bus_2_full_rid,
timer_m_axi_rdata => timer_bus_2_full_rdata,
timer_m_axi_rresp => timer_bus_2_full_rresp,
timer_m_axi_rlast => timer_bus_2_full_rlast,
timer_m_axi_rvalid => timer_bus_2_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
------------------------
-- CPU Instantiations --
------------------------
plasoc_cpu_0_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_0_full_awid,
axi_awaddr => cpu_bus_0_full_awaddr,
axi_awlen => cpu_bus_0_full_awlen,
axi_awsize => cpu_bus_0_full_awsize,
axi_awburst => cpu_bus_0_full_awburst,
axi_awlock => cpu_bus_0_full_awlock,
axi_awcache => cpu_bus_0_full_awcache,
axi_awprot => cpu_bus_0_full_awprot,
axi_awqos => cpu_bus_0_full_awqos,
axi_awregion => cpu_bus_0_full_awregion,
axi_awvalid => cpu_bus_0_full_awvalid,
axi_awready => cpu_bus_0_full_awready,
axi_wdata => cpu_bus_0_full_wdata,
axi_wstrb => cpu_bus_0_full_wstrb,
axi_wlast => cpu_bus_0_full_wlast,
axi_wvalid => cpu_bus_0_full_wvalid,
axi_wready => cpu_bus_0_full_wready,
axi_bid => cpu_bus_0_full_bid,
axi_bresp => cpu_bus_0_full_bresp,
axi_bvalid => cpu_bus_0_full_bvalid,
axi_bready => cpu_bus_0_full_bready,
axi_arid => cpu_bus_0_full_arid,
axi_araddr => cpu_bus_0_full_araddr,
axi_arlen => cpu_bus_0_full_arlen,
axi_arsize => cpu_bus_0_full_arsize,
axi_arburst => cpu_bus_0_full_arburst,
axi_arlock => cpu_bus_0_full_arlock,
axi_arcache => cpu_bus_0_full_arcache,
axi_arprot => cpu_bus_0_full_arprot,
axi_arqos => cpu_bus_0_full_arqos,
axi_arregion => cpu_bus_0_full_arregion,
axi_arvalid => cpu_bus_0_full_arvalid,
axi_arready => cpu_bus_0_full_arready,
axi_rid => cpu_bus_0_full_rid,
axi_rdata => cpu_bus_0_full_rdata,
axi_rresp => cpu_bus_0_full_rresp,
axi_rlast => cpu_bus_0_full_rlast,
axi_rvalid => cpu_bus_0_full_rvalid,
axi_rready => cpu_bus_0_full_rready,
intr_in => cpu_0_int);
plasoc_cpu_1_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_1_full_awid,
axi_awaddr => cpu_bus_1_full_awaddr,
axi_awlen => cpu_bus_1_full_awlen,
axi_awsize => cpu_bus_1_full_awsize,
axi_awburst => cpu_bus_1_full_awburst,
axi_awlock => cpu_bus_1_full_awlock,
axi_awcache => cpu_bus_1_full_awcache,
axi_awprot => cpu_bus_1_full_awprot,
axi_awqos => cpu_bus_1_full_awqos,
axi_awregion => cpu_bus_1_full_awregion,
axi_awvalid => cpu_bus_1_full_awvalid,
axi_awready => cpu_bus_1_full_awready,
axi_wdata => cpu_bus_1_full_wdata,
axi_wstrb => cpu_bus_1_full_wstrb,
axi_wlast => cpu_bus_1_full_wlast,
axi_wvalid => cpu_bus_1_full_wvalid,
axi_wready => cpu_bus_1_full_wready,
axi_bid => cpu_bus_1_full_bid,
axi_bresp => cpu_bus_1_full_bresp,
axi_bvalid => cpu_bus_1_full_bvalid,
axi_bready => cpu_bus_1_full_bready,
axi_arid => cpu_bus_1_full_arid,
axi_araddr => cpu_bus_1_full_araddr,
axi_arlen => cpu_bus_1_full_arlen,
axi_arsize => cpu_bus_1_full_arsize,
axi_arburst => cpu_bus_1_full_arburst,
axi_arlock => cpu_bus_1_full_arlock,
axi_arcache => cpu_bus_1_full_arcache,
axi_arprot => cpu_bus_1_full_arprot,
axi_arqos => cpu_bus_1_full_arqos,
axi_arregion => cpu_bus_1_full_arregion,
axi_arvalid => cpu_bus_1_full_arvalid,
axi_arready => cpu_bus_1_full_arready,
axi_rid => cpu_bus_1_full_rid,
axi_rdata => cpu_bus_1_full_rdata,
axi_rresp => cpu_bus_1_full_rresp,
axi_rlast => cpu_bus_1_full_rlast,
axi_rvalid => cpu_bus_1_full_rvalid,
axi_rready => cpu_bus_1_full_rready,
intr_in => cpu_1_int);
plasoc_cpu_2_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_2_full_awid,
axi_awaddr => cpu_bus_2_full_awaddr,
axi_awlen => cpu_bus_2_full_awlen,
axi_awsize => cpu_bus_2_full_awsize,
axi_awburst => cpu_bus_2_full_awburst,
axi_awlock => cpu_bus_2_full_awlock,
axi_awcache => cpu_bus_2_full_awcache,
axi_awprot => cpu_bus_2_full_awprot,
axi_awqos => cpu_bus_2_full_awqos,
axi_awregion => cpu_bus_2_full_awregion,
axi_awvalid => cpu_bus_2_full_awvalid,
axi_awready => cpu_bus_2_full_awready,
axi_wdata => cpu_bus_2_full_wdata,
axi_wstrb => cpu_bus_2_full_wstrb,
axi_wlast => cpu_bus_2_full_wlast,
axi_wvalid => cpu_bus_2_full_wvalid,
axi_wready => cpu_bus_2_full_wready,
axi_bid => cpu_bus_2_full_bid,
axi_bresp => cpu_bus_2_full_bresp,
axi_bvalid => cpu_bus_2_full_bvalid,
axi_bready => cpu_bus_2_full_bready,
axi_arid => cpu_bus_2_full_arid,
axi_araddr => cpu_bus_2_full_araddr,
axi_arlen => cpu_bus_2_full_arlen,
axi_arsize => cpu_bus_2_full_arsize,
axi_arburst => cpu_bus_2_full_arburst,
axi_arlock => cpu_bus_2_full_arlock,
axi_arcache => cpu_bus_2_full_arcache,
axi_arprot => cpu_bus_2_full_arprot,
axi_arqos => cpu_bus_2_full_arqos,
axi_arregion => cpu_bus_2_full_arregion,
axi_arvalid => cpu_bus_2_full_arvalid,
axi_arready => cpu_bus_2_full_arready,
axi_rid => cpu_bus_2_full_rid,
axi_rdata => cpu_bus_2_full_rdata,
axi_rresp => cpu_bus_2_full_rresp,
axi_rlast => cpu_bus_2_full_rlast,
axi_rvalid => cpu_bus_2_full_rvalid,
axi_rready => cpu_bus_2_full_rready,
intr_in => cpu_2_int);
---------------------------------------------
-- CPUID GPIO AXI Full2Lite Instantiations --
---------------------------------------------
cpuid_gpio_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_0_full_awid,
s_axi_awaddr => cpuid_gpio_bus_0_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_0_full_awlen,
s_axi_awsize => cpuid_gpio_bus_0_full_awsize,
s_axi_awburst => cpuid_gpio_bus_0_full_awburst,
s_axi_awlock => cpuid_gpio_bus_0_full_awlock,
s_axi_awcache => cpuid_gpio_bus_0_full_awcache,
s_axi_awprot => cpuid_gpio_bus_0_full_awprot,
s_axi_awqos => cpuid_gpio_bus_0_full_awqos,
s_axi_awregion => cpuid_gpio_bus_0_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_0_full_awvalid,
s_axi_awready => cpuid_gpio_bus_0_full_awready,
s_axi_wdata => cpuid_gpio_bus_0_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_0_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_0_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_0_full_wvalid,
s_axi_wready => cpuid_gpio_bus_0_full_wready,
s_axi_bid => cpuid_gpio_bus_0_full_bid,
s_axi_bresp => cpuid_gpio_bus_0_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_0_full_bvalid,
s_axi_bready => cpuid_gpio_bus_0_full_bready,
s_axi_arid => cpuid_gpio_bus_0_full_arid,
s_axi_araddr => cpuid_gpio_bus_0_full_araddr,
s_axi_arlen => cpuid_gpio_bus_0_full_arlen,
s_axi_arsize => cpuid_gpio_bus_0_full_arsize,
s_axi_arburst => cpuid_gpio_bus_0_full_arburst,
s_axi_arlock => cpuid_gpio_bus_0_full_arlock,
s_axi_arcache => cpuid_gpio_bus_0_full_arcache,
s_axi_arprot => cpuid_gpio_bus_0_full_arprot,
s_axi_arqos => cpuid_gpio_bus_0_full_arqos,
s_axi_arregion => cpuid_gpio_bus_0_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_0_full_arvalid,
s_axi_arready => cpuid_gpio_bus_0_full_arready,
s_axi_rid => cpuid_gpio_bus_0_full_rid,
s_axi_rdata => cpuid_gpio_bus_0_full_rdata,
s_axi_rresp => cpuid_gpio_bus_0_full_rresp,
s_axi_rlast => cpuid_gpio_bus_0_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_0_full_rvalid,
s_axi_rready => cpuid_gpio_bus_0_full_rready,
m_axi_awaddr => cpuid_gpio_bus_0_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_0_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_0_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_0_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_0_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_0_lite_wready,
m_axi_wdata => cpuid_gpio_bus_0_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_0_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_0_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_0_lite_bready,
m_axi_bresp => cpuid_gpio_bus_0_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_0_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_0_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_0_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_0_lite_arready,
m_axi_rdata => cpuid_gpio_bus_0_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_0_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_0_lite_rready,
m_axi_rresp => cpuid_gpio_bus_0_lite_rresp);
cpuid_gpio_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_1_full_awid,
s_axi_awaddr => cpuid_gpio_bus_1_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_1_full_awlen,
s_axi_awsize => cpuid_gpio_bus_1_full_awsize,
s_axi_awburst => cpuid_gpio_bus_1_full_awburst,
s_axi_awlock => cpuid_gpio_bus_1_full_awlock,
s_axi_awcache => cpuid_gpio_bus_1_full_awcache,
s_axi_awprot => cpuid_gpio_bus_1_full_awprot,
s_axi_awqos => cpuid_gpio_bus_1_full_awqos,
s_axi_awregion => cpuid_gpio_bus_1_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_1_full_awvalid,
s_axi_awready => cpuid_gpio_bus_1_full_awready,
s_axi_wdata => cpuid_gpio_bus_1_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_1_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_1_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_1_full_wvalid,
s_axi_wready => cpuid_gpio_bus_1_full_wready,
s_axi_bid => cpuid_gpio_bus_1_full_bid,
s_axi_bresp => cpuid_gpio_bus_1_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_1_full_bvalid,
s_axi_bready => cpuid_gpio_bus_1_full_bready,
s_axi_arid => cpuid_gpio_bus_1_full_arid,
s_axi_araddr => cpuid_gpio_bus_1_full_araddr,
s_axi_arlen => cpuid_gpio_bus_1_full_arlen,
s_axi_arsize => cpuid_gpio_bus_1_full_arsize,
s_axi_arburst => cpuid_gpio_bus_1_full_arburst,
s_axi_arlock => cpuid_gpio_bus_1_full_arlock,
s_axi_arcache => cpuid_gpio_bus_1_full_arcache,
s_axi_arprot => cpuid_gpio_bus_1_full_arprot,
s_axi_arqos => cpuid_gpio_bus_1_full_arqos,
s_axi_arregion => cpuid_gpio_bus_1_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_1_full_arvalid,
s_axi_arready => cpuid_gpio_bus_1_full_arready,
s_axi_rid => cpuid_gpio_bus_1_full_rid,
s_axi_rdata => cpuid_gpio_bus_1_full_rdata,
s_axi_rresp => cpuid_gpio_bus_1_full_rresp,
s_axi_rlast => cpuid_gpio_bus_1_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_1_full_rvalid,
s_axi_rready => cpuid_gpio_bus_1_full_rready,
m_axi_awaddr => cpuid_gpio_bus_1_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_1_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_1_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_1_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_1_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_1_lite_wready,
m_axi_wdata => cpuid_gpio_bus_1_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_1_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_1_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_1_lite_bready,
m_axi_bresp => cpuid_gpio_bus_1_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_1_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_1_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_1_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_1_lite_arready,
m_axi_rdata => cpuid_gpio_bus_1_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_1_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_1_lite_rready,
m_axi_rresp => cpuid_gpio_bus_1_lite_rresp);
cpuid_gpio_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_2_full_awid,
s_axi_awaddr => cpuid_gpio_bus_2_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_2_full_awlen,
s_axi_awsize => cpuid_gpio_bus_2_full_awsize,
s_axi_awburst => cpuid_gpio_bus_2_full_awburst,
s_axi_awlock => cpuid_gpio_bus_2_full_awlock,
s_axi_awcache => cpuid_gpio_bus_2_full_awcache,
s_axi_awprot => cpuid_gpio_bus_2_full_awprot,
s_axi_awqos => cpuid_gpio_bus_2_full_awqos,
s_axi_awregion => cpuid_gpio_bus_2_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_2_full_awvalid,
s_axi_awready => cpuid_gpio_bus_2_full_awready,
s_axi_wdata => cpuid_gpio_bus_2_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_2_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_2_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_2_full_wvalid,
s_axi_wready => cpuid_gpio_bus_2_full_wready,
s_axi_bid => cpuid_gpio_bus_2_full_bid,
s_axi_bresp => cpuid_gpio_bus_2_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_2_full_bvalid,
s_axi_bready => cpuid_gpio_bus_2_full_bready,
s_axi_arid => cpuid_gpio_bus_2_full_arid,
s_axi_araddr => cpuid_gpio_bus_2_full_araddr,
s_axi_arlen => cpuid_gpio_bus_2_full_arlen,
s_axi_arsize => cpuid_gpio_bus_2_full_arsize,
s_axi_arburst => cpuid_gpio_bus_2_full_arburst,
s_axi_arlock => cpuid_gpio_bus_2_full_arlock,
s_axi_arcache => cpuid_gpio_bus_2_full_arcache,
s_axi_arprot => cpuid_gpio_bus_2_full_arprot,
s_axi_arqos => cpuid_gpio_bus_2_full_arqos,
s_axi_arregion => cpuid_gpio_bus_2_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_2_full_arvalid,
s_axi_arready => cpuid_gpio_bus_2_full_arready,
s_axi_rid => cpuid_gpio_bus_2_full_rid,
s_axi_rdata => cpuid_gpio_bus_2_full_rdata,
s_axi_rresp => cpuid_gpio_bus_2_full_rresp,
s_axi_rlast => cpuid_gpio_bus_2_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_2_full_rvalid,
s_axi_rready => cpuid_gpio_bus_2_full_rready,
m_axi_awaddr => cpuid_gpio_bus_2_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_2_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_2_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_2_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_2_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_2_lite_wready,
m_axi_wdata => cpuid_gpio_bus_2_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_2_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_2_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_2_lite_bready,
m_axi_bresp => cpuid_gpio_bus_2_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_2_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_2_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_2_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_2_lite_arready,
m_axi_rdata => cpuid_gpio_bus_2_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_2_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_2_lite_rready,
m_axi_rresp => cpuid_gpio_bus_2_lite_rresp);
------------------------------------------
-- CPU INT AXI Full2Lite Instantiations --
------------------------------------------
int_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_0_full_awid,
s_axi_awaddr => int_bus_0_full_awaddr,
s_axi_awlen => int_bus_0_full_awlen,
s_axi_awsize => int_bus_0_full_awsize,
s_axi_awburst => int_bus_0_full_awburst,
s_axi_awlock => int_bus_0_full_awlock,
s_axi_awcache => int_bus_0_full_awcache,
s_axi_awprot => int_bus_0_full_awprot,
s_axi_awqos => int_bus_0_full_awqos,
s_axi_awregion => int_bus_0_full_awregion,
s_axi_awvalid => int_bus_0_full_awvalid,
s_axi_awready => int_bus_0_full_awready,
s_axi_wdata => int_bus_0_full_wdata,
s_axi_wstrb => int_bus_0_full_wstrb,
s_axi_wlast => int_bus_0_full_wlast,
s_axi_wvalid => int_bus_0_full_wvalid,
s_axi_wready => int_bus_0_full_wready,
s_axi_bid => int_bus_0_full_bid,
s_axi_bresp => int_bus_0_full_bresp,
s_axi_bvalid => int_bus_0_full_bvalid,
s_axi_bready => int_bus_0_full_bready,
s_axi_arid => int_bus_0_full_arid,
s_axi_araddr => int_bus_0_full_araddr,
s_axi_arlen => int_bus_0_full_arlen,
s_axi_arsize => int_bus_0_full_arsize,
s_axi_arburst => int_bus_0_full_arburst,
s_axi_arlock => int_bus_0_full_arlock,
s_axi_arcache => int_bus_0_full_arcache,
s_axi_arprot => int_bus_0_full_arprot,
s_axi_arqos => int_bus_0_full_arqos,
s_axi_arregion => int_bus_0_full_arregion,
s_axi_arvalid => int_bus_0_full_arvalid,
s_axi_arready => int_bus_0_full_arready,
s_axi_rid => int_bus_0_full_rid,
s_axi_rdata => int_bus_0_full_rdata,
s_axi_rresp => int_bus_0_full_rresp,
s_axi_rlast => int_bus_0_full_rlast,
s_axi_rvalid => int_bus_0_full_rvalid,
s_axi_rready => int_bus_0_full_rready,
m_axi_awaddr => int_bus_0_lite_awaddr,
m_axi_awprot => int_bus_0_lite_awprot,
m_axi_awvalid => int_bus_0_lite_awvalid,
m_axi_awready => int_bus_0_lite_awready,
m_axi_wvalid => int_bus_0_lite_wvalid,
m_axi_wready => int_bus_0_lite_wready,
m_axi_wdata => int_bus_0_lite_wdata,
m_axi_wstrb => int_bus_0_lite_wstrb,
m_axi_bvalid => int_bus_0_lite_bvalid,
m_axi_bready => int_bus_0_lite_bready,
m_axi_bresp => int_bus_0_lite_bresp,
m_axi_araddr => int_bus_0_lite_araddr,
m_axi_arprot => int_bus_0_lite_arprot,
m_axi_arvalid => int_bus_0_lite_arvalid,
m_axi_arready => int_bus_0_lite_arready,
m_axi_rdata => int_bus_0_lite_rdata,
m_axi_rvalid => int_bus_0_lite_rvalid,
m_axi_rready => int_bus_0_lite_rready,
m_axi_rresp => int_bus_0_lite_rresp);
int_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_1_full_awid,
s_axi_awaddr => int_bus_1_full_awaddr,
s_axi_awlen => int_bus_1_full_awlen,
s_axi_awsize => int_bus_1_full_awsize,
s_axi_awburst => int_bus_1_full_awburst,
s_axi_awlock => int_bus_1_full_awlock,
s_axi_awcache => int_bus_1_full_awcache,
s_axi_awprot => int_bus_1_full_awprot,
s_axi_awqos => int_bus_1_full_awqos,
s_axi_awregion => int_bus_1_full_awregion,
s_axi_awvalid => int_bus_1_full_awvalid,
s_axi_awready => int_bus_1_full_awready,
s_axi_wdata => int_bus_1_full_wdata,
s_axi_wstrb => int_bus_1_full_wstrb,
s_axi_wlast => int_bus_1_full_wlast,
s_axi_wvalid => int_bus_1_full_wvalid,
s_axi_wready => int_bus_1_full_wready,
s_axi_bid => int_bus_1_full_bid,
s_axi_bresp => int_bus_1_full_bresp,
s_axi_bvalid => int_bus_1_full_bvalid,
s_axi_bready => int_bus_1_full_bready,
s_axi_arid => int_bus_1_full_arid,
s_axi_araddr => int_bus_1_full_araddr,
s_axi_arlen => int_bus_1_full_arlen,
s_axi_arsize => int_bus_1_full_arsize,
s_axi_arburst => int_bus_1_full_arburst,
s_axi_arlock => int_bus_1_full_arlock,
s_axi_arcache => int_bus_1_full_arcache,
s_axi_arprot => int_bus_1_full_arprot,
s_axi_arqos => int_bus_1_full_arqos,
s_axi_arregion => int_bus_1_full_arregion,
s_axi_arvalid => int_bus_1_full_arvalid,
s_axi_arready => int_bus_1_full_arready,
s_axi_rid => int_bus_1_full_rid,
s_axi_rdata => int_bus_1_full_rdata,
s_axi_rresp => int_bus_1_full_rresp,
s_axi_rlast => int_bus_1_full_rlast,
s_axi_rvalid => int_bus_1_full_rvalid,
s_axi_rready => int_bus_1_full_rready,
m_axi_awaddr => int_bus_1_lite_awaddr,
m_axi_awprot => int_bus_1_lite_awprot,
m_axi_awvalid => int_bus_1_lite_awvalid,
m_axi_awready => int_bus_1_lite_awready,
m_axi_wvalid => int_bus_1_lite_wvalid,
m_axi_wready => int_bus_1_lite_wready,
m_axi_wdata => int_bus_1_lite_wdata,
m_axi_wstrb => int_bus_1_lite_wstrb,
m_axi_bvalid => int_bus_1_lite_bvalid,
m_axi_bready => int_bus_1_lite_bready,
m_axi_bresp => int_bus_1_lite_bresp,
m_axi_araddr => int_bus_1_lite_araddr,
m_axi_arprot => int_bus_1_lite_arprot,
m_axi_arvalid => int_bus_1_lite_arvalid,
m_axi_arready => int_bus_1_lite_arready,
m_axi_rdata => int_bus_1_lite_rdata,
m_axi_rvalid => int_bus_1_lite_rvalid,
m_axi_rready => int_bus_1_lite_rready,
m_axi_rresp => int_bus_1_lite_rresp);
int_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_2_full_awid,
s_axi_awaddr => int_bus_2_full_awaddr,
s_axi_awlen => int_bus_2_full_awlen,
s_axi_awsize => int_bus_2_full_awsize,
s_axi_awburst => int_bus_2_full_awburst,
s_axi_awlock => int_bus_2_full_awlock,
s_axi_awcache => int_bus_2_full_awcache,
s_axi_awprot => int_bus_2_full_awprot,
s_axi_awqos => int_bus_2_full_awqos,
s_axi_awregion => int_bus_2_full_awregion,
s_axi_awvalid => int_bus_2_full_awvalid,
s_axi_awready => int_bus_2_full_awready,
s_axi_wdata => int_bus_2_full_wdata,
s_axi_wstrb => int_bus_2_full_wstrb,
s_axi_wlast => int_bus_2_full_wlast,
s_axi_wvalid => int_bus_2_full_wvalid,
s_axi_wready => int_bus_2_full_wready,
s_axi_bid => int_bus_2_full_bid,
s_axi_bresp => int_bus_2_full_bresp,
s_axi_bvalid => int_bus_2_full_bvalid,
s_axi_bready => int_bus_2_full_bready,
s_axi_arid => int_bus_2_full_arid,
s_axi_araddr => int_bus_2_full_araddr,
s_axi_arlen => int_bus_2_full_arlen,
s_axi_arsize => int_bus_2_full_arsize,
s_axi_arburst => int_bus_2_full_arburst,
s_axi_arlock => int_bus_2_full_arlock,
s_axi_arcache => int_bus_2_full_arcache,
s_axi_arprot => int_bus_2_full_arprot,
s_axi_arqos => int_bus_2_full_arqos,
s_axi_arregion => int_bus_2_full_arregion,
s_axi_arvalid => int_bus_2_full_arvalid,
s_axi_arready => int_bus_2_full_arready,
s_axi_rid => int_bus_2_full_rid,
s_axi_rdata => int_bus_2_full_rdata,
s_axi_rresp => int_bus_2_full_rresp,
s_axi_rlast => int_bus_2_full_rlast,
s_axi_rvalid => int_bus_2_full_rvalid,
s_axi_rready => int_bus_2_full_rready,
m_axi_awaddr => int_bus_2_lite_awaddr,
m_axi_awprot => int_bus_2_lite_awprot,
m_axi_awvalid => int_bus_2_lite_awvalid,
m_axi_awready => int_bus_2_lite_awready,
m_axi_wvalid => int_bus_2_lite_wvalid,
m_axi_wready => int_bus_2_lite_wready,
m_axi_wdata => int_bus_2_lite_wdata,
m_axi_wstrb => int_bus_2_lite_wstrb,
m_axi_bvalid => int_bus_2_lite_bvalid,
m_axi_bready => int_bus_2_lite_bready,
m_axi_bresp => int_bus_2_lite_bresp,
m_axi_araddr => int_bus_2_lite_araddr,
m_axi_arprot => int_bus_2_lite_arprot,
m_axi_arvalid => int_bus_2_lite_arvalid,
m_axi_arready => int_bus_2_lite_arready,
m_axi_rdata => int_bus_2_lite_rdata,
m_axi_rvalid => int_bus_2_lite_rvalid,
m_axi_rready => int_bus_2_lite_rready,
m_axi_rresp => int_bus_2_lite_rresp);
---------------------------------------------
-- CPU Signal AXI Full2Lite Instantiations --
---------------------------------------------
signal_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_0_full_awid,
s_axi_awaddr => signal_bus_0_full_awaddr,
s_axi_awlen => signal_bus_0_full_awlen,
s_axi_awsize => signal_bus_0_full_awsize,
s_axi_awburst => signal_bus_0_full_awburst,
s_axi_awlock => signal_bus_0_full_awlock,
s_axi_awcache => signal_bus_0_full_awcache,
s_axi_awprot => signal_bus_0_full_awprot,
s_axi_awqos => signal_bus_0_full_awqos,
s_axi_awregion => signal_bus_0_full_awregion,
s_axi_awvalid => signal_bus_0_full_awvalid,
s_axi_awready => signal_bus_0_full_awready,
s_axi_wdata => signal_bus_0_full_wdata,
s_axi_wstrb => signal_bus_0_full_wstrb,
s_axi_wlast => signal_bus_0_full_wlast,
s_axi_wvalid => signal_bus_0_full_wvalid,
s_axi_wready => signal_bus_0_full_wready,
s_axi_bid => signal_bus_0_full_bid,
s_axi_bresp => signal_bus_0_full_bresp,
s_axi_bvalid => signal_bus_0_full_bvalid,
s_axi_bready => signal_bus_0_full_bready,
s_axi_arid => signal_bus_0_full_arid,
s_axi_araddr => signal_bus_0_full_araddr,
s_axi_arlen => signal_bus_0_full_arlen,
s_axi_arsize => signal_bus_0_full_arsize,
s_axi_arburst => signal_bus_0_full_arburst,
s_axi_arlock => signal_bus_0_full_arlock,
s_axi_arcache => signal_bus_0_full_arcache,
s_axi_arprot => signal_bus_0_full_arprot,
s_axi_arqos => signal_bus_0_full_arqos,
s_axi_arregion => signal_bus_0_full_arregion,
s_axi_arvalid => signal_bus_0_full_arvalid,
s_axi_arready => signal_bus_0_full_arready,
s_axi_rid => signal_bus_0_full_rid,
s_axi_rdata => signal_bus_0_full_rdata,
s_axi_rresp => signal_bus_0_full_rresp,
s_axi_rlast => signal_bus_0_full_rlast,
s_axi_rvalid => signal_bus_0_full_rvalid,
s_axi_rready => signal_bus_0_full_rready,
m_axi_awaddr => signal_bus_0_lite_awaddr,
m_axi_awprot => signal_bus_0_lite_awprot,
m_axi_awvalid => signal_bus_0_lite_awvalid,
m_axi_awready => signal_bus_0_lite_awready,
m_axi_wvalid => signal_bus_0_lite_wvalid,
m_axi_wready => signal_bus_0_lite_wready,
m_axi_wdata => signal_bus_0_lite_wdata,
m_axi_wstrb => signal_bus_0_lite_wstrb,
m_axi_bvalid => signal_bus_0_lite_bvalid,
m_axi_bready => signal_bus_0_lite_bready,
m_axi_bresp => signal_bus_0_lite_bresp,
m_axi_araddr => signal_bus_0_lite_araddr,
m_axi_arprot => signal_bus_0_lite_arprot,
m_axi_arvalid => signal_bus_0_lite_arvalid,
m_axi_arready => signal_bus_0_lite_arready,
m_axi_rdata => signal_bus_0_lite_rdata,
m_axi_rvalid => signal_bus_0_lite_rvalid,
m_axi_rready => signal_bus_0_lite_rready,
m_axi_rresp => signal_bus_0_lite_rresp);
signal_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_1_full_awid,
s_axi_awaddr => signal_bus_1_full_awaddr,
s_axi_awlen => signal_bus_1_full_awlen,
s_axi_awsize => signal_bus_1_full_awsize,
s_axi_awburst => signal_bus_1_full_awburst,
s_axi_awlock => signal_bus_1_full_awlock,
s_axi_awcache => signal_bus_1_full_awcache,
s_axi_awprot => signal_bus_1_full_awprot,
s_axi_awqos => signal_bus_1_full_awqos,
s_axi_awregion => signal_bus_1_full_awregion,
s_axi_awvalid => signal_bus_1_full_awvalid,
s_axi_awready => signal_bus_1_full_awready,
s_axi_wdata => signal_bus_1_full_wdata,
s_axi_wstrb => signal_bus_1_full_wstrb,
s_axi_wlast => signal_bus_1_full_wlast,
s_axi_wvalid => signal_bus_1_full_wvalid,
s_axi_wready => signal_bus_1_full_wready,
s_axi_bid => signal_bus_1_full_bid,
s_axi_bresp => signal_bus_1_full_bresp,
s_axi_bvalid => signal_bus_1_full_bvalid,
s_axi_bready => signal_bus_1_full_bready,
s_axi_arid => signal_bus_1_full_arid,
s_axi_araddr => signal_bus_1_full_araddr,
s_axi_arlen => signal_bus_1_full_arlen,
s_axi_arsize => signal_bus_1_full_arsize,
s_axi_arburst => signal_bus_1_full_arburst,
s_axi_arlock => signal_bus_1_full_arlock,
s_axi_arcache => signal_bus_1_full_arcache,
s_axi_arprot => signal_bus_1_full_arprot,
s_axi_arqos => signal_bus_1_full_arqos,
s_axi_arregion => signal_bus_1_full_arregion,
s_axi_arvalid => signal_bus_1_full_arvalid,
s_axi_arready => signal_bus_1_full_arready,
s_axi_rid => signal_bus_1_full_rid,
s_axi_rdata => signal_bus_1_full_rdata,
s_axi_rresp => signal_bus_1_full_rresp,
s_axi_rlast => signal_bus_1_full_rlast,
s_axi_rvalid => signal_bus_1_full_rvalid,
s_axi_rready => signal_bus_1_full_rready,
m_axi_awaddr => signal_bus_1_lite_awaddr,
m_axi_awprot => signal_bus_1_lite_awprot,
m_axi_awvalid => signal_bus_1_lite_awvalid,
m_axi_awready => signal_bus_1_lite_awready,
m_axi_wvalid => signal_bus_1_lite_wvalid,
m_axi_wready => signal_bus_1_lite_wready,
m_axi_wdata => signal_bus_1_lite_wdata,
m_axi_wstrb => signal_bus_1_lite_wstrb,
m_axi_bvalid => signal_bus_1_lite_bvalid,
m_axi_bready => signal_bus_1_lite_bready,
m_axi_bresp => signal_bus_1_lite_bresp,
m_axi_araddr => signal_bus_1_lite_araddr,
m_axi_arprot => signal_bus_1_lite_arprot,
m_axi_arvalid => signal_bus_1_lite_arvalid,
m_axi_arready => signal_bus_1_lite_arready,
m_axi_rdata => signal_bus_1_lite_rdata,
m_axi_rvalid => signal_bus_1_lite_rvalid,
m_axi_rready => signal_bus_1_lite_rready,
m_axi_rresp => signal_bus_1_lite_rresp);
signal_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_2_full_awid,
s_axi_awaddr => signal_bus_2_full_awaddr,
s_axi_awlen => signal_bus_2_full_awlen,
s_axi_awsize => signal_bus_2_full_awsize,
s_axi_awburst => signal_bus_2_full_awburst,
s_axi_awlock => signal_bus_2_full_awlock,
s_axi_awcache => signal_bus_2_full_awcache,
s_axi_awprot => signal_bus_2_full_awprot,
s_axi_awqos => signal_bus_2_full_awqos,
s_axi_awregion => signal_bus_2_full_awregion,
s_axi_awvalid => signal_bus_2_full_awvalid,
s_axi_awready => signal_bus_2_full_awready,
s_axi_wdata => signal_bus_2_full_wdata,
s_axi_wstrb => signal_bus_2_full_wstrb,
s_axi_wlast => signal_bus_2_full_wlast,
s_axi_wvalid => signal_bus_2_full_wvalid,
s_axi_wready => signal_bus_2_full_wready,
s_axi_bid => signal_bus_2_full_bid,
s_axi_bresp => signal_bus_2_full_bresp,
s_axi_bvalid => signal_bus_2_full_bvalid,
s_axi_bready => signal_bus_2_full_bready,
s_axi_arid => signal_bus_2_full_arid,
s_axi_araddr => signal_bus_2_full_araddr,
s_axi_arlen => signal_bus_2_full_arlen,
s_axi_arsize => signal_bus_2_full_arsize,
s_axi_arburst => signal_bus_2_full_arburst,
s_axi_arlock => signal_bus_2_full_arlock,
s_axi_arcache => signal_bus_2_full_arcache,
s_axi_arprot => signal_bus_2_full_arprot,
s_axi_arqos => signal_bus_2_full_arqos,
s_axi_arregion => signal_bus_2_full_arregion,
s_axi_arvalid => signal_bus_2_full_arvalid,
s_axi_arready => signal_bus_2_full_arready,
s_axi_rid => signal_bus_2_full_rid,
s_axi_rdata => signal_bus_2_full_rdata,
s_axi_rresp => signal_bus_2_full_rresp,
s_axi_rlast => signal_bus_2_full_rlast,
s_axi_rvalid => signal_bus_2_full_rvalid,
s_axi_rready => signal_bus_2_full_rready,
m_axi_awaddr => signal_bus_2_lite_awaddr,
m_axi_awprot => signal_bus_2_lite_awprot,
m_axi_awvalid => signal_bus_2_lite_awvalid,
m_axi_awready => signal_bus_2_lite_awready,
m_axi_wvalid => signal_bus_2_lite_wvalid,
m_axi_wready => signal_bus_2_lite_wready,
m_axi_wdata => signal_bus_2_lite_wdata,
m_axi_wstrb => signal_bus_2_lite_wstrb,
m_axi_bvalid => signal_bus_2_lite_bvalid,
m_axi_bready => signal_bus_2_lite_bready,
m_axi_bresp => signal_bus_2_lite_bresp,
m_axi_araddr => signal_bus_2_lite_araddr,
m_axi_arprot => signal_bus_2_lite_arprot,
m_axi_arvalid => signal_bus_2_lite_arvalid,
m_axi_arready => signal_bus_2_lite_arready,
m_axi_rdata => signal_bus_2_lite_rdata,
m_axi_rvalid => signal_bus_2_lite_rvalid,
m_axi_rready => signal_bus_2_lite_rready,
m_axi_rresp => signal_bus_2_lite_rresp);
------------------------------------------
-- CPU Timer AXI Full2Lite Instantiations --
------------------------------------------
timer_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_0_full_awid,
s_axi_awaddr => timer_bus_0_full_awaddr,
s_axi_awlen => timer_bus_0_full_awlen,
s_axi_awsize => timer_bus_0_full_awsize,
s_axi_awburst => timer_bus_0_full_awburst,
s_axi_awlock => timer_bus_0_full_awlock,
s_axi_awcache => timer_bus_0_full_awcache,
s_axi_awprot => timer_bus_0_full_awprot,
s_axi_awqos => timer_bus_0_full_awqos,
s_axi_awregion => timer_bus_0_full_awregion,
s_axi_awvalid => timer_bus_0_full_awvalid,
s_axi_awready => timer_bus_0_full_awready,
s_axi_wdata => timer_bus_0_full_wdata,
s_axi_wstrb => timer_bus_0_full_wstrb,
s_axi_wlast => timer_bus_0_full_wlast,
s_axi_wvalid => timer_bus_0_full_wvalid,
s_axi_wready => timer_bus_0_full_wready,
s_axi_bid => timer_bus_0_full_bid,
s_axi_bresp => timer_bus_0_full_bresp,
s_axi_bvalid => timer_bus_0_full_bvalid,
s_axi_bready => timer_bus_0_full_bready,
s_axi_arid => timer_bus_0_full_arid,
s_axi_araddr => timer_bus_0_full_araddr,
s_axi_arlen => timer_bus_0_full_arlen,
s_axi_arsize => timer_bus_0_full_arsize,
s_axi_arburst => timer_bus_0_full_arburst,
s_axi_arlock => timer_bus_0_full_arlock,
s_axi_arcache => timer_bus_0_full_arcache,
s_axi_arprot => timer_bus_0_full_arprot,
s_axi_arqos => timer_bus_0_full_arqos,
s_axi_arregion => timer_bus_0_full_arregion,
s_axi_arvalid => timer_bus_0_full_arvalid,
s_axi_arready => timer_bus_0_full_arready,
s_axi_rid => timer_bus_0_full_rid,
s_axi_rdata => timer_bus_0_full_rdata,
s_axi_rresp => timer_bus_0_full_rresp,
s_axi_rlast => timer_bus_0_full_rlast,
s_axi_rvalid => timer_bus_0_full_rvalid,
s_axi_rready => timer_bus_0_full_rready,
m_axi_awaddr => timer_bus_0_lite_awaddr,
m_axi_awprot => timer_bus_0_lite_awprot,
m_axi_awvalid => timer_bus_0_lite_awvalid,
m_axi_awready => timer_bus_0_lite_awready,
m_axi_wvalid => timer_bus_0_lite_wvalid,
m_axi_wready => timer_bus_0_lite_wready,
m_axi_wdata => timer_bus_0_lite_wdata,
m_axi_wstrb => timer_bus_0_lite_wstrb,
m_axi_bvalid => timer_bus_0_lite_bvalid,
m_axi_bready => timer_bus_0_lite_bready,
m_axi_bresp => timer_bus_0_lite_bresp,
m_axi_araddr => timer_bus_0_lite_araddr,
m_axi_arprot => timer_bus_0_lite_arprot,
m_axi_arvalid => timer_bus_0_lite_arvalid,
m_axi_arready => timer_bus_0_lite_arready,
m_axi_rdata => timer_bus_0_lite_rdata,
m_axi_rvalid => timer_bus_0_lite_rvalid,
m_axi_rready => timer_bus_0_lite_rready,
m_axi_rresp => timer_bus_0_lite_rresp);
timer_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_1_full_awid,
s_axi_awaddr => timer_bus_1_full_awaddr,
s_axi_awlen => timer_bus_1_full_awlen,
s_axi_awsize => timer_bus_1_full_awsize,
s_axi_awburst => timer_bus_1_full_awburst,
s_axi_awlock => timer_bus_1_full_awlock,
s_axi_awcache => timer_bus_1_full_awcache,
s_axi_awprot => timer_bus_1_full_awprot,
s_axi_awqos => timer_bus_1_full_awqos,
s_axi_awregion => timer_bus_1_full_awregion,
s_axi_awvalid => timer_bus_1_full_awvalid,
s_axi_awready => timer_bus_1_full_awready,
s_axi_wdata => timer_bus_1_full_wdata,
s_axi_wstrb => timer_bus_1_full_wstrb,
s_axi_wlast => timer_bus_1_full_wlast,
s_axi_wvalid => timer_bus_1_full_wvalid,
s_axi_wready => timer_bus_1_full_wready,
s_axi_bid => timer_bus_1_full_bid,
s_axi_bresp => timer_bus_1_full_bresp,
s_axi_bvalid => timer_bus_1_full_bvalid,
s_axi_bready => timer_bus_1_full_bready,
s_axi_arid => timer_bus_1_full_arid,
s_axi_araddr => timer_bus_1_full_araddr,
s_axi_arlen => timer_bus_1_full_arlen,
s_axi_arsize => timer_bus_1_full_arsize,
s_axi_arburst => timer_bus_1_full_arburst,
s_axi_arlock => timer_bus_1_full_arlock,
s_axi_arcache => timer_bus_1_full_arcache,
s_axi_arprot => timer_bus_1_full_arprot,
s_axi_arqos => timer_bus_1_full_arqos,
s_axi_arregion => timer_bus_1_full_arregion,
s_axi_arvalid => timer_bus_1_full_arvalid,
s_axi_arready => timer_bus_1_full_arready,
s_axi_rid => timer_bus_1_full_rid,
s_axi_rdata => timer_bus_1_full_rdata,
s_axi_rresp => timer_bus_1_full_rresp,
s_axi_rlast => timer_bus_1_full_rlast,
s_axi_rvalid => timer_bus_1_full_rvalid,
s_axi_rready => timer_bus_1_full_rready,
m_axi_awaddr => timer_bus_1_lite_awaddr,
m_axi_awprot => timer_bus_1_lite_awprot,
m_axi_awvalid => timer_bus_1_lite_awvalid,
m_axi_awready => timer_bus_1_lite_awready,
m_axi_wvalid => timer_bus_1_lite_wvalid,
m_axi_wready => timer_bus_1_lite_wready,
m_axi_wdata => timer_bus_1_lite_wdata,
m_axi_wstrb => timer_bus_1_lite_wstrb,
m_axi_bvalid => timer_bus_1_lite_bvalid,
m_axi_bready => timer_bus_1_lite_bready,
m_axi_bresp => timer_bus_1_lite_bresp,
m_axi_araddr => timer_bus_1_lite_araddr,
m_axi_arprot => timer_bus_1_lite_arprot,
m_axi_arvalid => timer_bus_1_lite_arvalid,
m_axi_arready => timer_bus_1_lite_arready,
m_axi_rdata => timer_bus_1_lite_rdata,
m_axi_rvalid => timer_bus_1_lite_rvalid,
m_axi_rready => timer_bus_1_lite_rready,
m_axi_rresp => timer_bus_1_lite_rresp);
timer_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_2_full_awid,
s_axi_awaddr => timer_bus_2_full_awaddr,
s_axi_awlen => timer_bus_2_full_awlen,
s_axi_awsize => timer_bus_2_full_awsize,
s_axi_awburst => timer_bus_2_full_awburst,
s_axi_awlock => timer_bus_2_full_awlock,
s_axi_awcache => timer_bus_2_full_awcache,
s_axi_awprot => timer_bus_2_full_awprot,
s_axi_awqos => timer_bus_2_full_awqos,
s_axi_awregion => timer_bus_2_full_awregion,
s_axi_awvalid => timer_bus_2_full_awvalid,
s_axi_awready => timer_bus_2_full_awready,
s_axi_wdata => timer_bus_2_full_wdata,
s_axi_wstrb => timer_bus_2_full_wstrb,
s_axi_wlast => timer_bus_2_full_wlast,
s_axi_wvalid => timer_bus_2_full_wvalid,
s_axi_wready => timer_bus_2_full_wready,
s_axi_bid => timer_bus_2_full_bid,
s_axi_bresp => timer_bus_2_full_bresp,
s_axi_bvalid => timer_bus_2_full_bvalid,
s_axi_bready => timer_bus_2_full_bready,
s_axi_arid => timer_bus_2_full_arid,
s_axi_araddr => timer_bus_2_full_araddr,
s_axi_arlen => timer_bus_2_full_arlen,
s_axi_arsize => timer_bus_2_full_arsize,
s_axi_arburst => timer_bus_2_full_arburst,
s_axi_arlock => timer_bus_2_full_arlock,
s_axi_arcache => timer_bus_2_full_arcache,
s_axi_arprot => timer_bus_2_full_arprot,
s_axi_arqos => timer_bus_2_full_arqos,
s_axi_arregion => timer_bus_2_full_arregion,
s_axi_arvalid => timer_bus_2_full_arvalid,
s_axi_arready => timer_bus_2_full_arready,
s_axi_rid => timer_bus_2_full_rid,
s_axi_rdata => timer_bus_2_full_rdata,
s_axi_rresp => timer_bus_2_full_rresp,
s_axi_rlast => timer_bus_2_full_rlast,
s_axi_rvalid => timer_bus_2_full_rvalid,
s_axi_rready => timer_bus_2_full_rready,
m_axi_awaddr => timer_bus_2_lite_awaddr,
m_axi_awprot => timer_bus_2_lite_awprot,
m_axi_awvalid => timer_bus_2_lite_awvalid,
m_axi_awready => timer_bus_2_lite_awready,
m_axi_wvalid => timer_bus_2_lite_wvalid,
m_axi_wready => timer_bus_2_lite_wready,
m_axi_wdata => timer_bus_2_lite_wdata,
m_axi_wstrb => timer_bus_2_lite_wstrb,
m_axi_bvalid => timer_bus_2_lite_bvalid,
m_axi_bready => timer_bus_2_lite_bready,
m_axi_bresp => timer_bus_2_lite_bresp,
m_axi_araddr => timer_bus_2_lite_araddr,
m_axi_arprot => timer_bus_2_lite_arprot,
m_axi_arvalid => timer_bus_2_lite_arvalid,
m_axi_arready => timer_bus_2_lite_arready,
m_axi_rdata => timer_bus_2_lite_rdata,
m_axi_rvalid => timer_bus_2_lite_rvalid,
m_axi_rready => timer_bus_2_lite_rready,
m_axi_rresp => timer_bus_2_lite_rresp);
----------------------------------------------------
-- Main Interconnect AXI Full2Lite Instantiations --
----------------------------------------------------
int_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_axi_full_awid,
s_axi_awaddr => int_axi_full_awaddr,
s_axi_awlen => int_axi_full_awlen,
s_axi_awsize => int_axi_full_awsize,
s_axi_awburst => int_axi_full_awburst,
s_axi_awlock => int_axi_full_awlock,
s_axi_awcache => int_axi_full_awcache,
s_axi_awprot => int_axi_full_awprot,
s_axi_awqos => int_axi_full_awqos,
s_axi_awregion => int_axi_full_awregion,
s_axi_awvalid => int_axi_full_awvalid,
s_axi_awready => int_axi_full_awready,
s_axi_wdata => int_axi_full_wdata,
s_axi_wstrb => int_axi_full_wstrb,
s_axi_wlast => int_axi_full_wlast,
s_axi_wvalid => int_axi_full_wvalid,
s_axi_wready => int_axi_full_wready,
s_axi_bid => int_axi_full_bid,
s_axi_bresp => int_axi_full_bresp,
s_axi_bvalid => int_axi_full_bvalid,
s_axi_bready => int_axi_full_bready,
s_axi_arid => int_axi_full_arid,
s_axi_araddr => int_axi_full_araddr,
s_axi_arlen => int_axi_full_arlen,
s_axi_arsize => int_axi_full_arsize,
s_axi_arburst => int_axi_full_arburst,
s_axi_arlock => int_axi_full_arlock,
s_axi_arcache => int_axi_full_arcache,
s_axi_arprot => int_axi_full_arprot,
s_axi_arqos => int_axi_full_arqos,
s_axi_arregion => int_axi_full_arregion,
s_axi_arvalid => int_axi_full_arvalid,
s_axi_arready => int_axi_full_arready,
s_axi_rid => int_axi_full_rid,
s_axi_rdata => int_axi_full_rdata,
s_axi_rresp => int_axi_full_rresp,
s_axi_rlast => int_axi_full_rlast,
s_axi_rvalid => int_axi_full_rvalid,
s_axi_rready => int_axi_full_rready,
m_axi_awaddr => int_axi_lite_awaddr,
m_axi_awprot => int_axi_lite_awprot,
m_axi_awvalid => int_axi_lite_awvalid,
m_axi_awready => int_axi_lite_awready,
m_axi_wvalid => int_axi_lite_wvalid,
m_axi_wready => int_axi_lite_wready,
m_axi_wdata => int_axi_lite_wdata,
m_axi_wstrb => int_axi_lite_wstrb,
m_axi_bvalid => int_axi_lite_bvalid,
m_axi_bready => int_axi_lite_bready,
m_axi_bresp => int_axi_lite_bresp,
m_axi_araddr => int_axi_lite_araddr,
m_axi_arprot => int_axi_lite_arprot,
m_axi_arvalid => int_axi_lite_arvalid,
m_axi_arready => int_axi_lite_arready,
m_axi_rdata => int_axi_lite_rdata,
m_axi_rvalid => int_axi_lite_rvalid,
m_axi_rready => int_axi_lite_rready,
m_axi_rresp => int_axi_lite_rresp);
timer_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_axi_full_awid,
s_axi_awaddr => timer_axi_full_awaddr,
s_axi_awlen => timer_axi_full_awlen,
s_axi_awsize => timer_axi_full_awsize,
s_axi_awburst => timer_axi_full_awburst,
s_axi_awlock => timer_axi_full_awlock,
s_axi_awcache => timer_axi_full_awcache,
s_axi_awprot => timer_axi_full_awprot,
s_axi_awqos => timer_axi_full_awqos,
s_axi_awregion => timer_axi_full_awregion,
s_axi_awvalid => timer_axi_full_awvalid,
s_axi_awready => timer_axi_full_awready,
s_axi_wdata => timer_axi_full_wdata,
s_axi_wstrb => timer_axi_full_wstrb,
s_axi_wlast => timer_axi_full_wlast,
s_axi_wvalid => timer_axi_full_wvalid,
s_axi_wready => timer_axi_full_wready,
s_axi_bid => timer_axi_full_bid,
s_axi_bresp => timer_axi_full_bresp,
s_axi_bvalid => timer_axi_full_bvalid,
s_axi_bready => timer_axi_full_bready,
s_axi_arid => timer_axi_full_arid,
s_axi_araddr => timer_axi_full_araddr,
s_axi_arlen => timer_axi_full_arlen,
s_axi_arsize => timer_axi_full_arsize,
s_axi_arburst => timer_axi_full_arburst,
s_axi_arlock => timer_axi_full_arlock,
s_axi_arcache => timer_axi_full_arcache,
s_axi_arprot => timer_axi_full_arprot,
s_axi_arqos => timer_axi_full_arqos,
s_axi_arregion => timer_axi_full_arregion,
s_axi_arvalid => timer_axi_full_arvalid,
s_axi_arready => timer_axi_full_arready,
s_axi_rid => timer_axi_full_rid,
s_axi_rdata => timer_axi_full_rdata,
s_axi_rresp => timer_axi_full_rresp,
s_axi_rlast => timer_axi_full_rlast,
s_axi_rvalid => timer_axi_full_rvalid,
s_axi_rready => timer_axi_full_rready,
m_axi_awaddr => timer_axi_lite_awaddr,
m_axi_awprot => timer_axi_lite_awprot,
m_axi_awvalid => timer_axi_lite_awvalid,
m_axi_awready => timer_axi_lite_awready,
m_axi_wvalid => timer_axi_lite_wvalid,
m_axi_wready => timer_axi_lite_wready,
m_axi_wdata => timer_axi_lite_wdata,
m_axi_wstrb => timer_axi_lite_wstrb,
m_axi_bvalid => timer_axi_lite_bvalid,
m_axi_bready => timer_axi_lite_bready,
m_axi_bresp => timer_axi_lite_bresp,
m_axi_araddr => timer_axi_lite_araddr,
m_axi_arprot => timer_axi_lite_arprot,
m_axi_arvalid => timer_axi_lite_arvalid,
m_axi_arready => timer_axi_lite_arready,
m_axi_rdata => timer_axi_lite_rdata,
m_axi_rvalid => timer_axi_lite_rvalid,
m_axi_rready => timer_axi_lite_rready,
m_axi_rresp => timer_axi_lite_rresp);
gpio_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => gpio_axi_full_awid,
s_axi_awaddr => gpio_axi_full_awaddr,
s_axi_awlen => gpio_axi_full_awlen,
s_axi_awsize => gpio_axi_full_awsize,
s_axi_awburst => gpio_axi_full_awburst,
s_axi_awlock => gpio_axi_full_awlock,
s_axi_awcache => gpio_axi_full_awcache,
s_axi_awprot => gpio_axi_full_awprot,
s_axi_awqos => gpio_axi_full_awqos,
s_axi_awregion => gpio_axi_full_awregion,
s_axi_awvalid => gpio_axi_full_awvalid,
s_axi_awready => gpio_axi_full_awready,
s_axi_wdata => gpio_axi_full_wdata,
s_axi_wstrb => gpio_axi_full_wstrb,
s_axi_wlast => gpio_axi_full_wlast,
s_axi_wvalid => gpio_axi_full_wvalid,
s_axi_wready => gpio_axi_full_wready,
s_axi_bid => gpio_axi_full_bid,
s_axi_bresp => gpio_axi_full_bresp,
s_axi_bvalid => gpio_axi_full_bvalid,
s_axi_bready => gpio_axi_full_bready,
s_axi_arid => gpio_axi_full_arid,
s_axi_araddr => gpio_axi_full_araddr,
s_axi_arlen => gpio_axi_full_arlen,
s_axi_arsize => gpio_axi_full_arsize,
s_axi_arburst => gpio_axi_full_arburst,
s_axi_arlock => gpio_axi_full_arlock,
s_axi_arcache => gpio_axi_full_arcache,
s_axi_arprot => gpio_axi_full_arprot,
s_axi_arqos => gpio_axi_full_arqos,
s_axi_arregion => gpio_axi_full_arregion,
s_axi_arvalid => gpio_axi_full_arvalid,
s_axi_arready => gpio_axi_full_arready,
s_axi_rid => gpio_axi_full_rid,
s_axi_rdata => gpio_axi_full_rdata,
s_axi_rresp => gpio_axi_full_rresp,
s_axi_rlast => gpio_axi_full_rlast,
s_axi_rvalid => gpio_axi_full_rvalid,
s_axi_rready => gpio_axi_full_rready,
m_axi_awaddr => gpio_axi_lite_awaddr,
m_axi_awprot => gpio_axi_lite_awprot,
m_axi_awvalid => gpio_axi_lite_awvalid,
m_axi_awready => gpio_axi_lite_awready,
m_axi_wvalid => gpio_axi_lite_wvalid,
m_axi_wready => gpio_axi_lite_wready,
m_axi_wdata => gpio_axi_lite_wdata,
m_axi_wstrb => gpio_axi_lite_wstrb,
m_axi_bvalid => gpio_axi_lite_bvalid,
m_axi_bready => gpio_axi_lite_bready,
m_axi_bresp => gpio_axi_lite_bresp,
m_axi_araddr => gpio_axi_lite_araddr,
m_axi_arprot => gpio_axi_lite_arprot,
m_axi_arvalid => gpio_axi_lite_arvalid,
m_axi_arready => gpio_axi_lite_arready,
m_axi_rdata => gpio_axi_lite_rdata,
m_axi_rvalid => gpio_axi_lite_rvalid,
m_axi_rready => gpio_axi_lite_rready,
m_axi_rresp => gpio_axi_lite_rresp);
uart_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => uart_axi_full_awid,
s_axi_awaddr => uart_axi_full_awaddr,
s_axi_awlen => uart_axi_full_awlen,
s_axi_awsize => uart_axi_full_awsize,
s_axi_awburst => uart_axi_full_awburst,
s_axi_awlock => uart_axi_full_awlock,
s_axi_awcache => uart_axi_full_awcache,
s_axi_awprot => uart_axi_full_awprot,
s_axi_awqos => uart_axi_full_awqos,
s_axi_awregion => uart_axi_full_awregion,
s_axi_awvalid => uart_axi_full_awvalid,
s_axi_awready => uart_axi_full_awready,
s_axi_wdata => uart_axi_full_wdata,
s_axi_wstrb => uart_axi_full_wstrb,
s_axi_wlast => uart_axi_full_wlast,
s_axi_wvalid => uart_axi_full_wvalid,
s_axi_wready => uart_axi_full_wready,
s_axi_bid => uart_axi_full_bid,
s_axi_bresp => uart_axi_full_bresp,
s_axi_bvalid => uart_axi_full_bvalid,
s_axi_bready => uart_axi_full_bready,
s_axi_arid => uart_axi_full_arid,
s_axi_araddr => uart_axi_full_araddr,
s_axi_arlen => uart_axi_full_arlen,
s_axi_arsize => uart_axi_full_arsize,
s_axi_arburst => uart_axi_full_arburst,
s_axi_arlock => uart_axi_full_arlock,
s_axi_arcache => uart_axi_full_arcache,
s_axi_arprot => uart_axi_full_arprot,
s_axi_arqos => uart_axi_full_arqos,
s_axi_arregion => uart_axi_full_arregion,
s_axi_arvalid => uart_axi_full_arvalid,
s_axi_arready => uart_axi_full_arready,
s_axi_rid => uart_axi_full_rid,
s_axi_rdata => uart_axi_full_rdata,
s_axi_rresp => uart_axi_full_rresp,
s_axi_rlast => uart_axi_full_rlast,
s_axi_rvalid => uart_axi_full_rvalid,
s_axi_rready => uart_axi_full_rready,
m_axi_awaddr => uart_axi_lite_awaddr,
m_axi_awprot => uart_axi_lite_awprot,
m_axi_awvalid => uart_axi_lite_awvalid,
m_axi_awready => uart_axi_lite_awready,
m_axi_wvalid => uart_axi_lite_wvalid,
m_axi_wready => uart_axi_lite_wready,
m_axi_wdata => uart_axi_lite_wdata,
m_axi_wstrb => uart_axi_lite_wstrb,
m_axi_bvalid => uart_axi_lite_bvalid,
m_axi_bready => uart_axi_lite_bready,
m_axi_bresp => uart_axi_lite_bresp,
m_axi_araddr => uart_axi_lite_araddr,
m_axi_arprot => uart_axi_lite_arprot,
m_axi_arvalid => uart_axi_lite_arvalid,
m_axi_arready => uart_axi_lite_arready,
m_axi_rdata => uart_axi_lite_rdata,
m_axi_rvalid => uart_axi_lite_rvalid,
m_axi_rready => uart_axi_lite_rready,
m_axi_rresp => uart_axi_lite_rresp);
lock_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => lock_axi_full_awid,
s_axi_awaddr => lock_axi_full_awaddr,
s_axi_awlen => lock_axi_full_awlen,
s_axi_awsize => lock_axi_full_awsize,
s_axi_awburst => lock_axi_full_awburst,
s_axi_awlock => lock_axi_full_awlock,
s_axi_awcache => lock_axi_full_awcache,
s_axi_awprot => lock_axi_full_awprot,
s_axi_awqos => lock_axi_full_awqos,
s_axi_awregion => lock_axi_full_awregion,
s_axi_awvalid => lock_axi_full_awvalid,
s_axi_awready => lock_axi_full_awready,
s_axi_wdata => lock_axi_full_wdata,
s_axi_wstrb => lock_axi_full_wstrb,
s_axi_wlast => lock_axi_full_wlast,
s_axi_wvalid => lock_axi_full_wvalid,
s_axi_wready => lock_axi_full_wready,
s_axi_bid => lock_axi_full_bid,
s_axi_bresp => lock_axi_full_bresp,
s_axi_bvalid => lock_axi_full_bvalid,
s_axi_bready => lock_axi_full_bready,
s_axi_arid => lock_axi_full_arid,
s_axi_araddr => lock_axi_full_araddr,
s_axi_arlen => lock_axi_full_arlen,
s_axi_arsize => lock_axi_full_arsize,
s_axi_arburst => lock_axi_full_arburst,
s_axi_arlock => lock_axi_full_arlock,
s_axi_arcache => lock_axi_full_arcache,
s_axi_arprot => lock_axi_full_arprot,
s_axi_arqos => lock_axi_full_arqos,
s_axi_arregion => lock_axi_full_arregion,
s_axi_arvalid => lock_axi_full_arvalid,
s_axi_arready => lock_axi_full_arready,
s_axi_rid => lock_axi_full_rid,
s_axi_rdata => lock_axi_full_rdata,
s_axi_rresp => lock_axi_full_rresp,
s_axi_rlast => lock_axi_full_rlast,
s_axi_rvalid => lock_axi_full_rvalid,
s_axi_rready => lock_axi_full_rready,
m_axi_awaddr => lock_axi_lite_awaddr,
m_axi_awprot => lock_axi_lite_awprot,
m_axi_awvalid => lock_axi_lite_awvalid,
m_axi_awready => lock_axi_lite_awready,
m_axi_wvalid => lock_axi_lite_wvalid,
m_axi_wready => lock_axi_lite_wready,
m_axi_wdata => lock_axi_lite_wdata,
m_axi_wstrb => lock_axi_lite_wstrb,
m_axi_bvalid => lock_axi_lite_bvalid,
m_axi_bready => lock_axi_lite_bready,
m_axi_bresp => lock_axi_lite_bresp,
m_axi_araddr => lock_axi_lite_araddr,
m_axi_arprot => lock_axi_lite_arprot,
m_axi_arvalid => lock_axi_lite_arvalid,
m_axi_arready => lock_axi_lite_arready,
m_axi_rdata => lock_axi_lite_rdata,
m_axi_rvalid => lock_axi_lite_rvalid,
m_axi_rready => lock_axi_lite_rready,
m_axi_rresp => lock_axi_lite_rresp);
----------------------
-- CPUID GPIO Cores --
----------------------
cpuid_gpio_0_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(0,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_0_lite_awprot,
axi_awvalid => cpuid_gpio_bus_0_lite_awvalid,
axi_awready => cpuid_gpio_bus_0_lite_awready,
axi_wvalid => cpuid_gpio_bus_0_lite_wvalid,
axi_wready => cpuid_gpio_bus_0_lite_wready,
axi_wdata => cpuid_gpio_bus_0_lite_wdata,
axi_wstrb => cpuid_gpio_bus_0_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_0_lite_bvalid,
axi_bready => cpuid_gpio_bus_0_lite_bready,
axi_bresp => cpuid_gpio_bus_0_lite_bresp,
axi_araddr => cpuid_gpio_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_0_lite_arprot,
axi_arvalid => cpuid_gpio_bus_0_lite_arvalid,
axi_arready => cpuid_gpio_bus_0_lite_arready,
axi_rdata => cpuid_gpio_bus_0_lite_rdata,
axi_rvalid => cpuid_gpio_bus_0_lite_rvalid,
axi_rready => cpuid_gpio_bus_0_lite_rready,
axi_rresp => cpuid_gpio_bus_0_lite_rresp,
int => open);
cpuid_gpio_1_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(1,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_1_lite_awprot,
axi_awvalid => cpuid_gpio_bus_1_lite_awvalid,
axi_awready => cpuid_gpio_bus_1_lite_awready,
axi_wvalid => cpuid_gpio_bus_1_lite_wvalid,
axi_wready => cpuid_gpio_bus_1_lite_wready,
axi_wdata => cpuid_gpio_bus_1_lite_wdata,
axi_wstrb => cpuid_gpio_bus_1_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_1_lite_bvalid,
axi_bready => cpuid_gpio_bus_1_lite_bready,
axi_bresp => cpuid_gpio_bus_1_lite_bresp,
axi_araddr => cpuid_gpio_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_1_lite_arprot,
axi_arvalid => cpuid_gpio_bus_1_lite_arvalid,
axi_arready => cpuid_gpio_bus_1_lite_arready,
axi_rdata => cpuid_gpio_bus_1_lite_rdata,
axi_rvalid => cpuid_gpio_bus_1_lite_rvalid,
axi_rready => cpuid_gpio_bus_1_lite_rready,
axi_rresp => cpuid_gpio_bus_1_lite_rresp,
int => open);
cpuid_gpio_2_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(2,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_2_lite_awprot,
axi_awvalid => cpuid_gpio_bus_2_lite_awvalid,
axi_awready => cpuid_gpio_bus_2_lite_awready,
axi_wvalid => cpuid_gpio_bus_2_lite_wvalid,
axi_wready => cpuid_gpio_bus_2_lite_wready,
axi_wdata => cpuid_gpio_bus_2_lite_wdata,
axi_wstrb => cpuid_gpio_bus_2_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_2_lite_bvalid,
axi_bready => cpuid_gpio_bus_2_lite_bready,
axi_bresp => cpuid_gpio_bus_2_lite_bresp,
axi_araddr => cpuid_gpio_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_2_lite_arprot,
axi_arvalid => cpuid_gpio_bus_2_lite_arvalid,
axi_arready => cpuid_gpio_bus_2_lite_arready,
axi_rdata => cpuid_gpio_bus_2_lite_rdata,
axi_rvalid => cpuid_gpio_bus_2_lite_rvalid,
axi_rready => cpuid_gpio_bus_2_lite_rready,
axi_rresp => cpuid_gpio_bus_2_lite_rresp,
int => open);
-------------------
-- CPU INT Cores --
-------------------
int_0_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_0_lite_awprot,
axi_awvalid => int_bus_0_lite_awvalid,
axi_awready => int_bus_0_lite_awready,
axi_wvalid => int_bus_0_lite_wvalid,
axi_wready => int_bus_0_lite_wready,
axi_wdata => int_bus_0_lite_wdata,
axi_wstrb => int_bus_0_lite_wstrb,
axi_bvalid => int_bus_0_lite_bvalid,
axi_bready => int_bus_0_lite_bready,
axi_bresp => int_bus_0_lite_bresp,
axi_araddr => int_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_0_lite_arprot,
axi_arvalid => int_bus_0_lite_arvalid,
axi_arready => int_bus_0_lite_arready,
axi_rdata => int_bus_0_lite_rdata,
axi_rvalid => int_bus_0_lite_rvalid,
axi_rready => int_bus_0_lite_rready,
axi_rresp => int_bus_0_lite_rresp,
cpu_int => cpu_0_int,
dev_ints => dev_0_ints);
int_1_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_1_lite_awprot,
axi_awvalid => int_bus_1_lite_awvalid,
axi_awready => int_bus_1_lite_awready,
axi_wvalid => int_bus_1_lite_wvalid,
axi_wready => int_bus_1_lite_wready,
axi_wdata => int_bus_1_lite_wdata,
axi_wstrb => int_bus_1_lite_wstrb,
axi_bvalid => int_bus_1_lite_bvalid,
axi_bready => int_bus_1_lite_bready,
axi_bresp => int_bus_1_lite_bresp,
axi_araddr => int_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_1_lite_arprot,
axi_arvalid => int_bus_1_lite_arvalid,
axi_arready => int_bus_1_lite_arready,
axi_rdata => int_bus_1_lite_rdata,
axi_rvalid => int_bus_1_lite_rvalid,
axi_rready => int_bus_1_lite_rready,
axi_rresp => int_bus_1_lite_rresp,
cpu_int => cpu_1_int,
dev_ints => dev_1_ints);
int_2_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_2_lite_awprot,
axi_awvalid => int_bus_2_lite_awvalid,
axi_awready => int_bus_2_lite_awready,
axi_wvalid => int_bus_2_lite_wvalid,
axi_wready => int_bus_2_lite_wready,
axi_wdata => int_bus_2_lite_wdata,
axi_wstrb => int_bus_2_lite_wstrb,
axi_bvalid => int_bus_2_lite_bvalid,
axi_bready => int_bus_2_lite_bready,
axi_bresp => int_bus_2_lite_bresp,
axi_araddr => int_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_2_lite_arprot,
axi_arvalid => int_bus_2_lite_arvalid,
axi_arready => int_bus_2_lite_arready,
axi_rdata => int_bus_2_lite_rdata,
axi_rvalid => int_bus_2_lite_rvalid,
axi_rready => int_bus_2_lite_rready,
axi_rresp => int_bus_2_lite_rresp,
cpu_int => cpu_2_int,
dev_ints => dev_2_ints);
----------------------
-- CPU Signal Cores --
----------------------
signal_0_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_0_lite_awprot,
axi_awvalid => signal_bus_0_lite_awvalid,
axi_awready => signal_bus_0_lite_awready,
axi_wvalid => signal_bus_0_lite_wvalid,
axi_wready => signal_bus_0_lite_wready,
axi_wdata => signal_bus_0_lite_wdata,
axi_wstrb => signal_bus_0_lite_wstrb,
axi_bvalid => signal_bus_0_lite_bvalid,
axi_bready => signal_bus_0_lite_bready,
axi_bresp => signal_bus_0_lite_bresp,
axi_araddr => signal_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_0_lite_arprot,
axi_arvalid => signal_bus_0_lite_arvalid,
axi_arready => signal_bus_0_lite_arready,
axi_rdata => signal_bus_0_lite_rdata,
axi_rvalid => signal_bus_0_lite_rvalid,
axi_rready => signal_bus_0_lite_rready,
axi_rresp => signal_bus_0_lite_rresp,
sig_out => sig_0_1,
sig_in => '0',
int => dev_0_ints(0));
signal_1_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_1_lite_awprot,
axi_awvalid => signal_bus_1_lite_awvalid,
axi_awready => signal_bus_1_lite_awready,
axi_wvalid => signal_bus_1_lite_wvalid,
axi_wready => signal_bus_1_lite_wready,
axi_wdata => signal_bus_1_lite_wdata,
axi_wstrb => signal_bus_1_lite_wstrb,
axi_bvalid => signal_bus_1_lite_bvalid,
axi_bready => signal_bus_1_lite_bready,
axi_bresp => signal_bus_1_lite_bresp,
axi_araddr => signal_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_1_lite_arprot,
axi_arvalid => signal_bus_1_lite_arvalid,
axi_arready => signal_bus_1_lite_arready,
axi_rdata => signal_bus_1_lite_rdata,
axi_rvalid => signal_bus_1_lite_rvalid,
axi_rready => signal_bus_1_lite_rready,
axi_rresp => signal_bus_1_lite_rresp,
sig_out => sig_1_2,
sig_in => sig_0_1,
int => dev_1_ints(0));
signal_2_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_2_lite_awprot,
axi_awvalid => signal_bus_2_lite_awvalid,
axi_awready => signal_bus_2_lite_awready,
axi_wvalid => signal_bus_2_lite_wvalid,
axi_wready => signal_bus_2_lite_wready,
axi_wdata => signal_bus_2_lite_wdata,
axi_wstrb => signal_bus_2_lite_wstrb,
axi_bvalid => signal_bus_2_lite_bvalid,
axi_bready => signal_bus_2_lite_bready,
axi_bresp => signal_bus_2_lite_bresp,
axi_araddr => signal_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_2_lite_arprot,
axi_arvalid => signal_bus_2_lite_arvalid,
axi_arready => signal_bus_2_lite_arready,
axi_rdata => signal_bus_2_lite_rdata,
axi_rvalid => signal_bus_2_lite_rvalid,
axi_rready => signal_bus_2_lite_rready,
axi_rresp => signal_bus_2_lite_rresp,
sig_out => open,
sig_in => sig_1_2,
int => dev_2_ints(0));
---------------------
-- CPU Timer Cores --
---------------------
time_0_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_0_lite_awprot,
axi_awvalid => timer_bus_0_lite_awvalid,
axi_awready => timer_bus_0_lite_awready,
axi_wvalid => timer_bus_0_lite_wvalid,
axi_wready => timer_bus_0_lite_wready,
axi_wdata => timer_bus_0_lite_wdata,
axi_wstrb => timer_bus_0_lite_wstrb,
axi_bvalid => timer_bus_0_lite_bvalid,
axi_bready => timer_bus_0_lite_bready,
axi_bresp => timer_bus_0_lite_bresp,
axi_araddr => timer_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_0_lite_arprot,
axi_arvalid => timer_bus_0_lite_arvalid,
axi_arready => timer_bus_0_lite_arready,
axi_rdata => timer_bus_0_lite_rdata,
axi_rvalid => timer_bus_0_lite_rvalid,
axi_rready => timer_bus_0_lite_rready,
axi_rresp => timer_bus_0_lite_rresp,
done => dev_0_ints(1));
time_1_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_1_lite_awprot,
axi_awvalid => timer_bus_1_lite_awvalid,
axi_awready => timer_bus_1_lite_awready,
axi_wvalid => timer_bus_1_lite_wvalid,
axi_wready => timer_bus_1_lite_wready,
axi_wdata => timer_bus_1_lite_wdata,
axi_wstrb => timer_bus_1_lite_wstrb,
axi_bvalid => timer_bus_1_lite_bvalid,
axi_bready => timer_bus_1_lite_bready,
axi_bresp => timer_bus_1_lite_bresp,
axi_araddr => timer_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_1_lite_arprot,
axi_arvalid => timer_bus_1_lite_arvalid,
axi_arready => timer_bus_1_lite_arready,
axi_rdata => timer_bus_1_lite_rdata,
axi_rvalid => timer_bus_1_lite_rvalid,
axi_rready => timer_bus_1_lite_rready,
axi_rresp => timer_bus_1_lite_rresp,
done => dev_1_ints(1));
time_2_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_2_lite_awprot,
axi_awvalid => timer_bus_2_lite_awvalid,
axi_awready => timer_bus_2_lite_awready,
axi_wvalid => timer_bus_2_lite_wvalid,
axi_wready => timer_bus_2_lite_wready,
axi_wdata => timer_bus_2_lite_wdata,
axi_wstrb => timer_bus_2_lite_wstrb,
axi_bvalid => timer_bus_2_lite_bvalid,
axi_bready => timer_bus_2_lite_bready,
axi_bresp => timer_bus_2_lite_bresp,
axi_araddr => timer_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_2_lite_arprot,
axi_arvalid => timer_bus_2_lite_arvalid,
axi_arready => timer_bus_2_lite_arready,
axi_rdata => timer_bus_2_lite_rdata,
axi_rvalid => timer_bus_2_lite_rvalid,
axi_rready => timer_bus_2_lite_rready,
axi_rresp => timer_bus_2_lite_rresp,
done => dev_2_ints(1));
-----------------------------
-- Main Interconnect Cores --
-----------------------------
int_main_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_axi_lite_awprot,
axi_awvalid => int_axi_lite_awvalid,
axi_awready => int_axi_lite_awready,
axi_wvalid => int_axi_lite_wvalid,
axi_wready => int_axi_lite_wready,
axi_wdata => int_axi_lite_wdata,
axi_wstrb => int_axi_lite_wstrb,
axi_bvalid => int_axi_lite_bvalid,
axi_bready => int_axi_lite_bready,
axi_bresp => int_axi_lite_bresp,
axi_araddr => int_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_axi_lite_arprot,
axi_arvalid => int_axi_lite_arvalid,
axi_arready => int_axi_lite_arready,
axi_rdata => int_axi_lite_rdata,
axi_rvalid => int_axi_lite_rvalid,
axi_rready => int_axi_lite_rready,
axi_rresp => int_axi_lite_rresp,
cpu_int => dev_0_ints(default_interrupt_total-1),
dev_ints => dev_ints);
timer_main_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_axi_lite_awprot,
axi_awvalid => timer_axi_lite_awvalid,
axi_awready => timer_axi_lite_awready,
axi_wvalid => timer_axi_lite_wvalid,
axi_wready => timer_axi_lite_wready,
axi_wdata => timer_axi_lite_wdata,
axi_wstrb => timer_axi_lite_wstrb,
axi_bvalid => timer_axi_lite_bvalid,
axi_bready => timer_axi_lite_bready,
axi_bresp => timer_axi_lite_bresp,
axi_araddr => timer_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_axi_lite_arprot,
axi_arvalid => timer_axi_lite_arvalid,
axi_arready => timer_axi_lite_arready,
axi_rdata => timer_axi_lite_rdata,
axi_rvalid => timer_axi_lite_rvalid,
axi_rready => timer_axi_lite_rready,
axi_rresp => timer_axi_lite_rresp,
done => dev_ints(0));
gpio_main_inst : plasoc_gpio
generic map (
data_in_width => data_in_width,
data_out_width => data_out_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => gpio_input,
data_out => gpio_output,
axi_awaddr => gpio_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => gpio_axi_lite_awprot,
axi_awvalid => gpio_axi_lite_awvalid,
axi_awready => gpio_axi_lite_awready,
axi_wvalid => gpio_axi_lite_wvalid,
axi_wready => gpio_axi_lite_wready,
axi_wdata => gpio_axi_lite_wdata,
axi_wstrb => gpio_axi_lite_wstrb,
axi_bvalid => gpio_axi_lite_bvalid,
axi_bready => gpio_axi_lite_bready,
axi_bresp => gpio_axi_lite_bresp,
axi_araddr => gpio_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => gpio_axi_lite_arprot,
axi_arvalid => gpio_axi_lite_arvalid,
axi_arready => gpio_axi_lite_arready,
axi_rdata => gpio_axi_lite_rdata,
axi_rvalid => gpio_axi_lite_rvalid,
axi_rready => gpio_axi_lite_rready,
axi_rresp => gpio_axi_lite_rresp,
int => dev_ints(1));
uart_main_inst : plasoc_uart
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width,
baud => uart_baud,
clock_frequency => uart_clock_frequency)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => uart_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => uart_axi_lite_awprot,
axi_awvalid => uart_axi_lite_awvalid,
axi_awready => uart_axi_lite_awready,
axi_wvalid => uart_axi_lite_wvalid,
axi_wready => uart_axi_lite_wready,
axi_wdata => uart_axi_lite_wdata,
axi_wstrb => uart_axi_lite_wstrb,
axi_bvalid => uart_axi_lite_bvalid,
axi_bready => uart_axi_lite_bready,
axi_bresp => uart_axi_lite_bresp,
axi_araddr => uart_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => uart_axi_lite_arprot,
axi_arvalid => uart_axi_lite_arvalid,
axi_arready => uart_axi_lite_arready,
axi_rdata => uart_axi_lite_rdata,
axi_rvalid => uart_axi_lite_rvalid,
axi_rready => uart_axi_lite_rready,
axi_rresp => uart_axi_lite_rresp,
tx => uart_tx,
rx => uart_rx,
status_in_avail => dev_ints(2));
lock_main_inst : koc_lock
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width,
control_default => lock_control_default)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => lock_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => lock_axi_lite_awprot,
axi_awvalid => lock_axi_lite_awvalid,
axi_awready => lock_axi_lite_awready,
axi_wvalid => lock_axi_lite_wvalid,
axi_wready => lock_axi_lite_wready,
axi_wdata => lock_axi_lite_wdata,
axi_wstrb => lock_axi_lite_wstrb,
axi_bvalid => lock_axi_lite_bvalid,
axi_bready => lock_axi_lite_bready,
axi_bresp => lock_axi_lite_bresp,
axi_araddr => lock_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => lock_axi_lite_arprot,
axi_arvalid => lock_axi_lite_arvalid,
axi_arready => lock_axi_lite_arready,
axi_rdata => lock_axi_lite_rdata,
axi_rvalid => lock_axi_lite_rvalid,
axi_rready => lock_axi_lite_rready,
axi_rresp => lock_axi_lite_rresp);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ShiftRegister is
Port ( CLK : in STD_LOGIC;
signalOutput : out My_STD_LOGIC_VECTOR); -- missing `(7 downto 0)` here
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal Q : STD_LOGIC_VECTOR (7 downto 0) := "10011000";
begin
Output <= Q;
process (CLK)
begin
if (CLK'event and CLK = '1') then
Q(7 downto 0) <= Q(6 downto 0) & Q(7);
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_McEliece_QD-Goppa_Decrypt_v4
-- Module Name: Tb_McEliece_QD-Goppa_Decrypt_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests mceliece_qd_goppa_decrypt_v4 circuit.
-- The test is done only for one value loaded into memories, and in the end the output
-- memories are verified.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
-- file_memory_L :
--
-- This file stores the private key, support elements L.
--
-- file_memory_h :
--
-- This file stores the private key, the inverted evaluation of all support elements L
-- into polynomial g, aka g(L)^(-1)
--
-- file_memory_codeword :
--
-- This file stores the ciphertext that will be decrypted.
--
-- file_memory_message :
--
-- This file stores the plaintext obtained by decrypting the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- file_memory_error :
--
-- This file stores the error array added to the codeword to transform into the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_v4 Rev 1.0
-- ram Rev 1.0
-- ram_double Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_mceliece_qd_goppa_decrypt_v4 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- number_of_errors : integer := 4;
-- size_number_of_errors : integer := 3;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
polynomial_evaluator_syndrome_pipeline_size : integer := 12;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 4;
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 2048;
size_codeword : integer := 11;
number_of_errors : integer := 27;
size_number_of_errors : integer := 5;
file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 7;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 6;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 22;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 22;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 22;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_7296_5632_128_13.dat"
);
end tb_mceliece_qd_goppa_decrypt_v4;
architecture Behavioral of tb_mceliece_qd_goppa_decrypt_v4 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component mceliece_qd_goppa_decrypt_v4
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_s : out STD_LOGIC;
write_enable_new_value_v : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal syndrome_generation_finalized : STD_LOGIC;
signal key_equation_finalized : STD_LOGIC;
signal decryption_finalized : STD_LOGIC;
signal address_value_h : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_L : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_codeword : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_error : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_s : STD_LOGIC;
signal write_enable_new_value_v : STD_LOGIC;
signal write_enable_new_value_sigma : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_new_value_error : STD_LOGIC;
signal write_enable_new_value_sigma_evaluated : STD_LOGIC;
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal true_address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal error_value_message : STD_LOGIC;
signal error_value_error : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
begin
test : mceliece_qd_goppa_decrypt_v4
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h,
value_L => value_L,
value_syndrome => value_syndrome,
value_codeword => value_codeword,
value_s => value_s,
value_v => value_v,
value_sigma => value_sigma,
value_sigma_evaluated => value_sigma_evaluated,
syndrome_generation_finalized => syndrome_generation_finalized,
key_equation_finalized => key_equation_finalized,
decryption_finalized => decryption_finalized,
address_value_h => address_value_h,
address_value_L => address_value_L,
address_value_syndrome => address_value_syndrome,
address_value_codeword => address_value_codeword,
address_value_s => address_value_s,
address_value_v => address_value_v,
address_value_sigma => address_value_sigma,
address_value_sigma_evaluated => address_value_sigma_evaluated,
new_value_syndrome => new_value_syndrome,
new_value_s => new_value_s,
new_value_v => new_value_v,
new_value_sigma => new_value_sigma,
new_value_message => new_value_message,
new_value_error => new_value_error,
new_value_sigma_evaluated => new_value_sigma_evaluated,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_s => write_enable_new_value_s,
write_enable_new_value_v => write_enable_new_value_v,
write_enable_new_value_sigma => write_enable_new_value_sigma,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_new_value_error => write_enable_new_value_error,
write_enable_new_value_sigma_evaluated => write_enable_new_value_sigma_evaluated,
address_new_value_syndrome => address_new_value_syndrome,
address_new_value_s => address_new_value_s,
address_new_value_v => address_new_value_v,
address_new_value_sigma => address_new_value_sigma,
address_new_value_message => address_new_value_message,
address_new_value_error => address_new_value_error,
address_new_value_sigma_evaluated => address_new_value_sigma_evaluated
);
mem_L : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_L,
rst_value => (others => '0'),
data_out => value_L
);
mem_h : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_h,
rst_value => (others => '0'),
data_out => value_h
);
mem_codeword : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_codeword,
rst_value => (others => '0'),
data_out => value_codeword
);
mem_sigma_evaluated : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma_evaluated,
rw_a => '0',
rw_b => write_enable_new_value_sigma_evaluated,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma_evaluated,
address_b => address_new_value_sigma_evaluated,
rst_value => (others => '0'),
data_out_a => value_sigma_evaluated,
data_out_b => open
);
test_mem_message : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_message,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_message,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_message,
address_b => true_address_new_value_message,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_message
);
test_mem_error : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_error,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_error,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_error,
address_b => true_address_new_value_error,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_error
);
true_mem_message : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_message,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_message,
rst_value => (others => '0'),
data_out => true_value_message
);
true_mem_error : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_error,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_error,
rst_value => (others => '0'),
data_out => true_value_error
);
mem_syndrome : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_syndrome,
rw_a => '0',
rw_b => write_enable_new_value_syndrome,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_syndrome,
address_b => address_new_value_syndrome,
rst_value => (others => '0'),
data_out_a => value_syndrome,
data_out_b => open
);
mem_F : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_s,
rw_a => '0',
rw_b => write_enable_new_value_s,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_s,
address_b => address_new_value_s,
rst_value => (others => '0'),
data_out_a => value_s,
data_out_b => open
);
mem_B : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_v,
rw_a => '0',
rw_b => write_enable_new_value_v,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_v,
address_b => address_new_value_v,
rst_value => (others => '0'),
data_out_a => value_v,
data_out_b => open
);
mem_sigma : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma,
rw_a => '0',
rw_b => write_enable_new_value_sigma,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma,
address_b => address_new_value_sigma,
rst_value => (others => '0'),
data_out_a => value_sigma,
data_out_b => open
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
process
variable i : integer;
variable syndrome_cycle_count : integer range 0 to 2000000000 := 0;
variable key_equation_cycle_count : integer range 0 to 2000000000 := 0;
variable correct_errors_cycle_count : integer range 0 to 2000000000 := 0;
begin
true_address_new_value_message <= (others => '0');
true_address_new_value_error <= (others => '0');
rst <= '1';
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_generation_finalized = '1';
syndrome_cycle_count := cycle_count - 2;
report "Circuit finish Syndrome = " & integer'image(syndrome_cycle_count/2) & " cycles";
wait until key_equation_finalized = '1';
key_equation_cycle_count := cycle_count - syndrome_cycle_count;
report "Circuit finish Key Equation = " & integer'image(key_equation_cycle_count/2) & " cycles";
wait until decryption_finalized = '1';
correct_errors_cycle_count := cycle_count - key_equation_cycle_count - syndrome_cycle_count;
report "Circuit finish Correct Errors = " & integer'image(correct_errors_cycle_count/2) & " cycles";
report "Circuit finish = " & integer'image(cycle_count/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
true_address_new_value_message(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
true_address_new_value_error(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
wait for PERIOD*2;
if (true_value_message(0) = test_value_message(0)) then
error_value_message <= '0';
else
error_value_message <= '1';
report "Computed values do not match expected ones";
end if;
if (true_value_error(0) = test_value_error(0)) then
error_value_error <= '0';
else
error_value_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD;
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
end loop;
wait for PERIOD;
test_bench_finish <= '1';
wait;
end process;
end Behavioral; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRUSBHC +
CFG_GRUSBDC;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_fifo is
port(
atm : in vl_logic_vector(35 downto 0);
clk : in vl_logic;
dbrk_traceme : in vl_logic;
dbrk_traceoff : in vl_logic;
dbrk_traceon : in vl_logic;
dct_buffer : in vl_logic_vector(29 downto 0);
dct_count : in vl_logic_vector(3 downto 0);
dtm : in vl_logic_vector(35 downto 0);
itm : in vl_logic_vector(35 downto 0);
jrst_n : in vl_logic;
reset_n : in vl_logic;
test_ending : in vl_logic;
test_has_ended : in vl_logic;
trc_on : in vl_logic;
tw : out vl_logic_vector(35 downto 0)
);
end finalproject_cpu_nios2_oci_fifo;
|
-- NEED RESULT: ARCH00035.P1: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P2: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P3: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P4: Target of a variable assignment may be a aggregate of slices passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00035
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00035)
-- ENT00035_Test_Bench(ARCH00035_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00035 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P1" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00035.P2" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P3" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_boolean_vector_2 : inout st_boolean_vector
; v_st_bit_vector_2 : inout st_bit_vector
; v_st_severity_level_vector_2 : inout st_severity_level_vector
; v_st_string_2 : inout st_string
; v_st_enum1_vector_2 : inout st_enum1_vector
; v_st_integer_vector_2 : inout st_integer_vector
; v_st_int1_vector_2 : inout st_int1_vector
; v_st_time_vector_2 : inout st_time_vector
; v_st_phys1_vector_2 : inout st_phys1_vector
; v_st_real_vector_2 : inout st_real_vector
; v_st_real1_vector_2 : inout st_real1_vector
; v_st_rec1_vector_2 : inout st_rec1_vector
; v_st_rec2_vector_2 : inout st_rec2_vector
; v_st_rec3_vector_2 : inout st_rec3_vector
; v_st_arr1_vector_2 : inout st_arr1_vector
; v_st_arr2_vector_2 : inout st_arr2_vector
; v_st_arr3_vector_2 : inout st_arr3_vector
)
is
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
end Proc1 ;
begin
Proc1 (
v_st_boolean_vector_2
, v_st_bit_vector_2
, v_st_severity_level_vector_2
, v_st_string_2
, v_st_enum1_vector_2
, v_st_integer_vector_2
, v_st_int1_vector_2
, v_st_time_vector_2
, v_st_phys1_vector_2
, v_st_real_vector_2
, v_st_real1_vector_2
, v_st_rec1_vector_2
, v_st_rec2_vector_2
, v_st_rec3_vector_2
, v_st_arr1_vector_2
, v_st_arr2_vector_2
, v_st_arr3_vector_2
) ;
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P4" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P4 ;
--
end ARCH00035 ;
--
entity ENT00035_Test_Bench is
end ENT00035_Test_Bench ;
--
architecture ARCH00035_Test_Bench of ENT00035_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00035 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00035_Test_Bench ;
|
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(0 to 0);
S_AXI_HP0_RID : out std_logic_vector(0 to 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(0 to 0);
S_AXI_HP0_AWID : in std_logic_vector(0 to 0);
S_AXI_HP0_WID : in std_logic_vector(0 to 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(1 downto 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(1 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(1 downto 0);
M_AXI_AWID : out std_logic_vector(23 downto 0);
M_AXI_AWADDR : out std_logic_vector(63 downto 0);
M_AXI_AWLEN : out std_logic_vector(15 downto 0);
M_AXI_AWSIZE : out std_logic_vector(5 downto 0);
M_AXI_AWBURST : out std_logic_vector(3 downto 0);
M_AXI_AWLOCK : out std_logic_vector(3 downto 0);
M_AXI_AWCACHE : out std_logic_vector(7 downto 0);
M_AXI_AWPROT : out std_logic_vector(5 downto 0);
M_AXI_AWREGION : out std_logic_vector(7 downto 0);
M_AXI_AWQOS : out std_logic_vector(7 downto 0);
M_AXI_AWUSER : out std_logic_vector(1 downto 0);
M_AXI_AWVALID : out std_logic_vector(1 downto 0);
M_AXI_AWREADY : in std_logic_vector(1 downto 0);
M_AXI_WID : out std_logic_vector(23 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(1 downto 0);
M_AXI_WUSER : out std_logic_vector(1 downto 0);
M_AXI_WVALID : out std_logic_vector(1 downto 0);
M_AXI_WREADY : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(23 downto 0);
M_AXI_BRESP : in std_logic_vector(3 downto 0);
M_AXI_BUSER : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic_vector(1 downto 0);
M_AXI_BREADY : out std_logic_vector(1 downto 0);
M_AXI_ARID : out std_logic_vector(23 downto 0);
M_AXI_ARADDR : out std_logic_vector(63 downto 0);
M_AXI_ARLEN : out std_logic_vector(15 downto 0);
M_AXI_ARSIZE : out std_logic_vector(5 downto 0);
M_AXI_ARBURST : out std_logic_vector(3 downto 0);
M_AXI_ARLOCK : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(7 downto 0);
M_AXI_ARPROT : out std_logic_vector(5 downto 0);
M_AXI_ARREGION : out std_logic_vector(7 downto 0);
M_AXI_ARQOS : out std_logic_vector(7 downto 0);
M_AXI_ARUSER : out std_logic_vector(1 downto 0);
M_AXI_ARVALID : out std_logic_vector(1 downto 0);
M_AXI_ARREADY : in std_logic_vector(1 downto 0);
M_AXI_RID : in std_logic_vector(23 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(3 downto 0);
M_AXI_RLAST : in std_logic_vector(1 downto 0);
M_AXI_RUSER : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic_vector(1 downto 0);
M_AXI_RREADY : out std_logic_vector(1 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_axi_interconnect_2_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(0 to 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(0 to 0);
S_AXI_WDATA : in std_logic_vector(63 downto 0);
S_AXI_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(0 to 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(0 to 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(0 to 0);
S_AXI_RDATA : out std_logic_vector(63 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(0 to 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(0 to 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(0 to 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(0 to 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(0 to 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal axi_dispctrl_0_BLUE_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_DE_O : std_logic;
signal axi_dispctrl_0_ENABLE_O : std_logic;
signal axi_dispctrl_0_FSYNC_O : std_logic;
signal axi_dispctrl_0_GREEN_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_HSYNC_O : std_logic;
signal axi_dispctrl_0_PXL_CLK_O : std_logic;
signal axi_dispctrl_0_RED_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_VDMA_CLK_O : std_logic;
signal axi_dispctrl_0_VSYNC_O : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_RID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_WID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_RVALID : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_TKEEP : std_logic_vector(3 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(31 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal axi_vdma_0_mm2s_introut : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd24 : std_logic_vector(23 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(1 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_I2C0_INT_N : std_logic;
signal processing_system7_0_I2C0_SCL_I : std_logic;
signal processing_system7_0_I2C0_SCL_O : std_logic;
signal processing_system7_0_I2C0_SCL_T : std_logic;
signal processing_system7_0_I2C0_SDA_I : std_logic;
signal processing_system7_0_I2C0_SDA_O : std_logic;
signal processing_system7_0_I2C0_SDA_T : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dispctrl_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_2_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
axi_dispctrl_0_HSYNC_O_pin <= axi_dispctrl_0_HSYNC_O;
axi_dispctrl_0_VSYNC_O_pin <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0_PXL_CLK_O_pin <= axi_dispctrl_0_PXL_CLK_O;
axi_dispctrl_0_DE_O_pin <= axi_dispctrl_0_DE_O;
axi_dispctrl_0_RED_O_pin <= axi_dispctrl_0_RED_O;
axi_dispctrl_0_GREEN_O_pin <= axi_dispctrl_0_GREEN_O;
axi_dispctrl_0_BLUE_O_pin <= axi_dispctrl_0_BLUE_O;
axi_dispctrl_0_ENABLE_O_pin <= axi_dispctrl_0_ENABLE_O;
processing_system7_0_I2C0_INT_N <= processing_system7_0_I2C0_INT_N_pin;
processing_system7_0_FCLK_CLK0_pin <= processing_system7_0_FCLK_CLK0(0);
pgassign1(1) <= axi_vdma_0_mm2s_introut;
pgassign1(0) <= processing_system7_0_I2C0_INT_N;
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd24(23 downto 0) <= B"000000000000000000000000";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(3 downto 0) <= B"1111";
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => processing_system7_0_I2C0_SDA_I,
I2C0_SDA_O => processing_system7_0_I2C0_SDA_O,
I2C0_SDA_T => processing_system7_0_I2C0_SDA_T,
I2C0_SCL_I => processing_system7_0_I2C0_SCL_I,
I2C0_SCL_O => processing_system7_0_I2C0_SCL_O,
I2C0_SCL_T => processing_system7_0_I2C0_SCL_T,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi_interconnect_1_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi_interconnect_1_S_AWVALID(0),
M_AXI_GP0_BREADY => axi_interconnect_1_S_BREADY(0),
M_AXI_GP0_RREADY => axi_interconnect_1_S_RREADY(0),
M_AXI_GP0_WLAST => axi_interconnect_1_S_WLAST(0),
M_AXI_GP0_WVALID => axi_interconnect_1_S_WVALID(0),
M_AXI_GP0_ARID => axi_interconnect_1_S_ARID,
M_AXI_GP0_AWID => axi_interconnect_1_S_AWID,
M_AXI_GP0_WID => axi_interconnect_1_S_WID,
M_AXI_GP0_ARBURST => axi_interconnect_1_S_ARBURST,
M_AXI_GP0_ARLOCK => axi_interconnect_1_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi_interconnect_1_S_ARSIZE,
M_AXI_GP0_AWBURST => axi_interconnect_1_S_AWBURST,
M_AXI_GP0_AWLOCK => axi_interconnect_1_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi_interconnect_1_S_AWSIZE,
M_AXI_GP0_ARPROT => axi_interconnect_1_S_ARPROT,
M_AXI_GP0_AWPROT => axi_interconnect_1_S_AWPROT,
M_AXI_GP0_ARADDR => axi_interconnect_1_S_ARADDR,
M_AXI_GP0_AWADDR => axi_interconnect_1_S_AWADDR,
M_AXI_GP0_WDATA => axi_interconnect_1_S_WDATA,
M_AXI_GP0_ARCACHE => axi_interconnect_1_S_ARCACHE,
M_AXI_GP0_ARLEN => axi_interconnect_1_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi_interconnect_1_S_ARQOS,
M_AXI_GP0_AWCACHE => axi_interconnect_1_S_AWCACHE,
M_AXI_GP0_AWLEN => axi_interconnect_1_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi_interconnect_1_S_AWQOS,
M_AXI_GP0_WSTRB => axi_interconnect_1_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi_interconnect_1_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi_interconnect_1_S_AWREADY(0),
M_AXI_GP0_BVALID => axi_interconnect_1_S_BVALID(0),
M_AXI_GP0_RLAST => axi_interconnect_1_S_RLAST(0),
M_AXI_GP0_RVALID => axi_interconnect_1_S_RVALID(0),
M_AXI_GP0_WREADY => axi_interconnect_1_S_WREADY(0),
M_AXI_GP0_BID => axi_interconnect_1_S_BID,
M_AXI_GP0_RID => axi_interconnect_1_S_RID,
M_AXI_GP0_BRESP => axi_interconnect_1_S_BRESP,
M_AXI_GP0_RRESP => axi_interconnect_1_S_RRESP,
M_AXI_GP0_RDATA => axi_interconnect_1_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_2_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_2_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_2_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_2_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_2_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_2_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_2_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_2_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_2_M_BID(0 to 0),
S_AXI_HP0_RID => axi_interconnect_2_M_RID(0 to 0),
S_AXI_HP0_RDATA => axi_interconnect_2_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_HP0_ARVALID => axi_interconnect_2_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_2_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_2_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_2_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_2_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_2_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_2_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_2_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_2_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_2_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_2_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_2_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_2_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_2_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_2_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_2_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_2_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_2_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_2_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_2_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_2_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_2_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_2_M_ARID(0 to 0),
S_AXI_HP0_AWID => axi_interconnect_2_M_AWID(0 to 0),
S_AXI_HP0_WID => axi_interconnect_2_M_WID(0 to 0),
S_AXI_HP0_WDATA => axi_interconnect_2_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_2_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => pgassign1,
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_dispctrl_0 : system_axi_dispctrl_0_wrapper
port map (
REF_CLK_I => processing_system7_0_FCLK_CLK0(0),
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
VDMA_CLK_O => axi_dispctrl_0_VDMA_CLK_O,
PXL_CLK_5X_O => open,
LOCKED_O => open,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
HSYNC_O => axi_dispctrl_0_HSYNC_O,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
DE_O => axi_dispctrl_0_DE_O,
RED_O => axi_dispctrl_0_RED_O,
GREEN_O => axi_dispctrl_0_GREEN_O,
BLUE_O => axi_dispctrl_0_BLUE_O,
ENABLE_O => axi_dispctrl_0_ENABLE_O,
DEBUG_O => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi_interconnect_1_M_ARESETN(0),
S_AXI_AWADDR => axi_interconnect_1_M_AWADDR(31 downto 0),
S_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_WDATA => axi_interconnect_1_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi_interconnect_1_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_ARADDR => axi_interconnect_1_M_ARADDR(31 downto 0),
S_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_RDATA => axi_interconnect_1_M_RDATA(31 downto 0),
S_AXI_RRESP => axi_interconnect_1_M_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_BRESP => axi_interconnect_1_M_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXIS_TREADY => axi_vdma_0_M_AXIS_MM2S_tready,
S_AXIS_ACLK => net_gnd0,
S_AXIS_ARESETN => net_vcc0,
S_AXIS_TDATA => axi_vdma_0_M_AXIS_MM2S_tdata,
S_AXIS_TVALID => axi_vdma_0_M_AXIS_MM2S_tvalid,
S_AXIS_TLAST => axi_vdma_0_M_AXIS_MM2S_tlast,
S_AXIS_TSTRB => axi_vdma_0_M_AXIS_MM2S_TKEEP
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi_interconnect_1_M_ARESETN,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi_interconnect_1_S_AWID,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_S_AWLOCK,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => axi_interconnect_1_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY(0 to 0),
S_AXI_WID => axi_interconnect_1_S_WID,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi_interconnect_1_S_WVALID(0 to 0),
S_AXI_WREADY => axi_interconnect_1_S_WREADY(0 to 0),
S_AXI_BID => axi_interconnect_1_S_BID,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID(0 to 0),
S_AXI_BREADY => axi_interconnect_1_S_BREADY(0 to 0),
S_AXI_ARID => axi_interconnect_1_S_ARID,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_S_ARLOCK,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => axi_interconnect_1_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY(0 to 0),
S_AXI_RID => axi_interconnect_1_S_RID,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_1_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign2,
M_AXI_AWID => open,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID,
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID,
M_AXI_WREADY => axi_interconnect_1_M_WREADY,
M_AXI_BID => net_gnd24,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd2,
M_AXI_BVALID => axi_interconnect_1_M_BVALID,
M_AXI_BREADY => axi_interconnect_1_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID,
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY,
M_AXI_RID => net_gnd24,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => net_gnd2,
M_AXI_RUSER => net_gnd2,
M_AXI_RVALID => axi_interconnect_1_M_RVALID,
M_AXI_RREADY => axi_interconnect_1_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_s2mm_aclk => net_gnd0,
m_axis_mm2s_aclk => axi_dispctrl_0_VDMA_CLK_O,
s_axis_s2mm_aclk => net_gnd0,
axi_resetn => axi_interconnect_1_M_ARESETN(1),
s_axi_lite_awvalid => axi_interconnect_1_M_AWVALID(1),
s_axi_lite_awready => axi_interconnect_1_M_AWREADY(1),
s_axi_lite_awaddr => axi_interconnect_1_M_AWADDR(40 downto 32),
s_axi_lite_wvalid => axi_interconnect_1_M_WVALID(1),
s_axi_lite_wready => axi_interconnect_1_M_WREADY(1),
s_axi_lite_wdata => axi_interconnect_1_M_WDATA(63 downto 32),
s_axi_lite_bresp => axi_interconnect_1_M_BRESP(3 downto 2),
s_axi_lite_bvalid => axi_interconnect_1_M_BVALID(1),
s_axi_lite_bready => axi_interconnect_1_M_BREADY(1),
s_axi_lite_arvalid => axi_interconnect_1_M_ARVALID(1),
s_axi_lite_arready => axi_interconnect_1_M_ARREADY(1),
s_axi_lite_araddr => axi_interconnect_1_M_ARADDR(40 downto 32),
s_axi_lite_rvalid => axi_interconnect_1_M_RVALID(1),
s_axi_lite_rready => axi_interconnect_1_M_RREADY(1),
s_axi_lite_rdata => axi_interconnect_1_M_RDATA(63 downto 32),
s_axi_lite_rresp => axi_interconnect_1_M_RRESP(3 downto 2),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_2_S_ARADDR,
m_axi_mm2s_arlen => axi_interconnect_2_S_ARLEN,
m_axi_mm2s_arsize => axi_interconnect_2_S_ARSIZE,
m_axi_mm2s_arburst => axi_interconnect_2_S_ARBURST,
m_axi_mm2s_arprot => axi_interconnect_2_S_ARPROT,
m_axi_mm2s_arcache => axi_interconnect_2_S_ARCACHE,
m_axi_mm2s_arvalid => axi_interconnect_2_S_ARVALID(0),
m_axi_mm2s_arready => axi_interconnect_2_S_ARREADY(0),
m_axi_mm2s_rdata => axi_interconnect_2_S_RDATA,
m_axi_mm2s_rresp => axi_interconnect_2_S_RRESP,
m_axi_mm2s_rlast => axi_interconnect_2_S_RLAST(0),
m_axi_mm2s_rvalid => axi_interconnect_2_S_RVALID(0),
m_axi_mm2s_rready => axi_interconnect_2_S_RREADY(0),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => axi_vdma_0_M_AXIS_MM2S_TKEEP,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => open,
m_axi_s2mm_awaddr => open,
m_axi_s2mm_awlen => open,
m_axi_s2mm_awsize => open,
m_axi_s2mm_awburst => open,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => open,
m_axi_s2mm_awready => net_gnd0,
m_axi_s2mm_wdata => open,
m_axi_s2mm_wstrb => open,
m_axi_s2mm_wlast => open,
m_axi_s2mm_wvalid => open,
m_axi_s2mm_wready => net_gnd0,
m_axi_s2mm_bresp => net_gnd2,
m_axi_s2mm_bvalid => net_gnd0,
m_axi_s2mm_bready => open,
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => net_gnd32,
s_axis_s2mm_tkeep => net_vcc4,
s_axis_s2mm_tvalid => net_gnd0,
s_axis_s2mm_tready => open,
s_axis_s2mm_tlast => net_gnd0,
s_axis_s2mm_tuser => net_gnd1(0 to 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => axi_vdma_0_mm2s_introut,
s2mm_introut => open,
axi_vdma_tstvec => open
);
axi_interconnect_2 : system_axi_interconnect_2_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => net_gnd1(0 to 0),
S_AXI_AWADDR => net_gnd32,
S_AXI_AWLEN => net_gnd8,
S_AXI_AWSIZE => net_gnd3,
S_AXI_AWBURST => net_gnd2,
S_AXI_AWLOCK => net_gnd2,
S_AXI_AWCACHE => net_gnd4,
S_AXI_AWPROT => net_gnd3,
S_AXI_AWQOS => net_gnd4,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => net_gnd1(0 to 0),
S_AXI_AWREADY => open,
S_AXI_WID => net_gnd1(0 to 0),
S_AXI_WDATA => net_gnd64,
S_AXI_WSTRB => net_gnd8,
S_AXI_WLAST => net_gnd1(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => net_gnd1(0 to 0),
S_AXI_WREADY => open,
S_AXI_BID => open,
S_AXI_BRESP => open,
S_AXI_BUSER => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd1(0 to 0),
S_AXI_ARID => net_gnd1(0 to 0),
S_AXI_ARADDR => axi_interconnect_2_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_2_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_2_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_2_S_ARBURST,
S_AXI_ARLOCK => net_gnd2,
S_AXI_ARCACHE => axi_interconnect_2_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_2_S_ARPROT,
S_AXI_ARQOS => net_gnd4,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_2_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_2_S_ARREADY(0 to 0),
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_2_S_RDATA,
S_AXI_RRESP => axi_interconnect_2_S_RRESP,
S_AXI_RLAST => axi_interconnect_2_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_2_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_2_S_RREADY(0 to 0),
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_2_M_AWID(0 to 0),
M_AXI_AWADDR => axi_interconnect_2_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_2_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_2_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_2_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_2_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_2_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_2_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_2_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_2_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_2_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_2_M_WID(0 to 0),
M_AXI_WDATA => axi_interconnect_2_M_WDATA,
M_AXI_WSTRB => axi_interconnect_2_M_WSTRB,
M_AXI_WLAST => axi_interconnect_2_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_2_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_2_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_2_M_BID(0 to 0),
M_AXI_BRESP => axi_interconnect_2_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_2_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_2_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_2_M_ARID(0 to 0),
M_AXI_ARADDR => axi_interconnect_2_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_2_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_2_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_2_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_2_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_2_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_2_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_2_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_2_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_2_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_2_M_RID(0 to 0),
M_AXI_RDATA => axi_interconnect_2_M_RDATA,
M_AXI_RRESP => axi_interconnect_2_M_RRESP,
M_AXI_RLAST => axi_interconnect_2_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_2_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_2_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
iobuf_0 : IOBUF
port map (
I => processing_system7_0_I2C0_SDA_O,
IO => processing_system7_0_I2C0_SDA_pin,
O => processing_system7_0_I2C0_SDA_I,
T => processing_system7_0_I2C0_SDA_T
);
iobuf_1 : IOBUF
port map (
I => processing_system7_0_I2C0_SCL_O,
IO => processing_system7_0_I2C0_SCL_pin,
O => processing_system7_0_I2C0_SCL_I,
T => processing_system7_0_I2C0_SCL_T
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(0 to 0);
S_AXI_HP0_RID : out std_logic_vector(0 to 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(0 to 0);
S_AXI_HP0_AWID : in std_logic_vector(0 to 0);
S_AXI_HP0_WID : in std_logic_vector(0 to 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(1 downto 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(1 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(1 downto 0);
M_AXI_AWID : out std_logic_vector(23 downto 0);
M_AXI_AWADDR : out std_logic_vector(63 downto 0);
M_AXI_AWLEN : out std_logic_vector(15 downto 0);
M_AXI_AWSIZE : out std_logic_vector(5 downto 0);
M_AXI_AWBURST : out std_logic_vector(3 downto 0);
M_AXI_AWLOCK : out std_logic_vector(3 downto 0);
M_AXI_AWCACHE : out std_logic_vector(7 downto 0);
M_AXI_AWPROT : out std_logic_vector(5 downto 0);
M_AXI_AWREGION : out std_logic_vector(7 downto 0);
M_AXI_AWQOS : out std_logic_vector(7 downto 0);
M_AXI_AWUSER : out std_logic_vector(1 downto 0);
M_AXI_AWVALID : out std_logic_vector(1 downto 0);
M_AXI_AWREADY : in std_logic_vector(1 downto 0);
M_AXI_WID : out std_logic_vector(23 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(1 downto 0);
M_AXI_WUSER : out std_logic_vector(1 downto 0);
M_AXI_WVALID : out std_logic_vector(1 downto 0);
M_AXI_WREADY : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(23 downto 0);
M_AXI_BRESP : in std_logic_vector(3 downto 0);
M_AXI_BUSER : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic_vector(1 downto 0);
M_AXI_BREADY : out std_logic_vector(1 downto 0);
M_AXI_ARID : out std_logic_vector(23 downto 0);
M_AXI_ARADDR : out std_logic_vector(63 downto 0);
M_AXI_ARLEN : out std_logic_vector(15 downto 0);
M_AXI_ARSIZE : out std_logic_vector(5 downto 0);
M_AXI_ARBURST : out std_logic_vector(3 downto 0);
M_AXI_ARLOCK : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(7 downto 0);
M_AXI_ARPROT : out std_logic_vector(5 downto 0);
M_AXI_ARREGION : out std_logic_vector(7 downto 0);
M_AXI_ARQOS : out std_logic_vector(7 downto 0);
M_AXI_ARUSER : out std_logic_vector(1 downto 0);
M_AXI_ARVALID : out std_logic_vector(1 downto 0);
M_AXI_ARREADY : in std_logic_vector(1 downto 0);
M_AXI_RID : in std_logic_vector(23 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(3 downto 0);
M_AXI_RLAST : in std_logic_vector(1 downto 0);
M_AXI_RUSER : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic_vector(1 downto 0);
M_AXI_RREADY : out std_logic_vector(1 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_axi_interconnect_2_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(0 to 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(0 to 0);
S_AXI_WDATA : in std_logic_vector(63 downto 0);
S_AXI_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(0 to 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(0 to 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(0 to 0);
S_AXI_RDATA : out std_logic_vector(63 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(0 to 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(0 to 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(0 to 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(0 to 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(0 to 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal axi_dispctrl_0_BLUE_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_DE_O : std_logic;
signal axi_dispctrl_0_ENABLE_O : std_logic;
signal axi_dispctrl_0_FSYNC_O : std_logic;
signal axi_dispctrl_0_GREEN_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_HSYNC_O : std_logic;
signal axi_dispctrl_0_PXL_CLK_O : std_logic;
signal axi_dispctrl_0_RED_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_VDMA_CLK_O : std_logic;
signal axi_dispctrl_0_VSYNC_O : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_RID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_WID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_RVALID : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_TKEEP : std_logic_vector(3 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(31 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal axi_vdma_0_mm2s_introut : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd24 : std_logic_vector(23 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(1 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_I2C0_INT_N : std_logic;
signal processing_system7_0_I2C0_SCL_I : std_logic;
signal processing_system7_0_I2C0_SCL_O : std_logic;
signal processing_system7_0_I2C0_SCL_T : std_logic;
signal processing_system7_0_I2C0_SDA_I : std_logic;
signal processing_system7_0_I2C0_SDA_O : std_logic;
signal processing_system7_0_I2C0_SDA_T : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dispctrl_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_2_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
axi_dispctrl_0_HSYNC_O_pin <= axi_dispctrl_0_HSYNC_O;
axi_dispctrl_0_VSYNC_O_pin <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0_PXL_CLK_O_pin <= axi_dispctrl_0_PXL_CLK_O;
axi_dispctrl_0_DE_O_pin <= axi_dispctrl_0_DE_O;
axi_dispctrl_0_RED_O_pin <= axi_dispctrl_0_RED_O;
axi_dispctrl_0_GREEN_O_pin <= axi_dispctrl_0_GREEN_O;
axi_dispctrl_0_BLUE_O_pin <= axi_dispctrl_0_BLUE_O;
axi_dispctrl_0_ENABLE_O_pin <= axi_dispctrl_0_ENABLE_O;
processing_system7_0_I2C0_INT_N <= processing_system7_0_I2C0_INT_N_pin;
processing_system7_0_FCLK_CLK0_pin <= processing_system7_0_FCLK_CLK0(0);
pgassign1(1) <= axi_vdma_0_mm2s_introut;
pgassign1(0) <= processing_system7_0_I2C0_INT_N;
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd24(23 downto 0) <= B"000000000000000000000000";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(3 downto 0) <= B"1111";
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => processing_system7_0_I2C0_SDA_I,
I2C0_SDA_O => processing_system7_0_I2C0_SDA_O,
I2C0_SDA_T => processing_system7_0_I2C0_SDA_T,
I2C0_SCL_I => processing_system7_0_I2C0_SCL_I,
I2C0_SCL_O => processing_system7_0_I2C0_SCL_O,
I2C0_SCL_T => processing_system7_0_I2C0_SCL_T,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi_interconnect_1_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi_interconnect_1_S_AWVALID(0),
M_AXI_GP0_BREADY => axi_interconnect_1_S_BREADY(0),
M_AXI_GP0_RREADY => axi_interconnect_1_S_RREADY(0),
M_AXI_GP0_WLAST => axi_interconnect_1_S_WLAST(0),
M_AXI_GP0_WVALID => axi_interconnect_1_S_WVALID(0),
M_AXI_GP0_ARID => axi_interconnect_1_S_ARID,
M_AXI_GP0_AWID => axi_interconnect_1_S_AWID,
M_AXI_GP0_WID => axi_interconnect_1_S_WID,
M_AXI_GP0_ARBURST => axi_interconnect_1_S_ARBURST,
M_AXI_GP0_ARLOCK => axi_interconnect_1_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi_interconnect_1_S_ARSIZE,
M_AXI_GP0_AWBURST => axi_interconnect_1_S_AWBURST,
M_AXI_GP0_AWLOCK => axi_interconnect_1_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi_interconnect_1_S_AWSIZE,
M_AXI_GP0_ARPROT => axi_interconnect_1_S_ARPROT,
M_AXI_GP0_AWPROT => axi_interconnect_1_S_AWPROT,
M_AXI_GP0_ARADDR => axi_interconnect_1_S_ARADDR,
M_AXI_GP0_AWADDR => axi_interconnect_1_S_AWADDR,
M_AXI_GP0_WDATA => axi_interconnect_1_S_WDATA,
M_AXI_GP0_ARCACHE => axi_interconnect_1_S_ARCACHE,
M_AXI_GP0_ARLEN => axi_interconnect_1_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi_interconnect_1_S_ARQOS,
M_AXI_GP0_AWCACHE => axi_interconnect_1_S_AWCACHE,
M_AXI_GP0_AWLEN => axi_interconnect_1_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi_interconnect_1_S_AWQOS,
M_AXI_GP0_WSTRB => axi_interconnect_1_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi_interconnect_1_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi_interconnect_1_S_AWREADY(0),
M_AXI_GP0_BVALID => axi_interconnect_1_S_BVALID(0),
M_AXI_GP0_RLAST => axi_interconnect_1_S_RLAST(0),
M_AXI_GP0_RVALID => axi_interconnect_1_S_RVALID(0),
M_AXI_GP0_WREADY => axi_interconnect_1_S_WREADY(0),
M_AXI_GP0_BID => axi_interconnect_1_S_BID,
M_AXI_GP0_RID => axi_interconnect_1_S_RID,
M_AXI_GP0_BRESP => axi_interconnect_1_S_BRESP,
M_AXI_GP0_RRESP => axi_interconnect_1_S_RRESP,
M_AXI_GP0_RDATA => axi_interconnect_1_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_2_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_2_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_2_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_2_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_2_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_2_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_2_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_2_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_2_M_BID(0 to 0),
S_AXI_HP0_RID => axi_interconnect_2_M_RID(0 to 0),
S_AXI_HP0_RDATA => axi_interconnect_2_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_HP0_ARVALID => axi_interconnect_2_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_2_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_2_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_2_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_2_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_2_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_2_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_2_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_2_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_2_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_2_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_2_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_2_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_2_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_2_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_2_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_2_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_2_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_2_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_2_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_2_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_2_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_2_M_ARID(0 to 0),
S_AXI_HP0_AWID => axi_interconnect_2_M_AWID(0 to 0),
S_AXI_HP0_WID => axi_interconnect_2_M_WID(0 to 0),
S_AXI_HP0_WDATA => axi_interconnect_2_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_2_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => pgassign1,
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_dispctrl_0 : system_axi_dispctrl_0_wrapper
port map (
REF_CLK_I => processing_system7_0_FCLK_CLK0(0),
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
VDMA_CLK_O => axi_dispctrl_0_VDMA_CLK_O,
PXL_CLK_5X_O => open,
LOCKED_O => open,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
HSYNC_O => axi_dispctrl_0_HSYNC_O,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
DE_O => axi_dispctrl_0_DE_O,
RED_O => axi_dispctrl_0_RED_O,
GREEN_O => axi_dispctrl_0_GREEN_O,
BLUE_O => axi_dispctrl_0_BLUE_O,
ENABLE_O => axi_dispctrl_0_ENABLE_O,
DEBUG_O => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi_interconnect_1_M_ARESETN(0),
S_AXI_AWADDR => axi_interconnect_1_M_AWADDR(31 downto 0),
S_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_WDATA => axi_interconnect_1_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi_interconnect_1_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_ARADDR => axi_interconnect_1_M_ARADDR(31 downto 0),
S_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_RDATA => axi_interconnect_1_M_RDATA(31 downto 0),
S_AXI_RRESP => axi_interconnect_1_M_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_BRESP => axi_interconnect_1_M_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXIS_TREADY => axi_vdma_0_M_AXIS_MM2S_tready,
S_AXIS_ACLK => net_gnd0,
S_AXIS_ARESETN => net_vcc0,
S_AXIS_TDATA => axi_vdma_0_M_AXIS_MM2S_tdata,
S_AXIS_TVALID => axi_vdma_0_M_AXIS_MM2S_tvalid,
S_AXIS_TLAST => axi_vdma_0_M_AXIS_MM2S_tlast,
S_AXIS_TSTRB => axi_vdma_0_M_AXIS_MM2S_TKEEP
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi_interconnect_1_M_ARESETN,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi_interconnect_1_S_AWID,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_S_AWLOCK,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => axi_interconnect_1_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY(0 to 0),
S_AXI_WID => axi_interconnect_1_S_WID,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi_interconnect_1_S_WVALID(0 to 0),
S_AXI_WREADY => axi_interconnect_1_S_WREADY(0 to 0),
S_AXI_BID => axi_interconnect_1_S_BID,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID(0 to 0),
S_AXI_BREADY => axi_interconnect_1_S_BREADY(0 to 0),
S_AXI_ARID => axi_interconnect_1_S_ARID,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_S_ARLOCK,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => axi_interconnect_1_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY(0 to 0),
S_AXI_RID => axi_interconnect_1_S_RID,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_1_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign2,
M_AXI_AWID => open,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID,
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID,
M_AXI_WREADY => axi_interconnect_1_M_WREADY,
M_AXI_BID => net_gnd24,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd2,
M_AXI_BVALID => axi_interconnect_1_M_BVALID,
M_AXI_BREADY => axi_interconnect_1_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID,
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY,
M_AXI_RID => net_gnd24,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => net_gnd2,
M_AXI_RUSER => net_gnd2,
M_AXI_RVALID => axi_interconnect_1_M_RVALID,
M_AXI_RREADY => axi_interconnect_1_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_s2mm_aclk => net_gnd0,
m_axis_mm2s_aclk => axi_dispctrl_0_VDMA_CLK_O,
s_axis_s2mm_aclk => net_gnd0,
axi_resetn => axi_interconnect_1_M_ARESETN(1),
s_axi_lite_awvalid => axi_interconnect_1_M_AWVALID(1),
s_axi_lite_awready => axi_interconnect_1_M_AWREADY(1),
s_axi_lite_awaddr => axi_interconnect_1_M_AWADDR(40 downto 32),
s_axi_lite_wvalid => axi_interconnect_1_M_WVALID(1),
s_axi_lite_wready => axi_interconnect_1_M_WREADY(1),
s_axi_lite_wdata => axi_interconnect_1_M_WDATA(63 downto 32),
s_axi_lite_bresp => axi_interconnect_1_M_BRESP(3 downto 2),
s_axi_lite_bvalid => axi_interconnect_1_M_BVALID(1),
s_axi_lite_bready => axi_interconnect_1_M_BREADY(1),
s_axi_lite_arvalid => axi_interconnect_1_M_ARVALID(1),
s_axi_lite_arready => axi_interconnect_1_M_ARREADY(1),
s_axi_lite_araddr => axi_interconnect_1_M_ARADDR(40 downto 32),
s_axi_lite_rvalid => axi_interconnect_1_M_RVALID(1),
s_axi_lite_rready => axi_interconnect_1_M_RREADY(1),
s_axi_lite_rdata => axi_interconnect_1_M_RDATA(63 downto 32),
s_axi_lite_rresp => axi_interconnect_1_M_RRESP(3 downto 2),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_2_S_ARADDR,
m_axi_mm2s_arlen => axi_interconnect_2_S_ARLEN,
m_axi_mm2s_arsize => axi_interconnect_2_S_ARSIZE,
m_axi_mm2s_arburst => axi_interconnect_2_S_ARBURST,
m_axi_mm2s_arprot => axi_interconnect_2_S_ARPROT,
m_axi_mm2s_arcache => axi_interconnect_2_S_ARCACHE,
m_axi_mm2s_arvalid => axi_interconnect_2_S_ARVALID(0),
m_axi_mm2s_arready => axi_interconnect_2_S_ARREADY(0),
m_axi_mm2s_rdata => axi_interconnect_2_S_RDATA,
m_axi_mm2s_rresp => axi_interconnect_2_S_RRESP,
m_axi_mm2s_rlast => axi_interconnect_2_S_RLAST(0),
m_axi_mm2s_rvalid => axi_interconnect_2_S_RVALID(0),
m_axi_mm2s_rready => axi_interconnect_2_S_RREADY(0),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => axi_vdma_0_M_AXIS_MM2S_TKEEP,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => open,
m_axi_s2mm_awaddr => open,
m_axi_s2mm_awlen => open,
m_axi_s2mm_awsize => open,
m_axi_s2mm_awburst => open,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => open,
m_axi_s2mm_awready => net_gnd0,
m_axi_s2mm_wdata => open,
m_axi_s2mm_wstrb => open,
m_axi_s2mm_wlast => open,
m_axi_s2mm_wvalid => open,
m_axi_s2mm_wready => net_gnd0,
m_axi_s2mm_bresp => net_gnd2,
m_axi_s2mm_bvalid => net_gnd0,
m_axi_s2mm_bready => open,
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => net_gnd32,
s_axis_s2mm_tkeep => net_vcc4,
s_axis_s2mm_tvalid => net_gnd0,
s_axis_s2mm_tready => open,
s_axis_s2mm_tlast => net_gnd0,
s_axis_s2mm_tuser => net_gnd1(0 to 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => axi_vdma_0_mm2s_introut,
s2mm_introut => open,
axi_vdma_tstvec => open
);
axi_interconnect_2 : system_axi_interconnect_2_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => net_gnd1(0 to 0),
S_AXI_AWADDR => net_gnd32,
S_AXI_AWLEN => net_gnd8,
S_AXI_AWSIZE => net_gnd3,
S_AXI_AWBURST => net_gnd2,
S_AXI_AWLOCK => net_gnd2,
S_AXI_AWCACHE => net_gnd4,
S_AXI_AWPROT => net_gnd3,
S_AXI_AWQOS => net_gnd4,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => net_gnd1(0 to 0),
S_AXI_AWREADY => open,
S_AXI_WID => net_gnd1(0 to 0),
S_AXI_WDATA => net_gnd64,
S_AXI_WSTRB => net_gnd8,
S_AXI_WLAST => net_gnd1(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => net_gnd1(0 to 0),
S_AXI_WREADY => open,
S_AXI_BID => open,
S_AXI_BRESP => open,
S_AXI_BUSER => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd1(0 to 0),
S_AXI_ARID => net_gnd1(0 to 0),
S_AXI_ARADDR => axi_interconnect_2_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_2_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_2_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_2_S_ARBURST,
S_AXI_ARLOCK => net_gnd2,
S_AXI_ARCACHE => axi_interconnect_2_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_2_S_ARPROT,
S_AXI_ARQOS => net_gnd4,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_2_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_2_S_ARREADY(0 to 0),
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_2_S_RDATA,
S_AXI_RRESP => axi_interconnect_2_S_RRESP,
S_AXI_RLAST => axi_interconnect_2_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_2_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_2_S_RREADY(0 to 0),
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_2_M_AWID(0 to 0),
M_AXI_AWADDR => axi_interconnect_2_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_2_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_2_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_2_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_2_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_2_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_2_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_2_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_2_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_2_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_2_M_WID(0 to 0),
M_AXI_WDATA => axi_interconnect_2_M_WDATA,
M_AXI_WSTRB => axi_interconnect_2_M_WSTRB,
M_AXI_WLAST => axi_interconnect_2_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_2_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_2_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_2_M_BID(0 to 0),
M_AXI_BRESP => axi_interconnect_2_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_2_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_2_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_2_M_ARID(0 to 0),
M_AXI_ARADDR => axi_interconnect_2_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_2_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_2_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_2_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_2_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_2_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_2_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_2_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_2_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_2_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_2_M_RID(0 to 0),
M_AXI_RDATA => axi_interconnect_2_M_RDATA,
M_AXI_RRESP => axi_interconnect_2_M_RRESP,
M_AXI_RLAST => axi_interconnect_2_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_2_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_2_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
iobuf_0 : IOBUF
port map (
I => processing_system7_0_I2C0_SDA_O,
IO => processing_system7_0_I2C0_SDA_pin,
O => processing_system7_0_I2C0_SDA_I,
T => processing_system7_0_I2C0_SDA_T
);
iobuf_1 : IOBUF
port map (
I => processing_system7_0_I2C0_SCL_O,
IO => processing_system7_0_I2C0_SCL_pin,
O => processing_system7_0_I2C0_SCL_I,
T => processing_system7_0_I2C0_SCL_T
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(0 to 0);
S_AXI_HP0_RID : out std_logic_vector(0 to 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(0 to 0);
S_AXI_HP0_AWID : in std_logic_vector(0 to 0);
S_AXI_HP0_WID : in std_logic_vector(0 to 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(1 downto 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(1 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(1 downto 0);
M_AXI_AWID : out std_logic_vector(23 downto 0);
M_AXI_AWADDR : out std_logic_vector(63 downto 0);
M_AXI_AWLEN : out std_logic_vector(15 downto 0);
M_AXI_AWSIZE : out std_logic_vector(5 downto 0);
M_AXI_AWBURST : out std_logic_vector(3 downto 0);
M_AXI_AWLOCK : out std_logic_vector(3 downto 0);
M_AXI_AWCACHE : out std_logic_vector(7 downto 0);
M_AXI_AWPROT : out std_logic_vector(5 downto 0);
M_AXI_AWREGION : out std_logic_vector(7 downto 0);
M_AXI_AWQOS : out std_logic_vector(7 downto 0);
M_AXI_AWUSER : out std_logic_vector(1 downto 0);
M_AXI_AWVALID : out std_logic_vector(1 downto 0);
M_AXI_AWREADY : in std_logic_vector(1 downto 0);
M_AXI_WID : out std_logic_vector(23 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(1 downto 0);
M_AXI_WUSER : out std_logic_vector(1 downto 0);
M_AXI_WVALID : out std_logic_vector(1 downto 0);
M_AXI_WREADY : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(23 downto 0);
M_AXI_BRESP : in std_logic_vector(3 downto 0);
M_AXI_BUSER : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic_vector(1 downto 0);
M_AXI_BREADY : out std_logic_vector(1 downto 0);
M_AXI_ARID : out std_logic_vector(23 downto 0);
M_AXI_ARADDR : out std_logic_vector(63 downto 0);
M_AXI_ARLEN : out std_logic_vector(15 downto 0);
M_AXI_ARSIZE : out std_logic_vector(5 downto 0);
M_AXI_ARBURST : out std_logic_vector(3 downto 0);
M_AXI_ARLOCK : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(7 downto 0);
M_AXI_ARPROT : out std_logic_vector(5 downto 0);
M_AXI_ARREGION : out std_logic_vector(7 downto 0);
M_AXI_ARQOS : out std_logic_vector(7 downto 0);
M_AXI_ARUSER : out std_logic_vector(1 downto 0);
M_AXI_ARVALID : out std_logic_vector(1 downto 0);
M_AXI_ARREADY : in std_logic_vector(1 downto 0);
M_AXI_RID : in std_logic_vector(23 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(3 downto 0);
M_AXI_RLAST : in std_logic_vector(1 downto 0);
M_AXI_RUSER : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic_vector(1 downto 0);
M_AXI_RREADY : out std_logic_vector(1 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_axi_interconnect_2_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(0 to 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(0 to 0);
S_AXI_WDATA : in std_logic_vector(63 downto 0);
S_AXI_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(0 to 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(0 to 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(0 to 0);
S_AXI_RDATA : out std_logic_vector(63 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(0 to 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(0 to 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(0 to 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(0 to 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(0 to 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal axi_dispctrl_0_BLUE_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_DE_O : std_logic;
signal axi_dispctrl_0_ENABLE_O : std_logic;
signal axi_dispctrl_0_FSYNC_O : std_logic;
signal axi_dispctrl_0_GREEN_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_HSYNC_O : std_logic;
signal axi_dispctrl_0_PXL_CLK_O : std_logic;
signal axi_dispctrl_0_RED_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_VDMA_CLK_O : std_logic;
signal axi_dispctrl_0_VSYNC_O : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_RID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_WID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_RVALID : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_TKEEP : std_logic_vector(3 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(31 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal axi_vdma_0_mm2s_introut : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd24 : std_logic_vector(23 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(1 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_I2C0_INT_N : std_logic;
signal processing_system7_0_I2C0_SCL_I : std_logic;
signal processing_system7_0_I2C0_SCL_O : std_logic;
signal processing_system7_0_I2C0_SCL_T : std_logic;
signal processing_system7_0_I2C0_SDA_I : std_logic;
signal processing_system7_0_I2C0_SDA_O : std_logic;
signal processing_system7_0_I2C0_SDA_T : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dispctrl_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_2_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
axi_dispctrl_0_HSYNC_O_pin <= axi_dispctrl_0_HSYNC_O;
axi_dispctrl_0_VSYNC_O_pin <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0_PXL_CLK_O_pin <= axi_dispctrl_0_PXL_CLK_O;
axi_dispctrl_0_DE_O_pin <= axi_dispctrl_0_DE_O;
axi_dispctrl_0_RED_O_pin <= axi_dispctrl_0_RED_O;
axi_dispctrl_0_GREEN_O_pin <= axi_dispctrl_0_GREEN_O;
axi_dispctrl_0_BLUE_O_pin <= axi_dispctrl_0_BLUE_O;
axi_dispctrl_0_ENABLE_O_pin <= axi_dispctrl_0_ENABLE_O;
processing_system7_0_I2C0_INT_N <= processing_system7_0_I2C0_INT_N_pin;
processing_system7_0_FCLK_CLK0_pin <= processing_system7_0_FCLK_CLK0(0);
pgassign1(1) <= axi_vdma_0_mm2s_introut;
pgassign1(0) <= processing_system7_0_I2C0_INT_N;
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd24(23 downto 0) <= B"000000000000000000000000";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(3 downto 0) <= B"1111";
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => processing_system7_0_I2C0_SDA_I,
I2C0_SDA_O => processing_system7_0_I2C0_SDA_O,
I2C0_SDA_T => processing_system7_0_I2C0_SDA_T,
I2C0_SCL_I => processing_system7_0_I2C0_SCL_I,
I2C0_SCL_O => processing_system7_0_I2C0_SCL_O,
I2C0_SCL_T => processing_system7_0_I2C0_SCL_T,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi_interconnect_1_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi_interconnect_1_S_AWVALID(0),
M_AXI_GP0_BREADY => axi_interconnect_1_S_BREADY(0),
M_AXI_GP0_RREADY => axi_interconnect_1_S_RREADY(0),
M_AXI_GP0_WLAST => axi_interconnect_1_S_WLAST(0),
M_AXI_GP0_WVALID => axi_interconnect_1_S_WVALID(0),
M_AXI_GP0_ARID => axi_interconnect_1_S_ARID,
M_AXI_GP0_AWID => axi_interconnect_1_S_AWID,
M_AXI_GP0_WID => axi_interconnect_1_S_WID,
M_AXI_GP0_ARBURST => axi_interconnect_1_S_ARBURST,
M_AXI_GP0_ARLOCK => axi_interconnect_1_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi_interconnect_1_S_ARSIZE,
M_AXI_GP0_AWBURST => axi_interconnect_1_S_AWBURST,
M_AXI_GP0_AWLOCK => axi_interconnect_1_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi_interconnect_1_S_AWSIZE,
M_AXI_GP0_ARPROT => axi_interconnect_1_S_ARPROT,
M_AXI_GP0_AWPROT => axi_interconnect_1_S_AWPROT,
M_AXI_GP0_ARADDR => axi_interconnect_1_S_ARADDR,
M_AXI_GP0_AWADDR => axi_interconnect_1_S_AWADDR,
M_AXI_GP0_WDATA => axi_interconnect_1_S_WDATA,
M_AXI_GP0_ARCACHE => axi_interconnect_1_S_ARCACHE,
M_AXI_GP0_ARLEN => axi_interconnect_1_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi_interconnect_1_S_ARQOS,
M_AXI_GP0_AWCACHE => axi_interconnect_1_S_AWCACHE,
M_AXI_GP0_AWLEN => axi_interconnect_1_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi_interconnect_1_S_AWQOS,
M_AXI_GP0_WSTRB => axi_interconnect_1_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi_interconnect_1_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi_interconnect_1_S_AWREADY(0),
M_AXI_GP0_BVALID => axi_interconnect_1_S_BVALID(0),
M_AXI_GP0_RLAST => axi_interconnect_1_S_RLAST(0),
M_AXI_GP0_RVALID => axi_interconnect_1_S_RVALID(0),
M_AXI_GP0_WREADY => axi_interconnect_1_S_WREADY(0),
M_AXI_GP0_BID => axi_interconnect_1_S_BID,
M_AXI_GP0_RID => axi_interconnect_1_S_RID,
M_AXI_GP0_BRESP => axi_interconnect_1_S_BRESP,
M_AXI_GP0_RRESP => axi_interconnect_1_S_RRESP,
M_AXI_GP0_RDATA => axi_interconnect_1_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_2_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_2_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_2_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_2_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_2_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_2_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_2_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_2_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_2_M_BID(0 to 0),
S_AXI_HP0_RID => axi_interconnect_2_M_RID(0 to 0),
S_AXI_HP0_RDATA => axi_interconnect_2_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_HP0_ARVALID => axi_interconnect_2_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_2_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_2_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_2_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_2_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_2_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_2_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_2_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_2_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_2_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_2_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_2_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_2_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_2_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_2_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_2_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_2_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_2_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_2_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_2_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_2_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_2_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_2_M_ARID(0 to 0),
S_AXI_HP0_AWID => axi_interconnect_2_M_AWID(0 to 0),
S_AXI_HP0_WID => axi_interconnect_2_M_WID(0 to 0),
S_AXI_HP0_WDATA => axi_interconnect_2_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_2_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => pgassign1,
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_dispctrl_0 : system_axi_dispctrl_0_wrapper
port map (
REF_CLK_I => processing_system7_0_FCLK_CLK0(0),
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
VDMA_CLK_O => axi_dispctrl_0_VDMA_CLK_O,
PXL_CLK_5X_O => open,
LOCKED_O => open,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
HSYNC_O => axi_dispctrl_0_HSYNC_O,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
DE_O => axi_dispctrl_0_DE_O,
RED_O => axi_dispctrl_0_RED_O,
GREEN_O => axi_dispctrl_0_GREEN_O,
BLUE_O => axi_dispctrl_0_BLUE_O,
ENABLE_O => axi_dispctrl_0_ENABLE_O,
DEBUG_O => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi_interconnect_1_M_ARESETN(0),
S_AXI_AWADDR => axi_interconnect_1_M_AWADDR(31 downto 0),
S_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_WDATA => axi_interconnect_1_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi_interconnect_1_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_ARADDR => axi_interconnect_1_M_ARADDR(31 downto 0),
S_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_RDATA => axi_interconnect_1_M_RDATA(31 downto 0),
S_AXI_RRESP => axi_interconnect_1_M_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_BRESP => axi_interconnect_1_M_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXIS_TREADY => axi_vdma_0_M_AXIS_MM2S_tready,
S_AXIS_ACLK => net_gnd0,
S_AXIS_ARESETN => net_vcc0,
S_AXIS_TDATA => axi_vdma_0_M_AXIS_MM2S_tdata,
S_AXIS_TVALID => axi_vdma_0_M_AXIS_MM2S_tvalid,
S_AXIS_TLAST => axi_vdma_0_M_AXIS_MM2S_tlast,
S_AXIS_TSTRB => axi_vdma_0_M_AXIS_MM2S_TKEEP
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi_interconnect_1_M_ARESETN,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi_interconnect_1_S_AWID,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_S_AWLOCK,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => axi_interconnect_1_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY(0 to 0),
S_AXI_WID => axi_interconnect_1_S_WID,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi_interconnect_1_S_WVALID(0 to 0),
S_AXI_WREADY => axi_interconnect_1_S_WREADY(0 to 0),
S_AXI_BID => axi_interconnect_1_S_BID,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID(0 to 0),
S_AXI_BREADY => axi_interconnect_1_S_BREADY(0 to 0),
S_AXI_ARID => axi_interconnect_1_S_ARID,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_S_ARLOCK,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => axi_interconnect_1_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY(0 to 0),
S_AXI_RID => axi_interconnect_1_S_RID,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_1_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign2,
M_AXI_AWID => open,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID,
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID,
M_AXI_WREADY => axi_interconnect_1_M_WREADY,
M_AXI_BID => net_gnd24,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd2,
M_AXI_BVALID => axi_interconnect_1_M_BVALID,
M_AXI_BREADY => axi_interconnect_1_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID,
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY,
M_AXI_RID => net_gnd24,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => net_gnd2,
M_AXI_RUSER => net_gnd2,
M_AXI_RVALID => axi_interconnect_1_M_RVALID,
M_AXI_RREADY => axi_interconnect_1_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_s2mm_aclk => net_gnd0,
m_axis_mm2s_aclk => axi_dispctrl_0_VDMA_CLK_O,
s_axis_s2mm_aclk => net_gnd0,
axi_resetn => axi_interconnect_1_M_ARESETN(1),
s_axi_lite_awvalid => axi_interconnect_1_M_AWVALID(1),
s_axi_lite_awready => axi_interconnect_1_M_AWREADY(1),
s_axi_lite_awaddr => axi_interconnect_1_M_AWADDR(40 downto 32),
s_axi_lite_wvalid => axi_interconnect_1_M_WVALID(1),
s_axi_lite_wready => axi_interconnect_1_M_WREADY(1),
s_axi_lite_wdata => axi_interconnect_1_M_WDATA(63 downto 32),
s_axi_lite_bresp => axi_interconnect_1_M_BRESP(3 downto 2),
s_axi_lite_bvalid => axi_interconnect_1_M_BVALID(1),
s_axi_lite_bready => axi_interconnect_1_M_BREADY(1),
s_axi_lite_arvalid => axi_interconnect_1_M_ARVALID(1),
s_axi_lite_arready => axi_interconnect_1_M_ARREADY(1),
s_axi_lite_araddr => axi_interconnect_1_M_ARADDR(40 downto 32),
s_axi_lite_rvalid => axi_interconnect_1_M_RVALID(1),
s_axi_lite_rready => axi_interconnect_1_M_RREADY(1),
s_axi_lite_rdata => axi_interconnect_1_M_RDATA(63 downto 32),
s_axi_lite_rresp => axi_interconnect_1_M_RRESP(3 downto 2),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_2_S_ARADDR,
m_axi_mm2s_arlen => axi_interconnect_2_S_ARLEN,
m_axi_mm2s_arsize => axi_interconnect_2_S_ARSIZE,
m_axi_mm2s_arburst => axi_interconnect_2_S_ARBURST,
m_axi_mm2s_arprot => axi_interconnect_2_S_ARPROT,
m_axi_mm2s_arcache => axi_interconnect_2_S_ARCACHE,
m_axi_mm2s_arvalid => axi_interconnect_2_S_ARVALID(0),
m_axi_mm2s_arready => axi_interconnect_2_S_ARREADY(0),
m_axi_mm2s_rdata => axi_interconnect_2_S_RDATA,
m_axi_mm2s_rresp => axi_interconnect_2_S_RRESP,
m_axi_mm2s_rlast => axi_interconnect_2_S_RLAST(0),
m_axi_mm2s_rvalid => axi_interconnect_2_S_RVALID(0),
m_axi_mm2s_rready => axi_interconnect_2_S_RREADY(0),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => axi_vdma_0_M_AXIS_MM2S_TKEEP,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => open,
m_axi_s2mm_awaddr => open,
m_axi_s2mm_awlen => open,
m_axi_s2mm_awsize => open,
m_axi_s2mm_awburst => open,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => open,
m_axi_s2mm_awready => net_gnd0,
m_axi_s2mm_wdata => open,
m_axi_s2mm_wstrb => open,
m_axi_s2mm_wlast => open,
m_axi_s2mm_wvalid => open,
m_axi_s2mm_wready => net_gnd0,
m_axi_s2mm_bresp => net_gnd2,
m_axi_s2mm_bvalid => net_gnd0,
m_axi_s2mm_bready => open,
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => net_gnd32,
s_axis_s2mm_tkeep => net_vcc4,
s_axis_s2mm_tvalid => net_gnd0,
s_axis_s2mm_tready => open,
s_axis_s2mm_tlast => net_gnd0,
s_axis_s2mm_tuser => net_gnd1(0 to 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => axi_vdma_0_mm2s_introut,
s2mm_introut => open,
axi_vdma_tstvec => open
);
axi_interconnect_2 : system_axi_interconnect_2_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => net_gnd1(0 to 0),
S_AXI_AWADDR => net_gnd32,
S_AXI_AWLEN => net_gnd8,
S_AXI_AWSIZE => net_gnd3,
S_AXI_AWBURST => net_gnd2,
S_AXI_AWLOCK => net_gnd2,
S_AXI_AWCACHE => net_gnd4,
S_AXI_AWPROT => net_gnd3,
S_AXI_AWQOS => net_gnd4,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => net_gnd1(0 to 0),
S_AXI_AWREADY => open,
S_AXI_WID => net_gnd1(0 to 0),
S_AXI_WDATA => net_gnd64,
S_AXI_WSTRB => net_gnd8,
S_AXI_WLAST => net_gnd1(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => net_gnd1(0 to 0),
S_AXI_WREADY => open,
S_AXI_BID => open,
S_AXI_BRESP => open,
S_AXI_BUSER => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd1(0 to 0),
S_AXI_ARID => net_gnd1(0 to 0),
S_AXI_ARADDR => axi_interconnect_2_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_2_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_2_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_2_S_ARBURST,
S_AXI_ARLOCK => net_gnd2,
S_AXI_ARCACHE => axi_interconnect_2_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_2_S_ARPROT,
S_AXI_ARQOS => net_gnd4,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_2_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_2_S_ARREADY(0 to 0),
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_2_S_RDATA,
S_AXI_RRESP => axi_interconnect_2_S_RRESP,
S_AXI_RLAST => axi_interconnect_2_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_2_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_2_S_RREADY(0 to 0),
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_2_M_AWID(0 to 0),
M_AXI_AWADDR => axi_interconnect_2_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_2_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_2_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_2_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_2_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_2_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_2_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_2_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_2_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_2_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_2_M_WID(0 to 0),
M_AXI_WDATA => axi_interconnect_2_M_WDATA,
M_AXI_WSTRB => axi_interconnect_2_M_WSTRB,
M_AXI_WLAST => axi_interconnect_2_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_2_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_2_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_2_M_BID(0 to 0),
M_AXI_BRESP => axi_interconnect_2_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_2_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_2_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_2_M_ARID(0 to 0),
M_AXI_ARADDR => axi_interconnect_2_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_2_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_2_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_2_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_2_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_2_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_2_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_2_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_2_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_2_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_2_M_RID(0 to 0),
M_AXI_RDATA => axi_interconnect_2_M_RDATA,
M_AXI_RRESP => axi_interconnect_2_M_RRESP,
M_AXI_RLAST => axi_interconnect_2_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_2_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_2_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
iobuf_0 : IOBUF
port map (
I => processing_system7_0_I2C0_SDA_O,
IO => processing_system7_0_I2C0_SDA_pin,
O => processing_system7_0_I2C0_SDA_I,
T => processing_system7_0_I2C0_SDA_T
);
iobuf_1 : IOBUF
port map (
I => processing_system7_0_I2C0_SCL_O,
IO => processing_system7_0_I2C0_SCL_pin,
O => processing_system7_0_I2C0_SCL_I,
T => processing_system7_0_I2C0_SCL_T
);
end architecture STRUCTURE;
|
package repro is
function return_true return boolean;
end repro;
package body repro is
function slv_ones(constant width : in integer) return bit_vector is
begin
return (1 to width => '1');
end function;
function return_true return boolean is
constant ones_c : bit_vector(31 downto 0) := slv_ones(32);
begin
return true;
end function;
end repro;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:50 04/20/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/Combined/Combined_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ProjLab01
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Combined_tb IS
END Combined_tb;
ARCHITECTURE behavior OF Combined_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ProjLab01
PORT(
CLK : IN std_logic;
RST : IN std_logic;
ALU_OUT : OUT std_logic_vector(15 downto 0);
DST_ADR : OUT std_logic_vector(15 downto 0);
STORE_DATA : OUT std_logic_vector(15 downto 0);
CCR : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal ALU_OUT : std_logic_vector(15 downto 0);
signal DST_ADR : std_logic_vector(15 downto 0);
signal STORE_DATA : std_logic_vector(15 downto 0);
signal CCR : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 1 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ProjLab01 PORT MAP (
CLK => CLK,
RST => RST,
ALU_OUT => ALU_OUT,
DST_ADR => DST_ADR,
STORE_DATA => STORE_DATA,
CCR => CCR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*2;
wait for CLK_period/2;
RST <= '0';
wait for CLK_period*10;
-- instruction <= X"5002";
--
-- wait for CLK_period;
--
-- instruction <= X"5101";
--
-- wait for CLK_period;
--
-- instruction <= X"A10F";
--
-- wait for CLK_period;
--
-- instruction <= X"950F";
--
-- wait for CLK_period;
--
-- instruction <= X"0050";
--
-- wait for CLK_period;
--
-- instruction <= X"2010";
--
-- wait for CLK_period;
--
-- instruction <= X"3010";
--
-- wait for CLK_period;
--
-- instruction <= X"0010";
--
-- wait for CLK_period;
--
-- instruction <= X"4A10";
--
-- wait for CLK_period;
--
-- instruction <= X"7A03";
--
-- wait for CLK_period;
--
-- instruction <= X"B201";
--
-- wait for CLK_period;
--
-- instruction <= X"C212";
wait for CLK_period;
-- insert stimulus here
wait;
end process;
END;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTX1;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*1;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 1;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 1;
constant CFG_STAT_CNT : integer := (4);
constant CFG_STAT_NMAX : integer := (0);
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#C00#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000035#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- FTMCTRL memory controller
constant CFG_MCTRLFT : integer := 0;
constant CFG_MCTRLFT_RAM8BIT : integer := 0;
constant CFG_MCTRLFT_RAM16BIT : integer := 0;
constant CFG_MCTRLFT_5CS : integer := 0;
constant CFG_MCTRLFT_SDEN : integer := 0;
constant CFG_MCTRLFT_SEPBUS : integer := 0;
constant CFG_MCTRLFT_INVCLK : integer := 0;
constant CFG_MCTRLFT_SD64 : integer := 0;
constant CFG_MCTRLFT_EDAC : integer := 0 + 0 + 0;
constant CFG_MCTRLFT_PAGE : integer := 0 + 0;
constant CFG_MCTRLFT_ROMASEL : integer := 0;
constant CFG_MCTRLFT_WFB : integer := 0;
constant CFG_MCTRLFT_NET : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (8);
constant CFG_DDR2SP_DELAY1 : integer := (8);
constant CFG_DDR2SP_DELAY2 : integer := (8);
constant CFG_DDR2SP_DELAY3 : integer := (8);
constant CFG_DDR2SP_DELAY4 : integer := (8);
constant CFG_DDR2SP_DELAY5 : integer := (8);
constant CFG_DDR2SP_DELAY6 : integer := (8);
constant CFG_DDR2SP_DELAY7 : integer := (8);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0060#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 1;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 1;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
--
-- Title : xor2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : xor2.vhd
-- Generated : Fri Oct 3 18:17:26 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {xor2} architecture {xor2}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity xor2 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end xor2;
--}} End of automatically maintained section
architecture xor2 of xor2 is
begin
Z <= A xor B;
end xor2;
|
-------------------------------------------------------------------------------
--
-- Title : xor2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : xor2.vhd
-- Generated : Fri Oct 3 18:17:26 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {xor2} architecture {xor2}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity xor2 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end xor2;
--}} End of automatically maintained section
architecture xor2 of xor2 is
begin
Z <= A xor B;
end xor2;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_inferred is
begin
o <= i;
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_inferred is
begin
o <= i;
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_inferred is
begin
o <= i;
end;
|
entity test is
end test;
architecture behv of test is
-- Crash "** Fatal: tree kind T_TYPE_CONV does not have item I_ATTRS"
constant AWIDTH : integer := integer(4); -- or natural
signal a : bit_vector (AWIDTH downto 0);
begin
end behv;
|
entity test is
end test;
architecture behv of test is
-- Crash "** Fatal: tree kind T_TYPE_CONV does not have item I_ATTRS"
constant AWIDTH : integer := integer(4); -- or natural
signal a : bit_vector (AWIDTH downto 0);
begin
end behv;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
-- NEED RESULT: ARCH00493: Aggregates with others choice associated with function return (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00493
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (5)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00493(ARCH00493)
-- ENT00493_Test_Bench(ARCH00493_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00493 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00493 ;
--
architecture ARCH00493 of ENT00493 is
begin
B1 :
block
--
function f_arr_1 return st_arr_1 is
begin
return ( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
end f_arr_1 ;
function f_time_matrix return st_time_matrix is
begin
return
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
end f_time_matrix ;
function f_bit_vector return st_bit_vector is
begin
return
( 0 => '1', 2 => '1', others => '0' ) ;
end f_bit_vector ;
function f_string return st_string is
begin
return
( 3 => 'a', 4 => 'b', others => '0' ) ;
end f_string ;
function f_rec_1 return rec_1 is
begin
return
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
end f_rec_1 ;
begin
process
variable bool : boolean := true;
begin
bool := bool and f_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and f_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and f_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and f_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and f_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and f_bit_vector = B"10100" ;
--
bool := bool and f_string = "ab0" ;
--
bool := bool and f_rec_1.f1 = 0 and f_rec_1.f4 = 0
and f_rec_1.f3 = 1 ;
-- bool := bool and f_rec_1.f2(1) = true
-- and f_rec_1.f2(0) = false and
-- f_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00493" ,
"Aggregates with others choice associated with function"
& " return (locally static)" ,
bool ) ;
wait ;
end process ;
end block B1 ;
end ARCH00493 ;
--
entity ENT00493_Test_Bench is
end ENT00493_Test_Bench ;
--
architecture ARCH00493_Test_Bench of ENT00493_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00493 ( ARCH00493 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00493_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use work.wbgen2_pkg.all;
entity wbgen2_fifo_sync is
generic (
g_width : integer;
g_size : integer;
g_usedw_size : integer);
port
(
clk_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_req_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
);
end wbgen2_fifo_sync;
architecture rtl of wbgen2_fifo_sync is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
signal empty_int : std_logic;
signal full_int : std_logic;
signal usedw_int : std_logic_vector(g_usedw_size-1 downto 0);
begin
wrapped_fifo: generic_sync_fifo
generic map (
g_data_width => g_width,
g_size => g_size,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => true)
port map (
rst_n_i => '1',
clk_i => clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
q_o => rd_data_o,
rd_i => rd_req_i,
empty_o => empty_int,
full_o => full_int,
almost_empty_o => open,
almost_full_o => open,
count_o => usedw_int);
rd_empty_o <= empty_int;
rd_full_o <= full_int;
rd_usedw_o <= usedw_int;
wr_empty_o <= empty_int;
wr_full_o <= full_int;
wr_usedw_o <= usedw_int;
end rtl;
|
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin
process
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin end process;
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 downto 0);
rot_m01 : in std_logic_vector(15 downto 0);
rot_m10 : in std_logic_vector(15 downto 0);
rot_m11 : in std_logic_vector(15 downto 0);
t_x : in std_logic_vector(9 downto 0);
t_y : in std_logic_vector(9 downto 0);
x_addr_out : out std_logic_vector(9 downto 0);
y_addr_out : out std_logic_vector(9 downto 0)
);
end vga_transform;
architecture Behavioral of vga_transform is
begin
process(clk)
variable m00_op, m01_op, m10_op, m11_op, x_op, y_op, t_x_op, t_y_op, x_s, y_s : signed(31 downto 0) := (others => '0');
variable x_p, y_p : signed(63 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if enable = '1' then
m00_op := resize(signed(rot_m00), 32);
m01_op := resize(signed(rot_m01), 32);
m10_op := resize(signed(rot_m10), 32);
m11_op := resize(signed(rot_m11), 32);
x_op(23 downto 14) := signed(x_addr_in);
y_op(23 downto 14) := signed(y_addr_in);
t_x_op(23 downto 14) := signed(t_x);
t_y_op(23 downto 14) := signed(t_y);
x_p := (m00_op * x_op + m01_op * y_op) srl 14;
y_p := (m10_op * x_op + m11_op * y_op) srl 14;
x_s := x_p(31 downto 0) + t_x_op;
y_s := y_p(31 downto 0) + t_y_op;
x_addr_out <= std_logic_vector(x_s(23 downto 14));
y_addr_out <= std_logic_vector(y_s(23 downto 14));
else
x_addr_out <= x_addr_in;
x_addr_out <= x_addr_in;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 downto 0);
rot_m01 : in std_logic_vector(15 downto 0);
rot_m10 : in std_logic_vector(15 downto 0);
rot_m11 : in std_logic_vector(15 downto 0);
t_x : in std_logic_vector(9 downto 0);
t_y : in std_logic_vector(9 downto 0);
x_addr_out : out std_logic_vector(9 downto 0);
y_addr_out : out std_logic_vector(9 downto 0)
);
end vga_transform;
architecture Behavioral of vga_transform is
begin
process(clk)
variable m00_op, m01_op, m10_op, m11_op, x_op, y_op, t_x_op, t_y_op, x_s, y_s : signed(31 downto 0) := (others => '0');
variable x_p, y_p : signed(63 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if enable = '1' then
m00_op := resize(signed(rot_m00), 32);
m01_op := resize(signed(rot_m01), 32);
m10_op := resize(signed(rot_m10), 32);
m11_op := resize(signed(rot_m11), 32);
x_op(23 downto 14) := signed(x_addr_in);
y_op(23 downto 14) := signed(y_addr_in);
t_x_op(23 downto 14) := signed(t_x);
t_y_op(23 downto 14) := signed(t_y);
x_p := (m00_op * x_op + m01_op * y_op) srl 14;
y_p := (m10_op * x_op + m11_op * y_op) srl 14;
x_s := x_p(31 downto 0) + t_x_op;
y_s := y_p(31 downto 0) + t_y_op;
x_addr_out <= std_logic_vector(x_s(23 downto 14));
y_addr_out <= std_logic_vector(y_s(23 downto 14));
else
x_addr_out <= x_addr_in;
x_addr_out <= x_addr_in;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 downto 0);
rot_m01 : in std_logic_vector(15 downto 0);
rot_m10 : in std_logic_vector(15 downto 0);
rot_m11 : in std_logic_vector(15 downto 0);
t_x : in std_logic_vector(9 downto 0);
t_y : in std_logic_vector(9 downto 0);
x_addr_out : out std_logic_vector(9 downto 0);
y_addr_out : out std_logic_vector(9 downto 0)
);
end vga_transform;
architecture Behavioral of vga_transform is
begin
process(clk)
variable m00_op, m01_op, m10_op, m11_op, x_op, y_op, t_x_op, t_y_op, x_s, y_s : signed(31 downto 0) := (others => '0');
variable x_p, y_p : signed(63 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if enable = '1' then
m00_op := resize(signed(rot_m00), 32);
m01_op := resize(signed(rot_m01), 32);
m10_op := resize(signed(rot_m10), 32);
m11_op := resize(signed(rot_m11), 32);
x_op(23 downto 14) := signed(x_addr_in);
y_op(23 downto 14) := signed(y_addr_in);
t_x_op(23 downto 14) := signed(t_x);
t_y_op(23 downto 14) := signed(t_y);
x_p := (m00_op * x_op + m01_op * y_op) srl 14;
y_p := (m10_op * x_op + m11_op * y_op) srl 14;
x_s := x_p(31 downto 0) + t_x_op;
y_s := y_p(31 downto 0) + t_y_op;
x_addr_out <= std_logic_vector(x_s(23 downto 14));
y_addr_out <= std_logic_vector(y_s(23 downto 14));
else
x_addr_out <= x_addr_in;
x_addr_out <= x_addr_in;
end if;
end if;
end process;
end Behavioral;
|
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62512)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc207.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00207ent IS
END c03s01b00x00p09n01i00207ent;
ARCHITECTURE c03s01b00x00p09n01i00207arch OF c03s01b00x00p09n01i00207ent IS
type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
subtype weekend is integer range Sat to Sun;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b00x00p09n01i00207 - Constraints for the subtype declaration do not match the base type of integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00207arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc207.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00207ent IS
END c03s01b00x00p09n01i00207ent;
ARCHITECTURE c03s01b00x00p09n01i00207arch OF c03s01b00x00p09n01i00207ent IS
type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
subtype weekend is integer range Sat to Sun;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b00x00p09n01i00207 - Constraints for the subtype declaration do not match the base type of integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00207arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc207.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00207ent IS
END c03s01b00x00p09n01i00207ent;
ARCHITECTURE c03s01b00x00p09n01i00207arch OF c03s01b00x00p09n01i00207ent IS
type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
subtype weekend is integer range Sat to Sun;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b00x00p09n01i00207 - Constraints for the subtype declaration do not match the base type of integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00207arch;
|
-- NEED RESULT: ARCH00421: Block statements passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00421
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 12.4.1 (1)
-- 12.4.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00421)
-- ENT00421_Test_Bench(ARCH00421_Test_Bench)
--
-- REVISION HISTORY:
--
-- 31-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00421 of E00000 is
begin
B :
block
generic ( g : integer := 10 ) ;
constant c : integer := g - 1 ;
begin
P :
process
variable v : integer := 2 * c ;
begin
test_report ( "ARCH00421" ,
"Block statements" ,
(c = 9) and -- this tests 12.4 1 (1)
(v = 18) -- this tests 12.4.1 (2)
) ;
wait ;
end process P ;
end block B ;
end ARCH00421 ;
entity ENT00421_Test_Bench is
end ENT00421_Test_Bench ;
architecture ARCH00421_Test_Bench of ENT00421_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00421 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00421_Test_Bench ;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
c <= d;
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a = '1' generate
end generate;
b <= c;
CASE_LABEL : case data generate
end generate;
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_117 : BOOLEAN;
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_116 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_55 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_55;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_117 assign process. --
ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
if (ap_sig_bdd_119) then
nfa_finals_buckets_address <= ap_const_lv32_1;
elsif (ap_sig_bdd_117) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_117 : BOOLEAN;
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_116 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_55 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_55;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_117 assign process. --
ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
if (ap_sig_bdd_119) then
nfa_finals_buckets_address <= ap_const_lv32_1;
elsif (ap_sig_bdd_117) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_117 : BOOLEAN;
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_116 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_55 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_55;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_117 assign process. --
ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
if (ap_sig_bdd_119) then
nfa_finals_buckets_address <= ap_const_lv32_1;
elsif (ap_sig_bdd_117) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
-------------------------------------------------------------------------------
-- Copyright (C) 2022 Nick Gasson
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation; either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The compiler generates calls to subprograms in this package to implement
-- certain predefined IEEE.STD_LOGIC_1164 operations. Do not call these
-- subprograms directly.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ieee_support is
-- Raise an error if VAL contains a '-'
procedure check_match_expression (val : std_ulogic_vector);
procedure check_match_expression (val : std_ulogic);
end package;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_565;
architecture augh of mul_565 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_565;
architecture augh of mul_565 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
o : out std_logic
);
end;
architecture a of ent is
begin
end;
|
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.dbe_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity wb_dma_interface is
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Clock Data Sink Input.
dma_clk_i : in std_logic;
-- Slave Data Sink port. To/From Data Sink Core
wb_sink_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_sink_cyc_i : in std_logic;
wb_sink_stb_i : in std_logic;
wb_sink_we_i : in std_logic;
wb_sink_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_ack_o : out std_logic;
wb_sink_stall_o : out std_logic;
-- Clock Data Source Input.
data_clk_i : in std_logic;
-- Slave Data Source port. To/From Data Source Core
wb_src_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_src_cyc_i : in std_logic;
wb_src_stb_i : in std_logic;
wb_src_we_i : in std_logic;
wb_src_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_ack_o : out std_logic;
wb_src_stall_o : out std_logic;
-- Slave Data Source port. To/From Data Source Core
wb_ctl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_ctl_cyc_i : in std_logic;
wb_ctl_stb_i : in std_logic;
wb_ctl_we_i : in std_logic;
wb_ctl_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_ack_o : out std_logic;
wb_ctl_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
--data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--data_valid_i : in std_logic;
--data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
--capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--dma_complete_o : out std_logic;
--dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end wb_dma_interface;
architecture rtl of wb_dma_interface is
--constant C_DATA_SIZE : natural := 32;
--constant C_OVF_COUNTER_SIZE : natural := 10;
-- FIFO signals index
--constant c_X_DATA : natural := 3;
--constant c_Y_DATA : natural := 2;
--constant c_Z_DATA : natural := 1;
--constant c_W_DATA : natural := 0;
-- Fifo Depth = 8K words * 32 bits/word
constant c_fifo_size : natural := 1024;
-- Register definition
constant c_FIFO_REG : std_logic_vector(2 downto 0) := "000";
------------------------------------------
-- Wishbone and Finite State Machine Signals
------------------------------------------
--type t_wishbone_state is (IDLE, CLASSIC, CABURST, EOBURST);
--signal wb_state : t_wishbone_state := IDLE;
signal cycle_progress : std_logic;
signal read_cycle_progress : std_logic;
signal write_cycle_progress : std_logic;
signal ack_int : std_logic;
signal stall_int : std_logic;
------------------------------------------
-- FIFO Signals
------------------------------------------
subtype fifo_data is std_logic_vector(c_wishbone_data_width downto 0);
--subtype fifo_count is std_logic_vector(12 downto 0);
subtype fifo_ctrl is std_logic;
--signal fifo_do_concat : std_logic_vector(C_NBITS_VALID_INPUT-1 downto 0);
signal data_i_d1 : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- read data_i: 32-bit (each) output: read output data_i
signal fifo_do : fifo_data;
-- status: 1-bit (each) output: flags and other fifo status outputs
signal fifo_empty : fifo_ctrl;
signal fifo_full : fifo_ctrl;
-- read control signals: 1-bit (each) input: read clock, enable and reset input signals
signal fifo_rdclk : fifo_ctrl;
signal fifo_rden : fifo_ctrl;
signal fifo_rst_n : fifo_ctrl;
-- counter fifo signals
--signal fifo_rd_data_count : fifo_count;
--signal fifo_wr_data_count : fifo_count;
-- write control signals: 1-bit (each) input: write clock and enable input signals
signal fifo_wrclk : fifo_ctrl;
signal fifo_wren : fifo_ctrl;
-- write data_i: 32-bit (each) input: write input data_i
signal fifo_di : fifo_data;
signal last_data_reg : std_logic;
-- Overflow counter. One extra bit for easy overflow detection
signal s_fifo_ovf_c : std_logic_vector(g_ovf_counter_width downto 0);
signal s_fifo_ovf : std_logic;
------------------------------------------
-- Internal Control
------------------------------------------
signal capture_ctl_reg : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal start_acq : std_logic;
signal start_acq_trig : std_logic;
------------------------------------------
-- Reset Synch
------------------------------------------
signal data_clk_rst_n : std_logic;
signal dma_clk_rst_n : std_logic;
------------------------------------------
-- DMA output signals
------------------------------------------
-- C_NBITS_DATA_INPUT+1 bits. C_NBITS_DATA_INPUT bits (LSBs) for data_i and 1 bit (MSB) for last data_i bit
signal dma_data_out0 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out0 : std_logic;
signal dma_data_out1 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out1 : std_logic;
signal dma_data_out2 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out2 : std_logic;
signal dma_data_out3 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out3 : std_logic;
signal dma_valid_s : std_logic;
signal dma_ready_s : std_logic;
signal dma_last_s : std_logic;
signal s_last_data : std_logic;
signal dma_valid_reg0 : std_logic;
-- Counter to coordinate the FIFO output - DMA input
signal output_counter_rd : std_logic_vector(1 downto 0);
signal pre_output_counter_wr : std_logic_vector(1 downto 0);
-- Internal signals
signal dma_complete_int : std_logic;
signal dma_last_int : std_logic;
signal dma_valid_int : std_logic;
signal dma_data_int : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- Functions. Improve this function. Not generic.
function f_end_counter(counter : std_logic_vector(c_wishbone_data_width-1 downto 0))
return boolean is
begin
if counter(c_wishbone_data_width-1) = '1' and
unsigned(counter(c_wishbone_data_width-2 downto 0)) = 0 then
return true;
else
return false;
end if;
end f_end_counter;
begin
-- DMA signals glue
--dma_last_o <= s_dma_last_glue;
--dma_valid_o <= s_dma_valid_glue;
--dma_data_o <= s_dma_data_glue;
-- Debug data_i
--dma_debug_clk_o <= dma_clk_i;
--
--dma_debug_trigger_o(15 downto 6) <= (others => '0');
--dma_debug_trigger_o(5) <= fifo_full(C_W_DATA);
--dma_debug_trigger_o(4) <= start_acq_trig;
--dma_debug_trigger_o(3) <= capture_ctl_reg(21);
--dma_debug_trigger_o(2) <= dma_ready_i;
--dma_debug_trigger_o(1) <= s_dma_last_glue;
--dma_debug_trigger_o(0) <= s_dma_valid_glue;
--
--dma_debug_data_o(255 downto 120) <= (others => '0');
--dma_debug_data_o(119 downto 109) <= s_fifo_ovf_c(10 downto 0);
--dma_debug_data_o(108) <= s_dma_complete;
--dma_debug_data_o(107) <= start_acq_trig;
--dma_debug_data_o(106) <= fifo_full(C_W_DATA);
--dma_debug_data_o(105 downto 84) <= capture_ctl_reg;
--dma_debug_data_o(83 downto 52) <= s_dma_data_glue(31 downto 0);
--dma_debug_data_o(51 downto 36) <= fifo_do(C_W_DATA)(15 downto 0);-- FIXXXX
--dma_debug_data_o(35 downto 34) <= output_counter_rd;
--dma_debug_data_o(33 downto 32) <= pre_output_counter_wr;
--dma_debug_data_o(31 downto 19) <= fifo_wr_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(18 downto 6) <= fifo_rd_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(5) <= dma_ready_s;
--dma_debug_data_o(4) <= dma_valid_reg0;
--dma_debug_data_o(3) <= dma_valid_s;
--dma_debug_data_o(2) <= dma_ready_i;
--dma_debug_data_o(1) <= s_dma_last_glue;
--dma_debug_data_o(0) <= s_dma_valid_glue;
--------------------------------
-- Wishbone interface instantiation
--------------------------------
--wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
--wb_cyc_i : in std_logic;
--wb_stb_i : in std_logic;
--wb_we_i : in std_logic;
--wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_cti_i : in std_logic_vector(2 downto 0);
--wb_bte_i : in std_logic_vector(1 downto 0);
wb_dat_o <= dma_data_int;
wb_ack_o <= ack_int;
wb_stall_o <= stall_int;
--FIXXX
-- Hard-wired slave pins
--slave_o.ACK <= slave_o_ACK;
--slave_o.ERR <= '0';
--slave_o.RTY <= '0';
--slave_o.STALL <= '0';
--slave_o.DAT <= slave_o_DAT;
-- Hard-wired master pins
--r_master_o.CYC <= r_master_o_CYC;
--w_master_o.CYC <= w_master_o_CYC;
--r_master_o.STB <= r_master_o_STB;
--w_master_o.STB <= w_master_o_STB;
--r_master_o.ADR <= read_issue_address;
--w_master_o.ADR <= write_issue_address;
--r_master_o.SEL <= (others => '1');
--w_master_o.SEL <= (others => '1');
--r_master_o.WE <= '0';
--w_master_o.WE <= '1';
--r_master_o.DAT <= (others => '0');
--w_master_o.DAT <= ring(index(write_issue_offset));
--------------------------------
-- Reset Logic
--------------------------------
-- FIFO reset cycle: RST must be held high for at least three RDCLK clock cycles,
-- and RDEN must be low for four clock cycles before RST becomes active high, and RDEN
-- remains low during this reset cycle.
-- Guarantees the synchronicity with the input clock on reset deassertion
cmp_reset_synch_dma : reset_synch
port map(
clk_i => dma_clk_i,
arst_n_i => arst_n_i,
rst_n_o => dma_clk_rst_n
);
cmp_reset_synch_data : reset_synch
port map(
clk_i => data_clk_i,
arst_n_i => arst_n_i,
rst_n_o => data_clk_rst_n
);
--------------------------------
-- Start Acquisition logic
--------------------------------
-- Simple trigger detector 0 -> 1 for start_acq.
-- Synchronize with bus clock data_clk_i might not be the same
p_start_acq_trig : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => data_clk_rst_n,
clk_i => data_clk_i,
data_i => start_acq,
synced_o => start_acq_trig,
npulse_o => open
);
-- MSB bit representing the start acquisition signal
start_acq <= capture_ctl_i(c_wishbone_data_width-1);
--------------------------------
-- Samples Counter Logic
--------------------------------
-- Hold counter for "capture_count" clock cycles
p_samples_counter : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
capture_ctl_reg <= (others => '0');
elsif rising_edge(data_clk_i) then
-- start counting and stop only when we have input all data to fifos
if capture_ctl_reg(c_wishbone_data_width-1) = '1' and
data_valid_i = '1' and fifo_full = '0' then
capture_ctl_reg <= std_logic_vector(unsigned(capture_ctl_reg) - 1);
-- assign only when 0 -> 1 transition of MSB of start_acq. MSB of capture_ctl_reg
elsif start_acq_trig = '1' then
if data_valid_i = '1' then
-- MSB of capture_ctl_i might not be 1 by this time. Force to 1 then...
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)) - 1);
else
-- Do not decrement now. wait until data_valid is set
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)));
end if;
end if;
end if;
end process p_samples_counter;
--------------------------------
-- DMA Last Data Logic
--------------------------------
p_last_data_proc : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
last_data_reg <= '0';
elsif rising_edge(data_clk_i) then
last_data_reg <= s_last_data;
end if;
end process p_last_data_proc;
-- bit c_wishbone_data_width-1 = 1 and bits c_wishbone_data_width-2 downto 0 = 0
s_last_data <= '1' when
f_end_counter(capture_ctl_reg(c_wishbone_data_width-1 downto 0)) and data_valid_i = '1' else '0';
--------------------------------
-- FIFO Write Enable Logic
--------------------------------
p_fifo_wr_en : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
fifo_wren <= '0';
data_i_d1 <= (others => '0');
elsif rising_edge(data_clk_i) then
-- We only need to consider one as all FIFOs are synchronized with each other
if fifo_full = '0' then
-- input data to fifo only when data is valid
fifo_wren <= capture_ctl_reg(c_wishbone_data_width-1) and data_valid_i;
end if;
--Necessary in order to input data to FIFO correctly as fifo_wren is registered
data_i_d1 <= data_i;
end if;
end process p_fifo_wr_en;
p_gen_ack : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
ack_int <= '0';
elsif rising_edge(dma_clk_i) then
if cycle_progress = '1' and wb_we_i = '0' and dma_valid_int = '1' then
ack_int <= '1';
else
ack_int <= '0';
end if;
end if;
end process;
p_gen_stall : process (dma_valid_s)
begin
stall_int <= dma_valid_s;
end process;
--------------------------------
-- DMA Output Logic
--------------------------------
cycle_progress <= wb_cyc_i and wb_stb_i; --and wb_we_i = '0';
read_cycle_progress <= cycle_progress and not wb_we_i;
write_cycle_progress <= cycle_progress and wb_we_i;
--dma_ready_s <= dma_ready_i or not s_dma_valid_glue;
dma_ready_s <= read_cycle_progress or not dma_valid_int;
-- fifo is not empty and dma is ready
--dma_valid_s <= '0' when fifo_empty = '1' else read_cycle_progress;
dma_valid_s <= not fifo_empty or read_cycle_progress;
-- We have a 2 output delay for FIFO. That being said, if we have a dma_ready_i signal it will take 2 dma clock cycles
-- in order to read the data_i from FIFO.
-- By this time, dma_ready_i might not be set and we have to wait for it. To solve this 2 delay read cycle
-- it is employed a small 4 position "buffer" to hold the values read from fifo but not yet passed to the DMA.
-- Note that dma_valid_reg0 is 1 clock cycle delayed in relation to dma_valid_s. That should give time to
-- FIFO output the data_i requested. Also not that that difference between pre_output_counter_wr and output_counter_rd
-- is at most (at any given point in time) not greater than 2. Thus, with a 2 bit counter, we will not have overflow
p_dma_pre_output : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
dma_valid_reg0 <= '0';
pre_output_counter_wr <= (others => '0');
-- fifo is not empty and dma is ready
elsif rising_edge(dma_clk_i) then
--if dma_valid_reg1 = '1' then -- fifo output should be valid by now as fifo_rden was enabled and it id not empty!
-- Store output from FIFO in the correct dma_data_outX if dma_valid_reg1 is valid.
-- On the next dma_valid_reg1 operation (next clock cycle if dma_valid_reg1 remains 1),
-- clear the past dma_data_outX if dma has read from it (read pointer is in the past write position).
if pre_output_counter_wr = "00" and dma_valid_reg0 = '1' then
-- Output only the last_data bit of fifo_do
dma_data_out0(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
-- Output the data from fifo itself
dma_data_out0(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out0 <= '1';
elsif output_counter_rd = "00" and dma_ready_s = '1' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
end if;
if pre_output_counter_wr = "01" and dma_valid_reg0 = '1' then
dma_data_out1(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out1(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out1 <= '1';
elsif output_counter_rd = "01" and dma_ready_s = '1' then
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
end if;
if pre_output_counter_wr = "10" and dma_valid_reg0 = '1' then
dma_data_out2(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out2(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out2 <= '1';
elsif output_counter_rd = "10" and dma_ready_s = '1' then
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
end if;
if pre_output_counter_wr = "11" and dma_valid_reg0 = '1' then
dma_data_out3(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out3(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out3 <= '1';
elsif output_counter_rd = "11" and dma_ready_s = '1' then
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
end if;
if dma_valid_reg0 = '1' then --dma_valid_reg0 = '1' then
pre_output_counter_wr <= std_logic_vector(unsigned(pre_output_counter_wr) + 1);
end if;
-- 2 clock cycle delay for read from fifo.
-- Nedded to break logic into one more FF as timing constraint wasn't met,
-- due to the use of dma_valid_s directly into fifo_rden.
-- This is not a problem since there is a 4 position "buffer" after this
-- to absorb dma_ready_i deassertion
dma_valid_reg0 <= dma_valid_s;
end if;
end process p_dma_pre_output;
-- Send to DMA the correct data_i from dma_data_out, based on the currently read pointer position
p_dma_output_proc : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_int <= (others => '0');
dma_valid_int <= '0';
--dma_be_o <= (others => '0');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= '0';
output_counter_rd <= (others => '0');
elsif rising_edge(dma_clk_i) then
if dma_ready_s = '1' then
-- verify wr counter and output corresponding output
case output_counter_rd is
when "11" =>
dma_data_int <= dma_data_out3(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out3;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out3(c_wishbone_data_width) and dma_valid_out3;
when "10" =>
dma_data_int <= dma_data_out2(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out2;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out2(c_wishbone_data_width) and dma_valid_out2;
when "01" =>
dma_data_int <= dma_data_out1(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out1;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out1(c_wishbone_data_width) and dma_valid_out1;
--when "01" =>
when others =>
dma_data_int <= dma_data_out0(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out0;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out0(c_wishbone_data_width) and dma_valid_out0;
end case;
-- Only increment output_counter_rd if it is different from pre_output_counter_wr
-- to prevent overflow!
if output_counter_rd /= pre_output_counter_wr then
output_counter_rd <= std_logic_vector(unsigned(output_counter_rd) + 1);
end if;
end if;
end if;
end process p_dma_output_proc;
-- Simple backpressure scheme. Should be almost full for correct behavior.
-- fifo_full is already synchronized with fifo write_clock
data_ready_o <= not fifo_full;
--------------------------------
-- DMA complete status
--------------------------------
dma_last_s <= dma_valid_int and read_cycle_progress and dma_last_int;
p_dma_complete : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_complete_int <= '0';
elsif rising_edge(dma_clk_i) then
if dma_last_s = '1' then
-- DMA could be held to 1 when completed, but it would be more difficult
-- to bring it back to 0, since the dma transfer is initiated in the data_clk_i domain
dma_complete_int <= not dma_complete_int;
end if;
end if;
end process p_dma_complete;
dma_complete_o <= dma_complete_int;
--------------------------------
-- DMA overflow (fifo full) status and counter
--------------------------------
-- Data is lost when this is asserted.
-- FIFO is full, there is data valid on input and we are in the middle of a dma transfer
s_fifo_ovf <= fifo_full and data_valid_i and
capture_ctl_reg(c_wishbone_data_width-1);
p_dma_overflow : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
s_fifo_ovf_c <= (others => '0');
elsif rising_edge(data_clk_i) then
if start_acq_trig = '1' then
s_fifo_ovf_c <= (others => '0');
elsif s_fifo_ovf = '1' then
-- Even if the counter wrapps around, an overflow will still be detected!
s_fifo_ovf_c <= '1' & std_logic_vector(unsigned(s_fifo_ovf_c(g_ovf_counter_width-1 downto 0)) + 1);
end if;
end if;
end process p_dma_overflow;
dma_ovf_o <= s_fifo_ovf_c(g_ovf_counter_width);
--------------------------------
-- FIFO instantiation
--------------------------------
cmp_fifo : generic_async_fifo
generic map(
g_data_width => c_wishbone_data_width+1,
g_size => c_fifo_size,
-- Read-side flag selection
g_with_rd_empty => true, -- with empty flag
--g_with_rd_count => false, -- with words counter
--g_with_wr_empty => false,
g_with_wr_full => true
--g_with_wr_count => false,
--g_almost_empty_threshold => ?, -- threshold for almost empty flag
--g_almost_full_threshold => ? -- threshold for almost full flag
)
port map(
rst_n_i => fifo_rst_n,
-- write port
clk_wr_i => fifo_wrclk,
d_i => fifo_di,
we_i => fifo_wren,
wr_empty_o => open,
wr_full_o => fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
-- read port
clk_rd_i => fifo_rdclk,
q_o => fifo_do,
rd_i => fifo_rden,
rd_empty_o => fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
fifo_rst_n <= arst_n_i;
fifo_rden <= dma_valid_s;
fifo_rdclk <= dma_clk_i;
-- Observe the FIFO reset cycle! dma_clk_buf is the clock for fifo_rd_en
fifo_wrclk <= data_clk_i;
-- -- c_wishbone_data_width + 1 bits.
-- -- It doesn't matter if the data_i is signed or unsigned since we do not care what the input data is.
-- -- The user has to treat this and extend the sign if necessary.
fifo_di <= last_data_reg & data_i_d1;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RAM_ARBITER_TEST IS
END RAM_ARBITER_TEST;
ARCHITECTURE behavior OF RAM_ARBITER_TEST IS
COMPONENT RAM_ARBITER_NEW
PORT(
RST_N : IN std_logic;
CLOCK : IN std_logic;
RST_DONE : OUT std_logic;
RD_EN_C1 : IN std_logic;
WR_EN_C1 : IN std_logic;
RDADDR_C1 : IN std_logic_vector(3 downto 0);
WRADDR_C1 : IN std_logic_vector(3 downto 0);
WRDATA_C1 : IN std_logic_vector(7 downto 0);
DATAIN_C2 : IN std_logic_vector(7 downto 0);
REQUEST_C2 : IN std_logic;
RD_NOT_WRITE_C2 : IN std_logic;
ADDR_C2 : IN std_logic_vector(3 downto 0);
RDDATA_C1 : OUT std_logic_vector(7 downto 0);
DATAOUT_C2 : OUT std_logic_vector(7 downto 0);
ACK_C2 : OUT std_logic
);
END COMPONENT;
--Inputs
signal RST_N : std_logic := '0';
signal CLOCK : std_logic := '0';
signal RD_EN_C1 : std_logic := '0';
signal WR_EN_C1 : std_logic := '0';
signal RDADDR_C1 : std_logic_vector(3 downto 0) := (others => '0');
signal WRADDR_C1 : std_logic_vector(3 downto 0) := (others => '0');
signal WRDATA_C1 : std_logic_vector(7 downto 0) := (others => '0');
signal DATAIN_C2 : std_logic_vector(7 downto 0) := (others => '0');
signal REQUEST_C2 : std_logic := '0';
signal RD_NOT_WRITE_C2 : std_logic := '0';
signal ADDR_C2 : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal RST_DONE : std_logic;
signal RDDATA_C1 : std_logic_vector(7 downto 0);
signal DATAOUT_C2 : std_logic_vector(7 downto 0);
signal ACK_C2 : std_logic;
-- Clock period definitions
constant CLOCK_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RAM_ARBITER_NEW PORT MAP (
RST_N => RST_N,
CLOCK => CLOCK,
RST_DONE => RST_DONE,
RD_EN_C1 => RD_EN_C1,
WR_EN_C1 => WR_EN_C1,
RDADDR_C1 => RDADDR_C1,
WRADDR_C1 => WRADDR_C1,
WRDATA_C1 => WRDATA_C1,
DATAIN_C2 => DATAIN_C2,
REQUEST_C2 => REQUEST_C2,
RD_NOT_WRITE_C2 => RD_NOT_WRITE_C2,
ADDR_C2 => ADDR_C2,
RDDATA_C1 => RDDATA_C1,
DATAOUT_C2 => DATAOUT_C2,
ACK_C2 => ACK_C2
);
-- Clock process definitions
CLOCK_process :process
begin
CLOCK <= '0';
wait for CLOCK_period/2;
CLOCK <= '1';
wait for CLOCK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
----------------------------------------------------------------------------------------
---- Test Case-1: Only Client1 wants to write
----------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
---- Test Case-2: Only Client1 wants to read
----------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
wait for 1700 ns;
WR_EN_C1<= '0';
RD_EN_C1<= '1';
RDADDR_C1 <="1010";
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
---- Test Case-3: Only Client2 wants to write
----------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
---- Test Case-4: Only Client2 wants to read
----------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '0';
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-5: Client1 wants to read and write in different RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
wait for 1700 ns;
RD_EN_C1<= '1';
RDADDR_C1 <="1010";
WRADDR_C1 <="1110";
WRDATA_C1 <="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-6: Client1 wants to read and write in different RAM location at different time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
wait for 1700 ns;
RD_EN_C1<= '1';
RDADDR_C1 <="1010";
wait for 500 ns;
WRADDR_C1 <="1110";
WRDATA_C1 <="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-7: Client1 wants to read and write in same RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
wait for 1700 ns;
RD_EN_C1<= '1';
RDADDR_C1 <="1010";
WRADDR_C1 <="1010";
WRDATA_C1 <="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-8: Client1 wants to read and write in same RAM location at different time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
wait for 500 ns;
WR_EN_C1<= '1';
WRADDR_C1 <="1010";
WRDATA_C1 <="10100011";
wait for 1700 ns;
RD_EN_C1<= '1';
RDADDR_C1 <="1010";
wait for 500 ns;
WRADDR_C1 <="1010";
WRDATA_C1 <="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
---- Test Case-9: Client2 wants to read and write in different RAM location at same time.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1001";
DATAIN_C2 <="00100011";
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1010";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
---- Test Case-10: Client2 wants to read and write in different RAM location at different time.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1001";
DATAIN_C2 <="00100011";
wait for 500 ns;
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1010";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
---- Test Case-11: Client2 wants to read and write in same RAM location at same time.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1010";
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="00100011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
---- Test Case-12: Client2 wants to read and write in same RAM location at different time.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1010";
wait for 500 ns;
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1010";
DATAIN_C2 <="00100011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-13: Client1 wants to write and client2 wants to read in different RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1 <="1001";
WRDATA_C1 <="10111011";
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-14: Client1 wants to write and client2 wants to read in different RAM location at different time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1 <="1001";
WRDATA_C1 <="10111011";
wait for 500 ns;
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-15: Client1 wants to write and client2 wants to read in same RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1 <="1110";
WRDATA_C1 <="10111011";
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-16: Client1 wants to write and client2 wants to read in same RAM location at different time
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '0';
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2 <="1110";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1 <="1110";
WRDATA_C1 <="10111011";
wait for 500 ns;
REQUEST_C2<= '1';
RD_NOT_WRITE_C2<= '1';
ADDR_C2 <="1110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-17: Client1 wants to read and Client2 wants to write in same RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2<="1010";
DATAIN_C2<="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-18: Client1 wants to read and Client2 wants to write in same RAM location at different time
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
wait for 500 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2<="1010";
DATAIN_C2<="10111011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-19: Client1 wants to read and Client2 wants to write in different RAM location at same time
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1000";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1000";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2<="1010";
DATAIN_C2<="10100011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-20: Client1 wants to read and Client2 wants to write in different RAM location at differnet time
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1000";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1000";
wait for 500 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<= '0';
ADDR_C2<="1010";
DATAIN_C2<="10100011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-21: Client1 wants to read and Client2 wants to read in same RAM location at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
wait for 300 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1010";
wait for 200 ns;
RD_EN_C1<='0';
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-22: Client1 wants to read and Client2 wants to read in same RAM location at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1010";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-23: Client1 wants to read and Client2 wants to read in different RAM location at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1001";
wait for 300 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1010";
wait for 200 ns;
RD_EN_C1<='0';
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-24: Client1 wants to read and Client2 wants to read in different RAM location at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
WR_EN_C1<='0';
RDADDR_C1<="1001";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1010";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-25: Client1 wants to read and write in the same RAM location and Client2 also wants to read in the
-- RAM location where Client1 has written at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
RDADDR_C1<="1001";
WRADDR_C1<="1001";
WRDATA_C1<="10100011";
wait for 300 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1001";
wait for 200 ns;
RD_EN_C1<='0';
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-26: Client1 wants to read and write in the same RAM location and Client2 also wants to read in the
-- RAM location where Client1 has written at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
RDADDR_C1<="1001";
WRADDR_C1<="1001";
WRDATA_C1<="10100011";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='1';
ADDR_C2<="1001";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-27: Client1 wants to read and write in the same RAM location and Client2 also wants to write in the
-- RAM location where Client1 has written at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
RDADDR_C1<="1001";
WRADDR_C1<="1001";
WRDATA_C1<="10100011";
wait for 300 ns;
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
wait for 200 ns;
WR_EN_C1<='0';
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-28: Client1 wants to read and write in the same RAM location and Client2 also wants to write in the
-- RAM location where Client1 has written at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 1700 ns;
RD_EN_C1<='1';
RDADDR_C1<="1001";
WRADDR_C1<="1001";
WRDATA_C1<="10100011";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-29: Client2 wants to read and write in the same RAM location and Client1 also wants to write in the
-- RAM location where Client2 has written at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<='1';
ADDR_C2 <="1001";
wait for 300 ns;
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
wait for 200 ns;
WR_EN_C1<= '1';
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-30: Client2 wants to read and write in the same RAM location and Client1 also wants to write in the
-- RAM location where Client2 has written at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
wait for 1700 ns;
WR_EN_C1<= '1';
RD_NOT_WRITE_C2<='1';
ADDR_C2 <="1001";
WRADDR_C1<="1001";
WRDATA_C1<="10101111";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-31: Client2 wants to read and write in the same RAM location and Client1 also wants to read in the
-- RAM location where Client2 has written at same time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_EN_C1<= '1';
RD_NOT_WRITE_C2<='1';
ADDR_C2 <="1001";
RDADDR_C1 <="1001";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-32: Client2 wants to read and write in the same RAM location and Client1 also wants to read in the
-- RAM location where Client2 has written at different time.
------------------------------------------------------------------------------------------------------------------
RST_N <='1';
WR_EN_C1<= '0';
RD_EN_C1<= '0';
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2 <="1001";
DATAIN_C2 <="11100011";
wait for 1700 ns;
RD_NOT_WRITE_C2<='1';
ADDR_C2 <="1001";
wait for 300 ns;
RD_EN_C1<= '1';
RDADDR_C1 <="1001";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-33: If any client resets (RST_N=0) the system at any time.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
wait for 1700 ns;
RST_N<='0';
RD_EN_C1<= '1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2<="0110";
DATAIN_C2<="10111011";
wait for 500 ns;
RST_N<='1';
RDADDR_C1<="1010";
wait for 300 ns;
RDADDR_C1<="0110";
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
----Test Case-34: If any client gives the inputs until RST_DONE is high.
------------------------------------------------------------------------------------------------------------------
RST_N<='1';
wait for 200 ns;
WR_EN_C1<= '1';
RD_EN_C1<= '0';
WRADDR_C1<="1010";
WRDATA_C1<="10101111";
RST_N<='0';
wait for 1700 ns;
RD_EN_C1<= '1';
WR_EN_C1<='0';
RDADDR_C1<="1010";
REQUEST_C2<='1';
RD_NOT_WRITE_C2<='0';
ADDR_C2<="0110";
DATAIN_C2<="10111011";
wait for 800 ns;
RST_N<='1';
RDADDR_C1<="1010";
----------------------------------------------------------------------------------------
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity add03 is
port (
a, b : std_logic_vector(8 DOWNTO 0);
borrow : std_logic;
res : out std_logic_vector(8 DOWNTO 0));
end add03;
LIBRARY ieee;
USE ieee.std_logic_arith.all;
architecture behav of add03 is
signal t : signed(8 DOWNTO 0);
begin
t <= signed(a) - signed(b) - borrow;
res <= std_logic_vector(t);
end behav;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-09-11 14:52:13-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.12 2007-09-11 14:52:13-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-09-11 14:52:13-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.12 2007-09-11 14:52:13-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.general_pkg.all;
entity dynamic_uart_tx is
port(
clk : in std_logic;
srst : in std_logic;
clocks_per_bit : in unsigned(15 downto 0); -- minimum 4, reccommended 16+
data_bits : in unsigned( 2 downto 0); -- add 4
parity_mode : in unsigned( 1 downto 0); -- 00 = none, X1 = odd, 10 = even
stop_2_bits : in std_logic;
txd : out std_logic;
data : in std_logic_vector(11 downto 0); --only lower [data_bits+4] are transmitted
en : in std_logic; --ignored if asserted when ready is low
ready : out std_logic
);
end dynamic_uart_tx;
architecture rtl of dynamic_uart_tx is
signal data_i : std_logic_vector(11 downto 0);
signal parity_i : std_logic;
signal clk_cnt : unsigned(15 downto 0) := (others=>'0');
signal data_cnt : unsigned(3 downto 0);
type t_state is (s_idle, s_data, s_parity, s_stop, s_stop_2, s_hold);
signal state : t_state := s_hold;
begin
p_tx : process(clk)
begin
if rising_edge(clk) then
if clk_cnt /= clocks_per_bit-1 then
clk_cnt <= clk_cnt+1; --default
else
clk_cnt <= (others=>'0');
end if;
case state is
when s_idle =>
clk_cnt <= (others=>'0');
data_cnt <= (others=>'0');
parity_i <= '0';
if en='1' then
data_i <= data;
state <= s_data;
txd <= '0'; --start bit
ready <= '0';
end if;
when s_data =>
if clk_cnt = clocks_per_bit-1 then
txd <= data_i(0);
data_i <= '0' & data_i(data_i'left downto 1);
parity_i <= parity_i xor data_i(0);
data_cnt <= data_cnt+1;
if data_cnt = ('0' & data_bits) + 3 then
if parity_mode(0)='1' or parity_mode(1)='1' then
state <= s_parity;
else
state <= s_stop;
end if;
end if;
end if;
when s_parity =>
if clk_cnt = clocks_per_bit-1 then
state <= s_stop;
if parity_mode(0)='1' then --odd
txd <= not(parity_i);
else
txd <= parity_i;
end if;
end if;
when s_stop =>
if clk_cnt = clocks_per_bit-1 then
txd <= '1'; --stop bit
if stop_2_bits='1' then
state <= s_stop_2;
else
state <= s_hold;
end if;
end if;
when s_stop_2 =>
if clk_cnt = clocks_per_bit-1 then
txd <= '1'; --stop bit
state <= s_hold;
end if;
when s_hold =>
txd <= '1';
if clk_cnt = clocks_per_bit-2 then --drops a cycle to make time for max speed transmission when en is asserted on the first cycle of idle
state <= s_idle;
ready <= '1';
end if;
end case;
if srst='1' then
clk_cnt <= (others=>'0');
ready <= '0';
state <= s_hold;
end if;
end if;
end process;
end rtl; |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : top.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : top
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N; Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : NOV 28, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for top
--=============================================================================
entity top is
port (
-- async receiver/transmitter com ports
CLOCK_50 : in std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic;
LEDR : out std_logic_vector (17 downto 0)
);
end top;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture structure of top is
signal rxReady : std_logic;
signal rxData : std_logic_vector(7 downto 0);
signal txBusy : std_logic;
signal txStart : std_logic;
signal txData : std_logic_vector(7 downto 0);
signal NN_start : std_logic; -- 0 - stop / 1 - start neural net
signal NN_sample : std_logic_vector (7 downto 0);
signal NN_result : std_logic_vector (1 downto 0);
signal NN_expected : std_logic_vector (1 downto 0);
signal NN_ready : std_logic;
component rs_232
port (
clk : in std_logic;
txStart : in std_logic;
txData : in std_logic_vector(7 downto 0);
rxD : in std_logic;
rxReady : out std_logic;
rxData : out std_logic_vector(7 downto 0);
txBusy : out std_logic;
txD : out std_logic
);
end component;
component controller
port (
-- async receiver/transmitter com ports
clk : in std_logic;
rxReady : in std_logic;
rxData : in std_logic_vector(7 downto 0); -- command string (character)
txBusy : in std_logic;
txStart : out std_logic;
txData : out std_logic_vector(7 downto 0);
-- LEDs (for debugging)
leds : out std_logic_vector (17 downto 0);
-- control ports
NN_start : out std_logic;
NN_sample : out std_logic_vector (7 downto 0);
NN_result : in std_logic_vector (1 downto 0);
NN_expected : in std_logic_vector (1 downto 0);
NN_ready : in std_logic
);
end component;
component NN_INSTANCE
port (
clk : in std_logic;
NN_start : in std_logic;
NN_sample : in std_logic_vector (7 downto 0);
NN_result : out std_logic_vector (1 downto 0);
NN_expected : out std_logic_vector (1 downto 0);
NN_ready : out std_logic
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
serial_interface : rs_232
port map (
clk => CLOCK_50,
txStart => txStart,
txData => txData,
rxD => UART_RXD,
rxReady => rxReady,
rxData => rxData,
txBusy => txBusy,
txD => UART_TXD
);
control_block : controller
port map (
clk => CLOCK_50,
rxReady => rxReady,
rxData => rxData,
txBusy => txBusy,
txStart => txStart,
txData => txData,
leds => LEDR,
NN_start => NN_start,
NN_sample => NN_sample,
NN_result => NN_result,
NN_expected => NN_expected,
NN_ready => NN_ready
);
neural_net : NN_INSTANCE
port map (
clk => CLOCK_50,
NN_start => NN_start,
NN_sample => NN_sample,
NN_result => NN_result,
NN_expected => NN_expected,
NN_ready => NN_ready
);
end structure;
--=============================================================================
-- architecture end
--============================================================================= |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Wing_VGA8 is
port (
vga_hsync : in std_logic;
vga_vsync : in std_logic;
vga_red1 : in std_logic;
vga_red0 : in std_logic;
vga_green1 : in std_logic;
vga_green0 : in std_logic;
vga_blue1 : in std_logic;
vga_blue0 : in std_logic;
wt_miso: inout std_logic_vector(7 downto 0);
wt_mosi: inout std_logic_vector(7 downto 0)
);
end Wing_VGA8;
architecture Behavioral of Wing_VGA8 is
begin
wt_miso(0) <= vga_vsync;
wt_miso(1) <= vga_hsync;
wt_miso(2) <= vga_blue0;
wt_miso(3) <= vga_blue1;
wt_miso(4) <= vga_green1;
wt_miso(5) <= vga_red1;
wt_miso(6) <= vga_green0;
wt_miso(7) <= vga_red0;
end Behavioral;
|
----------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity periferico_io is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
read_en, write_en : in STD_LOGIC; --señales de habilitación para la lectura y escritura en los periféricos
address: in STD_LOGIC_VECTOR (31 downto 0); --dirección del periférico mapeada en el espacio de direcciones
dato_bus_i : in STD_LOGIC_VECTOR (31 downto 0); --dato de entrada al periférico desde el bus
dato_bus_o : out STD_LOGIC_VECTOR (31 downto 0); --dato de salida del periférico hacia el bus
dato_inout : inout STD_LOGIC_VECTOR (7 downto 0) --conexión del periférico hacia el exterior
);
end periferico_io;
architecture Behavioral of periferico_io is
signal config_perif : STD_LOGIC_VECTOR (31 downto 0);
signal reg_salida, reg_entrada : STD_LOGIC_VECTOR (7 downto 0);
begin
-- configuración del periferico
process(clk, reset)
begin
if reset = '1' then
config_perif <= (others => '0');
elsif falling_edge(clk) then
if write_en = '1' then
--La dirección terminada en 0 es el puerto de config
if address(3 downto 0) = x"0" then
config_perif <= dato_bus_i;
end if;
end if;
end if;
end process;
-- config_perif = 00000002 lectura
-- config_perif = 00000004 escritura
-- config_perif = 0000000X no inicializado
--Si el periferico se usa de entrada
process(clk, reset)
begin
if reset = '1' then
reg_entrada <= (others => '0');
elsif falling_edge(clk) then
if read_en = '1' then
if address(3 downto 0) = x"4" then
if config_perif(3 downto 0) = x"2" then -- si config como lectura
--se almacena el dato dentro del periferico
reg_entrada <= dato_inout;
end if;
end if;
end if;
end if;
end process;
dato_bus_o <= x"000000" & reg_entrada; --se saca el dato hacia el bus
--Si el periferico se usa de salida
process(clk, reset)
begin
if reset = '1' then
reg_salida <= (others => '0');
elsif falling_edge(clk) then
if write_en = '1' then
if address(3 downto 0) = x"4" then
if config_perif(3 downto 0) = x"4" then -- config como escritura
--se almacena el dato dentro del periferico. Solo 8 bits
reg_salida <= dato_bus_i(7 downto 0);
end if;
end if;
end if;
end if;
end process;
--se saca el dato cuando es de salida, sino se deja a alta impedancia
dato_inout <= reg_salida when config_perif(3 downto 0) = x"4" else (others => 'Z');
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testMUX IS
END testMUX;
Architecture Test OF testMUX IS
COMPONENT mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e, f : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL s_a, s_b, s_c, s_d, s_e, s_f : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_S : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
test_mux : mux GENERIC MAP(16) PORT MAP(s_a, s_b, s_c, s_d, s_e, s_f, s_sel, s_S);
ProcessSimulation : PROCESS
BEGIN
s_a <= "0000000000000000";
s_b <= "0000000000000001";
s_c <= "0000000000000011";
s_d <= "0000000000000111";
s_e <= "0000000000001111";
s_f <= "0000000000011111";
s_sel <= "1111";
WAIT FOR 10 ns;
s_sel <= "0011";
WAIT FOR 10 ns;
s_sel <= "0100";
WAIT FOR 10 ns;
s_sel <= "0101";
WAIT FOR 10 ns;
s_sel <= "0110";
WAIT FOR 10 ns;
s_sel <= "0111";
WAIT FOR 10 ns;
s_sel <= "1000";
WAIT FOR 10 ns;
WAIT;
END PROCESS ProcessSimulation;
END Test;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eudet_tlu is
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
deadtime_i : IN std_logic_vector(15 downto 0);
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end eudet_tlu;
architecture rtl of eudet_tlu is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
-- constants
signal C_DEADTIME : integer := 2000; -- clk_i cycles
signal C_CLKDIVIDER : integer := 16; -- 160 MHz -> 10Mhz
-- State machine
type state_type is (IDLE, TRIGGER, RECEIVE, DEAD);
signal state : state_type;
-- Sync inputs
signal sync_eudet_trig_t : std_logic;
signal sync_eudet_rst_i : std_logic;
signal trig_tag_t : std_logic_vector(15 downto 0); -- only 15:1 good
signal eudet_busy_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_bust_t : std_logic;
signal clk_counter : unsigned (7 downto 0);
signal bit_counter : unsigned (4 downto 0);
signal dead_counter : unsigned (15 downto 0);
signal deadtime_t : std_logic_vector(15 downto 0);
begin
-- Sync async inputs
trig_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_trig_i, sync_out => sync_eudet_trig_t);
rst_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_rst_i, sync_out => sync_eudet_rst_i);
eudet_busy_o <= eudet_busy_t;
eudet_clk_o <= eudet_clk_t;
rst_o <= '0';
state_machine: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
state <= IDLE;
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
dead_counter <= (others => '0');
deadtime_t <= (others => '0');
trig_tag_t <= (others => '0');
trig_tag_o <= (others => '0');
trig_o <= '0';
elsif rising_edge(clk_i) then
case state is
when IDLE =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_o <= '0';
if (sync_eudet_trig_t = '1') then
state <= TRIGGER;
end if;
when TRIGGER =>
-- Raise busy and wait until trigger is negated
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_tag_t <= (others => '0');
dead_counter <= (others => '0');
if (sync_eudet_trig_t = '0' and simple_mode_i = '0') then
state <= RECEIVE;
elsif (sync_eudet_trig_t = '0' and simple_mode_i = '1') then
state <= DEAD;
end if;
when RECEIVE =>
eudet_busy_t <= '1';
trig_o <= '0';
clk_counter <= clk_counter + 1;
dead_counter <= (others => '0');
if (clk_counter = (C_CLKDIVIDER-1)) then
clk_counter <= (others => '0');
eudet_clk_t <= not eudet_clk_t;
if (eudet_clk_t = '1') then --sampling on negative edge
bit_counter <= bit_counter + 1;
trig_tag_t <= eudet_trig_i & trig_tag_t(15 downto 1); -- do not need synced vers here
end if;
end if;
if (bit_counter = "10000") then
state <= DEAD;
trig_tag_o <= '0' & trig_tag_t(14 downto 0);
end if;
when DEAD =>
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
if (dead_counter = 0) then
trig_o <= '1'; -- Trigger now (16 clock cycles after the initial trigger?)
end if;
dead_counter <= dead_counter + 1;
if (dead_counter >= unsigned(deadtime_t) and busy_i = '0') then
state <= IDLE;
end if;
when others =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
state <= IDLE;
end case;
deadtime_t <= deadtime_i;
end if;
end process state_machine;
end rtl;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
-- SHA256 Hashing Module - Testbench
-- Kristian Klomsten Skordal <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
entity tb_sha256 is
end entity tb_sha256;
architecture testbench of tb_sha256 is
-- Input signals:
signal reset : std_logic := '0';
signal update : std_logic := '0';
signal enable : std_logic := '1';
signal word_input : std_logic_vector(31 downto 0) := (others => '0');
-- Output signals:
signal ready : std_logic;
signal word_address : std_logic_vector(3 downto 0);
signal debug_port : std_logic_vector(31 downto 0);
signal hash_output : std_logic_vector(255 downto 0);
-- Clock signal:
signal clk : std_logic;
constant clk_period : time := 10 ns;
-- Other signals:
signal testdata_address : std_logic_vector(5 downto 0);
begin
uut: entity work.sha256
port map(
clk => clk,
reset => reset,
enable => enable,
ready => ready,
update => update,
word_address => word_address,
word_input => word_input,
hash_output => hash_output,
debug_port => debug_port
);
testdata_address(3 downto 0) <= word_address;
testdata: entity work.testrom
port map(
clk => clk,
word_address => testdata_address,
word_output => word_input
);
clock: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process clock;
stimulus: process
begin
testdata_address(5 downto 4) <= b"00";
wait for clk_period * 2;
-- Reset the module:
reset <= '1';
wait for clk_period;
reset <= '0';
wait for clk_period;
-- The module should now be ready for work:
assert ready = '1' report "Module is not ready after reset!";
wait for clk_period;
-- Start hashing the first test data:
update <= '1';
wait for clk_period;
update <= '0';
wait until ready = '1';
assert hash_output = x"ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad"
report "Hash of 'abc' is not ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad!";
wait for clk_period;
-- Reset the module to prepare for the second set of test data:
reset <= '1';
wait for clk_period;
reset <= '0';
wait for clk_period;
-- Check again that the module is ready for work:
assert ready = '1' report "Module is not ready after reset!";
wait for clk_period;
-- Run the first block:
testdata_address(4) <= '1';
update <= '1';
wait for clk_period;
update <= '0';
wait until ready = '1';
assert hash_output = x"85e655d6417a17953363376a624cde5c76e09589cac5f811cc4b32c1f20e533a"
report "Hash from the first round of testdata 2 is not 85e655d6417a17953363376a624cde5c76e09589cac5f811cc4b32c1f20e533a!";
wait for clk_period;
-- Run the second block:
testdata_address(5) <= '1';
update <= '1';
wait for clk_period;
update <= '0';
wait until ready = '1';
assert hash_output = x"248d6a61d20638b8e5c026930c3e6039a33ce45964ff2167f6ecedd419db06c1"
report "Hash from the second round of testdata 2 is not 248d6a61d20638b8e5c026930c3e6039a33ce45964ff2167f6ecedd419db06c1!";
wait for clk_period;
report "Victory 8D";
wait;
end process stimulus;
end architecture testbench;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:22 05/12/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-projects/AVC2013/avc_platform/servo_controller_tb.vhd
-- Project Name: avc_platform
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: servo_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY servo_controller_tb IS
END servo_controller_tb;
ARCHITECTURE behavior OF servo_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT servo_controller
PORT(
clk : IN std_logic;
rst : IN std_logic;
servo_position : IN std_logic_vector(0 to 7);
servo_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal servo_position : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal servo_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: servo_controller PORT MAP (
clk => clk,
rst => rst,
servo_position => servo_position,
servo_out => servo_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1' ;
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0' ;
servo_position <= X"80";
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:22 05/12/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-projects/AVC2013/avc_platform/servo_controller_tb.vhd
-- Project Name: avc_platform
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: servo_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY servo_controller_tb IS
END servo_controller_tb;
ARCHITECTURE behavior OF servo_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT servo_controller
PORT(
clk : IN std_logic;
rst : IN std_logic;
servo_position : IN std_logic_vector(0 to 7);
servo_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal servo_position : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal servo_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: servo_controller PORT MAP (
clk => clk,
rst => rst,
servo_position => servo_position,
servo_out => servo_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1' ;
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0' ;
servo_position <= X"80";
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v1.01.b
--
-- Description:
-- This file contains a parameterizable N-bit up counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Data width of counter
--
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- Active low clear
-- Data -- Serial data in
-- Cnt_en -- Count enable
-- Load -- Load line enable
-- Qout -- Shift register shift enable
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : integer :=9
);
port(
Clr : in std_logic;
Clk : in std_logic;
Data : in std_logic_vector (0 to C_SIZE-1);
Cnt_en : in std_logic;
Load : in std_logic;
Qout : inout std_logic_vector (0 to C_SIZE-1)
);
end upcnt_n;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of upcnt_n is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal q_int : unsigned (0 to C_SIZE-1);
begin
----------------------------------------------------------------------------
-- PROCESS: UP_COUNT_GEN
-- purpose: Up counter
----------------------------------------------------------------------------
UP_COUNT_GEN : process(Clk)
begin
if (Clk'event) and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
q_int <= (others => '0');
elsif (Load = '1') then -- Load in start value
q_int <= unsigned(Data);
elsif Cnt_en = '1' then -- If count enable is high
q_int <= q_int + 1;
else
q_int <= q_int;
end if;
end if;
end process UP_COUNT_GEN;
Qout <= std_logic_vector(q_int);
end architecture RTL;
-------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: shift8.vhd
-- Version: v1.01.b
-- Description:
-- This file contains an 8 bit shift register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- System reset
-- Data_ld -- Shift register data load enable
-- Data_in -- Shift register data in
-- Shift_in -- Shift register serial data in
-- Shift_en -- Shift register shift enable
-- Shift_out -- Shift register serial data out
-- Data_out -- Shift register shift data out
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shift8 is
port(
Clk : in std_logic; -- Clock
Clr : in std_logic; -- Clear
Data_ld : in std_logic; -- Data load enable
Data_in : in std_logic_vector (7 downto 0);-- Data to load in
Shift_in : in std_logic; -- Serial data in
Shift_en : in std_logic; -- Shift enable
Shift_out : out std_logic; -- Shift serial data out
Data_out : out std_logic_vector (7 downto 0) -- Shifted data
);
end shift8;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of shift8 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal data_int : std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS: SHIFT_REG_GEN
-- purpose: generate shift register
----------------------------------------------------------------------------
SHIFT_REG_GEN : process(Clk)
begin
if Clk'event and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
data_int <= (others => '0');
elsif (Data_ld = '1') then -- Load data
data_int <= Data_in;
elsif Shift_en = '1' then -- If shift enable is high
data_int <= data_int(6 downto 0) & Shift_in; -- Shift the data
end if;
end if;
end process SHIFT_REG_GEN;
Shift_out <= data_int(7);
Data_out <= data_int;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic_pkg.vhd - Package
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_pkg.vhd
-- Version: v1.01.b
-- Description: This file contains the constants used in the design of the
-- iic bus interface.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package iic_pkg is
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1'; -- Reset Constant
constant NUM_IIC_REGS : integer := 11; -- should be same as C_NUM_IIC_REGS in axi_iic top
constant DATA_BITS : natural := 8; -- FIFO Width Generic
constant TX_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
constant RC_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
--IPIF Generics that must remain at these values for the IIC
constant INCLUDE_DEV_PENCODER : BOOLEAN := False;
constant IPIF_ABUS_WIDTH : INTEGER := 32;
constant INCLUDE_DEV_ISC : Boolean := false;
type STD_LOGIC_VECTOR_ARRAY is array (0 to NUM_IIC_REGS-1) of std_logic_vector(24 to 31);
type INTEGER_ARRAY is array (24 to 31) of integer;
----------------------------------------------------------------------------
-- Function and Procedure Declarations
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer;
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector;
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector;
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return
INTEGER_ARRAY;
end package iic_pkg;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body iic_pkg is
----------------------------------------------------------------------------
-- Function Definitions
----------------------------------------------------------------------------
-- Function num_ctr_bits
--
-- This function returns the number of bits required to count 1/2 the period
-- of the SCL clock.
--
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer is
variable num_bits : integer :=0;
variable i : integer :=0;
begin
-- for loop used because XST service pack 2 does not support While loops
if C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ > C_S_AXI_ACLK_FREQ_HZ/212766 then
for i in 0 to 30 loop -- 30 is a magic number needed for for loops
if 2**i < C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
else
for i in 0 to 30 loop
if 2**i < C_S_AXI_ACLK_FREQ_HZ/212766 then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
end if;
end function num_ctr_bits;
----------------------------------------------------------------------------
-- Function ten_bit_addr_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector is
begin
if C_TEN_BIT_ADR = 0 then
return (b"00000000");
else
return (b"00000111");
end if;
end function ten_bit_addr_used;
----------------------------------------------------------------------------
-- Function gpo_bit_used
--
-- This function returns b"00000000" up to b"11111111" depending on
-- C_GPO_WIDTH
--
----------------------------------------------------------------------------
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector is
begin
if C_GPO_WIDTH = 1 then
return (b"00000001");
elsif C_GPO_WIDTH = 2 then
return (b"00000011");
elsif C_GPO_WIDTH = 3 then
return (b"00000111");
elsif C_GPO_WIDTH = 4 then
return (b"00001111");
elsif C_GPO_WIDTH = 5 then
return (b"00011111");
elsif C_GPO_WIDTH = 6 then
return (b"00111111");
elsif C_GPO_WIDTH = 7 then
return (b"01111111");
elsif C_GPO_WIDTH = 8 then
return (b"11111111");
end if;
end function gpo_bit_used;
----------------------------------------------------------------------------
-- Function count_reg_bits_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY)
return INTEGER_ARRAY is
variable count : INTEGER_ARRAY;
begin
for i in 24 to 31 loop
count(i) := 0;
for m in 0 to NUM_IIC_REGS-1 loop --IP_REG_NUM - 1
if (REG_BITS_USED(m)(i) = '1') then
count(i) := count(i) + 1;
end if;
end loop;
end loop;
return count;
end function count_reg_bits_used;
end package body iic_pkg;
-------------------------------------------------------------------------------
-- debounce.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: debounce.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from a signal based upon
-- using user definable delay parameters. It accepts a "Stable"
-- signal which allows the filter to dynamically stretch its
-- delay based on whether another signal is Stable or not. If
-- the filter has detected a change on is "Noisy" input then it
-- will signal its output is "unstable". That can be cross
-- coupled into the "Stable" input of another filter if
-- necessary.
-- Notes:
-- 1) A default assignment based on the generic C_DEFAULT is made for the flip
-- flop output of the delay logic when C_INERTIAL_DELAY > 0. Otherwise, the
-- logic is free running and no reset is possible.
-- 2) A C_INERTIAL_DELAY value of 0 eliminates the debounce logic and connects
-- input to output directly.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613486
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INERTIAL_DELAY -- Filtering delay
-- C_DEFAULT -- User logic high address
-- Definition of Ports:
-- Sysclk -- System clock
-- Stable -- IIC signal is Stable
-- Unstable_n -- IIC signal is unstable
-- Noisy -- IIC signal is Noisy
-- Clean -- IIC signal is Clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity debounce is
generic (
C_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_DEFAULT : std_logic := '1'
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Stable : in std_logic;
Unstable_n : out std_logic;
Noisy : in std_logic;
Clean : out std_logic);
end entity debounce;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of debounce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- XST proceses default assignments for configuration purposes
signal clean_cs : std_logic := C_DEFAULT;
signal stable_cs : std_logic := '1';
signal debounce_ct : integer range 0 to 255;
signal Noisy_d1 : std_logic := '1';
signal Noisy_d2 : std_logic := '1';
begin
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
-- INPUT_DOUBLE_REGS : process(Sysclk)
-- begin
-- if Sysclk'event and Sysclk = '1' then
-- Noisy_d1 <= Noisy;
-- Noisy_d2 <= Noisy_d1; -- double buffer async input
-- end if;
-- end process INPUT_DOUBLE_REGS;
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Noisy,
prmry_vect_in => (others => '0'),
scndry_aclk => Sysclk,
scndry_resetn => '0',
scndry_out => Noisy_d2,
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- GEN_INERTIAL : Generate when C_INERTIAL_DELAY > 0
----------------------------------------------------------------------------
GEN_INERTIAL : if (C_INERTIAL_DELAY > 0) generate
----------------------------------------------------------------------------
-- GEN_INERTIAL : C_INERTIAL_DELAY > 0
-- Inertial delay filters out pulses that are smaller in width then the
-- specified delay. If the C_INERTIAL_DELAY is 0 then the input is passed
-- directly to the "Clean" output signal.
----------------------------------------------------------------------------
INRTL_PROCESS : process (Sysclk) is
begin
if ((rising_edge(Sysclk))) then
if Rst = '1' then
clean_cs <= C_DEFAULT;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
elsif (clean_cs = Noisy_d2) then
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
else
if (debounce_ct > 0) then
debounce_ct <= debounce_ct - 1;
Unstable_n <= '0';
else
if Stable = '1' then
clean_cs <= Noisy_d2;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
end if;
end if;
end if;
end if;
end process INRTL_PROCESS;
s0 : Clean <= clean_cs;
end generate GEN_INERTIAL;
----------------------------------------------------------------------------
-- NO_INERTIAL : C_INERTIAL_DELAY = 0
-- No inertial delay means output is always Stable
----------------------------------------------------------------------------
NO_INERTIAL : if (C_INERTIAL_DELAY = 0) generate
s0 : Clean <= Noisy_d2;
s1 : Unstable_n <= '1';
end generate NO_INERTIAL;
end architecture RTL;
-------------------------------------------------------------------------------
-- reg_interface.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: reg_interface.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the interface between the IPIF
-- and the iic controller. All registers are generated
-- here and all interrupts are processed here.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_arith.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_TX_FIFO_BITS -- Transmit FIFO bit size
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_RC_FIFO_BITS -- Receive FIFO bit size
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_DATA_WIDTH -- Slave bus data width
-- C_NUM_IIC_REGS -- Number of IIC Registers
--
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Bus2IIC_Addr -- Bus to IIC address bus
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-- Gpo -- General purpose outputs
-- Cr -- Control register
-- Msms_rst -- MSMS reset signal
-- Rsta_rst -- Repeated start reset
-- Msms_set -- MSMS set
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-- Aas -- Addressed as slave indicator
-- Bb -- Bus busy indicator
-- Srw -- Slave read/write indicator
-- Abgc -- Addressed by general call indicator
-- Dtr -- Data transmit register
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Dtre -- Data transmit register empty
-- Drr -- Data receive register
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Ro_prev -- Receive over run prevent
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Al -- Arbitration lost indicator
-- Txer -- Received acknowledge indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- Tx_fifo_data -- FIFO data to transmit
-- Tx_data_exists -- next FIFO data exists
-- Tx_fifo_wr -- Decode to enable writes to FIFO
-- Tx_fifo_rd -- Decode to enable read from FIFO
-- Tx_fifo_rst -- Reset Tx FIFO on IP Reset or CR(6)
-- Tx_fifo_Full -- Transmit FIFO full indicator
-- Tx_addr -- Transmit FIFO address
-- Rc_fifo_data -- Read Fifo data for AXI
-- Rc_fifo_wr -- Write IIC data to fifo
-- Rc_fifo_rd -- AXI read from fifo
-- Rc_fifo_Full -- Read Fifo is full prevent rcv overrun
-- Rc_data_Exists -- Next FIFO data exists
-- Rc_addr -- Receive FIFO address
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity reg_interface is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_TX_FIFO_BITS : integer := 4;
C_RC_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_BITS : integer := 4;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_SIZE : integer := 32;
C_NUM_IIC_REGS : integer;
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port(
-- IPIF Interface Signals
Clk : in std_logic;
Rst : in std_logic;
Bus2IIC_Addr : in std_logic_vector (0 to C_S_AXI_ADDR_WIDTH-1);
Bus2IIC_Data : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_WrCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
Bus2IIC_RdCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
IIC2Bus_Data : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
IIC2Bus_IntrEvent : out std_logic_vector (0 to 7);
-- Internal iic Bus Registers
-- GPO Register Offset 124h
Gpo : out std_logic_vector(32 - C_GPO_WIDTH to
C_S_AXI_DATA_WIDTH - 1);
-- Control Register Offset 100h
Cr : out std_logic_vector(0 to 7);
Msms_rst : in std_logic;
Rsta_rst : in std_logic;
Msms_set : out std_logic;
DynMsmsSet : in std_logic;
DynRstaSet : in std_logic;
Cr_txModeSelect_set : in std_logic;
Cr_txModeSelect_clr : in std_logic;
-- Status Register Offest 04h
Aas : in std_logic;
Bb : in std_logic;
Srw : in std_logic;
Abgc : in std_logic;
-- Data Transmit Register Offset 108h
Dtr : out std_logic_vector(0 to 7);
Rdy_new_xmt : in std_logic;
Dtre : out std_logic;
-- Data Receive Register Offset 10Ch
Drr : out std_logic_vector(0 to 7);
Data_i2c : in std_logic_vector(0 to 7);
New_rcv_dta : in std_logic;
Ro_prev : out std_logic;
-- Address Register Offset 10h
Adr : out std_logic_vector(0 to 7);
-- Ten Bit Address Register Offset 1Ch
Ten_adr : out std_logic_vector(5 to 7) := (others => '0');
Al : in std_logic;
Txer : in std_logic;
Tx_under_prev : in std_logic;
-- Timing Parameters to iic_control
Timing_param_tsusta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : out std_logic_vector(C_SIZE-1 downto 0);
-- FIFO input (fifo write) and output (fifo read)
Tx_fifo_data : in std_logic_vector(0 to 7);
Tx_data_exists : in std_logic;
Tx_fifo_wr : out std_logic;
Tx_fifo_rd : out std_logic;
Tx_fifo_rst : out std_logic;
Tx_fifo_Full : in std_logic;
Tx_addr : in std_logic_vector(0 to C_TX_FIFO_BITS - 1);
Rc_fifo_data : in std_logic_vector(0 to 7);
Rc_fifo_wr : out std_logic;
Rc_fifo_rd : out std_logic;
Rc_fifo_Full : in std_logic;
Rc_data_Exists : in std_logic;
Rc_addr : in std_logic_vector(0 to C_RC_FIFO_BITS - 1);
reg_empty : in std_logic
);
end reg_interface;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of reg_interface is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
constant IIC_CNT : integer := (C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ - 14);
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
-- number of SYSCLK in iic SCL High time
constant HIGH_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- number of SYSCLK in iic SCL Low time
constant LOW_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- half of HIGH_CNT
constant HIGH_CNT_2 : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/4, C_SIZE);
----------------------------------------------------------------------------
-- Function calc_tsusta
--
-- This function returns Setup time integer value for repeated start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for repeated start condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/175438, C_SIZE);
-- Added to have 5.7 us (tr+tsu-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sta)
else
-- Fast Mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sta)
end if;
end FUNCTION calc_tsusta;
----------------------------------------------------------------------------
-- Function calc_tsusto
--
-- This function returns Setup time integer value for stop condition for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusto (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for stop condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us (tr+tsu-sto)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sto)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sto)
end if;
end FUNCTION calc_tsusto;
----------------------------------------------------------------------------
-- Function calc_thdsta
--
-- This function returns Hold time integer value for reapeted start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_thdsta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate (repeated) START hold time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/232558, C_SIZE);
-- Added to have 4.3 us (tf+thd-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tf+thd-sta)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tf+thd-sta)
end if;
end FUNCTION calc_thdsta;
----------------------------------------------------------------------------
-- Function calc_tsudat
--
-- This function returns Data Setup time integer value for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsudat (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 250 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1818181, C_SIZE);
-- Added to have 550 ns (tf+tsu-dat)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 100 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2500000, C_SIZE);
-- Added to have 400 ns (tf+tsu-dat)
else
-- Fast-mode Plus timing is 50 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/5882353, C_SIZE);
-- Added to have 170 ns (tf+tsu-dat)
end if;
end FUNCTION calc_tsudat;
----------------------------------------------------------------------------
-- Function calc_tbuf
--
-- This function returns Bus free time between a STOP and START condition
-- integer value for Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tbuf (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 1.3 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/625000, C_SIZE);
-- Added to have 1.6 us
else
-- Fast-mode Plus timing is 0.5 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1612904, C_SIZE);
-- Added to have 0.62 us
end if;
end FUNCTION calc_tbuf;
----------------------------------------------------------------------------
-- Function calc_thddat
--
-- This function returns the data hold time integer value for I2C and
-- SMBus/PMBus protocols.
----------------------------------------------------------------------------
FUNCTION calc_thddat (
constant C_SMBUS_PMBUS_HOST : integer;
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data hold time depending on SMBus/PMBus compatability
if (C_SMBUS_PMBUS_HOST = 1) then
-- hold time of 300 ns for SMBus/PMBus
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/3333334, C_SIZE);
else
-- hold time of 0 ns for normal I2C
RETURN conv_std_logic_vector(1, C_SIZE);
end if;
end FUNCTION calc_thddat;
-- Set-up time for a repeated start
constant TSUSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Set-up time for a stop
constant TSUSTO : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusto(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Hold time (repeated) START condition. After this period, the first clock
-- pulse is generated.
constant THDSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thdsta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data setup time.
constant TSUDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsudat(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Bus free time.
constant TBUF : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tbuf(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data Hold time
constant THDDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thddat(C_SMBUS_PMBUS_HOST, C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
----------------------------------------------------------------------------
-- Signal and Type Declarations
----------------------------------------------------------------------------
signal cr_i : std_logic_vector(0 to 7); -- intrnl control reg
signal sr_i : std_logic_vector(0 to 7); -- intrnl statuss reg
signal dtr_i : std_logic_vector(0 to 7); -- intrnl dta trnsmt reg
signal drr_i : std_logic_vector(0 to 7); -- intrnl dta receive reg
signal adr_i : std_logic_vector(0 to 7); -- intrnl slave addr reg
signal rc_fifo_pirq_i : std_logic_vector(4 to 7); -- intrnl slave addr reg
signal ten_adr_i : std_logic_vector(5 to 7) := (others => '0');
-- intrnl slave addr reg
signal ro_a : std_logic; -- receive overrun SRFF
signal ro_i : std_logic; -- receive overrun SRFF
signal dtre_i : std_logic; -- data tranmit register empty register
signal new_rcv_dta_d1 : std_logic; -- delay new_rcv_dta to find rising edge
signal msms_d1 : std_logic; -- delay msms cr(5)
signal ro_prev_i : std_logic; -- internal Ro_prev
signal msms_set_i : std_logic; -- SRFF set on falling edge of msms
signal rtx_i : std_logic_vector(0 to 7);
signal rrc_i : std_logic_vector(0 to 7);
signal rtn_i : std_logic_vector(0 to 7);
signal rpq_i : std_logic_vector(0 to 7);
signal gpo_i : std_logic_vector(32 - C_GPO_WIDTH to 31); -- GPO
signal timing_param_tsusta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsusto_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thdsta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsudat_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tbuf_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thigh_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tlow_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thddat_i : std_logic_vector(C_SIZE-1 downto 0);
signal rback_data : std_logic_vector(0 to 32 * C_NUM_IIC_REGS - 1)
:= (others => '0');
begin
----------------------------------------------------------------------------
-- CONTROL_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
CONTROL_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
cr_i <= (others => '0');
elsif -- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
Bus2IIC_WrCE(0) = '1' then
cr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else -- Load Control Register with iic data
cr_i(0) <= cr_i(0);
cr_i(1) <= cr_i(1);
cr_i(2) <= (cr_i(2) or DynRstaSet) and not(Rsta_rst);
cr_i(3) <= cr_i(3);
cr_i(4) <= (cr_i(4) or Cr_txModeSelect_set) and
not(Cr_txModeSelect_clr);
cr_i(5) <= (cr_i(5) or DynMsmsSet) and not (Msms_rst);
cr_i(6) <= cr_i(6);
cr_i(7) <= cr_i(7);
end if;
end if;
end process CONTROL_REGISTER_PROCESS;
Cr <= cr_i;
----------------------------------------------------------------------------
-- Delay msms by one clock to find falling edge
----------------------------------------------------------------------------
MSMS_DELAY_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
msms_d1 <= '0';
else
msms_d1 <= cr_i(5);
end if;
end if;
end process MSMS_DELAY_PROCESS;
----------------------------------------------------------------------------
-- Set when a fall edge of msms has occurred and Ro_prev is active
-- This will prevent a throttle condition when a master receiver and
-- trying to initiate a stop condition.
----------------------------------------------------------------------------
MSMS_EDGE_SET_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
msms_set_i <= '0';
elsif ro_prev_i = '1' and cr_i(5) = '0' and msms_d1 = '1' then
msms_set_i <= '1';
elsif (cr_i(5) = '1' and msms_d1 = '0') or Bb = '0' then
msms_set_i <= '0';
else
msms_set_i <= msms_set_i;
end if;
end if;
end process MSMS_EDGE_SET_PROCESS;
Msms_set <= msms_set_i;
----------------------------------------------------------------------------
-- STATUS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process resets the status register. The status register is read only
----------------------------------------------------------------------------
STATUS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
sr_i <= (others => '0');
else -- Load Status Register with iic data
sr_i(0) <= not Tx_data_exists;
sr_i(1) <= not Rc_data_Exists;
sr_i(2) <= Rc_fifo_Full;
sr_i(3) <= Tx_fifo_Full; -- addressed by a general call
sr_i(4) <= Srw; -- slave read/write
sr_i(5) <= Bb; -- bus busy
sr_i(6) <= Aas; -- addressed as slave
sr_i(7) <= Abgc; -- addressed by a general call
end if;
end if;
end process STATUS_REGISTER_PROCESS;
----------------------------------------------------------------------------
-- Transmit FIFO CONTROL signal GENERATION
----------------------------------------------------------------------------
-- This process allows the AXI to write data to the write FIFO and assigns
-- that data to the output port and to the internal signals for reading
----------------------------------------------------------------------------
FIFO_GEN_DTR : if C_TX_FIFO_EXIST generate
-------------------------------------------------------------------------
-- FIFO_WR_CNTL_PROCESS - Tx fifo write process
-------------------------------------------------------------------------
FIFO_WR_CNTL_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_wr <= '0';
elsif
Bus2IIC_WrCE(2) = '1' then
Tx_fifo_wr <= '1';
else
Tx_fifo_wr <= '0';
end if;
end if;
end process FIFO_WR_CNTL_PROCESS;
-------------------------------------------------------------------------
-- FIFO_DTR_REG_PROCESS
-------------------------------------------------------------------------
FIFO_DTR_REG_PROCESS : process (Tx_fifo_data)
begin -- process
Dtr <= Tx_fifo_data;
dtr_i <= Tx_fifo_data;
end process FIFO_DTR_REG_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RD_PROCESS
-------------------------------------------------------------------------
-- This process generates the Read from the Transmit FIFO
-------------------------------------------------------------------------
Tx_FIFO_RD_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_rd <= '0';
elsif Rdy_new_xmt = '1' then
Tx_fifo_rd <= '1';
elsif Rdy_new_xmt = '0' --and Tx_data_exists = '1'
then Tx_fifo_rd <= '0';
end if;
end if;
end process Tx_FIFO_RD_PROCESS;
-------------------------------------------------------------------------
-- DTRE_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
DTRE_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
dtre_i <= '0';
else
dtre_i <= not (Tx_data_exists);
end if;
end if;
end process DTRE_PROCESS;
-------------------------------------------------------------------------
-- Additional FIFO Interrupt
-------------------------------------------------------------------------
-- FIFO_Int_PROCESS generates interrupts back to the IPIF when Tx FIFO
-- exists
-------------------------------------------------------------------------
FIFO_INT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(7) <= '0';
else
IIC2Bus_IntrEvent(7) <= not Tx_addr(3); -- Tx FIFO half empty
end if;
end if;
end process FIFO_INT_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RESET_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
TX_FIFO_RESET_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_rst <= '1';
else
Tx_fifo_rst <= cr_i(6);
end if;
end if;
end process TX_FIFO_RESET_PROCESS;
end generate FIFO_GEN_DTR;
Dtre <= dtre_i;
----------------------------------------------------------------------------
-- If a read FIFO exists then generate control signals
----------------------------------------------------------------------------
RD_FIFO_CNTRL : if (C_RC_FIFO_EXIST) generate
-------------------------------------------------------------------------
-- WRITE_TO_READ_FIFO_PROCESS
-------------------------------------------------------------------------
WRITE_TO_READ_FIFO_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Rc_fifo_wr <= '0';
-- Load iic Data When new data x-fer complete and not x-mitting
elsif
New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
Rc_fifo_wr <= '1';
else
Rc_fifo_wr <= '0';
end if;
end if;
end process WRITE_TO_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
AXI_READ_FROM_READ_FIFO_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Rc_fifo_rd <= '0';
elsif Bus2IIC_RdCE(3) = '1' then
Rc_fifo_rd <= '1';
else
Rc_fifo_rd <= '0';
end if;
end if;
end process AXI_READ_FROM_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
RD_FIFO_DRR_PROCESS : process (Rc_fifo_data)
begin
Drr <= Rc_fifo_data;
drr_i <= Rc_fifo_data;
end process RD_FIFO_DRR_PROCESS;
-------------------------------------------------------------------------
-- Rc_FIFO_PIRQ
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Rc_FIFO_PIRQ register is enabled.
-------------------------------------------------------------------------
Rc_FIFO_PIRQ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
rc_fifo_pirq_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(8) = '1' then
rc_fifo_pirq_i(4 to 7) <= Bus2IIC_Data(28 to 31);
else
rc_fifo_pirq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
end if;
end if;
end process Rc_FIFO_PIRQ_PROCESS;
-------------------------------------------------------------------------
-- RC_FIFO_FULL_PROCESS
-------------------------------------------------------------------------
-- This process throttles the bus when receiving and the RC_FIFO_PIRQ is
-- equalto the Receive FIFO Occupancy value
-------------------------------------------------------------------------
RC_FIFO_FULL_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ro_prev_i <= '0';
elsif msms_set_i = '1' then
ro_prev_i <= '0';
elsif (rc_fifo_pirq_i(4) = Rc_addr(3) and
rc_fifo_pirq_i(5) = Rc_addr(2) and
rc_fifo_pirq_i(6) = Rc_addr(1) and
rc_fifo_pirq_i(7) = Rc_addr(0)) and
Rc_data_Exists = '1'
then
ro_prev_i <= '1';
else
ro_prev_i <= '0';
end if;
end if;
end process RC_FIFO_FULL_PROCESS;
Ro_prev <= ro_prev_i;
end generate RD_FIFO_CNTRL;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
-- This process determines when the data receive register has had new data
-- written to it without a read of the old data
----------------------------------------------------------------------------
NEW_RECIEVE_DATA_PROCESS : process (Clk) -- delay new_rcv_dta to find edge
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
new_rcv_dta_d1 <= '0';
else
new_rcv_dta_d1 <= New_rcv_dta;
end if;
end if;
end process NEW_RECIEVE_DATA_PROCESS;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
RCV_OVRUN_PROCESS : process (Clk)
begin
-- SRFF set when new data is received, reset when a read of DRR occurs
-- The second SRFF is set when new data is again received before a
-- read of DRR occurs. This sets the Receive Overrun Status Bit
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ro_a <= '0';
elsif New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
ro_a <= '1';
elsif New_rcv_dta = '0' and Bus2IIC_RdCE(3) = '1'
then ro_a <= '0';
else
ro_a <= ro_a;
end if;
end if;
end process RCV_OVRUN_PROCESS;
----------------------------------------------------------------------------
-- ADDRESS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the address register is enabled.
----------------------------------------------------------------------------
ADDRESS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
-- Bus2IIC_WrReq = '1' and Bus2IIC_WrCE(4) = '1' then
Bus2IIC_WrCE(4) = '1' then
adr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else
adr_i <= adr_i;
end if;
end if;
end process ADDRESS_REGISTER_PROCESS;
Adr <= adr_i;
--PER_BIT_0_TO_31_GEN : for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
-- BIT_0_TO_31_LOOP : process (rback_data, Bus2IIC_RdCE) is
-- begin
-- if (or_reduce(Bus2IIC_RdCE) = '1') then
-- for m in 0 to C_NUM_IIC_REGS-1 loop
-- if (Bus2IIC_RdCE(m) = '1') then
-- IIC2Bus_Data(i) <= rback_data(m*32 + i);
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end loop;
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end process BIT_0_TO_31_LOOP;
--end generate PER_BIT_0_TO_31_GEN;
OUTPUT_DATA_GEN_P : process (rback_data, Bus2IIC_RdCE, Bus2IIC_Addr) is
begin
if (or_reduce(Bus2IIC_RdCE) = '1') then
--IIC2Bus_Data <= rback_data((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))
-- to ((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))+31)); -- CR
--case Bus2IIC_Addr(C_S_AXI_ADDR_WIDTH-8 to C_S_AXI_ADDR_WIDTH-1) is
case Bus2IIC_Addr(1 to 8) is
when X"00" => IIC2Bus_Data <= rback_data(0 to 31); -- CR
when X"04" => IIC2Bus_Data <= rback_data(32 to 63); -- SR
when X"08" => IIC2Bus_Data <= rback_data(64 to 95); -- TX_FIFO
when X"0C" => IIC2Bus_Data <= rback_data(96 to 127); -- RX_FIFO
when X"10" => IIC2Bus_Data <= rback_data(128 to 159); -- ADR
when X"14" => IIC2Bus_Data <= rback_data(160 to 191); -- TX_FIFO_OCY
when X"18" => IIC2Bus_Data <= rback_data(192 to 223); -- RX_FIFO_OCY
when X"1C" => IIC2Bus_Data <= rback_data(224 to 255); -- TEN_ADR
when X"20" => IIC2Bus_Data <= rback_data(256 to 287); -- RX_FIFO_PIRQ
when X"24" => IIC2Bus_Data <= rback_data(288 to 319); -- GPO
when X"28" => IIC2Bus_Data <= rback_data(320 to 351); -- TSUSTA
when X"2C" => IIC2Bus_Data <= rback_data(352 to 383); -- TSUSTO
when X"30" => IIC2Bus_Data <= rback_data(384 to 415); -- THDSTA
when X"34" => IIC2Bus_Data <= rback_data(416 to 447); -- TSUDAT
when X"38" => IIC2Bus_Data <= rback_data(448 to 479); -- TBUF
when X"3C" => IIC2Bus_Data <= rback_data(480 to 511); -- THIGH
when X"40" => IIC2Bus_Data <= rback_data(512 to 543); -- TLOW
when X"44" => IIC2Bus_Data <= rback_data(544 to 575); -- THDDAT
when others => IIC2Bus_Data <= (others => '0');
end case;
else
IIC2Bus_Data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
----------------------------------------------------------------------------
-- READ_REGISTER_PROCESS
----------------------------------------------------------------------------
rback_data(32*1-8 to 32*1-1) <= cr_i(0 to 7);
rback_data(32*2-9 to 32*2-1) <= '0' & sr_i(0 to 7);--reg_empty & sr_i(0 to 7);
rback_data(32*3-8 to 32*3-1) <= dtr_i(0 to 7);
rback_data(32*4-8 to 32*4-1) <= drr_i(0 to 7);
rback_data(32*5-8 to 32*5-2) <= adr_i(0 to 6);
rback_data(32*6-8 to 32*6-1) <= rtx_i(0 to 7);
rback_data(32*7-8 to 32*7-1) <= rrc_i(0 to 7);
rback_data(32*8-8 to 32*8-1) <= rtn_i(0 to 7);
rback_data(32*9-8 to 32*9-1) <= rpq_i(0 to 7);
----------------------------------------------------------------------------
-- GPO_RBACK_GEN generate
----------------------------------------------------------------------------
GPO_RBACK_GEN : if C_GPO_WIDTH /= 0 generate
rback_data(32*10-C_GPO_WIDTH to 32*10-1)
<= gpo_i(32 - C_GPO_WIDTH to C_S_AXI_DATA_WIDTH - 1);
end generate GPO_RBACK_GEN;
rback_data(32*11-C_SIZE to 32*11-1) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
rback_data(32*12-C_SIZE to 32*12-1) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
rback_data(32*13-C_SIZE to 32*13-1) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
rback_data(32*14-C_SIZE to 32*14-1) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
rback_data(32*15-C_SIZE to 32*15-1) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
rback_data(32*16-C_SIZE to 32*16-1) <= timing_param_thigh_i(C_SIZE-1 downto 0);
rback_data(32*17-C_SIZE to 32*17-1) <= timing_param_tlow_i(C_SIZE-1 downto 0);
rback_data(32*18-C_SIZE to 32*18-1) <= timing_param_thddat_i(C_SIZE-1 downto 0);
rtx_i(0 to 3) <= (others => '0');
rtx_i(4) <= Tx_addr(3);
rtx_i(5) <= Tx_addr(2);
rtx_i(6) <= Tx_addr(1);
rtx_i(7) <= Tx_addr(0);
rrc_i(0 to 3) <= (others => '0');
rrc_i(4) <= Rc_addr(3);
rrc_i(5) <= Rc_addr(2);
rrc_i(6) <= Rc_addr(1);
rrc_i(7) <= Rc_addr(0);
rtn_i(0 to 4) <= (others => '0');
rtn_i(5 to 7) <= ten_adr_i(5 to 7);
rpq_i(0 to 3) <= (others => '0');
rpq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
----------------------------------------------------------------------------
-- Interrupts
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
INT_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(0 to 6) <= (others => '0');
else
IIC2Bus_IntrEvent(0) <= Al; -- arbitration lost interrupt
IIC2Bus_IntrEvent(1) <= Txer; -- transmit error interrupt
IIC2Bus_IntrEvent(2) <= Tx_under_prev; --dtre_i;
-- Data Tx Register Empty interrupt
IIC2Bus_IntrEvent(3) <= ro_prev_i; --New_rcv_dta;
-- Data Rc Register Full interrupt
IIC2Bus_IntrEvent(4) <= not Bb;
IIC2Bus_IntrEvent(5) <= Aas;
IIC2Bus_IntrEvent(6) <= not Aas;
end if;
end if;
end process INT_PROCESS;
----------------------------------------------------------------------------
-- Ten Bit Slave Address Generate
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
TEN_ADR_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- TEN_ADR_REGISTER_PROCESS
-------------------------------------------------------------------------
TEN_ADR_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ten_adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(7) = '1' then
ten_adr_i(5 to 7) <= Bus2IIC_Data(29 to 31);
else
ten_adr_i <= ten_adr_i;
end if;
end if;
end process TEN_ADR_REGISTER_PROCESS;
Ten_adr <= ten_adr_i;
end generate TEN_ADR_GEN;
----------------------------------------------------------------------------
-- General Purpose Ouput Register Generate
----------------------------------------------------------------------------
-- Generate the GPO if C_GPO_WIDTH is not equal to zero
----------------------------------------------------------------------------
GPO_GEN : if (C_GPO_WIDTH /= 0) generate
-------------------------------------------------------------------------
-- GPO_REGISTER_PROCESS
-------------------------------------------------------------------------
GPO_REGISTER_PROCESS : process (Clk)
begin -- process
if Clk'event and Clk = '1' then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
gpo_i <= C_DEFAULT_VALUE(C_GPO_WIDTH - 1 downto 0);
elsif -- Load Status Register with AXI
-- data if there is a write CE
--Bus2IIC_WrCE(C_NUM_IIC_REGS - 1) = '1' then
Bus2IIC_WrCE(9) = '1' then
gpo_i(32 - C_GPO_WIDTH to 31) <=
Bus2IIC_Data(32 - C_GPO_WIDTH to 31);
else
gpo_i <= gpo_i;
end if;
end if;
end process GPO_REGISTER_PROCESS;
Gpo <= gpo_i;
end generate GPO_GEN;
----------------------------------------------------------------------------
-- TSUSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusta register is enabled.
----------------------------------------------------------------------------
TSUSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
--timing_param_tsusta_i <= (others => '0');
timing_param_tsusta_i <= TSUSTA;
elsif -- Load tsusta Register with AXI
-- data if there is a write request
-- and the tsusta register is enabled
Bus2IIC_WrCE(10) = '1' then
timing_param_tsusta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusta_i(C_SIZE-1 downto 0) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTA_REGISTER_PROCESS;
Timing_param_tsusta <= timing_param_tsusta_i;
----------------------------------------------------------------------------
-- TSUSTO_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusto register is enabled.
----------------------------------------------------------------------------
TSUSTO_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
--timing_param_tsusto_i <= (others => '0');
timing_param_tsusto_i <= TSUSTO;
elsif -- Load tsusto Register with AXI
-- data if there is a write request
-- and the tsusto register is enabled
Bus2IIC_WrCE(11) = '1' then
timing_param_tsusto_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusto_i(C_SIZE-1 downto 0) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTO_REGISTER_PROCESS;
Timing_param_tsusto <= timing_param_tsusto_i;
----------------------------------------------------------------------------
-- THDSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
THDSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thdsta_i <= THDSTA;
elsif -- Load thdsta Register with AXI
-- data if there is a write request
-- and the thdsta register is enabled
Bus2IIC_WrCE(12) = '1' then
timing_param_thdsta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thdsta_i(C_SIZE-1 downto 0) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDSTA_REGISTER_PROCESS;
Timing_param_thdsta <= timing_param_thdsta_i;
----------------------------------------------------------------------------
-- TSUDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
TSUDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tsudat_i <= TSUDAT;
elsif -- Load tsudat Register with AXI
-- data if there is a write request
-- and the tsudat register is enabled
Bus2IIC_WrCE(13) = '1' then
timing_param_tsudat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsudat_i(C_SIZE-1 downto 0) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUDAT_REGISTER_PROCESS;
Timing_param_tsudat <= timing_param_tsudat_i;
----------------------------------------------------------------------------
-- TBUF_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tbuf register is enabled.
----------------------------------------------------------------------------
TBUF_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tbuf_i <= TBUF;
elsif -- Load tbuf Register with AXI
-- data if there is a write request
-- and the tbuf register is enabled
Bus2IIC_WrCE(14) = '1' then
timing_param_tbuf_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tbuf_i(C_SIZE-1 downto 0) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
end if;
end if;
end process TBUF_REGISTER_PROCESS;
Timing_param_tbuf <= timing_param_tbuf_i;
----------------------------------------------------------------------------
-- THIGH_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
THIGH_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thigh_i <= HIGH_CNT;
elsif -- Load thigh Register with AXI
-- data if there is a write request
-- and the thigh register is enabled
Bus2IIC_WrCE(15) = '1' then
timing_param_thigh_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thigh_i(C_SIZE-1 downto 0) <= timing_param_thigh_i(C_SIZE-1 downto 0);
end if;
end if;
end process THIGH_REGISTER_PROCESS;
Timing_param_thigh <= timing_param_thigh_i;
----------------------------------------------------------------------------
-- TLOW_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
TLOW_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tlow_i <= LOW_CNT;
elsif -- Load tlow Register with AXI
-- data if there is a write request
-- and the tlow register is enabled
Bus2IIC_WrCE(16) = '1' then
timing_param_tlow_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tlow_i(C_SIZE-1 downto 0) <= timing_param_tlow_i(C_SIZE-1 downto 0);
end if;
end if;
end process TLOW_REGISTER_PROCESS;
Timing_param_tlow <= timing_param_tlow_i;
----------------------------------------------------------------------------
-- THDDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thddat register is enabled.
----------------------------------------------------------------------------
THDDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thddat_i <= THDDAT;
elsif -- Load thddat Register with AXI
-- data if there is a write request
-- and the thddat register is enabled
Bus2IIC_WrCE(17) = '1' then
timing_param_thddat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thddat_i(C_SIZE-1 downto 0) <= timing_param_thddat_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDDAT_REGISTER_PROCESS;
Timing_param_thddat <= timing_param_thddat_i;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic_control.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_control.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the main state machines for the iic
-- bus interface logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
use axi_iic_v2_0_14.upcnt_n;
use axi_iic_v2_0_14.shift8;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_ACLK_FREQ_HZ-- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum IIC frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
--
-- Definition of Ports:
-- Sys_clk -- System clock
-- Reset -- System Reset
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Txak -- Value for acknowledge when xmit
-- Gc_en -- General purpose outputs
-- Ro_prev -- Receive over run prevent
-- Dtre -- Data transmit register empty
-- Msms -- Data transmit register empty
-- Msms_rst -- Msms Reset signal
-- Msms_set -- Msms set
-- Rsta -- Repeated start
-- Rsta_rst -- Repeated start Reset
-- Tx -- Master read/write
-- Dtr -- Data transmit register
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Bb -- Bus busy indicator
-- Dtc -- Data transfer
-- Aas -- Addressed as slave indicator
-- Al -- Arbitration lost indicator
-- Srw -- Slave read/write indicator
-- Txer -- Received acknowledge indicator
-- Abgc -- Addressed by general call indicator
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- EarlyAckHdr -- ACK_HEADER state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- AckDataState -- Data ack acknowledge signal
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic_control is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SIZE : integer := 32;
C_TEN_BIT_ADR : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0 -- SMBUS/PMBUS support
);
port(
-- System signals
Sys_clk : in std_logic;
Reset : in std_logic;
-- iic bus tristate driver control signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Timing_param_tsusta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : in std_logic_vector(C_SIZE-1 downto 0);
-- interface signals from uP
Txak : in std_logic;
Gc_en : in std_logic;
Ro_prev : in std_logic;
Dtre : in std_logic;
Msms : in std_logic;
Msms_rst : out std_logic;
Msms_set : in std_logic;
Rsta : in std_logic;
Rsta_rst : out std_logic;
Tx : in std_logic;
Dtr : in std_logic_vector(7 downto 0);
Adr : in std_logic_vector(7 downto 0);
Ten_adr : in std_logic_vector(7 downto 5);
Bb : out std_logic;
Dtc : out std_logic;
Aas : out std_logic;
Al : out std_logic;
Srw : out std_logic;
Txer : out std_logic;
Abgc : out std_logic;
Data_i2c : out std_logic_vector(7 downto 0);
New_rcv_dta : out std_logic;
Rdy_new_xmt : out std_logic;
Tx_under_prev : out std_logic;
EarlyAckHdr : out std_logic;
EarlyAckDataState : out std_logic;
AckDataState : out std_logic;
reg_empty :out std_logic
);
end iic_control;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic_control is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Bus free time.
constant CLR_REG : std_logic_vector(7 downto 0) := "00000000";
constant START_CNT : std_logic_vector(3 downto 0) := "0000";
constant CNT_DONE : std_logic_vector(3 downto 0) := "1000";
constant ZERO_CNT : std_logic_vector(C_SIZE-1 downto 0):= (others => '0');
constant ZERO : std_logic := '0';
constant ENABLE_N : std_logic := '0';
constant CNT_ALMOST_DONE : std_logic_vector (3 downto 0) := "0111";
type state_type is (IDLE,
HEADER,
ACK_HEADER,
RCV_DATA,
ACK_DATA,
XMIT_DATA,
WAIT_ACK);
signal state : state_type;
type scl_state_type is (SCL_IDLE,
START_WAIT,
START,
START_EDGE,
SCL_LOW_EDGE,
SCL_LOW,
SCL_HIGH_EDGE,
SCL_HIGH,
STOP_EDGE,
STOP_WAIT);
signal scl_state : scl_state_type;
signal next_scl_state : scl_state_type;
signal scl_rin : std_logic; -- sampled version of scl
signal scl_d1 : std_logic; -- sampled version of scl
signal scl_rin_d1 : std_logic; -- delayed version of Scl_rin
signal scl_cout : std_logic; -- combinatorial scl output
signal scl_cout_reg : std_logic; -- registered version of scl_cout
signal scl_rising_edge : std_logic; -- falling edge of SCL
signal scl_falling_edge : std_logic; -- falling edge of SCL
signal scl_f_edg_d1 : std_logic; -- falling edge of SCL delayed one
-- clock
signal scl_f_edg_d2 : std_logic; -- falling edge of SCL delayed two
-- clock
signal scl_f_edg_d3 : std_logic; -- falling edge of SCL delayed three
-- clock
signal sda_rin : std_logic; -- sampled version of sda
signal sda_d1 : std_logic; -- sampled version of sda
signal sda_rin_d1 : std_logic; -- delayed version of sda_rin
signal sda_falling : std_logic; -- Pulses when SDA falls
signal sda_rising : std_logic; -- Pulses when SDA rises
signal sda_changing : std_logic; -- Pulses when SDA changes
signal sda_setup : std_logic; -- SDA setup time in progress
signal sda_setup_cnt : std_logic_vector (C_SIZE-1 downto 0);
-- SDA setup time count
signal sda_cout : std_logic; -- combinatorial sda output
signal sda_cout_reg : std_logic; -- registered version of sda_cout
signal sda_cout_reg_d1 : std_logic; -- delayed sda output for arb
-- comparison
signal sda_sample : std_logic; -- SDA_RIN sampled at SCL rising edge
signal slave_sda : std_logic; -- sda value when slave
signal master_sda : std_logic; -- sda value when master
signal sda_oe : std_logic;
signal master_slave : std_logic; -- 1 if master, 0 if slave
-- Shift Register and the controls
signal shift_reg : std_logic_vector(7 downto 0); -- iic data shift reg
signal shift_out : std_logic;
signal shift_reg_en : std_logic;
signal shift_reg_ld : std_logic;
signal shift_reg_ld_d1 : std_logic;
signal i2c_header : std_logic_vector(7 downto 0);-- I2C header register
signal i2c_header_en : std_logic;
signal i2c_header_ld : std_logic;
signal i2c_shiftout : std_logic;
-- Used to check slave address detected
signal addr_match : std_logic;
signal arb_lost : std_logic; -- 1 if arbitration is lost
signal msms_d1 : std_logic; -- Msms processed to initiate a stop
-- sequence after data has been transmitted
signal msms_d2 : std_logic; -- delayed sample of msms_d1
signal msms_rst_i : std_logic; -- internal msms_rst
signal detect_start : std_logic; -- START condition has been detected
signal detect_stop : std_logic; -- STOP condition has been detected
signal detect_stop_b: std_logic;
signal sm_stop : std_logic; -- STOP condition needs to be generated
-- from state machine
signal bus_busy : std_logic; -- indicates that the bus is busy
-- set when START, cleared when STOP
signal bus_busy_d1 : std_logic; -- delayed sample of bus busy
signal gen_start : std_logic; -- uP wants to generate a START
signal gen_stop : std_logic; -- uP wants to generate a STOP
signal rep_start : std_logic; -- uP wants to generate a repeated START
signal stop_scl : std_logic; -- signal in SCL state machine
-- indicating a STOP
signal stop_scl_reg : std_logic; -- registered version of STOP_SCL
-- Bit counter 0 to 7
signal bit_cnt : std_logic_vector(3 downto 0);
signal bit_cnt_ld : std_logic;
signal bit_cnt_clr : std_logic;
signal bit_cnt_en : std_logic;
-- Clock Counter
signal clk_cnt : std_logic_vector (C_SIZE-1 downto 0);
signal clk_cnt_rst : std_logic;
signal clk_cnt_en : std_logic;
signal stop_start_wait : std_logic;
-- the following signals are only here because Viewlogic's VHDL compiler won't
-- allow a constant to be used in a component instantiation
signal reg_clr : std_logic_vector(7 downto 0);
signal zero_sig : std_logic;
signal cnt_zero : std_logic_vector(C_SIZE-1 downto 0);
signal cnt_start : std_logic_vector(3 downto 0);
signal data_i2c_i : std_logic_vector(7 downto 0);
signal aas_i : std_logic; -- internal addressed as slave
-- signal
signal srw_i : std_logic; -- internal slave read write signal
signal abgc_i : std_logic; -- internal addressed by a general
-- call
signal dtc_i : std_logic; -- internal data transmit compete
-- signal
signal dtc_i_d1 : std_logic; -- delayed internal data transmit
-- complete
signal dtc_i_d2 : std_logic; -- 2nd register delay of dtc
signal al_i : std_logic; -- internal arbitration lost signal
signal al_prevent : std_logic; -- prevent arbitration lost when
-- last word
signal rdy_new_xmt_i : std_logic; -- internal ready to transmit new
-- data
signal tx_under_prev_i : std_logic; -- TX underflow prevent signal
signal rsta_tx_under_prev : std_logic; -- Repeated Start Tx underflow
-- prevent
signal rsta_d1 : std_logic; -- Delayed one clock version of Rsta
signal dtre_d1 : std_logic; -- Delayed one clock version of Dtre
signal txer_i : std_logic; -- internal Txer signal
signal txer_edge : std_logic; -- Pulse for Txer IRQ
-- the following signal are used only when 10-bit addressing has been
-- selected
signal msb_wr : std_logic; -- the 1st byte of 10 bit addressing
-- comp
signal msb_wr_d : std_logic; -- delayed version of msb_wr
signal msb_wr_d1 : std_logic; -- delayed version of msb_wr_d
signal sec_addr : std_logic := '0'; -- 2nd byte qualifier
signal sec_adr_match : std_logic; -- 2nd byte compare
signal adr_dta_l : std_logic := '0'; -- prevents 2nd adr byte load
-- in DRR
signal new_rcv_dta_i : std_logic; -- internal New_rcv_dta
signal ro_prev_d1 : std_logic; -- delayed version of Ro_prev
signal gen_stop_and_scl_hi : std_logic; -- signal to prevent SCL state
-- machine from getting stuck during a No Ack
signal setup_cnt_rst : std_logic;
signal tx_under_prev_d1 : std_logic;
signal tx_under_prev_fe : std_logic;
signal rsta_re : std_logic;
signal gen_stop_d1 : std_logic;
signal gen_stop_re : std_logic;
----Mathew
signal shift_cnt : std_logic_vector(8 downto 0);
-- signal reg_empty : std_logic;
----------
begin
----------------------------------------------------------------------------
-- SCL Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Scl_T <= '0' when scl_cout_reg = '0'
-- Receive fifo overflow throttle condition
or Ro_prev = '1'
-- SDA changing requires additional setup to SCL change
or (sda_setup = '1' )
-- Restart w/ transmit underflow prevention throttle
-- condition
or rsta_tx_under_prev = '1' else
'1';
Scl_O <= '0';
----------------------------------------------------------------------------
-- SDA Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Sda_T <= '0' when ((master_slave = '1' and arb_lost = '0'
and sda_cout_reg = '0')
or (master_slave = '0' and slave_sda = '0')
or stop_scl_reg = '1') else
'1';
Sda_O <= '0';
-- the following signals are only here because Viewlogic's VHDL compiler
-- won't allow a constant to be used in a component instantiation
reg_clr <= CLR_REG;
zero_sig <= ZERO;
cnt_zero <= ZERO_CNT;
cnt_start <= START_CNT;
----------------------------------------------------------------------------
-- INT_DTRE_RSTA_DELAY_PROCESS
----------------------------------------------------------------------------
-- This process delays Dtre and RSTA by one clock to edge detect
-- Dtre = data transmit register empty
-- Rsta = firmware restart command
----------------------------------------------------------------------------
INT_DTRE_RSTA_DELAY_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_d1 <= '0';
dtre_d1 <= '0';
ro_prev_d1 <= '0';
gen_stop_d1 <= '0';
tx_under_prev_d1 <= '0';
else
rsta_d1 <= Rsta;
dtre_d1 <= Dtre;
ro_prev_d1 <= Ro_prev;
gen_stop_d1 <= gen_stop;
tx_under_prev_d1 <= tx_under_prev_i;
end if;
end if;
end process INT_DTRE_RSTA_DELAY_PROCESS;
tx_under_prev_fe <= tx_under_prev_d1 and not tx_under_prev_i;
rsta_re <= Rsta and not rsta_d1 ;
gen_stop_re <= gen_stop and not gen_stop_d1;
----------------------------------------------------------------------------
-- INT_RSTA_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused, by a repeated start condition.
----------------------------------------------------------------------------
INT_RSTA_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_tx_under_prev <= '0';
elsif (Rsta = '1' and rsta_d1 = '0' and Dtre = '1' ) then
rsta_tx_under_prev <= '1';
elsif (Dtre = '0' and dtre_d1 = '1') then
rsta_tx_under_prev <= '0';
else
rsta_tx_under_prev <= rsta_tx_under_prev;
end if;
end if;
end process INT_RSTA_TX_UNDER_PREV_PROCESS;
----------------------------------------------------------------------------
-- INT_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused. Transmit underflow can occur in both
-- master and slave situations
----------------------------------------------------------------------------
INT_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
tx_under_prev_i <= '0';
elsif (Dtre = '1' and (state = WAIT_ACK or state = ACK_HEADER)
and scl_falling_edge = '1' and gen_stop = '0'
and ((aas_i = '0' and srw_i = '0')
or (aas_i = '1' and srw_i = '1'))) then
tx_under_prev_i <= '1';
elsif (state = RCV_DATA or state = IDLE or Dtre='0') then
tx_under_prev_i <= '0';
end if;
end if;
end process INT_TX_UNDER_PREV_PROCESS;
Tx_under_prev <= tx_under_prev_i;
----------------------------------------------------------------------------
-- SDASETUP
----------------------------------------------------------------------------
-- Whenever SDA changes there is an associated setup time that must be
-- obeyed before SCL can change. (The exceptions are starts/stops which
-- haven't other timing specifications.) It doesn't matter whether this is
-- a Slave | Master, TX | RX. The "setup" counter and the "sdasetup" process
-- guarantee this time is met regardless of the devices on the bus and their
-- attempts to manage setup time. The signal sda_setup, when asserted,
-- causes SCL to be held low until the setup condition is removed. Anytime a
-- change in SDA is detected on the bus the setup process is invoked. Also,
-- sda_setup is asserted if the transmit throttle condition is active.
-- When it deactivates, SDA **may** change on the SDA bus. In this way,
-- the SCL_STATE machine will be held off as well because it waits for SCL
-- to actually go high.
----------------------------------------------------------------------------
SETUP_CNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => sda_setup,
Load => sda_changing,
Qout => sda_setup_cnt
);
----------------------------------------------------------------------------
-- SDASETUP Process
----------------------------------------------------------------------------
SDASETUP : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_setup <= '0';
elsif (
-- If SDA is changing on the bus then enforce setup time
sda_changing = '1'
-- or if SDA is about to change ...
or tx_under_prev_i = '1') -- modified
-- For either of the above cases the controller only cares
-- about SDA setup when it is legal to change SDA.
and scl_rin='0' then
sda_setup <= '1';
elsif (sda_setup_cnt=Timing_param_tsudat) then
sda_setup <= '0';
end if;
end if;
end process SDASETUP;
----------------------------------------------------------------------------
-- Arbitration Process
-- This process checks the master's outgoing SDA with the incoming SDA to
-- determine if control of the bus has been lost. SDA is checked only when
-- SCL is high and during the states HEADER and XMIT_DATA (when data is
-- actively being clocked out of the controller). When arbitration is lost,
-- a Reset is generated for the Msms bit per the product spec.
-- Note that when arbitration is lost, the mode is switched to slave.
-- arb_lost stays set until scl state machine goes to IDLE state
----------------------------------------------------------------------------
ARBITRATION : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
arb_lost <= '0';
msms_rst_i <= '0';
elsif scl_state = SCL_IDLE or scl_state = STOP_WAIT then
arb_lost <= '0';
msms_rst_i <= '0';
elsif (master_slave = '1') then
-- Actively generating SCL clock as the master and (possibly)
-- participating in multi-master arbitration.
if (scl_rising_edge='1'
and (state = HEADER or state = XMIT_DATA)) then
if (sda_cout_reg='1' and sda_rin = '0') then
-- Other master drove SDA to 0 but the controller is trying
-- to drive a 1. That is the exact case for loss of
-- arbitration
arb_lost <= '1';
msms_rst_i <= '1';
else
arb_lost <= '0';
msms_rst_i <= '0';
end if;
else
msms_rst_i <= '0';
end if;
end if;
end if;
end process ARBITRATION;
Msms_rst <= msms_rst_i
-- The spec states that the Msms bit should be cleared when an
-- address is not-acknowledged. The sm_stop indicates that
-- a not-acknowledge occured on either a data or address
-- (header) transfer. This fixes CR439859.
or sm_stop;
----------------------------------------------------------------------------
-- SCL_GENERATOR_COMB Process
-- This process generates SCL and SDA when in Master mode. It generates the
-- START and STOP conditions. If arbitration is lost, SCL will not be
-- generated until the end of the byte transfer.
----------------------------------------------------------------------------
SCL_GENERATOR_COMB : process (
scl_state,
arb_lost,
sm_stop,
gen_stop,
rep_start,
bus_busy,
gen_start,
master_slave,
stop_scl_reg,
clk_cnt,
scl_rin,
sda_rin,
state,
sda_cout_reg,
master_sda,
detect_stop_b,
stop_start_wait,
Timing_param_tsusta,
Timing_param_tsusto,
Timing_param_thdsta,
Timing_param_thddat,
Timing_param_tbuf,
Timing_param_tlow,
Timing_param_thigh
)
begin
-- state machine defaults
scl_cout <= '1';
sda_cout <= sda_cout_reg;
stop_scl <= stop_scl_reg;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
next_scl_state <= scl_state;
Rsta_rst <= (ENABLE_N);
stop_start_wait <= detect_stop_b;
case scl_state is
when SCL_IDLE =>
sda_cout <= '1';
stop_scl <= '0';
clk_cnt_en <= detect_stop_b;
clk_cnt_rst <= not(detect_stop_b);
stop_start_wait <= detect_stop_b;
if clk_cnt = Timing_param_tbuf then
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
stop_start_wait <= '0';
end if;
-- leave IDLE state when master, bus is idle, and gen_start
if master_slave = '1' and bus_busy = '0' and gen_start = '1' then
if stop_start_wait = '1' then
next_scl_state <= START_WAIT;
else
next_scl_state <= START;
end if;
else
next_scl_state <= SCL_IDLE;
end if;
when START_WAIT =>
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
stop_scl <= '0';
if clk_cnt = Timing_param_tbuf then
next_scl_state <= START;
stop_start_wait <= '0';
else
next_scl_state <= START_WAIT;
end if;
when START =>
-- generate start condition
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
sda_cout <= '0';
stop_scl <= '0';
if sda_rin='0' then
next_scl_state <= START_EDGE;
else
next_scl_state <= START;
end if;
when START_EDGE =>
-- This state ensures that the hold time for the (repeated) start
-- condition is met. The hold time is measured from the Vih level
-- of SDA so it is critical for SDA to be sampled low prior to
-- starting the hold time counter.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
-- generate Reset for repeat start bit if repeat start condition
if rep_start = '1' then
Rsta_rst <= not(ENABLE_N);
end if;
if clk_cnt = Timing_param_thdsta then
next_scl_state <= SCL_LOW_EDGE;
else
next_scl_state <= START_EDGE;
end if;
when SCL_LOW_EDGE =>
clk_cnt_rst <= '1';
scl_cout <= '0';
stop_scl <= '0';
if (scl_rin='0') then
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
end if;
if ((scl_rin = '0') and (clk_cnt = Timing_param_thddat)) then
-- SCL sampled to be 0 so everything on the bus can see that it
-- is low too. The very large propagation delays caused by
-- potentially large (~300ns or more) fall time should not be
-- ignored by the controller.It must VERIFY that the bus is low.
next_scl_state <= SCL_LOW;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
else
next_scl_state <= SCL_LOW_EDGE;
end if;
when SCL_LOW =>
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '0';
stop_scl <= '0';
-- SDA (the data) can only be changed when SCL is low. Note that
-- STOPS and RESTARTS could appear after the SCL low period
-- has expired because the controller is throttled.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- Pull SDA low in anticipation of raising it to generate the
-- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Wait until minimum low clock period requirement is met then
-- proceed to release the SCL_COUT so that it is "possible" for the
-- scl clock to go high on the bus. Note that a SLAVE device can
-- continue to hold SCL low to throttle the bus OR the master
-- itself may hold SCL low because of an internal throttle
-- condition.
if clk_cnt = Timing_param_tlow then
next_scl_state <= SCL_HIGH_EDGE;
else
next_scl_state <= SCL_LOW;
end if;
when SCL_HIGH_EDGE =>
clk_cnt_rst <= '1';
stop_scl <= '0';
-- SCL low time met. Try to release SCL to make it go high.
scl_cout <= '1';
-- SDA (the data) can only be changed when SCL is low. In this
-- state the fsm wants to change SCL to high and is waiting to see
-- it go high. However, other processes may be inhibiting SCL from
-- going high because the controller is throttled. While throttled,
-- and scl is still low:
-- (1) a STOP may be requested by the firmware, **OR**
-- (2) a RESTART may be requested (with or without data available)
-- by the firmware, **OR**
-- (3) new data may get loaded into the TX_FIFO and the first bit
-- is available to be loaded onto the SDA pin
-- Removed this condition as sda_cout should not go low when
-- SCL goes high. SDA should be changed in SCL_LOW state.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- -- Pull SDA low in anticipation of raising it to generate the
-- -- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
--if stop_scl_reg = '1' then
-- stop_scl <= '1';
-- sda_cout <= '0';
--elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Nothing in the controller should
-- a) sample SDA_RIN until the controller actually verifies that
-- SCL has gone high, and
-- b) change SDA_COUT given that it is trying to change SCL now.
-- Note that other processes may inhibit SCL from going high to
-- wait for the transmit data register to be filled with data. In
-- that case data setup requirements imposed by the I2C spec must
-- be satisfied. Regardless, the SCL clock generator can wait here
-- in SCL_HIGH_EDGE until that is accomplished.
if (scl_rin='1') then
next_scl_state <= SCL_HIGH;
else
next_scl_state <= SCL_HIGH_EDGE;
end if;
when SCL_HIGH =>
-- SCL is now high (released) on the external bus. At this point
-- the state machine doesn't have to worry about any throttle
-- conditions -- by definition they are removed as SCL is no longer
-- low. The firmware **must** signal the desire to STOP or Repeat
-- Start when throttled.
-- It is decision time. Should another SCL clock pulse get
-- generated? (IE a low period + high period?) The answer depends
-- on whether the previous clock was a DATA XFER clock or an ACK
-- CLOCK. Should a Repeated Start be generated? Should a STOP be
-- generated?
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '1';
if (arb_lost='1') then
-- No point in continuing! The other master will generate the
-- clock.
next_scl_state <= SCL_IDLE;
else
-- Determine HIGH time based on need to generate a repeated
-- start, a stop or the full high period of the SCL clock.
-- (Without some analysis it isn't clear if rep_start and
-- stop_scl_reg are mutually exclusive. Hence the priority
-- encoder.)
if rep_start = '1' then
if (clk_cnt=Timing_param_tsusta) then
-- The hidden assumption here is that SDA has been released
-- by the slave|master receiver after the ACK clock so that
-- a repeated start is possible
next_scl_state <= START;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
end if;
elsif stop_scl_reg = '1' then
if (clk_cnt=Timing_param_tsusto) then
-- The hidden assumption here is that SDA has been pulled
-- low by the master after the ACK clock so that a
-- stop is possible
next_scl_state <= STOP_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
sda_cout <= '1'; -- issue the stop
stop_scl <= '0';
end if;
else
-- Neither repeated start nor stop requested
if clk_cnt= Timing_param_thigh then
next_scl_state <= SCL_LOW_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
end if;
end if;
end if;
when STOP_EDGE =>
if (sda_rin='1') then
next_scl_state <= STOP_WAIT;
else
next_scl_state <= STOP_EDGE;
end if;
when STOP_WAIT =>
-- The Stop setup time was satisfied and SDA was sampled high
-- indicating the stop occured. Now wait the TBUF time required
-- between a stop and the next start.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
stop_scl <= '0';
if clk_cnt = Timing_param_tbuf then
next_scl_state <= SCL_IDLE;
else
next_scl_state <= STOP_WAIT;
end if;
-- coverage off
when others =>
next_scl_state <= SCL_IDLE;
-- coverage on
end case;
end process SCL_GENERATOR_COMB;
----------------------------------------------------------------------------
--PROCESS : SCL_GENERATOR_REGS
----------------------------------------------------------------------------
SCL_GENERATOR_REGS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_state <= SCL_IDLE;
sda_cout_reg <= '1';
scl_cout_reg <= '1';
stop_scl_reg <= '0';
else
scl_state <= next_scl_state;
sda_cout_reg <= sda_cout;
-- Ro_prev = receive overflow prevent = case where controller must
-- hold SCL low itself until receive fifo is emptied by the firmware
scl_cout_reg <= scl_cout and not Ro_prev;
stop_scl_reg <= stop_scl;
end if;
end if;
end process SCL_GENERATOR_REGS;
----------------------------------------------------------------------------
-- Clock Counter Implementation
-- The following code implements the counter that divides the sys_clock for
-- creation of SCL. Control lines for this counter are set in SCL state
-- machine
----------------------------------------------------------------------------
CLKCNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => clk_cnt_en,
Load => clk_cnt_rst,
Qout => clk_cnt
);
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
sda_rin <= Sda_I;
scl_rin <= Scl_I;
INPUT_REGS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
sda_rin_d1 <= sda_rin; -- delay sda_rin to find edges
scl_rin_d1 <= scl_rin; -- delay Scl_rin to find edges
sda_cout_reg_d1 <= sda_cout_reg;
end if;
end process INPUT_REGS;
----------------------------------------------------------------------------
-- Master Slave Mode Select Process
-- This process allows software to write the value of Msms with each data
-- word to be transmitted. So writing a '0' to Msms will initiate a stop
-- sequence on the I2C bus after the that byte in the DTR has been sent.
----------------------------------------------------------------------------
MSMS_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msms_d1 <= '0';
msms_d2 <= '0';
else
msms_d1 <= (Msms and not msms_rst_i)
or ((msms_d1 and not (dtc_i_d1 and not dtc_i_d2) and
not msms_rst_i)
and not Msms_set and not txer_i) ;
msms_d2 <= msms_d1;
end if;
end if;
end process MSMS_PROCESS;
----------------------------------------------------------------------------
-- START/STOP Detect Process
-- This process detects the start condition by finding the falling edge of
-- sda_rin and checking that SCL is high. It detects the stop condition on
-- the bus by finding a rising edge of SDA when SCL is high.
----------------------------------------------------------------------------
sda_falling <= sda_rin_d1 and not sda_rin;
sda_rising <= not sda_rin_d1 and sda_rin;
sda_changing <= sda_falling or sda_rising or tx_under_prev_fe
or rsta_re or gen_stop_re;
----------------------------------------------------------------------------
-- START Detect Process
----------------------------------------------------------------------------
START_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or state = HEADER then
detect_start <= '0';
elsif sda_falling = '1' then
if scl_rin = '1' then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end if;
end process START_DET_PROCESS;
----------------------------------------------------------------------------
-- STOP Detect Process
----------------------------------------------------------------------------
STOP_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_start = '1' then
detect_stop <= '0';
elsif sda_rising = '1' then
if scl_rin = '1' then
detect_stop <= '1';
else
detect_stop <= '0';
end if;
elsif msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
detect_stop <= '0'; -- clear on a generate start condition
end if;
end if;
end process STOP_DET_PROCESS;
STOP_DET_PROCESS_B : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_start = '1' then
detect_stop_b <= '0';
elsif sda_rising = '1' then
if scl_rin = '1' then
detect_stop_b <= '1';
else
detect_stop_b <= '0';
end if;
elsif scl_state = START then
-- rising edge of Msms - generate start condition
detect_stop_b <= '0'; -- clear on a generate start condition
end if;
end if;
end process STOP_DET_PROCESS_B;
----------------------------------------------------------------------------
-- Bus Busy Process
-- This process sets bus_busy as soon as START is detected which would
-- always set arb lost (Al).
----------------------------------------------------------------------------
SET_BUS_BUSY_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy <= '0';
else
if detect_stop = '1' then
bus_busy <= '0';
elsif detect_start = '1' then
bus_busy <= '1';
end if;
end if;
end if;
end process SET_BUS_BUSY_PROCESS;
----------------------------------------------------------------------------
-- BUS_BUSY_REG_PROCESS:
-- This process describes a delayed version of the bus busy bit which is
-- used to determine arb lost (Al).
----------------------------------------------------------------------------
BUS_BUSY_REG_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy_d1 <= '0';
else
bus_busy_d1 <= bus_busy;
end if;
end if;
end process BUS_BUSY_REG_PROCESS;
----------------------------------------------------------------------------
-- GEN_START_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of start condition
----------------------------------------------------------------------------
GEN_START_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_start <= '0';
else
if msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
gen_start <= '1';
elsif detect_start = '1' then
gen_start <= '0';
end if;
end if;
end if;
end process GEN_START_PROCESS;
----------------------------------------------------------------------------
-- GEN_STOP_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of stop condition
----------------------------------------------------------------------------
GEN_STOP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop <= '0';
else
if arb_lost = '0' and msms_d2 = '1' and msms_d1 = '0' then
-- falling edge of Msms - generate stop condition only
-- if arbitration has not been lost
gen_stop <= '1';
elsif detect_stop = '1' then
gen_stop <= '0';
end if;
end if;
end if;
end process GEN_STOP_PROCESS;
----------------------------------------------------------------------------
-- GEN_MASTRE_SLAVE_PROCESS
-- This process sets the master slave bit based on Msms if and only if
-- it is not in the middle of a cycle, i.e. bus_busy = '0'
----------------------------------------------------------------------------
GEN_MASTRE_SLAVE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_slave <= '0';
else
if bus_busy = '0' then
master_slave <= msms_d1;
elsif arb_lost = '1' then
master_slave <= '0';
else
master_slave <= master_slave;
end if;
end if;
end if;
end process GEN_MASTRE_SLAVE_PROCESS;
rep_start <= Rsta; -- repeat start signal is Rsta control bit
----------------------------------------------------------------------------
-- GEN_STOP_AND_SCL_HIGH
----------------------------------------------------------------------------
-- This process does not go high until both gen_stop and SCL have gone high
-- This is used to prevent the SCL state machine from getting stuck when a
-- slave no acks during the last data byte being transmitted
----------------------------------------------------------------------------
GEN_STOP_AND_SCL_HIGH : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop_and_scl_hi <= '0';
elsif gen_stop = '0' then
gen_stop_and_scl_hi <= '0'; --clear
elsif gen_stop = '1' and scl_rin = '1' then
gen_stop_and_scl_hi <= '1';
else
gen_stop_and_scl_hi <= gen_stop_and_scl_hi; --hold condition
end if;
end if;
end process GEN_STOP_AND_SCL_HIGH;
----------------------------------------------------------------------------
-- SCL_EDGE_PROCESS
----------------------------------------------------------------------------
-- This process generates a 1 Sys_clk wide pulse for both the rising edge
-- and the falling edge of SCL_RIN
----------------------------------------------------------------------------
SCL_EDGE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_falling_edge <= '0';
scl_rising_edge <= '0';
scl_f_edg_d1 <= '0';
scl_f_edg_d2 <= '0';
scl_f_edg_d3 <= '0';
else
scl_falling_edge <= scl_rin_d1 and (not scl_rin); -- 1 to 0
scl_rising_edge <= (not scl_rin_d1) and scl_rin; -- 0 to 1
scl_f_edg_d1 <= scl_falling_edge;
scl_f_edg_d2 <= scl_f_edg_d1;
scl_f_edg_d3 <= scl_f_edg_d2;
end if;
end if;
end process SCL_EDGE_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_HDR_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_HEADER state
----------------------------------------------------------------------------
EARLY_ACK_HDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckHdr <= '0';
elsif (scl_f_edg_d3 = '1' and state = ACK_HEADER) then
EarlyAckHdr <= '1';
else
EarlyAckHdr <= '0';
end if;
end if;
end process EARLY_ACK_HDR_PROCESS;
----------------------------------------------------------------------------
-- ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- ACK_DATA state
----------------------------------------------------------------------------
ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
AckDataState <= '0';
elsif (state = ACK_DATA) then
AckDataState <= '1';
else
AckDataState <= '0';
end if;
end if;
end process ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_DATA ot RCV_DATA state state
----------------------------------------------------------------------------
EARLY_ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckDataState <= '0';
elsif (state = ACK_DATA or (state = RCV_DATA and
(bit_cnt = CNT_ALMOST_DONE or bit_cnt = CNT_DONE))) then
EarlyAckDataState <= '1';
else
EarlyAckDataState <= '0';
end if;
end if;
end process EARLY_ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- uP Status Register Bits Processes
-- Dtc - data transfer complete. Since this only checks whether the
-- bit_cnt="0111" it will be true for both data and address transfers.
-- While one byte of data is being transferred, this bit is cleared.
-- It is set by the falling edge of the 9th clock of a byte transfer and
-- is not cleared at Reset
----------------------------------------------------------------------------
DTC_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i <= '0';
elsif scl_falling_edge = '1' then
if bit_cnt = "0111" then
dtc_i <= '1';
else
dtc_i <= '0';
end if;
end if;
end if;
end process DTC_I_BIT;
Dtc <= dtc_i;
----------------------------------------------------------------------------
-- DTC_DELAY_PROCESS
----------------------------------------------------------------------------
DTC_DELAY_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i_d1 <= '0';
dtc_i_d2 <= '0';
else
dtc_i_d1 <= dtc_i;
dtc_i_d2 <= dtc_i_d1;
end if;
end if;
end process DTC_DELAY_PROCESS;
----------------------------------------------------------------------------
-- aas_i - Addressed As Slave Bit
----------------------------------------------------------------------------
-- When its own specific address (adr) matches the I2C Address, this bit is
-- set.
-- Then the CPU needs to check the Srw bit and this bit when a
-- TX-RX mode accordingly.
----------------------------------------------------------------------------
AAS_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
aas_i <= '0';
elsif detect_stop = '1' or addr_match = '0' then
aas_i <= '0';
elsif state = ACK_HEADER then
aas_i <= addr_match;
-- the signal address match compares adr with I2_ADDR
else
aas_i <= aas_i;
end if;
end if;
end process AAS_I_BIT;
----------------------------------------------------------------------------
-- INT_AAS_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal aas_i signal to the output port Aas
----------------------------------------------------------------------------
INT_AAS_PROCESS : process (aas_i, sec_adr_match)
begin -- process
Aas <= aas_i and sec_adr_match;
end process INT_AAS_PROCESS;
----------------------------------------------------------------------------
-- Bb - Bus Busy Bit
----------------------------------------------------------------------------
-- This bit indicates the status of the bus. This bit is set when a START
-- signal is detected and cleared when a stop signal is detected. It is
-- also cleared on Reset. This bit is identical to the signal bus_busy set
-- in the process set_bus_busy.
----------------------------------------------------------------------------
Bb <= bus_busy;
----------------------------------------------------------------------------
-- Al - Arbitration Lost Bit
----------------------------------------------------------------------------
-- This bit is set when the arbitration procedure is lost.
-- Arbitration is lost when:
-- 1. SDA is sampled low when the master drives high during addr or data
-- transmit cycle
-- 2. SDA is sampled low when the master drives high during the
-- acknowledge bit of a data receive cycle
-- 3. A start cycle is attempted when the bus is busy
-- 4. A repeated start is requested in slave mode
-- 5. A stop condition is detected that the master did not request it.
-- This bit is cleared upon Reset and when the software writes a '0' to it
-- Conditions 1 & 2 above simply result in sda_rin not matching sda_cout
-- while SCL is high. This design will not generate a START condition while
-- the bus is busy. When a START is detected, this hardware will set the bus
-- busy bit and gen_start stays set until detect_start asserts, therefore
-- will have to compare with a delayed version of bus_busy. Condition 3 is
-- really just a check on the uP software control registers as is condition
-- 4. Condition 5 is also taken care of by the fact that sda_rin does not
-- equal sda_cout, however, this process also tests for if a stop condition
-- has been detected when this master did not generate it
----------------------------------------------------------------------------
AL_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_i <= '0';
elsif master_slave = '1' then
if (arb_lost = '1') or
(bus_busy_d1 = '1' and gen_start = '1') or
(detect_stop = '1' and al_prevent = '0' and sm_stop = '0') then
al_i <= '1';
else
al_i <= '0'; -- generate a pulse on al_i, arb lost interrupt
end if;
elsif Rsta = '1' then
-- repeated start requested while slave
al_i <= '1';
else
al_i <= '0';
end if;
end if;
end process AL_I_BIT;
----------------------------------------------------------------------------
-- INT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal al_i signal to the output port Al
----------------------------------------------------------------------------
INT_ARB_LOST_PROCESS : process (al_i)
begin -- process
Al <= al_i;
end process INT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- PREVENT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process prevents arb lost (al_i) when a stop has been initiated by
-- this device operating as a master.
----------------------------------------------------------------------------
PREVENT_ARB_LOST_PROCESS : process (Sys_clk)
begin -- make an SR flip flop that sets on gen_stop and resets on
-- detect_start
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_prevent <= '0';
elsif (gen_stop = '1' and detect_start = '0')
or (sm_stop = '1' and detect_start = '0')then
al_prevent <= '1';
elsif detect_start = '1' then
al_prevent <= '0';
else
al_prevent <= al_prevent;
end if;
end if;
end process PREVENT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- srw_i - Slave Read/Write Bit
----------------------------------------------------------------------------
-- When aas_i is set, srw_i indicates the value of the R/W command bit of
-- the calling address sent from the master. This bit is only valid when a
-- complete transfer has occurred and no other transfers have been
-- initiated. The CPU uses this bit to set the slave transmit/receive mode.
-- This bit is Reset by Reset
----------------------------------------------------------------------------
SRW_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
srw_i <= '0';
elsif state = ACK_HEADER then
srw_i <= i2c_header(0);
else
srw_i <= srw_i;
end if;
end if;
end process SRW_I_BIT;
Srw <= srw_i;
----------------------------------------------------------------------------
-- TXER_BIT process
----------------------------------------------------------------------------
-- This process determines the state of the acknowledge bit which may be
-- used as a transmit error or by a master receiver to indicate to the
-- slave that the last byte has been transmitted
----------------------------------------------------------------------------
TXER_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_i <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_i <= sda_sample;
end if;
end if;
end if;
end process TXER_BIT;
----------------------------------------------------------------------------
-- TXER_EDGE process
----------------------------------------------------------------------------
-- This process creates a one wide clock pulse for Txer IRQ
----------------------------------------------------------------------------
TXER_EDGE_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_edge <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_edge <= sda_sample;
end if;
elsif scl_f_edg_d2 = '1' then
txer_edge <= '0';
end if;
end if;
end process TXER_EDGE_PROCESS;
Txer <= txer_edge;
----------------------------------------------------------------------------
-- uP Data Register
-- Register for uP interface data_i2c_i
----------------------------------------------------------------------------
DATA_I2C_I_PROC : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
data_i2c_i <= (others => '0');
new_rcv_dta_i <= '0';
elsif (state = ACK_DATA) and Ro_prev = '0' and scl_falling_edge = '1'
and adr_dta_l = '0' then
data_i2c_i <= shift_reg;
new_rcv_dta_i <= '1';
else
data_i2c_i <= data_i2c_i;
new_rcv_dta_i <= '0';
end if;
end if;
end process DATA_I2C_I_PROC;
----------------------------------------------------------------------------
-- INT_NEW_RCV_DATA_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal receive data signals to the output port
----------------------------------------------------------------------------
INT_NEW_RCV_DATA_PROCESS : process (new_rcv_dta_i)
begin -- process
New_rcv_dta <= new_rcv_dta_i;
end process INT_NEW_RCV_DATA_PROCESS;
Data_i2c <= data_i2c_i;
----------------------------------------------------------------------------
-- Determine if Addressed As Slave or by General Call
----------------------------------------------------------------------------
-- This process determines when the I2C has been addressed as a slave
-- that is the I2C header matches the slave address stored in ADR or a
-- general call has happened
----------------------------------------------------------------------------
NO_TEN_BIT_GEN : if C_TEN_BIT_ADR = 0 generate
addr_match <= '1' when (i2c_header(7 downto 1) = Adr(7 downto 1))
or (abgc_i = '1')
else '0';
-- Seven bit addressing, sec_adr_match is always true.
sec_adr_match <= '1';
end generate NO_TEN_BIT_GEN;
TEN_BIT_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- The msb_wr signal indicates that the just received i2c_header matches
-- the required first byte of a 2-byte, 10-bit address. Since the
-- i2c_header shift register clocks on the scl rising edge but the timing
-- of signals dependent on msb_wr expect it to change on the falling edge
-- the scl_f_edge_d1 qualifier is used to create the expected timing.
-------------------------------------------------------------------------
MSB_WR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr <= '0';
elsif (abgc_i = '1') or
(scl_f_edg_d1 = '1'
and i2c_header(7 downto 3) = "11110"
and (i2c_header(2 downto 1) = Ten_adr(7 downto 6)))
then
msb_wr <= '1';
elsif (scl_f_edg_d1='1') then
msb_wr <= '0';
end if;
end if;
end process MSB_WR_PROCESS;
-------------------------------------------------------------------------
-- MSB_WR_D_PROCESS
-------------------------------------------------------------------------
-- msb_wr delay process
-------------------------------------------------------------------------
MSB_WR_D_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr_d <= '0';
msb_wr_d1 <= '0';
else
msb_wr_d <= msb_wr;
msb_wr_d1 <= msb_wr_d; -- delayed to align with srw_i
end if;
end if;
end process MSB_WR_D_PROCESS;
-------------------------------------------------------------------------
-- SRFF set on leading edge of MSB_WR, Reset on DTC and SCL falling edge
-- this will qualify the 2nd byte as address and prevent it from being
-- loaded into the DRR or Rc FIFO
-------------------------------------------------------------------------
SECOND_ADDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_addr <= '0';
elsif (msb_wr = '1' and msb_wr_d = '0'
and i2c_header(0) = '0') then
-- First byte of two byte (10-bit addr) matched and
-- direction=write. Set sec_addr flag to indicate next byte
-- should be checked against remainder of the address.
sec_addr <= '1';
elsif dtc_i = '1' and Ro_prev = '0' and scl_f_edg_d1 = '1'
then
sec_addr <= '0';
else
sec_addr <= sec_addr;
end if;
end if;
end process SECOND_ADDR_PROCESS;
-------------------------------------------------------------------------
-- Compare 2nd byte to see if it matches slave address
-- A repeated start with the Master writing to the slave must also
-- compare the second address byte.
-- A repeated start with the Master reading from the slave only compares
-- the first (most significant).
-------------------------------------------------------------------------
SECOND_ADDR_COMP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_adr_match <= '0';
elsif detect_stop = '1'
-- Repeated Start and Master Writing to Slave
or (state = ACK_HEADER and i2c_header(0) = '0'
and master_slave = '0' and msb_wr_d = '1' and abgc_i = '0') then
sec_adr_match <= '0';
elsif (abgc_i = '1')
or (sec_addr = '1' and (shift_reg(7) = Ten_adr(5)
and shift_reg(6 downto 0) = Adr (7 downto 1)
and dtc_i = '1' and msb_wr_d1 = '1')) then
sec_adr_match <= '1';
else
sec_adr_match <= sec_adr_match;
end if;
end if;
end process SECOND_ADDR_COMP_PROCESS;
-------------------------------------------------------------------------
-- Prevents 2nd byte of 10 bit address from being loaded into DRR.
-- When in ACK_HEADER and srw_i is lo then a repeated start or start
-- condition occured and data is being written to slave so the next
-- byte will be the remaining portion of the 10 bit address
-------------------------------------------------------------------------
ADR_DTA_L_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
adr_dta_l <= '0';
elsif ((i2c_header(0) = '0' and
msb_wr = '1' and
msb_wr_d = '0') and
sec_adr_match = '0') or
(state = ACK_HEADER and srw_i = '0' and
master_slave = '0' and
msb_wr_d1 = '1') then
adr_dta_l <= '1';
elsif (state = ACK_HEADER and
master_slave = '1' and
msb_wr_d1 = '0') then
adr_dta_l <= '0';
elsif (state = ACK_DATA and Ro_prev = '0'
and scl_falling_edge = '1')
or (detect_start = '1') or (abgc_i = '1')
-- or (state = ACK_HEADER and srw_i = '1' and master_slave = '0')
then
adr_dta_l <= '0';
else
adr_dta_l <= adr_dta_l;
end if;
end if;
end process ADR_DTA_L_PROCESS;
-- Set address match high to get 2nd byte of slave address
addr_match <= '1' when (msb_wr = '1' and sec_adr_match = '1')
or (sec_addr = '1')
else '0';
end generate TEN_BIT_GEN;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Address by general call process
----------------------------------------------------------------------------
ABGC_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
abgc_i <= '0';
elsif detect_stop = '1' or detect_start = '1' then
abgc_i <= '0';
elsif i2c_header(7 downto 0) = "00000000" and Gc_en = '1'
and (state = ACK_HEADER) then
abgc_i <= '1';
end if;
end if;
end process ABGC_PROCESS;
Abgc <= abgc_i;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Sample the SDA_RIN for use in checking the acknowledge bit received by
-- the controller
----------------------------------------------------------------------------
SDA_SMPL: process (Sys_clk) is
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_sample <= '0';
elsif (scl_rising_edge='1') then
sda_sample <= sda_rin;
end if;
end if;
end process SDA_SMPL;
----------------------------------------------------------------------------
-- Main State Machine Process
-- The following process contains the main I2C state machine for both master
-- and slave modes. This state machine is clocked on the falling edge of SCL
-- DETECT_STOP must stay as an asynchronous Reset because once STOP has been
-- generated, SCL clock stops. Note that the bit_cnt signal updates on the
-- scl_falling_edge pulse and is available on scl_f_edg_d1. So the count is
-- available prior to the STATE changing.
----------------------------------------------------------------------------
STATE_MACHINE : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_stop = '1' then
state <= IDLE;
sm_stop <= '0';
elsif scl_f_edg_d2 = '1' or (Ro_prev = '0' and ro_prev_d1 = '1') then
case state is
------------- IDLE STATE -------------
when IDLE =>
--sm_stop <= sm_stop ;
if detect_start = '1' then
state <= HEADER;
end if;
------------- HEADER STATE -------------
when HEADER =>
--sm_stop <= sm_stop ;
if bit_cnt = CNT_DONE then
state <= ACK_HEADER;
end if;
------------- ACK_HEADER STATE -------------
when ACK_HEADER =>
-- sm_stop <= sm_stop ;
if arb_lost = '1' then
state <= IDLE;
elsif sda_sample = '0' then
-- ack has been received, check for master/slave
if master_slave = '1' then
-- master, so check tx bit for direction
if Tx = '0' then
-- receive mode
state <= RCV_DATA;
else
--transmit mode
state <= XMIT_DATA;
end if;
else
if addr_match = '1' then
--if aas_i = '1' then
-- addressed slave, so check I2C_HEADER(0)
-- for direction
if i2c_header(0) = '0' then
-- receive mode
state <= RCV_DATA;
else
-- transmit mode
state <= XMIT_DATA;
end if;
else
-- not addressed, go back to IDLE
state <= IDLE;
end if;
end if;
else
-- not acknowledge received, stop as the address put on
-- the bus was not recognized/accepted by any slave
state <= IDLE;
if master_slave = '1' then
sm_stop <= '1';
end if;
end if;
------------- RCV_DATA State --------------
when RCV_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
if master_slave = '0' and addr_match = '0' then
state <= IDLE;
else
-- Send an acknowledge
state <= ACK_DATA;
end if;
end if;
------------ XMIT_DATA State --------------
when XMIT_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
-- Wait for acknowledge
state <= WAIT_ACK;
end if;
------------- ACK_DATA State --------------
when ACK_DATA =>
--sm_stop <= sm_stop ;
if Ro_prev = '0' then -- stay in ACK_DATA until
state <= RCV_DATA; -- a read of DRR has occurred
else
state <= ACK_DATA;
end if;
------------- WAIT_ACK State --------------
when WAIT_ACK =>
if arb_lost = '1' then
state <= IDLE;
elsif (sda_sample = '0') then
if (master_slave = '0' and addr_match = '0') then
state <= IDLE;
else
state <= XMIT_DATA;
end if;
else
-- not acknowledge received. The master transmitter is
-- being told to quit sending data as the slave won't take
-- anymore. Generate a STOP per spec. (Note that it
-- isn't strickly necessary for the master to get off the
-- bus at this point. It could retain ownership. However,
-- product specification indicates that it will get off
-- the bus) The slave transmitter is being informed by the
-- master that it won't take any more data.
if master_slave = '1' then
sm_stop <= '1';
end if;
state <= IDLE;
end if;
-- coverage off
when others =>
state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process STATE_MACHINE;
LEVEL_1_GEN: if C_SDA_LEVEL = 1 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '1';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_1_GEN;
LEVEL_0_GEN: if C_SDA_LEVEL = 0 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '0';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_0_GEN;
----------------------------------------------------------------------------
-- Slave SDA
----------------------------------------------------------------------------
SLV_SDA : process(Sys_clk)
begin
-- For the slave SDA, address match(aas_i) only has to be checked when
-- state is ACK_HEADER because state
-- machine will never get to state XMIT_DATA or ACK_DATA
-- unless address match is a one.
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
slave_sda <= '1';
elsif (addr_match = '1' and state = ACK_HEADER) or
(state = ACK_DATA) then
slave_sda <= Txak;
elsif (state = XMIT_DATA) then
slave_sda <= shift_out;
else
slave_sda <= '1';
end if;
end if;
end process SLV_SDA;
------------------------------------------------------------
--Mathew : Added below process for CR 707697
SHIFT_COUNT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_cnt <= "000000000";
elsif(shift_reg_ld = '1') then
shift_cnt <= "000000001";
elsif(shift_reg_en = '1') then
shift_cnt <= shift_cnt(7 downto 0) & shift_cnt(8);
else
shift_cnt <= shift_cnt;
end if;
end if;
end process SHIFT_COUNT ;
reg_empty <= '1' when shift_cnt(8) = '1' else '0';
------------------------------------------------------------
----------------------------------------------------------------------------
-- I2C Data Shift Register
----------------------------------------------------------------------------
I2CDATA_REG : entity axi_iic_v2_0_14.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => shift_reg_ld,
Data_in => Dtr,
Shift_in => sda_rin,
Shift_en => shift_reg_en,
Shift_out => shift_out,
Data_out => shift_reg);
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_EN_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_EN_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_en <= '0';
elsif (
-- Grab second byte of 10-bit address?
(master_slave = '1' and state = HEADER and scl_rising_edge='1')
-- Grab data byte
or (state = RCV_DATA and scl_rising_edge='1'
and detect_start = '0')
-- Send data byte. Note use of scl_f_edg_d2 which is the 2 clock
-- delayed version of the SCL falling edge signal
or (state = XMIT_DATA and scl_f_edg_d2 = '1'
and detect_start = '0')) then
shift_reg_en <= '1';
else
shift_reg_en <= '0';
end if;
end if;
end process I2CDATA_REG_EN_CTRL;
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_LD_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_LD_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld <= '0';
elsif (
(master_slave = '1' and state = IDLE)
or (state = WAIT_ACK)
-- Slave Transmitter (i2c_header(0)='1' mean master wants to read)
or (state = ACK_HEADER and i2c_header(0) = '1'
and master_slave = '0')
-- Master has a byte to transmit
or (state = ACK_HEADER and Tx = '1' and master_slave = '1')
-- ??
or (state = RCV_DATA and detect_start = '1'))
or tx_under_prev_i = '1' then
shift_reg_ld <= '1';
else
shift_reg_ld <= '0';
end if;
end if;
end process I2CDATA_REG_LD_CTRL;
----------------------------------------------------------------------------
-- SHFT_REG_LD_PROCESS
----------------------------------------------------------------------------
-- This process registers shift_reg_ld signal
----------------------------------------------------------------------------
SHFT_REG_LD_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld_d1 <= '0';
else -- Delay shift_reg_ld one clock
shift_reg_ld_d1 <= shift_reg_ld;
end if;
end if;
end process SHFT_REG_LD_PROCESS;
----------------------------------------------------------------------------
-- NEW_XMT_PROCESS
----------------------------------------------------------------------------
-- This process sets Rdy_new_xmt signal high for one sysclk after data has
-- been loaded into the shift register. This is used to create the Dtre
-- interrupt.
----------------------------------------------------------------------------
NEW_XMT_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
rdy_new_xmt_i <= '0';
elsif state = XMIT_DATA or (state = HEADER and Msms = '1') then
rdy_new_xmt_i <= (not (shift_reg_ld)) and shift_reg_ld_d1;
end if;
end if;
end process NEW_XMT_PROCESS;
Rdy_new_xmt <= rdy_new_xmt_i;
----------------------------------------------------------------------------
-- I2C Header Shift Register
-- Header/Address Shift Register
----------------------------------------------------------------------------
I2CHEADER_REG : entity axi_iic_v2_0_14.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => i2c_header_ld,
Data_in => reg_clr,
Shift_in => sda_rin,
Shift_en => i2c_header_en,
Shift_out => i2c_shiftout,
Data_out => i2c_header);
----------------------------------------------------------------------------
-- Process : I2CHEADER_REG_CTRL
----------------------------------------------------------------------------
I2CHEADER_REG_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
i2c_header_en <= '0';
elsif (state = HEADER and scl_rising_edge='1') then
i2c_header_en <= '1';
else
i2c_header_en <= '0';
end if;
end if;
end process I2CHEADER_REG_CTRL;
i2c_header_ld <= '0';
----------------------------------------------------------------------------
-- Bit Counter
----------------------------------------------------------------------------
BITCNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => 4
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_start,
Cnt_en => bit_cnt_en,
Load => bit_cnt_ld,
Qout => bit_cnt);
----------------------------------------------------------------------------
-- Process : Counter control lines
----------------------------------------------------------------------------
BIT_CNT_EN_CNTL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bit_cnt_en <= '0';
elsif (state = HEADER and scl_falling_edge = '1')
or (state = RCV_DATA and scl_falling_edge = '1')
or (state = XMIT_DATA and scl_falling_edge = '1') then
bit_cnt_en <= '1';
else
bit_cnt_en <= '0';
end if;
end if;
end process BIT_CNT_EN_CNTL;
bit_cnt_ld <= '1' when (state = IDLE) or (state = ACK_HEADER)
or (state = ACK_DATA)
or (state = WAIT_ACK)
or (detect_start = '1') else '0';
end architecture RTL;
-------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from the SCL and SDA signals
-- using user definable delay parameters. SCL cross couples to
-- SDA to prevent SDA from changing near changes in SDA.
-- Notes:
-- 1) The default value for both debounce instances is '1' to conform to the
-- IIC bus default value of '1' ('H').
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.debounce;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- SCL_INERTIAL_DELAY -- SCL filtering delay
-- SDA_INERTIAL_DELAY -- SDA filtering delay
-- Definition of Ports:
-- Sysclk -- System clock
-- Scl_noisy -- IIC SCL is noisy
-- Scl_clean -- IIC SCL is clean
-- Sda_noisy -- IIC SDA is Noisy
-- Sda_clean -- IIC SDA is clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity filter is
generic (
SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
SDA_INERTIAL_DELAY : integer range 0 to 255 := 5
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Scl_noisy : in std_logic;
Scl_clean : out std_logic;
Sda_noisy : in std_logic;
Sda_clean : out std_logic
);
end entity filter;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of filter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
signal scl_unstable_n : std_logic;
begin
----------------------------------------------------------------------------
-- The inertial delay is cross coupled between the two IIC signals to ensure
-- that a delay in SCL because of a glitch also prevents any changes in SDA
-- until SCL is clean. This prevents inertial delay on SCL from creating a
-- situation whereby SCL is held high but SDA transitions low to high thus
-- making the core think a STOP has occured. Changes on SDA do not inihibit
-- SCL because that could alter the timing relationships for the clock
-- edges. If other I2C devices follow the spec then SDA should be stable
-- prior to the rising edge of SCL anyway. (Excluding noise of course)
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Assertion that reports the SCL inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SCL inertial delay of "
& integer'image(SCL_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SCL_DEBOUNCE : entity axi_iic_v2_0_14.debounce
generic map (
C_INERTIAL_DELAY => SCL_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => '1',
Unstable_n => scl_unstable_n,
Noisy => Scl_noisy,
Clean => Scl_clean);
----------------------------------------------------------------------------
-- Assertion that reports the SDA inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SDA inertial delay of "
& integer'image(SDA_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SDA_DEBOUNCE : entity axi_iic_v2_0_14.debounce
generic map (
C_INERTIAL_DELAY => SDA_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => scl_unstable_n,
Unstable_n => open,
Noisy => Sda_noisy,
Clean => Sda_clean);
end architecture RTL;
-------------------------------------------------------------------------------
-- dynamic_master.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: dynamic_master.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the control logic for the dynamic master.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Dynamic_MSMS -- Dynamic master slave mode select
-- Cr -- Control register
-- Tx_fifo_rd_i -- Transmit FIFO read
-- Tx_data_exists -- Trnasmit FIFO exists
-- AckDataState -- Data ack acknowledge signal
-- Tx_fifo_data -- Transmit FIFO read input
-- EarlyAckHdr -- Ack_header state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- Bb -- Bus busy indicator
-- Msms_rst_r -- MSMS reset indicator
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Msms_rst -- MSMS reset signal
-- TxFifoRd -- Transmit FIFO read output signal
-- Txak -- Transmit ack signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity dynamic_master is
port(
Clk : in std_logic;
Rst : in std_logic;
Dynamic_MSMS : in std_logic_vector(0 to 1);
Cr : in std_logic_vector(0 to 7);
Tx_fifo_rd_i : in std_logic;
Tx_data_exists : in std_logic;
AckDataState : in std_logic;
Tx_fifo_data : in std_logic_vector(0 to 7);
EarlyAckHdr : in std_logic;
EarlyAckDataState : in std_logic;
Bb : in std_logic;
Msms_rst_r : in std_logic;
DynMsmsSet : out std_logic;
DynRstaSet : out std_logic;
Msms_rst : out std_logic;
TxFifoRd : out std_logic;
Txak : out std_logic;
Cr_txModeSelect_set : out std_logic;
Cr_txModeSelect_clr : out std_logic
);
end dynamic_master;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of dynamic_master is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal firstDynStartSeen : std_logic; -- used to detect re-start during
-- dynamic start generation
signal dynamic_MSMS_d : std_logic_vector(0 to 1);
signal rxCntDone : std_logic;
signal forceTxakHigh : std_logic;
signal earlyAckDataState_d1: std_logic;
signal ackDataState_d1 : std_logic;
signal rdByteCntr : unsigned(0 to 7);
signal rdCntrFrmTxFifo : std_logic;
signal callingReadAccess : std_logic;
signal dynamic_start : std_logic;
signal dynamic_stop : std_logic;
-------------------------------------------------------------------------------
begin
-- In the case where the tx fifo only contains a single byte (the address)
-- which contains both start and stop bits set the controller has to rely on
-- the tx fifo data exists flag to qualify the fifo output. Otherwise the
-- controller emits a continous stream of bytes. This fixes CR439857
dynamic_start <= Dynamic_MSMS(1) and Tx_data_exists;
dynamic_stop <= Dynamic_MSMS(0) and Tx_data_exists;
DynMsmsSet <= dynamic_start -- issue dynamic start by setting MSMS
and not(Cr(5)) -- when MSMS is not already set and
and not(Bb); -- bus isn't busy
DynRstaSet <= dynamic_start -- issue repeated start when
and Tx_fifo_rd_i
and firstDynStartSeen; -- MSMS is already set
Msms_rst <= (dynamic_stop and Tx_fifo_rd_i)
or Msms_rst_r
or rxCntDone;
TxFifoRd <= Tx_fifo_rd_i or rdCntrFrmTxFifo;
forceTxakHigh <= '1' when (EarlyAckDataState='1' and callingReadAccess='1'
and rdByteCntr = 0) else
'0';
Txak <= Cr(3) or forceTxakHigh;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MSMS_DLY_PROCESS
-- purpose: Dynamic Master MSMS registering
-----------------------------------------------------------------------------
DYN_MSMS_DLY_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
dynamic_MSMS_d <= (others => '0');
else
dynamic_MSMS_d <= Dynamic_MSMS;
end if;
end if;
end process DYN_MSMS_DLY_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_START_PROCESS
-- purpose: reset firstDynStartSeen if CR(5) MSMS is cleared
-----------------------------------------------------------------------------
DYN_START_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
firstDynStartSeen <= '0';
else
if(Cr(5) = '0') then
firstDynStartSeen <= '0';
elsif(firstDynStartSeen = '0' and Tx_fifo_rd_i = '1'
and dynamic_start = '1') then
firstDynStartSeen <= '1';
end if;
end if;
end if;
end process DYN_START_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_ACCESS_PROCESS
-- purpose: capture access direction initiated via dynamic Start
-----------------------------------------------------------------------------
DYN_RD_ACCESS_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
callingReadAccess <= '0';
else
if(Tx_fifo_rd_i = '1' and dynamic_start = '1') then
callingReadAccess <= Tx_fifo_data(7);
end if;
end if;
end if;
end process DYN_RD_ACCESS_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_SET_PROCESS
-- purpose: Set the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_SET_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_set <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_set <= not callingReadAccess;
else
Cr_txModeSelect_set <= '0';
end if;
end if;
end process DYN_MODE_SELECT_SET_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_CLR_PROCESS
-- purpose: Clear the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_CLR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_clr <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_clr <= callingReadAccess;
else
Cr_txModeSelect_clr <= '0';
end if;
end if;
end process DYN_MODE_SELECT_CLR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of tx to process
-----------------------------------------------------------------------------
DYN_RD_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdCntrFrmTxFifo <= '0';
else
if(EarlyAckHdr='1' and Tx_data_exists='1'
and callingReadAccess='1') then
rdCntrFrmTxFifo <= '1';
else
rdCntrFrmTxFifo <= '0';
end if;
end if;
end if;
end process DYN_RD_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of rx bytes to process
-----------------------------------------------------------------------------
DYN_RD_BYTE_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdByteCntr <= (others => '0');
else
if(rdCntrFrmTxFifo='1') then
rdByteCntr <= unsigned(Tx_fifo_data);
elsif(EarlyAckDataState='1' and earlyAckDataState_d1='0'
and rdByteCntr /= 0) then
rdByteCntr <= rdByteCntr - 1;
end if;
end if;
end if;
end process DYN_RD_BYTE_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: Initialize read byte counter in order to control master
-- generation of ack to slave.
-----------------------------------------------------------------------------
DYN_EARLY_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
earlyAckDataState_d1 <= '0';
else
earlyAckDataState_d1 <= EarlyAckDataState;
end if;
end if;
end process DYN_EARLY_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Register ackdatastate
-----------------------------------------------------------------------------
DYN_STATE_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
ackDataState_d1 <= '0';
else
ackDataState_d1 <= AckDataState;
end if;
end if;
end process DYN_STATE_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Generation of receive count done to generate stop
-----------------------------------------------------------------------------
DYN_RX_CNT_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxCntDone <= '0';
else
if(AckDataState='1' and ackDataState_d1='0' and callingReadAccess='1'
and rdByteCntr = 0) then
rxCntDone <= '1';
else
rxCntDone <= '0';
end if;
end if;
end if;
end process DYN_RX_CNT_PROCESS;
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_ipif_ssp1.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_ipif_ssp1.vhd
-- Version: v1.01.b
--
-- Description: AXI IPIF Slave Services Package 1
-- This block provides the following services:
-- - wraps the axi_lite_ipif interface to IPIC block and
-- sets up its address decoding.
-- - Provides the Software Reset register
-- - Provides interrupt servicing
-- - IPIC multiplexing service between the external IIC
-- register block IP2Bus data path and the internal
-- Interrupt controller's IP2Bus data path.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
-- NLR 01/07/11
-- ^^^^^^
-- - Updated the version to v1_01_b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
library axi_iic_v2_0_14;
library axi_lite_ipif_v3_0_4;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_IIC_REGS -- Number of IIC registers
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- Target FPGA architecture
-------------------------------------------------------------------------------
-- Definition of Ports:
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IP interconnect port signals
-- Bus2IP_Clk -- Bus to IIC clock
-- Bus2IP_Reset -- Bus to IIC reset
-- Bus2IIC_Addr -- Bus to IIC address
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_RNW -- Bus to IIC read not write
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_ipif_ssp1 is
generic
(
C_NUM_IIC_REGS : integer := 10;
-- Number of IIC Registers
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7"
-- Select the target architecture type
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2Bus_IntrEvent : in std_logic_vector (0 to 7);
-- IIC Interrupt events
IIC2INTC_Irpt : out std_logic; -- IP-2-interrupt controller
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals used by the IIC registers.
Bus2IIC_Clk : out std_logic;
Bus2IIC_Reset : out std_logic;
Bus2IIC_Addr : out std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
Bus2IIC_Data : out std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_RNW : out std_logic;
Bus2IIC_RdCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
Bus2IIC_WrCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
IIC2Bus_Data : in std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1)
);
end entity axi_ipif_ssp1;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_ipif_ssp1 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant INTR_BASEADDR : std_logic_vector := X"00000000";
constant INTR_HIGHADDR : std_logic_vector
:= X"0000003F";
constant RST_BASEADDR : std_logic_vector
:= X"00000040";
constant RST_HIGHADDR : std_logic_vector
:= X"00000043";
constant IIC_REG_BASEADDR : std_logic_vector
:= X"00000100";
constant IIC_REG_HIGHADDR : std_logic_vector
:= X"000001FF";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & INTR_BASEADDR, -- Interrupt controller
ZEROES & INTR_HIGHADDR,
ZEROES & RST_BASEADDR, -- Software reset register
ZEROES & RST_HIGHADDR,
ZEROES & IIC_REG_BASEADDR, -- IIC registers
ZEROES & IIC_REG_HIGHADDR
);
constant C_ARD_IDX_INTERRUPT : integer := 0;
constant C_ARD_IDX_RESET : integer := 1;
constant C_ARD_IDX_IIC_REGS : integer := 2;
-- The C_IP_INTR_MODE_ARRAY must have the same width as the IP2Bus_IntrEvent
-- entity port.
constant C_IP_INTR_MODE_ARRAY : integer_array_type
:= (3, 3, 3, 3, 3, 3, 3, 3);
constant C_INCLUDE_DEV_PENCODER : boolean := FALSE;
constant C_INCLUDE_DEV_ISC : boolean := FALSE;
constant C_NUM_INTERRUPT_REGS : integer := 16;
constant C_NUM_RESET_REGS : integer := 1;
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_ARD_IDX_INTERRUPT => C_NUM_INTERRUPT_REGS,
C_ARD_IDX_RESET => C_NUM_RESET_REGS,
C_ARD_IDX_IIC_REGS => C_NUM_IIC_REGS
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"000001FF";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
SUBTYPE INTERRUPT_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)+C_ARD_NUM_CE_ARRAY(0)-1;
SUBTYPE RESET_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)+C_ARD_NUM_CE_ARRAY(1)-1;
SUBTYPE IIC_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)+C_ARD_NUM_CE_ARRAY(2)-1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Signals
signal AXI_Bus2IP_Clk : std_logic;
signal AXI_Bus2IP_Resetn: std_logic;
signal AXI_Bus2IP_Reset : std_logic;
signal AXI_IP2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_IP2Bus_WrAck : std_logic;
signal AXI_IP2Bus_RdAck : std_logic;
signal AXI_IP2Bus_WrAck1 : std_logic;
signal AXI_IP2Bus_RdAck1 : std_logic;
signal AXI_IP2Bus_WrAck2 : std_logic;
signal AXI_IP2Bus_RdAck2 : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal AXI_IP2Bus_Error : std_logic;
signal AXI_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal AXI_Bus2IP_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_Bus2IP_RNW : std_logic;
signal AXI_Bus2IP_CS : std_logic_vector(0 to
((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal AXI_Bus2IP_RdCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal AXI_Bus2IP_WrCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- Derived IPIC signals for use with the reset register functionality
signal reset2Bus_Error : std_logic;
signal reset2IP_Reset : std_logic;
-- Derived IPIC signals for use with the interrupt controller
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
AXI_Bus2IP_Reset <= not AXI_Bus2IP_Resetn;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
-- System signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
-- AXI Interface signals
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Resetn => AXI_Bus2IP_Resetn,
IP2Bus_Data => AXI_IP2Bus_Data,
IP2Bus_WrAck => AXI_IP2Bus_WrAck,
IP2Bus_RdAck => AXI_IP2Bus_RdAck,
IP2Bus_Error => AXI_IP2Bus_Error,
Bus2IP_Addr => AXI_Bus2IP_Addr,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_RNW => AXI_Bus2IP_RNW,
Bus2IP_BE => open,
Bus2IP_CS => AXI_Bus2IP_CS,
Bus2IP_RdCE => AXI_Bus2IP_RdCE,
Bus2IP_WrCE => AXI_Bus2IP_WrCE
);
-------------------------------------------------------------------------------
-- INTERRUPT DEVICE
-------------------------------------------------------------------------------
X_INTERRUPT_CONTROL : entity interrupt_control_v3_1_4.interrupt_control
generic map (
C_NUM_CE => C_NUM_INTERRUPT_REGS, -- [integer range 4 to 16]
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC => 1, -- [integer range 1 to 29]
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY, -- [INTEGER_ARRAY_TYPE]
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_PENCODER, -- [boolean]
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC, -- [boolean]
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH -- [integer range 32 to 128]
)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Reset => reset2IP_Reset,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
Interrupt_RdCE => AXI_Bus2IP_RdCE(INTERRUPT_CE_RNG),
Interrupt_WrCE => AXI_Bus2IP_WrCE(INTERRUPT_CE_RNG),
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => "00",
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => "0",
-- Inputs from the IP Interface
IP2Bus_IntrEvent => IIC2Bus_IntrEvent,
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IIC2INTC_Irpt,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => Intr2Bus_DBus,
Intr2Bus_WrAck => open,
Intr2Bus_RdAck => open,
Intr2Bus_Error => open,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-------------------------------------------------------------------------------
-- SOFT RESET REGISTER
-------------------------------------------------------------------------------
X_SOFT_RESET : entity axi_iic_v2_0_14.soft_reset
generic map (
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH, -- [integer]
-- Width of the write data bus
C_RESET_WIDTH => 4)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Reset => AXI_Bus2IP_Reset,
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_WrCE => AXI_Bus2IP_WrCE(RESET_CE_RNG'LEFT),
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
-- Final Device Reset Output
reset2IP_Reset => reset2IP_Reset,
-- Status Reply Outputs to the Bus
reset2Bus_WrAck => open,
reset2Bus_Error => reset2Bus_Error,
Reset2Bus_ToutSup => open);
-------------------------------------------------------------------------------
-- IIC Register (External) Connections
-------------------------------------------------------------------------------
Bus2IIC_Clk <= AXI_Bus2IP_Clk;
Bus2IIC_Reset <= reset2IP_Reset;
Bus2IIC_Addr <= AXI_Bus2IP_Addr;
Bus2IIC_Data <= AXI_Bus2IP_Data;
Bus2IIC_RNW <= AXI_Bus2IP_RNW;
Bus2IIC_RdCE <= AXI_Bus2IP_RdCE(IIC_CE_RNG);
Bus2IIC_WrCE <= AXI_Bus2IP_WrCE(IIC_CE_RNG);
-------------------------------------------------------------------------------
-- Read Ack/Write Ack generation
-------------------------------------------------------------------------------
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_RdAck2 <= or_reduce(AXI_Bus2IP_CS) and AXI_Bus2IP_RNW;
AXI_IP2Bus_RdAck1 <= AXI_IP2Bus_RdAck2;
end if;
end process;
AXI_IP2Bus_RdAck <= (not (AXI_IP2Bus_RdAck1)) and AXI_IP2Bus_RdAck2;
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_WrAck2 <= (or_reduce(AXI_Bus2IP_CS) and not AXI_Bus2IP_RNW);
AXI_IP2Bus_WrAck1 <= AXI_IP2Bus_WrAck2;
end if;
end process;
AXI_IP2Bus_WrAck <= (not AXI_IP2Bus_WrAck1) and AXI_IP2Bus_WrAck2;
-------------------------------------------------------------------------------
-- Data and Error generation
-------------------------------------------------------------------------------
AXI_IP2Bus_Data <= Intr2Bus_DBus or IIC2Bus_Data;
AXI_IP2Bus_Error <= reset2Bus_Error;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the top level file for the iic Bus
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613282
-- ~~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_IIC_REGS -- Number of IIC Registers
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IIC Signals
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic is
generic (
-- System Generics
C_NUM_IIC_REGS : integer := 10;
--IIC Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_SCL_INERTIAL_DELAY : integer := 0;
C_SDA_INERTIAL_DELAY : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_EXIST : boolean := TRUE;
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7";
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IIC Bus Signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to C_GPO_WIDTH-1)
);
end entity iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Calls the function from the iic_pkg.vhd
constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
signal Msms_rst : std_logic;
signal Msms_set : std_logic;
signal Rsta_rst : std_logic;
signal Dtc : std_logic;
signal Rdy_new_xmt : std_logic;
signal New_rcv_dta : std_logic;
signal Ro_prev : std_logic;
signal Dtre : std_logic;
signal Bb : std_logic;
signal Aas : std_logic;
signal Al : std_logic;
signal Srw : std_logic;
signal Txer : std_logic;
signal Tx_under_prev : std_logic;
signal Abgc : std_logic;
signal Data_i2c : std_logic_vector(0 to 7);
signal Adr : std_logic_vector(0 to 7);
signal Ten_adr : std_logic_vector(5 to 7);
signal Cr : std_logic_vector(0 to 7);
signal Drr : std_logic_vector(0 to 7);
signal Dtr : std_logic_vector(0 to 7);
signal Tx_fifo_data : std_logic_vector(0 to 7);
signal Tx_data_exists : std_logic;
signal Tx_fifo_wr : std_logic;
signal Tx_fifo_wr_i : std_logic;
signal Tx_fifo_wr_d : std_logic;
signal Tx_fifo_rd : std_logic;
signal Tx_fifo_rd_i : std_logic;
signal Tx_fifo_rd_d : std_logic;
signal Tx_fifo_rst : std_logic;
signal Tx_fifo_full : std_logic;
signal Tx_addr : std_logic_vector(0 to TX_FIFO_BITS - 1);
signal Rc_fifo_data : std_logic_vector(0 to 7);
signal Rc_fifo_wr : std_logic;
signal Rc_fifo_wr_i : std_logic;
signal Rc_fifo_wr_d : std_logic;
signal Rc_fifo_rd : std_logic;
signal Rc_fifo_rd_i : std_logic;
signal Rc_fifo_rd_d : std_logic;
signal Rc_fifo_full : std_logic;
signal Rc_Data_Exists : std_logic;
signal Rc_addr : std_logic_vector(0 to RC_FIFO_BITS -1);
signal Bus2IIC_Clk : std_logic;
signal Bus2IIC_Reset : std_logic;
signal IIC2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1) :=
(others => '0');
signal IIC2Bus_IntrEvent : std_logic_vector(0 to 7) := (others => '0');
signal Bus2IIC_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal Bus2IIC_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal Bus2IIC_RNW : std_logic;
signal Bus2IIC_RdCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
signal Bus2IIC_WrCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
-- signals for dynamic start/stop
signal ctrlFifoDin : std_logic_vector(0 to 1);
signal dynamic_MSMS : std_logic_vector(0 to 1);
signal dynRstaSet : std_logic;
signal dynMsmsSet : std_logic;
signal txak : std_logic;
signal earlyAckDataState : std_logic;
signal ackDataState : std_logic;
signal earlyAckHdr : std_logic;
signal cr_txModeSelect_set : std_logic;
signal cr_txModeSelect_clr : std_logic;
signal txFifoRd : std_logic;
signal Msms_rst_r : std_logic;
signal ctrl_fifo_wr_i : std_logic;
-- Cleaned up inputs
signal scl_clean : std_logic;
signal sda_clean : std_logic;
-- Timing Parameters
signal Timing_param_tsusta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsusto : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thdsta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsudat : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tbuf : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thigh : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tlow : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thddat : std_logic_vector(C_SIZE-1 downto 0);
----------Mathew
-- signal transfer_done : std_logic;
signal reg_empty : std_logic;
----------Mathew
begin
----------------------------------------------------------------------------
-- axi_ipif_ssp1 instantiation
----------------------------------------------------------------------------
X_AXI_IPIF_SSP1 : entity axi_iic_v2_0_14.axi_ipif_ssp1
generic map (
C_NUM_IIC_REGS => C_NUM_IIC_REGS,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
-- Width of AXI Data Bus (in bits) Must be 32
C_FAMILY => C_FAMILY)
port map (
-- System signals ----------------------------------------------------
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent, -- IIC Interrupt events
IIC2INTC_Irpt => IIC2INTC_Irpt,
-- AXI Interface signals --------------
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals used by the IIC registers. ----
Bus2IIC_Clk => Bus2IIC_Clk,
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data,
Bus2IIC_RNW => Bus2IIC_RNW,
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data
);
----------------------------------------------------------------------------
-- reg_interface instantiation
----------------------------------------------------------------------------
REG_INTERFACE_I : entity axi_iic_v2_0_14.reg_interface
generic map (
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
C_TX_FIFO_EXIST => C_TX_FIFO_EXIST ,
C_TX_FIFO_BITS => 4 ,
C_RC_FIFO_EXIST => C_RC_FIFO_EXIST ,
C_RC_FIFO_BITS => 4 ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR ,
C_GPO_WIDTH => C_GPO_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SIZE => C_SIZE ,
C_NUM_IIC_REGS => C_NUM_IIC_REGS ,
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map (
Clk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data(0 to C_S_AXI_DATA_WIDTH - 1),
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data(0 to C_S_AXI_DATA_WIDTH - 1),
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent,
Gpo => Gpo(0 to C_GPO_WIDTH-1),
Cr => Cr,
Dtr => Dtr,
Drr => Drr,
Adr => Adr,
Ten_adr => Ten_adr,
Msms_set => Msms_set,
Msms_rst => Msms_rst,
DynMsmsSet => dynMsmsSet,
DynRstaSet => dynRstaSet,
Cr_txModeSelect_set => cr_txModeSelect_set,
Cr_txModeSelect_clr => cr_txModeSelect_clr,
Rsta_rst => Rsta_rst,
Rdy_new_xmt => Rdy_new_xmt,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Aas => Aas,
Bb => Bb,
Srw => Srw,
Al => Al,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Tx_fifo_data => Tx_fifo_data(0 to 7),
Tx_data_exists => Tx_data_exists,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_full => Tx_fifo_full,
Tx_fifo_rst => Tx_fifo_rst,
Tx_addr => Tx_addr(0 to TX_FIFO_BITS - 1),
Rc_fifo_data => Rc_fifo_data(0 to 7),
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_full => Rc_fifo_full,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr => Rc_addr(0 to RC_FIFO_BITS - 1),
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- The V5 inputs are so fast that they typically create glitches longer then
-- the clock period due to the extremely slow rise/fall times on SDA/SCL
-- signals. The inertial delay filter removes these.
----------------------------------------------------------------------------
FILTER_I: entity axi_iic_v2_0_14.filter
generic map (
SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY -- [range 0 to 255]
)
port map
(
Sysclk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Scl_noisy => Scl_I,
Scl_clean => scl_clean,
Sda_noisy => Sda_I,
Sda_clean => sda_clean
);
----------------------------------------------------------------------------
-- iic_control instantiation
----------------------------------------------------------------------------
IIC_CONTROL_I : entity axi_iic_v2_0_14.iic_control
generic map
(
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SIZE => C_SIZE ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR,
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST
)
port map
(
Sys_clk => Bus2IIC_Clk,
Reset => Cr(7),
Sda_I => sda_clean,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => scl_clean,
Scl_O => Scl_O,
Scl_T => Scl_T,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Txak => txak,
Msms => Cr(5),
Msms_set => Msms_set,
Msms_rst => Msms_rst_r,
Rsta => Cr(2),
Rsta_rst => Rsta_rst,
Tx => Cr(4),
Gc_en => Cr(1),
Dtr => Dtr,
Adr => Adr,
Ten_adr => Ten_adr,
Bb => Bb,
Dtc => Dtc,
Aas => Aas,
Al => Al,
Srw => Srw,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Rdy_new_xmt => Rdy_new_xmt,
EarlyAckHdr => earlyAckHdr,
EarlyAckDataState => earlyAckDataState,
AckDataState => ackDataState,
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- Transmitter FIFO instantiation
----------------------------------------------------------------------------
WRITE_FIFO_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => Tx_fifo_wr_i,
Data_In => Bus2IIC_Data(24 to 31),
FIFO_Read => txFifoRd,
Data_Out => Tx_fifo_data(0 to 7),
FIFO_Full => Tx_fifo_full,
Data_Exists => Tx_data_exists,
Addr => Tx_addr(0 to TX_FIFO_BITS - 1)
);
-------Mathew
-- transfer_done <= '1' when Tx_data_exists = '0' and reg_empty ='1' else '0';
-------Mathew
----------------------------------------------------------------------------
-- Receiver FIFO instantiation
----------------------------------------------------------------------------
READ_FIFO_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => RC_FIFO_BITS
)
port map (
Clk => Bus2IIC_Clk,
Reset => Bus2IIC_Reset,
FIFO_Write => Rc_fifo_wr_i,
Data_In => Data_i2c(0 to 7),
FIFO_Read => Rc_fifo_rd_i,
Data_Out => Rc_fifo_data(0 to 7),
FIFO_Full => Rc_fifo_full,
Data_Exists => Rc_Data_Exists,
Addr => Rc_addr(0 to RC_FIFO_BITS - 1)
);
----------------------------------------------------------------------------
-- PROCESS: TX_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
TX_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Tx_fifo_wr_d <= '0';
Tx_fifo_rd_d <= '0';
else
Tx_fifo_wr_d <= Tx_fifo_wr;
Tx_fifo_rd_d <= Tx_fifo_rd;
end if;
end if;
end process TX_FIFO_WR_GEN;
----------------------------------------------------------------------------
-- PROCESS: RC_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
RC_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Rc_fifo_wr_d <= '0';
Rc_fifo_rd_d <= '0';
else
Rc_fifo_wr_d <= Rc_fifo_wr;
Rc_fifo_rd_d <= Rc_fifo_rd;
end if;
end if;
end process RC_FIFO_WR_GEN;
Tx_fifo_wr_i <= Tx_fifo_wr and (not Tx_fifo_wr_d);
Rc_fifo_wr_i <= Rc_fifo_wr and (not Rc_fifo_wr_d);
Tx_fifo_rd_i <= Tx_fifo_rd and (not Tx_fifo_rd_d);
Rc_fifo_rd_i <= Rc_fifo_rd and (not Rc_fifo_rd_d);
----------------------------------------------------------------------------
-- Dynamic master interface
-- Dynamic master start/stop and control logic
----------------------------------------------------------------------------
DYN_MASTER_I : entity axi_iic_v2_0_14.dynamic_master
port map (
Clk => Bus2IIC_Clk ,
Rst => Tx_fifo_rst ,
dynamic_MSMS => dynamic_MSMS ,
Cr => Cr ,
Tx_fifo_rd_i => Tx_fifo_rd_i ,
Tx_data_exists => Tx_data_exists ,
ackDataState => ackDataState ,
Tx_fifo_data => Tx_fifo_data ,
earlyAckHdr => earlyAckHdr ,
earlyAckDataState => earlyAckDataState ,
Bb => Bb ,
Msms_rst_r => Msms_rst_r ,
dynMsmsSet => dynMsmsSet ,
dynRstaSet => dynRstaSet ,
Msms_rst => Msms_rst ,
txFifoRd => txFifoRd ,
txak => txak ,
cr_txModeSelect_set => cr_txModeSelect_set,
cr_txModeSelect_clr => cr_txModeSelect_clr
);
-- virtual reset. Since srl fifo address is rst at the same time, only the
-- first entry in the srl fifo needs to have a value of '00' to appear
-- reset. Also, force data to 0 if a byte write is done to the txFifo.
ctrlFifoDin <= Bus2IIC_Data(22 to 23) when (Tx_fifo_rst = '0' and
Bus2IIC_Reset = '0') else
"00";
-- continuously write srl fifo while reset active
ctrl_fifo_wr_i <= Tx_fifo_rst or Bus2IIC_Reset or Tx_fifo_wr_i;
----------------------------------------------------------------------------
-- Control FIFO instantiation
-- fifo used to set/reset MSMS bit in control register to create automatic
-- START/STOP conditions
----------------------------------------------------------------------------
WRITE_FIFO_CTRL_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => 2,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => ctrl_fifo_wr_i,
Data_In => ctrlFifoDin,
FIFO_Read => txFifoRd,
Data_Out => dynamic_MSMS,
FIFO_Full => open,
Data_Exists => open,
Addr => open
);
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_iic.vhd
-- Version: v1.01.b
-- Description:
-- This file is the top level file that contains the IIC AXI
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf in iic_control to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282 and CR#613486
-- - Release of v1.01.b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- IIC Signals
-- sda_i -- IIC serial data input
-- sda_o -- IIC serial data output
-- sda_t -- IIC seral data output enable
-- scl_i -- IIC serial clock input
-- scl_o -- IIC serial clock output
-- scl_t -- IIC serial clock output enable
-- gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_iic is
generic (
-- FPGA Family Type specification
C_FAMILY : string := "virtex7";
-- Select the target architecture type
-- AXI Parameters
--C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9
C_S_AXI_ADDR_WIDTH : integer := 9; --9
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-- AXI IIC Feature generics
C_IIC_FREQ : integer := 100E3;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 1;
C_S_AXI_ACLK_FREQ_HZ : integer := 25E6;
C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_LEVEL : integer := 1; -- delay in nanoseconds
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port (
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
iic2intc_irpt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
--((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- IIC interface signals
sda_i : in std_logic;
sda_o : out std_logic;
sda_t : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_t : out std_logic;
gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0)
);
end entity axi_iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant C_NUM_IIC_REGS : integer := 18;
begin
X_IIC: entity axi_iic_v2_0_14.iic
generic map (
-- System Generics
C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers
--iic Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz
C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer]
C_GPO_WIDTH => C_GPO_WIDTH, -- [integer]
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
-- Transmit FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_TX_FIFO_EXIST => TRUE, -- [boolean]
-- Recieve FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_RC_FIFO_EXIST => TRUE, -- [boolean]
-- AXI interface generics
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9]
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32]
-- Width of the AXI Data Bus (in bits)
C_FAMILY => C_FAMILY, -- [string]
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map
(
-- System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
IIC2INTC_IRPT => iic2intc_iRPT,
-- AXI Interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IIC Bus Signals
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
GPO => gpo
);
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity projeto1 is
port(
clock : in std_logic;
direction, reset : in std_logic := '0';
enable : in std_logic := '1';
q : out std_logic_vector (3 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
process (clock, reset)
variable contagem : integer range 0 to 9;
begin
if (reset = '1') then
contagem := 0;
elsif (clock'event and clock = '1') then
if (enable = '1') then
if(direction = '1') then
contagem := contagem + 1;
else
contagem := contagem - 1;
end if;
end if;
end if;
q <= conv_std_logic_vector(contagem,4);
end process;
end Behavioral; |
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