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entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s <= to_unsigned(j, WIDTH);
end loop;
end loop;
wait;
end process;
end architecture;
|
entity tounsigned is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of tounsigned is
constant WIDTH : integer := 20;
constant ITERS : integer := 10;
signal s : unsigned(WIDTH - 1 downto 0);
begin
process is
begin
for i in 1 to ITERS loop
for j in 0 to integer'(2 ** WIDTH - 1) loop
s <= to_unsigned(j, WIDTH);
end loop;
end loop;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((10 <= 11),WR_RD_DEEP_COUNT,
((7/14)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((11 <= 10),WR_RD_DEEP_COUNT,
((14/7)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(9 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(10 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 2048 ,
RST_INC => 2 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 14,
DOUT_WIDTH => 14 ,
DATA_PART_CNT => 0,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p04n02i02860ent IS
END c13s10b00x00p04n02i02860ent;
ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
constant a : string := %%%%;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a'length=1 and a="%" )
report "***PASSED TEST: c13s10b00x00p04n02i02860"
severity NOTE;
assert ( a'length=1 and a="%" )
report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p04n02i02860arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p04n02i02860ent IS
END c13s10b00x00p04n02i02860ent;
ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
constant a : string := %%%%;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a'length=1 and a="%" )
report "***PASSED TEST: c13s10b00x00p04n02i02860"
severity NOTE;
assert ( a'length=1 and a="%" )
report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p04n02i02860arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p04n02i02860ent IS
END c13s10b00x00p04n02i02860ent;
ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
constant a : string := %%%%;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a'length=1 and a="%" )
report "***PASSED TEST: c13s10b00x00p04n02i02860"
severity NOTE;
assert ( a'length=1 and a="%" )
report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p04n02i02860arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity_lv is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
------------------------- lV network port
-- the router just sends the packets out. no need for any incomming packets support.
-- the output of the LV network will be connected to the PEs
credit_in_LV : in std_logic;
valid_out_LV : out std_logic;
TX_LV: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based_parity_lv;
architecture behavior of router_credit_based_parity_lv is
COMPONENT PACKETIZER_LV is
generic (
DATA_WIDTH: integer := 13;
current_address : integer := 0;
SHMU_address : integer := 0
);
port (
reset, clk: in std_logic;
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: in std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: in std_logic;
credit_in_LV: in std_logic;
valid_out_LV : out std_logic;
TX_LV: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
begin
-- packetizer for LV network
packetizer: PACKETIZER_LV generic map(DATA_WIDTH => 13, current_address => current_address, SHMU_address => 0)
port map (reset => reset, clk => clk,
faulty_packet_N => faulty_packet_N, faulty_packet_E => faulty_packet_E, faulty_packet_W => faulty_packet_W,
faulty_packet_S => faulty_packet_S, faulty_packet_L => faulty_packet_L,
healthy_packet_N => healthy_packet_N, healthy_packet_E => healthy_packet_E, healthy_packet_W => healthy_packet_W,
healthy_packet_S => healthy_packet_S, healthy_packet_L => healthy_packet_L,
credit_in_LV => credit_in_LV,
valid_out_LV => valid_out_LV,
TX_LV => TX_LV);
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:42 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_adc/clk_adc_stub.vhdl
-- Design : clk_adc
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_adc is
Port (
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC;
clk_250Mhz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_adc;
architecture stub of clk_adc is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in1_p,clk_in1_n,clk_250Mhz,locked";
begin
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"memmory.mif",
DEFAULT_DATA,
8,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for network cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package net is
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
tx_dv : std_ulogic;
rx_clk : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable: std_ulogic;
end record;
constant eth_in_none : eth_in_type :=
('0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_in_vector is array (natural range <>) of eth_in_type;
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type :=
('0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
type eth_out_vector is array (natural range <>) of eth_out_type;
type eth_sgmii_in_type is record
clkp : std_ulogic;
clkn : std_ulogic;
rxp : std_ulogic;
rxn : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
end record;
type eth_sgmii_out_type is record
reset : std_ulogic;
txp : std_ulogic;
txn : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
end record;
type greth_mdiochain_down_type is record
first : std_ulogic;
tick : std_ulogic;
mdio_i : std_ulogic;
end record;
type greth_mdiochain_up_type is record
lock : std_ulogic;
mdio_o : std_ulogic;
mdio_oe: std_ulogic;
end record;
constant greth_mdiochain_down_first: greth_mdiochain_down_type :=
(first => '1', tick => '0', mdio_i => '0');
constant greth_mdiochain_up_last: greth_mdiochain_up_type :=
(lock => '0', mdio_o => '0', mdio_oe => '0');
component eth_arb
generic(
fullduplex : integer := 0;
mdiomaster : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
ethi : in eth_in_type;
etho : out eth_out_type;
methi : in eth_out_type;
metho : out eth_in_type;
dethi : in eth_out_type;
detho : out eth_in_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0;
mdiochain : integer range 0 to 1 := 0;
iotest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type;
mdchain_ui : in greth_mdiochain_down_type := greth_mdiochain_down_first;
mdchain_uo : out greth_mdiochain_up_type;
mdchain_di : out greth_mdiochain_down_type;
mdchain_do : in greth_mdiochain_up_type := greth_mdiochain_up_last
);
end component;
component greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm_mb
generic (
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 1;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greths is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component;
component greths_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component;
component rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0;
mode100 : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type ;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component sgmii is
generic (
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
phy_addr : integer := 0;
mode : integer := 0 -- unused
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
ser_rx_p : in std_logic;
ser_rx_n : in std_logic;
ser_tx_p : out std_logic;
ser_tx_n : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
tx_clk : out std_logic;
tx_rstn : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
rx_clk : out std_logic;
rx_rstn : out std_logic;
-- optional MDIO interface to PCS
mdc : in std_logic;
mdio_o : in std_logic := '0';
mdio_oe : in std_logic := '1';
mdio_i : out std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component ;
component comma_detect is
generic (
bsbreak : integer range 0 to 31 := 0; -- number of extra deassertion cycles between bitslip assertions in a sequence
bswait : integer range 0 to 127 := 7 -- number of cycles to pause recognition after a sequence is issued
);
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end component;
component word_aligner is
generic(
comma : std_logic_vector(9 downto 3) := "0011111");
port(
clk : in std_logic; -- rx clock
rstn : in std_logic; -- asynchronous reset
rx_in : in std_logic_vector(9 downto 0); -- Data in
rx_out : out std_logic_vector(9 downto 0) -- Data out
);
end component;
component elastic_buffer is
generic (
tech : integer := 0;
abits : integer := 7
);
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
wr_data : in std_logic_vector(9 downto 0);
rd_clk : in std_logic;
rd_rst : in std_logic;
rd_data : out std_logic_vector(9 downto 0)
) ;
end component ;
component gmii_to_mii is
port (
tx_rstn : in std_logic;
rx_rstn : in std_logic;
-- MAC SIDE
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- PHY SIDE
miii : in eth_in_type;
miio : out eth_out_type
) ;
end component ;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simple_multishot_timer is
generic (
match_val : natural range 1 to natural'high
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC
);
end simple_multishot_timer;
architecture behavioral of simple_multishot_timer is
function check_timer_match(X : UNSIGNED; Y: natural) return boolean is
begin
return to_integer(X) = Y;
end check_timer_match;
constant count_bits_count : integer := (integer(ceil(log2(real(match_val)))));
signal timer_value : UNSIGNED(count_bits_count DOWNTO 0) := (others => '0');
begin
process (clk, rst)
begin
if (rst = '1') then
timer_value <= to_unsigned(0, timer_value'length);
done <= '0';
elsif rising_edge(clk) then
if check_timer_match(timer_value, match_val) then
done <= '1';
timer_value <= to_unsigned(1, timer_value'length);
else
timer_value <= timer_value + 1;
done <= '0';
end if;
end if;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2657.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02657ent IS
END c13s03b01x00p02n01i02657ent;
ARCHITECTURE c13s03b01x00p02n01i02657arch OF c13s03b01x00p02n01i02657ent IS
BEGIN
TESTING: PROCESS
variable <k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02657 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2657.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02657ent IS
END c13s03b01x00p02n01i02657ent;
ARCHITECTURE c13s03b01x00p02n01i02657arch OF c13s03b01x00p02n01i02657ent IS
BEGIN
TESTING: PROCESS
variable <k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02657 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2657.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02657ent IS
END c13s03b01x00p02n01i02657ent;
ARCHITECTURE c13s03b01x00p02n01i02657arch OF c13s03b01x00p02n01i02657ent IS
BEGIN
TESTING: PROCESS
variable <k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02657 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02657arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_unsigned(i, 32));
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_unsigned(i, 32));
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_unsigned(i, 32));
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_unsigned(i, 32));
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
|
-------------------------------------------
-- Package Name: Hex4Dig2SSeg_Package --
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Hex4Dig2SSeg_Package is
-- 4 hex digits on SSeg displays
component Hex4Digs2SSeg is
port (
clock : in std_logic; -- Input clock
-- sw0 : in std_logic; -- Switch to control clock
incr : in std_logic_vector (3 downto 0); -- Buttons to increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0) -- Cathodes for segments
);
end component;
-- component Anodes4DispCntrl is
-- port (
-- clock : in std_logic; -- Clock
-- anodes : out std_logic_vector (3 downto 0) -- Anodes for display
-- );
-- end component;
-- Use debounce pulses from buttons
component Deb4Btns is
port (
clk : in std_logic;
btns : in std_logic_vector (3 downto 0);
pulses : out std_logic_vector (3 downto 0)
);
end component;
-- Control clock with switch, either 1KHz or 5Hz
component ClockController is
port (
clock : in std_logic;
clk2Hz : out std_logic;
clk5Hz : out std_logic;
clk1KHz : out std_logic
);
end component;
-- Hex to SSeg decoder
component HexD2SSeg is
port (
HexChar : in std_logic_vector (3 downto 0);
Segments : out std_logic_vector (7 downto 0)
);
end component;
-- Debounce circuitry
component debounce is
port (
clk : in std_logic;
key : in std_logic;
pulse : out std_logic
);
end component;
-- Clock Divider with TC input
component cdiv is
port (
Cin : in std_logic;
TCvl : in integer;
Cout : out std_logic
);
end component;
end Hex4Dig2SSeg_Package;
|
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity regfile_tb is
-- Generic declarations of the tested unit
generic(
INITREG_T : STD_LOGIC_VECTOR := "00000000";
ADDRESS_BIT_SIZE_T : INTEGER := 8 );
end regfile_tb;
architecture TB_ARCHITECTURE of regfile_tb is
-- Component declaration of the tested unit
component regfile
generic(
INITREG_T : STD_LOGIC_VECTOR := "00000000";
ADDRESS_BIT_SIZE_T : INTEGER := 8 );
port(
init : in STD_LOGIC;
write_data_port : in STD_LOGIC_VECTOR(INITREG_T'range);
write_address : in STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
read_data_port_1 : out STD_LOGIC_VECTOR(INITREG_T'range);
read_data_port_2 : out STD_LOGIC_VECTOR(INITREG_T'range);
read_address_1 : in STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
read_address_2 : in STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
write_enabled : in STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal init : STD_LOGIC;
signal write_data_port : STD_LOGIC_VECTOR(INITREG_T'range);
signal write_address : STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
signal read_address_1 : STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
signal read_address_2 : STD_LOGIC_VECTOR(ADDRESS_BIT_SIZE_T-1 downto 0);
signal write_enabled : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal read_data_port_1 : STD_LOGIC_VECTOR(INITREG_T'range);
signal read_data_port_2 : STD_LOGIC_VECTOR(INITREG_T'range);
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : regfile
generic map (
INITREG_T => INITREG_T,
ADDRESS_BIT_SIZE_T => ADDRESS_BIT_SIZE_T
)
port map (
init => init,
write_data_port => write_data_port,
write_address => write_address,
read_data_port_1 => read_data_port_1,
read_data_port_2 => read_data_port_2,
read_address_1 => read_address_1,
read_address_2 => read_address_2,
write_enabled => write_enabled
);
MAIN : process
begin
init <= '1';
wait for 10ns;
init <= '0';
wait for 10ns;
write_data_port <= "00000111";
write_address <= "00000010";
write_enabled <= '1';
wait for 10ns;
write_enabled <= '0';
wait;
end process;
-- Add your stimulus here ...
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_regfile of regfile_tb is
for TB_ARCHITECTURE
for UUT : regfile
use entity work.regfile(beh_regfile);
end for;
end for;
end TESTBENCH_FOR_regfile;
|
library verilog;
use verilog.vl_types.all;
entity excute is
port(
clock : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_src1 : in vl_logic_vector(31 downto 0);
in_src2 : in vl_logic_vector(31 downto 0);
in_dst : in vl_logic_vector(4 downto 0);
in_imm : in vl_logic_vector(31 downto 0);
out_dst : out vl_logic_vector(4 downto 0);
out_dst_data : out vl_logic_vector(31 downto 0);
write_dst : out vl_logic;
dmem_address : out vl_logic_vector(31 downto 0);
dmem_data : inout vl_logic_vector(31 downto 0);
dmem_write : out vl_logic;
dmem_read : out vl_logic;
cnt_ex : out vl_logic;
cnt_read : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
in_databus2 : in vl_logic_vector(63 downto 0)
);
end excute;
|
library verilog;
use verilog.vl_types.all;
entity excute is
port(
clock : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_src1 : in vl_logic_vector(31 downto 0);
in_src2 : in vl_logic_vector(31 downto 0);
in_dst : in vl_logic_vector(4 downto 0);
in_imm : in vl_logic_vector(31 downto 0);
out_dst : out vl_logic_vector(4 downto 0);
out_dst_data : out vl_logic_vector(31 downto 0);
write_dst : out vl_logic;
dmem_address : out vl_logic_vector(31 downto 0);
dmem_data : inout vl_logic_vector(31 downto 0);
dmem_write : out vl_logic;
dmem_read : out vl_logic;
cnt_ex : out vl_logic;
cnt_read : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
in_databus2 : in vl_logic_vector(63 downto 0)
);
end excute;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1518);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed);
etho.txd(7 downto 4) <= "0000";
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
etho.gbit <= '0';
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Shift Out Register (74HC(T)595 and similar types)
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Maximum frequency 74HC595 : 100 MHz
-- 74HCT595 : 57 MHz
--
-- At 50 MHz it takes about 360ns (+ 25ns propgation delay from the 74HCT595)
-- until the output is visible at the outputs. The maximum latency of 380ns
-- appears it a transaction is has started directly before the transaction.
--
-- ## Pins
--
-- Master Reset (Pin 10) should be connected to high-level,
-- Output Enable (Pin 13) should be at low-level.
--
-- ## Waveform
--
-- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-- clke __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
-- ___ ___ ___ ___ ___ ___ ___ ___
-- sck ______| |___| |___| |___| |___| |___| |___| |___| |_________
-- _______ _______ _______ _______ _______ _______ _______ _______
-- dout __X_______X_______X_______X_______X_______X_______X_______X_______X_________
-- bit 0 1 2 3 4 5 6 7 8 9
-- ___
-- load ______________________________________________________________________| |__
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package shiftout_pkg is
type shiftout_out_type is record
sck : std_logic; -- or SH_CP (Pin 11)
dout : std_logic; -- or DS (Pin 14)
load : std_logic; -- or ST_CP (Pin 12)
end record;
component shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic);
end component shiftout;
end package shiftout_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.shiftout_pkg.all;
entity shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic
);
end entity shiftout;
architecture behavioral of shiftout is
signal clk_enable : std_logic := '1'; -- clock enable for the SCK speed
type shiftout_state_type is (
STATE_IDLE, STATE_WRITE, STATE_WRITE_NEXT, STATE_LOAD, STATE_LOAD_WAIT);
type shiftout_type is record
state : shiftout_state_type;
value : std_logic_vector(7 downto 0); -- copy of the input value
-- value currently loaded into the shift register
value_buffer : std_logic_vector(7 downto 0);
bitcount : integer range 0 to 9; -- Number of bits loaded
o : shiftout_out_type;
end record shiftout_type;
signal r, rin : shiftout_type := (
state => STATE_IDLE,
value => (others => '0'),
value_buffer => (others => '0'),
bitcount => 0,
o => (
sck => '0',
dout => '0',
load => '0'));
begin
seq_proc : process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process (clk_enable, r, r.bitcount, r.o, r.state, r.value,
r.value_buffer(6 downto 0), r.value_buffer(7), value_p) is
variable v : shiftout_type;
begin
v := r;
case r.state is
when STATE_IDLE =>
-- Wait until the input changes
if r.value /= value_p then
v.value := value_p;
v.value_buffer := value_p;
v.bitcount := 0;
v.state := STATE_WRITE_NEXT;
end if;
-- Clock high
when STATE_WRITE =>
if clk_enable = '1' then
v.o.sck := '1';
v.state := STATE_WRITE_NEXT;
end if;
-- Clock low and switch to the next bit
when STATE_WRITE_NEXT =>
if clk_enable = '1' then
v.o.sck := '0';
-- MSB first
v.o.dout := r.value_buffer(7);
v.value_buffer := r.value_buffer(6 downto 0) & '0';
v.bitcount := r.bitcount + 1;
if r.bitcount = 8 then
v.state := STATE_LOAD;
else
v.state := STATE_WRITE;
end if;
end if;
-- Load high
when STATE_LOAD =>
if clk_enable = '1' then
v.o.dout := '0';
v.o.load := '1';
v.state := STATE_LOAD_WAIT;
end if;
-- Load low
when STATE_LOAD_WAIT =>
if clk_enable = '1' then
v.o.load := '0';
v.state := STATE_IDLE;
end if;
end case;
-- register outputs
register_p <= r.o;
rin <= v;
end process comb_proc;
-- TODO clk_enable generation
-- to adapt to higher clk frequencies
end architecture behavioral;
|
-------------------------------------------------------------------------------
-- Title : Shift Out Register (74HC(T)595 and similar types)
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Maximum frequency 74HC595 : 100 MHz
-- 74HCT595 : 57 MHz
--
-- At 50 MHz it takes about 360ns (+ 25ns propgation delay from the 74HCT595)
-- until the output is visible at the outputs. The maximum latency of 380ns
-- appears it a transaction is has started directly before the transaction.
--
-- ## Pins
--
-- Master Reset (Pin 10) should be connected to high-level,
-- Output Enable (Pin 13) should be at low-level.
--
-- ## Waveform
--
-- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-- clke __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
-- ___ ___ ___ ___ ___ ___ ___ ___
-- sck ______| |___| |___| |___| |___| |___| |___| |___| |_________
-- _______ _______ _______ _______ _______ _______ _______ _______
-- dout __X_______X_______X_______X_______X_______X_______X_______X_______X_________
-- bit 0 1 2 3 4 5 6 7 8 9
-- ___
-- load ______________________________________________________________________| |__
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package shiftout_pkg is
type shiftout_out_type is record
sck : std_logic; -- or SH_CP (Pin 11)
dout : std_logic; -- or DS (Pin 14)
load : std_logic; -- or ST_CP (Pin 12)
end record;
component shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic);
end component shiftout;
end package shiftout_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.shiftout_pkg.all;
entity shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic
);
end entity shiftout;
architecture behavioral of shiftout is
signal clk_enable : std_logic := '1'; -- clock enable for the SCK speed
type shiftout_state_type is (
STATE_IDLE, STATE_WRITE, STATE_WRITE_NEXT, STATE_LOAD, STATE_LOAD_WAIT);
type shiftout_type is record
state : shiftout_state_type;
value : std_logic_vector(7 downto 0); -- copy of the input value
-- value currently loaded into the shift register
value_buffer : std_logic_vector(7 downto 0);
bitcount : integer range 0 to 9; -- Number of bits loaded
o : shiftout_out_type;
end record shiftout_type;
signal r, rin : shiftout_type := (
state => STATE_IDLE,
value => (others => '0'),
value_buffer => (others => '0'),
bitcount => 0,
o => (
sck => '0',
dout => '0',
load => '0'));
begin
seq_proc : process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process (clk_enable, r, r.bitcount, r.o, r.state, r.value,
r.value_buffer(6 downto 0), r.value_buffer(7), value_p) is
variable v : shiftout_type;
begin
v := r;
case r.state is
when STATE_IDLE =>
-- Wait until the input changes
if r.value /= value_p then
v.value := value_p;
v.value_buffer := value_p;
v.bitcount := 0;
v.state := STATE_WRITE_NEXT;
end if;
-- Clock high
when STATE_WRITE =>
if clk_enable = '1' then
v.o.sck := '1';
v.state := STATE_WRITE_NEXT;
end if;
-- Clock low and switch to the next bit
when STATE_WRITE_NEXT =>
if clk_enable = '1' then
v.o.sck := '0';
-- MSB first
v.o.dout := r.value_buffer(7);
v.value_buffer := r.value_buffer(6 downto 0) & '0';
v.bitcount := r.bitcount + 1;
if r.bitcount = 8 then
v.state := STATE_LOAD;
else
v.state := STATE_WRITE;
end if;
end if;
-- Load high
when STATE_LOAD =>
if clk_enable = '1' then
v.o.dout := '0';
v.o.load := '1';
v.state := STATE_LOAD_WAIT;
end if;
-- Load low
when STATE_LOAD_WAIT =>
if clk_enable = '1' then
v.o.load := '0';
v.state := STATE_IDLE;
end if;
end case;
-- register outputs
register_p <= r.o;
rin <= v;
end process comb_proc;
-- TODO clk_enable generation
-- to adapt to higher clk frequencies
end architecture behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_empty_device is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_empty_device;
architecture behave of zpuino_empty_device is
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
wb_dat_o <= (others => DontCareValue);
end behave;
|
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity WriteBack is
PORT ( Clk, rst : in std_logic;
DataIn1, DataIn2, DataIn3 : in std_logic_vector(15 downto 0);
ControlIn : in std_logic_vector (1 downto 0);
DataOut : out std_logic_vector (15 downto 0)
);
END WriteBack;
architecture arch_WriteBack of WriteBack is
begin
DataOut <= DataIn1 when ControlIn = "00" else
DataIn2 when ControlIn = "01" else
DataIn3 when ControlIn = "10" else
(others => '0');
end architecture arch_WriteBack;
|
architecture RTL of FIFO is
signal sig1 : std_logic;
type state_machine is (idle, write, read, done);
-- Violations below
signal sig1 : std_logic;
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v; -- input/output voltage
nolock : integer := 0
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
dolock : if nolock = 0 generate
pad_pci_lock : iopad
generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
end generate;
donolock : if nolock = 1 generate
pcii.lock <= pci_lock;
end generate;
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
|
--------------------------------------------------------------------------------------------------
-- Pulse Generator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.pulse_gen_pkg.all;
entity tb_pulse_gen is
end tb_pulse_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of tb_pulse_gen is
signal clk : std_logic;
signal rst : std_logic;
signal pulse : std_logic;
begin
--Instantiate clock generator
clk_gen : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Unit under test
uut : pulse_gen
generic map(CLKS_PER_PULSE => 20)
port map( clk => clk,
rst => rst,
pulse => pulse);
--main process
main : process
begin
rst <= '1';
wait until rising_edge(clk);
wait until falling_edge(clk);
rst <= '0';
wait;
end process;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_14.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_14
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_14
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_14 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_vld : OUT std_logic
);
END TWDLROM_3_14;
ARCHITECTURE rtl OF TWDLROM_3_14 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_14_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_14_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_14_re_tmp <= twdlIn_re;
twdl_3_14_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_14_re <= std_logic_vector(twdl_3_14_re_tmp);
twdl_3_14_im <= std_logic_vector(twdl_3_14_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_14_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_14_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
library verilog;
use verilog.vl_types.all;
entity arm_ex_stage is
port(
clk : in vl_logic;
IDEX_rd_we : in vl_logic;
IDEX_cpsr_we : in vl_logic;
IDEX_rd_data_sel: in vl_logic;
IDEX_is_imm : in vl_logic;
IDEX_alu_or_mac : in vl_logic;
IDEX_up_down : in vl_logic;
IDEX_mac_sel : in vl_logic;
IDEX_alu_sel : in vl_logic_vector(3 downto 0);
IDEX_cpsr_mask : in vl_logic_vector(3 downto 0);
IDEX_is_alu_for_mem_addr: in vl_logic;
IDEX_rd_sel : in vl_logic;
IDEX_mem_write_en: in vl_logic_vector(3 downto 0);
IDEX_ld_byte_or_word: in vl_logic;
IDEX_cpsr : in vl_logic_vector(31 downto 0);
IDEX_inst_11_0 : in vl_logic_vector(11 downto 0);
IDEX_inst_19_16 : in vl_logic_vector(3 downto 0);
IDEX_inst_15_12 : in vl_logic_vector(3 downto 0);
IDEX_rs_or_rd_data: in vl_logic_vector(31 downto 0);
IDEX_rn_data : in vl_logic_vector(31 downto 0);
IDEX_rm_data : in vl_logic_vector(31 downto 0);
cpsr_result_in_EX: out vl_logic_vector(31 downto 0);
cpsr_we : out vl_logic;
EXID_rd_we : out vl_logic;
EXID_rd_num : out vl_logic_vector(3 downto 0);
EXMEM_data_result: out vl_logic_vector(31 downto 0);
EXMEM_rd_data : out vl_logic_vector(31 downto 0);
EXMEM_rd_we : out vl_logic;
EXMEM_rd_data_sel: out vl_logic;
EXMEM_des_reg_num: out vl_logic_vector(3 downto 0);
EXMEM_mem_write_en: out vl_logic_vector(3 downto 0);
EXMEM_ld_byte_or_word: out vl_logic
);
end arm_ex_stage;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18288)
`protect data_block
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`protect begin_protected
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fNkEkDN5WlCozBEr3V6Tt5l7D3RXQTr8ThnZGNVzjFrn62qsQfXUXwspLBCDpY04
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
dmamst : integer := NAHBMST;
fifodepth : integer := 5;
hslvndx : integer := 0;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#;
haddr : integer := 16#A00#;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcie_master_target_sp605 is
generic (
master : integer := 1;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System In terface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pciedma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 9; -- PCI device ID
vendor_id : integer := 16#10EE#; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#
);
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
dmamst : integer := NAHBMST;
fifodepth : integer := 5;
hslvndx : integer := 0;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#;
haddr : integer := 16#A00#;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcie_master_target_sp605 is
generic (
master : integer := 1;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System In terface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pciedma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 9; -- PCI device ID
vendor_id : integer := 16#10EE#; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#
);
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
package pcie is
component pcie_master_fifo_sp605 is
generic (
memtech : integer := DEFMEMTECH;
dmamst : integer := NAHBMST;
fifodepth : integer := 5;
hslvndx : integer := 0;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#;
haddr : integer := 16#A00#;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcie_master_target_sp605 is
generic (
master : integer := 1;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
rst : in std_logic;
clk : in std_logic;
-- System In terface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pciedma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 9; -- PCI device ID
vendor_id : integer := 16#10EE#; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#FFE#
);
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:13:34 11/16/2015
-- Design Name:
-- Module Name: io_mapping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity io_mapping is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
ram_data : inout STD_LOGIC_VECTOR (3 downto 0);
bus_chip_select : out STD_LOGIC_VECTOR (3 downto 0); -- The chip select lines from the bus
store : in STD_LOGIC;
bus_data : inout STD_LOGIC_VECTOR (3 downto 0); -- The data lines from the bus
bus_ready : in STD_LOGIC; --Ready from the bus
oe : out STD_LOGIC;
bus_status_out : out STD_LOGIC_VECTOR(1 downto 0);
bus_parity : in STD_LOGIC; --Parity from the bus
clk : in STD_LOGIC;
rst : in STD_LOGIC;
read_mode : in STD_LOGIC
);
end io_mapping;
architecture Behavioral of io_mapping is
component Reg is
Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
component io_decode is
Port ( select_line : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal i_data_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_NOR_result : STD_LOGIC;
signal i_reg_data_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_data_out : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_data_en : STD_LOGIC;
signal i_data_bus : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_status_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_status_out : STD_LOGIC_VECTOR(3 downto 0);
--signal i_reg_status_en : STD_LOGIC_VECTOR;
signal i_reg_cs_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_cs_out : STD_LOGIC_VECTOR(3 downto 0);
--signal i_reg_cs_en : STD_LOGIC_VECTOR;
signal i_select : STD_LOGIC_VECTOR(1 downto 0);
signal i_decode_en : STD_LOGIC;
signal i_reg_enables : STD_LOGIC_VECTOR(3 downto 0);
signal i_rst_or : STD_LOGIC;
begin
DECODE: io_decode
port map( select_line => i_select,
en => i_decode_en,
data => i_reg_enables);
REG_DATA: Reg
port map( data_in => i_reg_data_in,
data_out => i_reg_data_out,
enable => i_reg_data_en,
clk => clk,
rst => rst
);
REG_STATUS: Reg
port map( data_in => i_reg_status_in,
data_out => i_reg_status_out,
enable => i_reg_enables(1),
clk => clk,
rst => rst
);
REG_CHIP_SELECT: Reg
port map( data_in => i_reg_cs_in,
data_out => i_reg_cs_out,
enable => i_reg_enables(0),
clk => clk,
rst => rst
);
i_NOR_result <= NOT(address(15) OR address(14) OR address(13) OR address(12)
OR address(11) OR address(10) OR address(9) OR address(8)
OR address(7) OR address(6) OR address(5) OR address(4)
OR address(3) OR address(2));
i_rst_or <= (NOT rst) AND i_NOR_result;
i_decode_en <= ((i_NOR_result AND store) AND (address(0) NAND address(1))) when rst = '0' else '1';
oe <= store;
i_select <= address(1 downto 0) when i_rst_or = '1' else "11";
--Register enable signals
i_reg_data_en <= read_mode OR i_reg_enables(2);
i_reg_status_out(1) <= bus_ready;
i_reg_status_out(0) <= bus_parity;
bus_status_out <= i_reg_status_out(3 downto 2);
--Register inputs and outputs
i_reg_data_in <= data_in when i_decode_en = '1' else i_data_bus;
i_reg_status_in <= data_in(3) & data_in(2) & bus_ready & bus_parity;
i_reg_cs_in <= data_in;
--Data selects
data_out <= ram_data when i_select = "11" else
i_reg_data_out when i_select = "10" else
i_reg_status_out(3 downto 2) & bus_ready & bus_parity when i_select = "01" else
i_reg_cs_out when i_select = "00";
--Tristates
i_data_bus <= "ZZZZ" when read_mode = '0' else bus_data;
bus_data <= "ZZZZ" when read_mode = '1' else i_reg_data_out;
bus_chip_select <= i_reg_cs_out;
ram_data <= data_in when store = '1' else "ZZZZ";
end Behavioral;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila_32768.vhd
-- /___/ /\ Timestamp : Fri Jul 19 12:11:29 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila_32768 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0);
TRIG4: in std_logic_vector(31 downto 0));
END chipscope_ila_32768;
ARCHITECTURE chipscope_ila_32768_a OF chipscope_ila_32768 IS
BEGIN
END chipscope_ila_32768_a;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila_32768.vhd
-- /___/ /\ Timestamp : Fri Jul 19 12:11:29 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila_32768 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0);
TRIG4: in std_logic_vector(31 downto 0));
END chipscope_ila_32768;
ARCHITECTURE chipscope_ila_32768_a OF chipscope_ila_32768 IS
BEGIN
END chipscope_ila_32768_a;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_stub.vhdl
-- Design : bg_mid
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_mid is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_mid;
architecture stub of bg_mid is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[14:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_stub.vhdl
-- Design : bg_mid
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_mid is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_mid;
architecture stub of bg_mid is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[14:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY mips_vram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END mips_vram_exdes;
ARCHITECTURE xilinx OF mips_vram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT mips_vram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : mips_vram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- This package defines identifiers for valid architecture options that can be
-- used for the arch generic in uaa.
library ieee;
use ieee.std_logic_1164.all;
package uaa_pkg is
type arch_type is (UAA_DSA, UAA_FCBT, UAA_SGA);
end package;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
ENTITY cpu IS
PORT ( Data : IN STD_LOGIC_VECTOR(24 DOWNTO 0) ;
Clock : IN STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
r0_stream, r1_stream, r2_stream, r3_stream, rsys_stream, rtemp0_stream, rtemp1_stream : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
debug_state: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; -- Used for debugging
END cpu ;
ARCHITECTURE Behavior OF cpu IS
SIGNAL r0_data, r1_data, r2_data, r3_data, rsys_data, rtemp0_data, rtemp1_in_data, rtemp1_out_data : STD_LOGIC_VECTOR(15 DOWNTO 0) ;
SIGNAL Imedout, Rsysin, Rsysout, ALU : STD_LOGIC;
SIGNAL Rtempin, Rtempout : STD_LOGIC_VECTOR(0 TO 1);
SIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3);
BEGIN
-- Unit Control
unit_control: uc PORT MAP ( Data, Clock, Imedout, Rin, Rout, Rtempin, Rtempout, Rsysin, Rsysout, ALU, debug_state);
-- ALU
logical_unit: alu_component PORT MAP (rtemp0_data, BusWires, ALU, rtemp1_in_data);
-- Registers
reg0: regn PORT MAP ( BusWires, Rin(0), Clock, r0_data ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, r1_data ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, r2_data ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, r3_data ) ;
regsys: regn PORT MAP ( BusWires, Rsysin, Clock, rsys_data ) ;
regtemp0: regn PORT MAP ( BusWires, Rtempin(0), Clock, rtemp0_data ) ;
regtemp1: regn PORT MAP ( rtemp1_in_data, Rtempin(1), Clock, rtemp1_out_data ) ;
-- Tri-States
tri_imed: trin PORT MAP ( Data(15 DOWNTO 0), Imedout, BusWires ) ;
tri_r0: trin PORT MAP ( r0_data, Rout(0), BusWires ) ;
tri_r1: trin PORT MAP ( r1_data, Rout(1), BusWires ) ;
tri_r2: trin PORT MAP ( r2_data, Rout(2), BusWires ) ;
tri_r3: trin PORT MAP ( r3_data, Rout(3), BusWires ) ;
tri_rsys: trin PORT MAP ( rsys_data, Rsysout, BusWires ) ;
tri_rtemp0: trin PORT MAP ( rtemp0_data, Rtempout(0), BusWires ) ;
tri_rtemp1: trin PORT MAP ( rtemp1_out_data, Rtempout(1), BusWires ) ;
-- Debugging Variables
r0_stream <= r0_data;
r1_stream <= r1_data;
r2_stream <= r2_data;
r3_stream <= r3_data;
rsys_stream <= rsys_data;
rtemp0_stream <= rtemp0_data;
rtemp1_stream <= rtemp1_in_data;
END Behavior ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 20:59:47 06/19/2008
-- Design Name:
-- Module Name: idea_com_inner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 2.00 (nnc) - Key can be programmed
-- Revision 2.01 (nnc) - Add loopback mode for cable testing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_com_inner is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com_inner;
architecture Behavioral of idea_com_inner is
-- The UART for the communication with the PC:
component uart
port ( mclkx16 : in STD_LOGIC;
reset : in STD_LOGIC;
read : in STD_LOGIC;
write : in STD_LOGIC;
--data : inout STD_LOGIC_VECTOR (7 downto 0);
rxdata : out STD_LOGIC_VECTOR (7 downto 0);
txdata : in STD_LOGIC_VECTOR (7 downto 0);
sin : in STD_LOGIC;
sout : out STD_LOGIC;
rxrdy : out STD_LOGIC;
txrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC );
end component;
--component idea_hw
-- Port ( CLK : in STD_LOGIC;
-- START : in STD_LOGIC;
-- READY : out STD_LOGIC;
-- KEY : in STD_LOGIC_VECTOR (127 downto 0);
-- X1 : in STD_LOGIC_VECTOR (15 downto 0);
-- X2 : in STD_LOGIC_VECTOR (15 downto 0);
-- X3 : in STD_LOGIC_VECTOR (15 downto 0);
-- X4 : in STD_LOGIC_VECTOR (15 downto 0);
-- Y1 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y2 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y3 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y4 : out STD_LOGIC_VECTOR (15 downto 0));
--end component;
COMPONENT idea_single
PORT(
KEY : IN std_logic_vector(127 downto 0);
clk_in : IN std_logic;
ready_out : OUT std_logic;
start_in : IN std_logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
-- All used signals for the top level are defined here:
signal read : STD_LOGIC := '1';
signal write : STD_LOGIC := '1';
signal rxrdy, txrdy : STD_LOGIC := '1';
signal parity_error, framing_error, overrun : STD_LOGIC := '0';
signal data : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal txdata : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal start_idea, ready_idea : STD_LOGIC := '0';
signal x1, x2, x3, x4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal y1, y2, y3, y4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal key : STD_logic_vector (127 downto 0) := x"00000000000000000000000000000000";
type STATE_TYPE is ( IDLE, WAIT_FOR_DATA, RECEIVED_BYTE, READ_BYTE,
WAIT_FOR_RXRDY_0, WAIT_FOR_IDEA_TO_DEACTIVATE_READY,
WAIT_FOR_IDEA_TO_COMPLETE,
WRITE_BYTE, WRITE_BYTE_NOW, WRITE_BYTE_ACK,
WAIT_FOR_TXRDY_1, LOOPBACK_MODE );
signal state : STATE_TYPE := IDLE;
signal byte_cntr : std_logic_vector(4 downto 0) := "00000";
signal loopback_select : std_logic := '0';
signal z1, z2, z3, z4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
begin
-- The UART module
uart1: uart port map( Clk, Reset,
read, write, data, txdata,
RxD, TxD,
rxrdy, txrdy,
parity_error, framing_error, overrun );
-- The encryption algorithm
-- idea1: idea_hw port map( clk, start_idea, ready_idea, key, x1, x2, x3, x4, y1, y2, y3, y4);
uut: idea_single PORT MAP (
KEY => key,
clk_in => Clk,
ready_out => ready_idea,
start_in => start_idea,
X1 => x1,
X2 => x2,
X3 => x3,
X4 => x4,
Y1 => y1,
Y2 => y2,
Y3 => y3,
Y4 => y4
);
-- mux for loopback mode
mux1 : multiplexer port map(
A => y1,
B => x1,
S => loopback_select,
O => z1);
mux2 : multiplexer port map(
A => y2,
B => x2,
S => loopback_select,
O => z2);
mux3 : multiplexer port map(
A => y3,
B => X3,
S => loopback_select,
O => z3);
mux4 : multiplexer port map(
A => y4,
B => X4,
S => loopback_select,
O => z4);
-- The state machine for the communication:
process ( Clk )
begin
if ( Clk'event and Clk='1' ) then
if ( Reset = '1' ) then
state <= IDLE;
byte_cntr <= "00000";
read <= '1';
write <= '1';
LEDs <= "00000000"; --LEDs <= "00000000"; hier ändern in original
else
if ( state = IDLE ) then
-- Initial state
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
elsif ( state = WAIT_FOR_DATA ) then
write <= '1';
-- Waiting for incoming data.
if ( rxrdy = '1' ) then
-- There is a byte at the receiver!
state <= RECEIVED_BYTE;
end if;
elsif ( state = RECEIVED_BYTE ) then
-- The UART signalizes, that there
-- is a new byte to be read!
read <= '0';
state <= READ_BYTE;
elsif ( state = READ_BYTE ) then
-- Read the byte and set the
-- right input registers of the
-- IDEA block.
LEDs(7) <= '1';
LEDs(0) <= framing_error;
LEDs(1) <= parity_error;
LEDs(2) <= overrun;
byte_cntr <= byte_cntr+"00001";
if ( byte_cntr = "00000" ) then
x1(7 downto 0) <= data;
elsif ( byte_cntr = "00001" ) then
x1(15 downto 8) <= data;
elsif ( byte_cntr = "00010" ) then
x2(7 downto 0) <= data;
elsif ( byte_cntr = "00011" ) then
x2(15 downto 8) <= data;
elsif ( byte_cntr = "00100" ) then
x3(7 downto 0) <= data;
elsif ( byte_cntr = "00101" ) then
x3(15 downto 8) <= data;
elsif ( byte_cntr = "00110" ) then
x4(7 downto 0) <= data;
elsif ( byte_cntr = "00111" ) then
x4(15 downto 8) <= data;
elsif ( byte_cntr = "01000" ) then
key(7 downto 0) <= data;
elsif ( byte_cntr = "01001" ) then
key(15 downto 8) <= data;
elsif ( byte_cntr = "01010" ) then
key(23 downto 16) <= data;
elsif ( byte_cntr = "01011" ) then
key(31 downto 24) <= data;
elsif ( byte_cntr = "01100" ) then
key(39 downto 32) <= data;
elsif ( byte_cntr = "01101" ) then
key(47 downto 40) <= data;
elsif ( byte_cntr = "01110" ) then
key(55 downto 48) <= data;
elsif ( byte_cntr = "01111" ) then
key(63 downto 56) <= data;
elsif ( byte_cntr = "10000" ) then
key(71 downto 64) <= data;
elsif ( byte_cntr = "10001" ) then
key(79 downto 72) <= data;
elsif ( byte_cntr = "10010" ) then
key(87 downto 80) <= data;
elsif ( byte_cntr = "10011" ) then
key(95 downto 88) <= data;
elsif ( byte_cntr = "10100" ) then
key(103 downto 96) <= data;
elsif ( byte_cntr = "10101" ) then
key(111 downto 104) <= data;
elsif ( byte_cntr = "10110" ) then
key(119 downto 112) <= data;
elsif ( byte_cntr = "10111" ) then
key(127 downto 120) <= data;
end if;
read <= '1';
state <= WAIT_FOR_RXRDY_0;
elsif ( state = WAIT_FOR_RXRDY_0 ) then
-- Wait until the UART has acknowledged
LEDs(7) <= '0';
-- that the data has been read.
if ( rxrdy = '0' ) then
if ( byte_cntr = "11000" ) then
-- add loopback mode
if (key = X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF") then
state <= LOOPBACK_MODE;
loopback_select <= '1';
else
start_idea <= '1';
state <= WAIT_FOR_IDEA_TO_DEACTIVATE_READY;
loopback_select <= '0';
end if;
-- added newly: 20130405
-- read <= '1';
else
state <= WAIT_FOR_DATA;
end if;
end if;
elsif(state=LOOPBACK_MODE) then
byte_cntr <= "00000";
state <= WRITE_BYTE;
elsif ( state = WAIT_FOR_IDEA_TO_DEACTIVATE_READY ) then
if ( ready_idea = '0' ) then
state <= WAIT_FOR_IDEA_TO_COMPLETE;
end if;
elsif ( state = WAIT_FOR_IDEA_TO_COMPLETE ) then
-- The IDEA algorithm has computed its results now.
byte_cntr <= "00000";
start_idea <= '0';
if ( ready_idea = '1' ) then
LEDs(1) <= '1';
state <= WRITE_BYTE;
end if;
elsif ( state = WRITE_BYTE ) then
-- Write back the computed data set
byte_cntr <= byte_cntr + "00001";
if ( byte_cntr = "00000" ) then
txdata <= z1(7 downto 0);
elsif ( byte_cntr = 1 ) then
txdata <= z1(15 downto 8);
elsif ( byte_cntr = 2 ) then
txdata <= z2(7 downto 0);
elsif ( byte_cntr = 3 ) then
txdata <= z2(15 downto 8);
elsif ( byte_cntr = 4 ) then
txdata <= z3(7 downto 0);
elsif ( byte_cntr = 5 ) then
txdata <= z3(15 downto 8);
elsif ( byte_cntr = 6 ) then
txdata <= z4(7 downto 0);
elsif ( byte_cntr = 7 ) then
txdata <= z4(15 downto 8);
end if;
state <= WRITE_BYTE_NOW;
elsif ( state = WRITE_BYTE_NOW ) then
write <= '0';
state <= WRITE_BYTE_ACK;
elsif ( state = WRITE_BYTE_ACK ) then
write <= '1';
if ( txrdy = '0' ) then
state <= WAIT_FOR_TXRDY_1;
end if;
elsif ( state = WAIT_FOR_TXRDY_1 ) then
if ( txrdy = '1' ) then
txdata <= "00000000";
if ( byte_cntr = "01000" ) then
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
LEDs(3) <= '1';
else
state <= WRITE_BYTE;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter(7 downto 0);
-- use the register value to fill the variable
frequency(15 downto 8) <= Freq_hi(7 downto 0);
--
frequency(7 downto 0) <= Freq_lo(7 downto 0);
-- use the register value to fill the variable
pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
--
pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency(15 downto 0));
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Altera multiplier
-- lpm_mult_component : lpm_mult
-- GENERIC MAP
-- (
-- lpm_hint => "MAXIMIZE_SPEED=5",
-- lpm_representation => "UNSIGNED",
-- lpm_type => "LPM_MULT",
-- lpm_widtha => 12,
-- lpm_widthb => 8,
-- lpm_widthp => 20,
-- lpm_widths => 1
-- )
-- PORT MAP
-- (
-- dataa(11 downto 0) => signal_mux,
-- datab(7 downto 0) => env_counter,
-- result => signal_vol
-- );
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specifiek values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
else
Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel(3 downto 0) is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context uvvm_util_context is
library uvvm_util;
use uvvm_util.types_pkg.all;
use uvvm_util.global_signals_and_shared_variables_pkg.all;
use uvvm_util.hierarchy_linked_list_pkg.all;
use uvvm_util.string_methods_pkg.all;
use uvvm_util.adaptations_pkg.all;
use uvvm_util.methods_pkg.all;
use uvvm_util.bfm_common_pkg.all;
use uvvm_util.alert_hierarchy_pkg.all;
use uvvm_util.license_pkg.all;
use uvvm_util.protected_types_pkg.all;
end context;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context uvvm_util_context is
library uvvm_util;
use uvvm_util.types_pkg.all;
use uvvm_util.global_signals_and_shared_variables_pkg.all;
use uvvm_util.hierarchy_linked_list_pkg.all;
use uvvm_util.string_methods_pkg.all;
use uvvm_util.adaptations_pkg.all;
use uvvm_util.methods_pkg.all;
use uvvm_util.bfm_common_pkg.all;
use uvvm_util.alert_hierarchy_pkg.all;
use uvvm_util.license_pkg.all;
use uvvm_util.protected_types_pkg.all;
end context;
|
entity array6 is
end entity;
architecture test of array6 is
type int_vec2 is array (natural range <>) of integer_vector;
constant a : int_vec2(1 to 3)(1 to 2) := ( (1, 2), (3, 4), (5, 6) );
begin
main: process is
variable v : a'subtype := a;
begin
assert a(1)(1) = 1;
assert a(3)(2) = 6;
wait for 1 ns;
assert v(1)(1) = 1;
assert v(3)(2) = 6;
assert v = a;
v(1)(2) := 99;
assert v /= a;
assert v(1) = (1, 99);
v(2) := (55, 666);
assert v(2)(2) = 666;
assert v(2 to 3) = ((55, 666), (5, 6));
wait;
end process;
end architecture;
|
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|
`protect begin_protected
`protect version = 1
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
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`protect begin_protected
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`protect begin_protected
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
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`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Recursion unit for recursive code.
--! @author Markus Fehrenz
--! @date 2011/01/12
--!
--! @details The recusion handling buffers the reorder ouput and
--! calculates the correct output depending on the feedback polynomial.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
entity recursionx is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Decoded bits input from the reordering units in std_logic
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic;
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Output decoded bits convolved with the feedback polynomial
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic
);
end entity recursionx;
architecture rtl of recursionx is
signal recursion_sreg : unsigned(ENCODER_MEMORY_DEPTH downto 0);
signal s_axis_input_tready_int : std_logic;
signal m_axis_output_tvalid_int : std_logic;
begin
s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
'0';
s_axis_input_tready <= s_axis_input_tready_int;
m_axis_output_tvalid <= m_axis_output_tvalid_int;
-- Use the feedback polynomial to convolve the global path.
pr_recursion : process(clk) is
variable v_bit : std_logic := '0';
variable v_recursion_state : unsigned(ENCODER_MEMORY_DEPTH downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
recursion_sreg <= (others => '0');
m_axis_output_tdata <= '0';
m_axis_output_tlast <= '0';
else
m_axis_output_tvalid_int <= s_axis_input_tvalid;
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
-- move current decoded output bits into shift register and reset if last flag is valid
if s_axis_input_tlast = '1' then
recursion_sreg <= (others => '0');
else
recursion_sreg <= s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1);
end if;
-- convolve with feedback polynomial with the output register.
v_bit := '0';
v_recursion_state := (s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1)) and
('1' & to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH));
for i in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_recursion_state(i);
end loop;
m_axis_output_tdata <= v_bit;
m_axis_output_tlast <= s_axis_input_tlast;
end if;
end if;
end if;
end process pr_recursion;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc324.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00324ent IS
END c03s02b01x00p04n01i00324ent;
ARCHITECTURE c03s02b01x00p04n01i00324arch OF c03s02b01x00p04n01i00324ent IS
type bit_vctor is array (integer => 1 to 8) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00324 - The index constraint is not valid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc324.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00324ent IS
END c03s02b01x00p04n01i00324ent;
ARCHITECTURE c03s02b01x00p04n01i00324arch OF c03s02b01x00p04n01i00324ent IS
type bit_vctor is array (integer => 1 to 8) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00324 - The index constraint is not valid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc324.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00324ent IS
END c03s02b01x00p04n01i00324ent;
ARCHITECTURE c03s02b01x00p04n01i00324arch OF c03s02b01x00p04n01i00324ent IS
type bit_vctor is array (integer => 1 to 8) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00324 - The index constraint is not valid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00324arch;
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity n is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end n;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of n is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_pow_fcond_power_result1_A : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_A_next : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X_next : sfixed(18 downto -13);
signal pow_fcond_power_result1 : sfixed(18 downto -13);
signal statevariable_none_noregime_q_temp_1 : sfixed (18 downto -13);
signal statevariable_none_noregime_q_temp_1_next : sfixed (18 downto -13);
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
Component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_rateScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_rateScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_alpha : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_alpha_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_none_fcond : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fcond_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_time_tau : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
signal DerivedVariable_time_tau_next : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_none_q_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component forwardRaten1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal forwardRaten1_Component_done : STD_LOGIC ; signal Exposure_per_time_forwardRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component reverseRaten1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal reverseRaten1_Component_done : STD_LOGIC ; signal Exposure_per_time_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
forwardRaten1_uut : forwardRaten1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => forwardRaten1_Component_done,
param_per_time_rate => param_per_time_forwardRaten1_rate,
param_voltage_midpoint => param_voltage_forwardRaten1_midpoint,
param_voltage_scale => param_voltage_forwardRaten1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_forwardRaten1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_forwardRaten1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_forwardRaten1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_forwardRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_forwardRaten1_r <= Exposure_per_time_forwardRaten1_r_internal;
reverseRaten1_uut : reverseRaten1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => reverseRaten1_Component_done,
param_per_time_rate => param_per_time_reverseRaten1_rate,
param_voltage_midpoint => param_voltage_reverseRaten1_midpoint,
param_voltage_scale => param_voltage_reverseRaten1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_reverseRaten1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_reverseRaten1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_reverseRaten1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_reverseRaten1_r <= Exposure_per_time_reverseRaten1_r_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRaten1_r_internal,exposure_per_time_reverseRaten1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
pre_pow_fcond_power_result1_A_next <= resize( statevariable_none_q_in ,18,-13);
pre_pow_fcond_power_result1_X_next <= resize( param_none_instances ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_pow_fcond_power_result1_A <= to_sfixed(0,18,-13);
pre_pow_fcond_power_result1_X <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_pow_fcond_power_result1_A <= pre_pow_fcond_power_result1_A_next ;
pre_pow_fcond_power_result1_X <= pre_pow_fcond_power_result1_X_next ;
end if;
end if;end if; subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamPow_fcond_power_result1 : ParamPow
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_pow_fcond_power_result1_X ,
A => pre_pow_fcond_power_result1_A ,
Output => pow_fcond_power_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRaten1_r_internal,exposure_per_time_reverseRaten1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
derivedvariable_per_time_alpha_next <= resize(( exposure_per_time_forwardRaten1_r_internal ),18,-2);
derivedvariable_per_time_beta_next <= resize(( exposure_per_time_reverseRaten1_r_internal ),18,-2);
derivedvariable_none_fcond_next <= resize((pow_fcond_power_result1),18,-13);
derivedvariable_none_inf_next <= resize(( derivedvariable_per_time_alpha_next / ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ),18,-13);
derivedvariable_time_tau_next <= resize(( to_sfixed ( 1 ,1 , -1 ) / ( ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ) ),6,-18);
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_n : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_alpha <= derivedvariable_per_time_alpha_next;
derivedvariable_per_time_beta <= derivedvariable_per_time_beta_next;
derivedvariable_none_fcond <= derivedvariable_none_fcond_next;
derivedvariable_none_inf <= derivedvariable_none_inf_next;
derivedvariable_time_tau <= derivedvariable_time_tau_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf ,statevariable_none_q_in)
begin
statevariable_none_noregime_q_temp_1_next <= resize(statevariable_none_q_in + ( ( derivedvariable_none_inf - statevariable_none_q_in ) / derivedvariable_time_tau ) * sysparam_time_timestep,18,-13);
end process state_variable_process_dynamics_comb;
uut_delayDone_statevariable_n : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_dyn_ready
);state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_none_noregime_q_temp_1 <= statevariable_none_noregime_q_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,derivedvariable_none_inf,statevariable_none_noregime_q_temp_1,statevariable_none_q_in,derivedvariable_time_tau,derivedvariable_none_inf)
variable statevariable_none_q_temp_1 : sfixed (18 downto -13);
begin
statevariable_none_q_temp_1 := statevariable_none_noregime_q_temp_1; statevariable_none_q_next <= statevariable_none_q_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_none_q <= statevariable_none_q_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_none_q_out <= statevariable_none_q_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_none_fcond <= derivedvariable_none_fcond_in;derivedvariable_none_fcond_out <= derivedvariable_none_fcond;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(forwardRaten1_component_done,reverseRaten1_component_done,CLK)
begin
if (forwardRaten1_component_done = '1' and reverseRaten1_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for DAC AD5668 --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.flink_definitions.all;
use work.dacad5668_pkg.all;
entity dacad5668Device_v1_0_S00_AXI is
generic (
-- Users to add parameters here
base_clk : INTEGER := 125000000;
sclk_frequency : INTEGER := 8000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
internal_reference : STD_LOGIC := '1';
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
osl_ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end dacad5668Device_v1_0_S00_AXI;
architecture arch_imp of dacad5668Device_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rlast : std_logic;
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS =>'0');
CONSTANT c_resolution : INTEGER := 65536;
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_configuration_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_configuration_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_resolution_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_channel_value_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_resolution_address) + 4);
CONSTANT c_usig_max_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_channel_value_address) + 4*NUMBER_OF_CHANNELS);
TYPE t_internal_reg IS RECORD
value_registers : t_value_regs;
conf_reg : STD_LOGIC;
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_reg := (
value_registers => (OTHERS => (OTHERS =>'0')),
conf_reg => '0'
);
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id, 16));
CONSTANT subtype_id : STD_LOGIC_VECTOR( 7 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1, 8));
CONSTANT interface_version : STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ri, ri_next : t_internal_reg := INTERNAL_REG_RESET;
SIGNAL dac_reset : STD_LOGIC := '1';
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= (OTHERS => '0');
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= (OTHERS => '0');
S_AXI_RLAST <= axi_rlast;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
IF(S_AXI_AWSIZE = "000") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_AWSIZE = "001") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_AWSIZE = "010") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_AWSIZE = "011") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_AWSIZE = "100") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_awaddr <= axi_awaddr;
END IF;
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
IF(S_AXI_ARSIZE = "000") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_ARSIZE = "001") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_ARSIZE = "010") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_ARSIZE = "011") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_ARSIZE = "100") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_araddr <= axi_araddr;
END IF;
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
--read data
process( axi_rvalid,axi_araddr,ri ) is
VARIABLE regNum: INTEGER RANGE 0 TO NUMBER_OF_CHANNELS := 0;
begin
if (axi_rvalid = '1') then
-- output the read dada
IF(axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF(axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF(axi_araddr = c_usig_number_of_channels_address)THEN
axi_rdata <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS, axi_rdata'length));
ELSIF(axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF(axi_araddr = c_usig_configuration_address) THEN
axi_rdata <= (others => '0');
axi_rdata(c_fLink_reset_bit_num) <= ri.conf_reg;
ELSIF(axi_araddr = c_usig_resolution_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(c_resolution, axi_rdata'length));
ELSIF (axi_araddr >= c_usig_channel_value_address AND axi_araddr < c_usig_max_address) THEN
regNum := to_integer(unsigned(axi_araddr) - unsigned(c_usig_channel_value_address)) / 4;
axi_rdata <= (others => '0');
axi_rdata((RESOLUTION - 1) DOWNTO 0) <= ri.value_registers(regNum);
ELSE
axi_rdata <= (others => '0');
END IF;
else
axi_rdata <= (others => '0');
end if;
end process;
--write
process( axi_wready,S_AXI_WVALID,S_AXI_WDATA,axi_awaddr,S_AXI_WSTRB,ri,S_AXI_ARESETN)
VARIABLE vi: t_internal_reg := INTERNAL_REG_RESET;
VARIABLE regNum: INTEGER RANGE 0 TO NUMBER_OF_CHANNELS := 0;
BEGIN
vi := ri;
IF(axi_wready = '1') THEN
IF(axi_awaddr = c_usig_configuration_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.conf_reg := S_AXI_WDATA(c_fLink_reset_bit_num);
END IF;
ELSIF(axi_awaddr >= c_usig_channel_value_address AND axi_awaddr < c_usig_max_address) THEN
regNum := to_integer(unsigned(axi_awaddr) - unsigned(c_usig_channel_value_address)) / 4;
IF(S_AXI_WSTRB(0) = '1')THEN
vi.value_registers(regNum)(7 DOWNTO 0) := S_AXI_WDATA(7 DOWNTO 0);
END IF;
IF(S_AXI_WSTRB(1) = '1') THEN
vi.value_registers(regNum)(15 DOWNTO 8) := S_AXI_WDATA(15 DOWNTO 8);
END IF;
END IF;
END IF;
IF(S_AXI_ARESETN = '0' OR vi.conf_reg = '1' )THEN
vi := INTERNAL_REG_RESET;
dac_reset <= '0';
ELSE
dac_reset <= '1';
END IF;
ri_next <= vi;
END PROCESS;
gen_dac: dacad5668
GENERIC MAP (
BASE_CLK => base_clk,
SCLK_FREQUENCY => sclk_frequency,
INTERNAL_REFERENCE => internal_reference
)
PORT MAP (
isl_clk => S_AXI_ACLK,
isl_reset_n => dac_reset,
it_set_values => ri.value_registers,
osl_LDAC_n => osl_LDAC_n,
osl_CLR_n => osl_CLR_n,
osl_sclk => osl_sclk,
oslv_Ss => osl_ss,
osl_mosi => osl_mosi
);
reg_proc : PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
end arch_imp;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_rnd;
architecture behaviour of s298_rnd is
constant s00000000000000: std_logic_vector(7 downto 0) := "10111101";
constant s00000001100000: std_logic_vector(7 downto 0) := "00000010";
constant s10000001100010: std_logic_vector(7 downto 0) := "10011011";
constant s10000001100011: std_logic_vector(7 downto 0) := "10111110";
constant s10000001100001: std_logic_vector(7 downto 0) := "01111111";
constant s10000001100000: std_logic_vector(7 downto 0) := "01010001";
constant s01000001100001: std_logic_vector(7 downto 0) := "10010110";
constant s01000001100000: std_logic_vector(7 downto 0) := "00001011";
constant s01000001100011: std_logic_vector(7 downto 0) := "11001111";
constant s01000001100010: std_logic_vector(7 downto 0) := "10011110";
constant s11001001100011: std_logic_vector(7 downto 0) := "11011011";
constant s11001001100010: std_logic_vector(7 downto 0) := "00101011";
constant s11001001100000: std_logic_vector(7 downto 0) := "01100001";
constant s11001001100001: std_logic_vector(7 downto 0) := "11110000";
constant s00100001100011: std_logic_vector(7 downto 0) := "01101111";
constant s00100001100010: std_logic_vector(7 downto 0) := "00001111";
constant s00100001100001: std_logic_vector(7 downto 0) := "11101011";
constant s00100001100000: std_logic_vector(7 downto 0) := "01011010";
constant s10101001100010: std_logic_vector(7 downto 0) := "00111000";
constant s10101001100011: std_logic_vector(7 downto 0) := "10110110";
constant s10101001100000: std_logic_vector(7 downto 0) := "01001000";
constant s10101001100001: std_logic_vector(7 downto 0) := "00000001";
constant s01101001100010: std_logic_vector(7 downto 0) := "10100100";
constant s01101001100011: std_logic_vector(7 downto 0) := "10111111";
constant s01101001100001: std_logic_vector(7 downto 0) := "10001001";
constant s01101001100000: std_logic_vector(7 downto 0) := "10101001";
constant s11101001100011: std_logic_vector(7 downto 0) := "10100110";
constant s11101001100010: std_logic_vector(7 downto 0) := "10111011";
constant s11101001100000: std_logic_vector(7 downto 0) := "01011100";
constant s11101001100001: std_logic_vector(7 downto 0) := "01100011";
constant s00010001100010: std_logic_vector(7 downto 0) := "11111000";
constant s00010001100011: std_logic_vector(7 downto 0) := "00100010";
constant s00010001100000: std_logic_vector(7 downto 0) := "00111101";
constant s00010001100001: std_logic_vector(7 downto 0) := "01001001";
constant s10010100011010: std_logic_vector(7 downto 0) := "10111000";
constant s10010100011011: std_logic_vector(7 downto 0) := "00011000";
constant s10010100011000: std_logic_vector(7 downto 0) := "01010110";
constant s10010100011001: std_logic_vector(7 downto 0) := "00100011";
constant s00000000011000: std_logic_vector(7 downto 0) := "01000011";
constant s00001100000001: std_logic_vector(7 downto 0) := "10110111";
constant s00001100000000: std_logic_vector(7 downto 0) := "00010011";
constant s00001100000010: std_logic_vector(7 downto 0) := "10110010";
constant s00001100000011: std_logic_vector(7 downto 0) := "11000111";
constant s10000100011001: std_logic_vector(7 downto 0) := "11111111";
constant s10000100011000: std_logic_vector(7 downto 0) := "00001100";
constant s10000100011010: std_logic_vector(7 downto 0) := "10110101";
constant s10000100011011: std_logic_vector(7 downto 0) := "01010100";
constant s10100001100010: std_logic_vector(7 downto 0) := "00000000";
constant s10100001100011: std_logic_vector(7 downto 0) := "01000001";
constant s10100001100001: std_logic_vector(7 downto 0) := "10100010";
constant s10100001100000: std_logic_vector(7 downto 0) := "01011011";
constant s01100001100001: std_logic_vector(7 downto 0) := "11100111";
constant s01100001100000: std_logic_vector(7 downto 0) := "01011101";
constant s01100001100011: std_logic_vector(7 downto 0) := "01001011";
constant s01100001100010: std_logic_vector(7 downto 0) := "00011011";
constant s11101000100110: std_logic_vector(7 downto 0) := "10101111";
constant s11101000100111: std_logic_vector(7 downto 0) := "01101101";
constant s11101000100101: std_logic_vector(7 downto 0) := "01011000";
constant s11101000100100: std_logic_vector(7 downto 0) := "00100101";
constant s00000000100100: std_logic_vector(7 downto 0) := "10100000";
constant s00011000100110: std_logic_vector(7 downto 0) := "00010001";
constant s00011000100111: std_logic_vector(7 downto 0) := "01111100";
constant s00011000100101: std_logic_vector(7 downto 0) := "11000100";
constant s00011000100100: std_logic_vector(7 downto 0) := "00110011";
constant s10011000100100: std_logic_vector(7 downto 0) := "11010111";
constant s10011000100101: std_logic_vector(7 downto 0) := "00000111";
constant s10011000100111: std_logic_vector(7 downto 0) := "11111010";
constant s10011000100110: std_logic_vector(7 downto 0) := "11010110";
constant s00000000100111: std_logic_vector(7 downto 0) := "11111001";
constant s00000000100110: std_logic_vector(7 downto 0) := "10001100";
constant s00000000100101: std_logic_vector(7 downto 0) := "01101000";
constant s01001001100011: std_logic_vector(7 downto 0) := "01000100";
constant s01001001100010: std_logic_vector(7 downto 0) := "01100000";
constant s01001001100000: std_logic_vector(7 downto 0) := "10111001";
constant s01001001100001: std_logic_vector(7 downto 0) := "10000101";
constant s11000001100000: std_logic_vector(7 downto 0) := "00010100";
constant s11000001100001: std_logic_vector(7 downto 0) := "11001100";
constant s11000001100011: std_logic_vector(7 downto 0) := "01111011";
constant s11000001100010: std_logic_vector(7 downto 0) := "11010011";
constant s00011001100001: std_logic_vector(7 downto 0) := "01110100";
constant s00011001100000: std_logic_vector(7 downto 0) := "01001010";
constant s00011001100011: std_logic_vector(7 downto 0) := "01110011";
constant s00011001100010: std_logic_vector(7 downto 0) := "11000110";
constant s10010001100010: std_logic_vector(7 downto 0) := "00110111";
constant s10010001100011: std_logic_vector(7 downto 0) := "11011001";
constant s10010001100001: std_logic_vector(7 downto 0) := "11100000";
constant s10010001100000: std_logic_vector(7 downto 0) := "11110100";
constant s10001100011000: std_logic_vector(7 downto 0) := "11100101";
constant s10001100011001: std_logic_vector(7 downto 0) := "11101110";
constant s10001100011011: std_logic_vector(7 downto 0) := "01110001";
constant s10001100011010: std_logic_vector(7 downto 0) := "11101000";
constant s01001100000001: std_logic_vector(7 downto 0) := "10111100";
constant s01001100000000: std_logic_vector(7 downto 0) := "10100001";
constant s01001100000010: std_logic_vector(7 downto 0) := "00111011";
constant s01001100000011: std_logic_vector(7 downto 0) := "10101000";
constant s11000100011001: std_logic_vector(7 downto 0) := "00011111";
constant s11000100011000: std_logic_vector(7 downto 0) := "10000010";
constant s11000100011010: std_logic_vector(7 downto 0) := "10011010";
constant s11000100011011: std_logic_vector(7 downto 0) := "11111101";
constant s00101100000000: std_logic_vector(7 downto 0) := "11110110";
constant s00101100000001: std_logic_vector(7 downto 0) := "11010000";
constant s00101100000010: std_logic_vector(7 downto 0) := "10010000";
constant s00101100000011: std_logic_vector(7 downto 0) := "00100111";
constant s10101100011001: std_logic_vector(7 downto 0) := "10110000";
constant s10101100011000: std_logic_vector(7 downto 0) := "10000100";
constant s10101100011010: std_logic_vector(7 downto 0) := "01110010";
constant s10101100011011: std_logic_vector(7 downto 0) := "01111110";
constant s10100100011011: std_logic_vector(7 downto 0) := "11111100";
constant s10100100011010: std_logic_vector(7 downto 0) := "01101110";
constant s10100100011001: std_logic_vector(7 downto 0) := "00010110";
constant s10100100011000: std_logic_vector(7 downto 0) := "00110100";
constant s00100100000011: std_logic_vector(7 downto 0) := "01110110";
constant s00100100000010: std_logic_vector(7 downto 0) := "00110101";
constant s00100100000001: std_logic_vector(7 downto 0) := "00110001";
constant s00100100000000: std_logic_vector(7 downto 0) := "11111011";
constant s11001100011000: std_logic_vector(7 downto 0) := "10100011";
constant s11001100011001: std_logic_vector(7 downto 0) := "11001011";
constant s11001100011010: std_logic_vector(7 downto 0) := "10011001";
constant s11001100011011: std_logic_vector(7 downto 0) := "01101001";
constant s01000100000000: std_logic_vector(7 downto 0) := "11110001";
constant s01000100000001: std_logic_vector(7 downto 0) := "11000001";
constant s01000100000010: std_logic_vector(7 downto 0) := "00011010";
constant s01000100000011: std_logic_vector(7 downto 0) := "01110101";
constant s00001010010001: std_logic_vector(7 downto 0) := "11001110";
constant s00001010010000: std_logic_vector(7 downto 0) := "01001100";
constant s00001010010011: std_logic_vector(7 downto 0) := "01000010";
constant s00001010010010: std_logic_vector(7 downto 0) := "00111110";
constant s00000010010000: std_logic_vector(7 downto 0) := "00000100";
constant s10000000011010: std_logic_vector(7 downto 0) := "10010011";
constant s10000000011011: std_logic_vector(7 downto 0) := "00100100";
constant s10000000011001: std_logic_vector(7 downto 0) := "11001000";
constant s10000000011000: std_logic_vector(7 downto 0) := "01101010";
constant s00101001100010: std_logic_vector(7 downto 0) := "11101100";
constant s00101001100011: std_logic_vector(7 downto 0) := "10010010";
constant s00101001100000: std_logic_vector(7 downto 0) := "10000111";
constant s00101001100001: std_logic_vector(7 downto 0) := "00001001";
constant s10001000011000: std_logic_vector(7 downto 0) := "11010100";
constant s10001000011001: std_logic_vector(7 downto 0) := "01100010";
constant s10001000011011: std_logic_vector(7 downto 0) := "11100010";
constant s10001000011010: std_logic_vector(7 downto 0) := "01001111";
constant s01001000011011: std_logic_vector(7 downto 0) := "11011101";
constant s01001000011010: std_logic_vector(7 downto 0) := "10101010";
constant s01001000011001: std_logic_vector(7 downto 0) := "01000000";
constant s01001000011000: std_logic_vector(7 downto 0) := "01100100";
constant s01000000011011: std_logic_vector(7 downto 0) := "10001000";
constant s01000000011010: std_logic_vector(7 downto 0) := "01111010";
constant s01000000011001: std_logic_vector(7 downto 0) := "01000110";
constant s01000000011000: std_logic_vector(7 downto 0) := "10011111";
constant s10011001100001: std_logic_vector(7 downto 0) := "01101011";
constant s10011001100000: std_logic_vector(7 downto 0) := "11100011";
constant s10011001100011: std_logic_vector(7 downto 0) := "11110010";
constant s10011001100010: std_logic_vector(7 downto 0) := "10110011";
constant s00000001100001: std_logic_vector(7 downto 0) := "00111111";
constant s00000001100010: std_logic_vector(7 downto 0) := "10010100";
constant s00000001100011: std_logic_vector(7 downto 0) := "10011101";
constant s10001001100000: std_logic_vector(7 downto 0) := "11000011";
constant s10001001100001: std_logic_vector(7 downto 0) := "01111001";
constant s10001001100010: std_logic_vector(7 downto 0) := "10100101";
constant s10001001100011: std_logic_vector(7 downto 0) := "00010000";
constant s10011010010000: std_logic_vector(7 downto 0) := "00001010";
constant s10011010010001: std_logic_vector(7 downto 0) := "11100100";
constant s10011010010010: std_logic_vector(7 downto 0) := "01010010";
constant s10011010010011: std_logic_vector(7 downto 0) := "11011110";
constant s00000010010011: std_logic_vector(7 downto 0) := "00011110";
constant s00000010010010: std_logic_vector(7 downto 0) := "10100111";
constant s00000010010001: std_logic_vector(7 downto 0) := "01010111";
constant s10010010010011: std_logic_vector(7 downto 0) := "01011111";
constant s10010010010010: std_logic_vector(7 downto 0) := "10001011";
constant s10010010010000: std_logic_vector(7 downto 0) := "01110000";
constant s10010010010001: std_logic_vector(7 downto 0) := "00111001";
constant s10011100011000: std_logic_vector(7 downto 0) := "11111110";
constant s10011100011001: std_logic_vector(7 downto 0) := "00001101";
constant s10011100011011: std_logic_vector(7 downto 0) := "00101010";
constant s10011100011010: std_logic_vector(7 downto 0) := "11010001";
constant s00000100000010: std_logic_vector(7 downto 0) := "10011000";
constant s00000100000011: std_logic_vector(7 downto 0) := "01011110";
constant s00000100000000: std_logic_vector(7 downto 0) := "00100000";
constant s00000100000001: std_logic_vector(7 downto 0) := "00010010";
constant s11100001100001: std_logic_vector(7 downto 0) := "01100110";
constant s11100001100000: std_logic_vector(7 downto 0) := "00100001";
constant s11100001100010: std_logic_vector(7 downto 0) := "10001010";
constant s11100001100011: std_logic_vector(7 downto 0) := "10000000";
constant s10010000100111: std_logic_vector(7 downto 0) := "01001101";
constant s10010000100110: std_logic_vector(7 downto 0) := "10101110";
constant s10010000100101: std_logic_vector(7 downto 0) := "11100110";
constant s10010000100100: std_logic_vector(7 downto 0) := "01111000";
constant s00010000100100: std_logic_vector(7 downto 0) := "00101100";
constant s00010000100101: std_logic_vector(7 downto 0) := "10101101";
constant s00010000100110: std_logic_vector(7 downto 0) := "11001101";
constant s00010000100111: std_logic_vector(7 downto 0) := "10001110";
constant s11100000100111: std_logic_vector(7 downto 0) := "11011100";
constant s11100000100110: std_logic_vector(7 downto 0) := "00110000";
constant s11100000100100: std_logic_vector(7 downto 0) := "11010101";
constant s11100000100101: std_logic_vector(7 downto 0) := "00011001";
constant s01100100000010: std_logic_vector(7 downto 0) := "11001001";
constant s01100100000011: std_logic_vector(7 downto 0) := "01100111";
constant s01100100000001: std_logic_vector(7 downto 0) := "00011100";
constant s01100100000000: std_logic_vector(7 downto 0) := "10111010";
constant s11100100011011: std_logic_vector(7 downto 0) := "10101011";
constant s11100100011010: std_logic_vector(7 downto 0) := "10000001";
constant s11100100011001: std_logic_vector(7 downto 0) := "00000011";
constant s11100100011000: std_logic_vector(7 downto 0) := "01010011";
constant s00011100000001: std_logic_vector(7 downto 0) := "10000110";
constant s00011100000000: std_logic_vector(7 downto 0) := "01001110";
constant s00011100000010: std_logic_vector(7 downto 0) := "00010101";
constant s00011100000011: std_logic_vector(7 downto 0) := "00010111";
constant s00010100000000: std_logic_vector(7 downto 0) := "00101110";
constant s00010100000001: std_logic_vector(7 downto 0) := "11110111";
constant s00010100000010: std_logic_vector(7 downto 0) := "00000110";
constant s00010100000011: std_logic_vector(7 downto 0) := "10110100";
constant s11101100011001: std_logic_vector(7 downto 0) := "00111100";
constant s11101100011000: std_logic_vector(7 downto 0) := "11101010";
constant s11101100011010: std_logic_vector(7 downto 0) := "10001111";
constant s11101100011011: std_logic_vector(7 downto 0) := "11101001";
constant s01101100000000: std_logic_vector(7 downto 0) := "11101101";
constant s01101100000001: std_logic_vector(7 downto 0) := "11000000";
constant s01101100000011: std_logic_vector(7 downto 0) := "11000101";
constant s01101100000010: std_logic_vector(7 downto 0) := "00110010";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "------";
case current_state is
when s00000000000000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "000000";
end if;
when s00000001100000 =>
if std_match(input, "000") then next_state <= s10000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10000001100000 =>
if std_match(input, "010") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100001 =>
if std_match(input, "001") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100011 =>
if std_match(input, "000") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100011 =>
if std_match(input, "010") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100010 =>
if std_match(input, "000") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100001; output <= "100001";
end if;
when s11101001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100001; output <= "100001";
end if;
when s00010001100010 =>
if std_match(input, "000") then next_state <= s10010100011010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10010100011010 =>
if std_match(input, "011") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011011; output <= "000000";
end if;
when s00000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "010100";
end if;
when s10000001100010 =>
if std_match(input, "010") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "100001";
end if;
when s11001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100010; output <= "100001";
end if;
when s00100001100000 =>
if std_match(input, "001") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100010 =>
if std_match(input, "011") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100001 =>
if std_match(input, "011") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100110 =>
if std_match(input, "000") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100110 =>
if std_match(input, "001") then next_state <= s10011000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100100; output <= "100010";
end if;
when s00000000100100 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100010";
end if;
when s10000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100001; output <= "100001";
end if;
when s01001001100011 =>
if std_match(input, "011") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100000; output <= "100001";
end if;
when s00100001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100001; output <= "100001";
end if;
when s10100001100011 =>
if std_match(input, "011") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100000; output <= "100001";
end if;
when s11101001100010 =>
if std_match(input, "011") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100001 =>
if std_match(input, "011") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10010001100010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100001";
end if;
when s00001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011010; output <= "000000";
end if;
when s10001100011000 =>
if std_match(input, "010") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011011; output <= "000000";
end if;
when s11000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000011; output <= "010100";
end if;
when s00101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000001 =>
if std_match(input, "001") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011010; output <= "000000";
end if;
when s11000100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000000; output <= "010100";
end if;
when s00100100000011 =>
if std_match(input, "011") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011010; output <= "000000";
end if;
when s00100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011011; output <= "000000";
end if;
when s00100100000000 =>
if std_match(input, "000") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11000100011010 =>
if std_match(input, "011") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11000100011011 =>
if std_match(input, "010") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000000 =>
if std_match(input, "000") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11001100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000011; output <= "010100";
end if;
when s11001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000010; output <= "010100";
end if;
when s11001100011010 =>
if std_match(input, "000") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11001100011011 =>
if std_match(input, "001") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011001; output <= "000000";
end if;
when s01001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011010; output <= "000000";
end if;
when s10001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000011; output <= "010100";
end if;
when s01000100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011001; output <= "000000";
end if;
when s01000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011001; output <= "000000";
end if;
when s01000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011010; output <= "000000";
end if;
when s01000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011010; output <= "000000";
end if;
when s10001100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000000; output <= "010100";
end if;
when s10001100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000011; output <= "010100";
end if;
when s00001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011011; output <= "000000";
end if;
when s10000100011000 =>
if std_match(input, "001") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000000; output <= "010100";
end if;
when s10000100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000011; output <= "010100";
end if;
when s10000100011011 =>
if std_match(input, "011") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000000 =>
if std_match(input, "011") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10010001100011 =>
if std_match(input, "001") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
end if;
when s10010001100001 =>
if std_match(input, "000") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00001010010001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000000011000; output <= "001100";
end if;
when s10000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "010100";
end if;
when s01000001100010 =>
if std_match(input, "000") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100010 =>
if std_match(input, "000") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100000; output <= "100001";
end if;
when s11000001100011 =>
if std_match(input, "010") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100010 =>
if std_match(input, "001") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100011 =>
if std_match(input, "011") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100000 =>
if std_match(input, "001") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100001; output <= "100001";
end if;
when s11000001100001 =>
if std_match(input, "001") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "100001";
end if;
when s10000000011011 =>
if std_match(input, "001") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "100001";
end if;
when s01001001100000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100001; output <= "100001";
end if;
when s11001001100010 =>
if std_match(input, "001") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01001001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "100001";
end if;
when s10000000011001 =>
if std_match(input, "010") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10000000011000 =>
if std_match(input, "000") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s00001010010000 =>
if std_match(input, "000") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s10001000011000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "010100";
end if;
when s01001000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100000; output <= "010100";
end if;
when s01001000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "010100";
end if;
when s01001000011001 =>
if std_match(input, "001") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001000011000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10001000011001 =>
if std_match(input, "001") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s01000000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "010100";
end if;
when s01000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "010100";
end if;
when s01000000011001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "010100";
end if;
when s01000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "010100";
end if;
when s10001000011011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "010100";
end if;
when s10001000011010 =>
if std_match(input, "000") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s00001010010011 =>
if std_match(input, "010") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00001010010010 =>
if std_match(input, "000") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00000010010000 =>
if std_match(input, "011") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s10000001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100000; output <= "100001";
end if;
when s10010001100000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00011001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100010; output <= "100001";
end if;
when s10011001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100011; output <= "100001";
end if;
when s00000001100001 =>
if std_match(input, "010") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10001001100000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "100001";
end if;
when s10001001100001 =>
if std_match(input, "000") then next_state <= s01000000011001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100010 =>
if std_match(input, "010") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "100001";
end if;
when s00000001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100001";
end if;
when s00000001100011 =>
if std_match(input, "011") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100000 =>
if std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "110") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "-00") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100010 =>
if std_match(input, "000") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "1-0") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100001; output <= "100001";
end if;
when s00011001100011 =>
if std_match(input, "011") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100011; output <= "100001";
end if;
when s11101001100001 =>
if std_match(input, "000") then next_state <= s00010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00010001100001 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100001";
end if;
when s10011010010000 =>
if std_match(input, "011") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010000; output <= "001100";
end if;
when s00000010010011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "001100";
end if;
when s00000010010010 =>
if std_match(input, "011") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s00000010010001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "001100";
end if;
when s10011010010001 =>
if std_match(input, "001") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "100") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "-10") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010010 =>
if std_match(input, "000") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "111") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "-01") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010011 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010010; output <= "001100";
end if;
when s00010001100000 =>
if std_match(input, "011") then next_state <= s10010010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s10010010010011 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
end if;
when s10010010010010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "001100";
end if;
when s10010010010000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s10010010010001 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s00010001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100001";
end if;
when s10011100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000001; output <= "010100";
end if;
when s00000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011000; output <= "000000";
end if;
when s00000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011010; output <= "000000";
end if;
when s00000100000000 =>
if std_match(input, "001") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011010; output <= "000000";
end if;
when s10011100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000001; output <= "010100";
end if;
when s10011100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000011; output <= "010100";
end if;
when s10011100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000001; output <= "010100";
end if;
when s11101001100000 =>
if std_match(input, "011") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100001 =>
if std_match(input, "000") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11100001100001 =>
if std_match(input, "001") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s00011000100111 =>
if std_match(input, "000") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10010000100111 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
end if;
when s10010000100110 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100010";
end if;
when s10010000100101 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
end if;
when s10010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100010";
end if;
when s00011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100100; output <= "100010";
end if;
when s10011000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100111; output <= "100010";
end if;
when s00000000100101 =>
if std_match(input, "001") then next_state <= s10001001100011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
end if;
when s00000000100110 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100010";
end if;
when s00000000100111 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100010";
end if;
when s10011000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100101 =>
if std_match(input, "011") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "1-1") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "1-0") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100101 =>
if std_match(input, "000") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100001100000 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100111; output <= "100001";
end if;
when s00010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010010010011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100010";
end if;
when s00010000100101 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100010";
end if;
when s00010000100110 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "100010";
end if;
when s10010100011000 =>
if std_match(input, "010") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011001 =>
if std_match(input, "010") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "010100";
end if;
when s00010000100111 =>
if std_match(input, "011") then next_state <= s10011100011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
end if;
when s11100001100010 =>
if std_match(input, "001") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100001100011 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100001";
end if;
when s01101001100011 =>
if std_match(input, "000") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100000 =>
if std_match(input, "011") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100011 =>
if std_match(input, "010") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100100; output <= "100010";
end if;
when s11101000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100110; output <= "100010";
end if;
when s11101000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100100; output <= "100010";
end if;
when s01100001100010 =>
if std_match(input, "010") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100000100111 =>
if std_match(input, "011") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100010";
end if;
when s11100000100100 =>
if std_match(input, "011") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100010";
end if;
when s01100001100000 =>
if std_match(input, "001") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s10100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100000; output <= "100001";
end if;
when s10101001100011 =>
if std_match(input, "001") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100010; output <= "100001";
end if;
when s10101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100010; output <= "100001";
end if;
when s10100100011000 =>
if std_match(input, "001") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011000; output <= "000000";
end if;
when s11100100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000011; output <= "010100";
end if;
when s00011100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011000; output <= "000000";
end if;
when s00011100000000 =>
if std_match(input, "000") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00011100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011001; output <= "000000";
end if;
when s00011100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011010; output <= "000000";
end if;
when s11100100011010 =>
if std_match(input, "001") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00010100000000 =>
if std_match(input, "010") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011000; output <= "000000";
end if;
when s00010100000010 =>
if std_match(input, "001") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000011 =>
if std_match(input, "000") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000010; output <= "010100";
end if;
when s11100100011000 =>
if std_match(input, "010") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011011; output <= "000000";
end if;
when s11101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000001; output <= "010100";
end if;
when s11101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000001; output <= "010100";
end if;
when s11101100011010 =>
if std_match(input, "011") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000000; output <= "010100";
end if;
when s01100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011011; output <= "000000";
end if;
when s01100100000000 =>
if std_match(input, "000") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000010; output <= "010100";
end if;
when s01101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011000; output <= "000000";
end if;
when s01101100000001 =>
if std_match(input, "011") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s01101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011001; output <= "000000";
end if;
when s01101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011010; output <= "000000";
end if;
when s10100100011011 =>
if std_match(input, "011") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10100100011010 =>
if std_match(input, "001") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000010; output <= "010100";
end if;
when s10101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000010; output <= "010100";
end if;
when s10101100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000000; output <= "010100";
end if;
when s10101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000011; output <= "010100";
end if;
when others => next_state <= "--------"; output <= "------";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
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