content
stringlengths 1
1.04M
⌀ |
|---|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity OneByteRegister is
Port (
clk : in STD_LOGIC;
load : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end OneByteRegister;
architecture Behavioral of OneByteRegister is
begin
loadproc:
process (clk)
begin
-- if (rising_edge(clk)) then
if (falling_edge(clk)) then
if (load = '1') then
dataOut <= dataIn;
end if;
end if;
end process loadproc;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising_edge (Clk)) then
if(rst = '0') then
DAT_out <= Dat_In;
else
DAT_out <= "00000000000000000000000000000000";
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising_edge (Clk)) then
if(rst = '0') then
DAT_out <= Dat_In;
else
DAT_out <= "00000000000000000000000000000000";
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
Port ( DAT_in : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
DAT_out : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture Behavioral of PC is
begin
process (clk,rst)
begin
if (rising_edge (Clk)) then
if(rst = '0') then
DAT_out <= Dat_In;
else
DAT_out <= "00000000000000000000000000000000";
end if;
end if;
end process;
end Behavioral;
|
-- --------------------------------------------------------------
-- Title : Debounce Logic
-- Project : Counter
-- -------- ------------------------------------------------------
-- File : gen_debouncer_.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 31.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : Debounce input signals from switches and buttons
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 31.10.2017 1.0 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gen_debouncer is
generic(
N : integer := 16);
port(
clk_i : in std_logic; -- input clock
reset_i : in std_logic; -- input reset
data_i : in std_logic_vector(N-1 downto 0); -- N signals to debounce
q_o : out std_logic_vector(N-1 downto 0)); -- debounced signal
end gen_debouncer;
|
-------------------------------------------------------------------------------
-- Title : UART receiver/transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity uart is
generic (
RESET_IMPL : reset_type := none
);
port (
txd_p : out std_logic;
rxd_p : in std_logic;
din_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic;
re_p : out std_logic;
dout_p : out std_logic_vector(7 downto 0);
we_p : out std_logic;
error_p : out std_logic;
full_p : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
clk : in std_logic);
end uart;
-------------------------------------------------------------------------------
architecture behavioural of uart is
signal busy : std_logic := '0';
signal clk_tx_en : std_logic := '0';
begin
-- 1/5 clock divider for generating the transmission clock
divider : process (clk)
variable counter : integer range 0 to 5 := 0;
begin
if rising_edge(clk) then
if clk_en = '1' then
counter := counter + 1;
if counter = 5 then
counter := 0;
clk_tx_en <= '1';
end if;
else
clk_tx_en <= '0';
end if;
end if;
end process;
-- Receiver
rx : uart_rx
generic map ( RESET_IMPL => RESET_IMPL )
port map (
rxd_p => rxd_p,
disable_p => busy,
data_p => dout_p,
we_p => we_p,
error_p => error_p,
full_p => full_p,
clk_rx_en => clk_en,
reset => reset,
clk => clk);
-- Transmitter
tx : uart_tx
generic map ( RESET_IMPL => RESET_IMPL )
port map (
txd_p => txd_p,
busy_p => busy,
data_p => din_p,
empty_p => empty_p,
re_p => re_p,
clk_tx_en => clk_tx_en,
reset => reset,
clk => clk);
end behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1462.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01462ent IS
END c08s07b00x00p04n01i01462ent;
ARCHITECTURE c08s07b00x00p04n01i01462arch OF c08s07b00x00p04n01i01462ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
variable p : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 2 then
p := 1;
elsif delay = 1 then
k := 1;
else
n := 1;
end if;
assert NOT((m = 0) and (p = 0) and (k = 1) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01462"
severity NOTE;
assert (m = 0) and (p = 0) and (k = 1) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01462 - only the condition after the second ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01462arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1462.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01462ent IS
END c08s07b00x00p04n01i01462ent;
ARCHITECTURE c08s07b00x00p04n01i01462arch OF c08s07b00x00p04n01i01462ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
variable p : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 2 then
p := 1;
elsif delay = 1 then
k := 1;
else
n := 1;
end if;
assert NOT((m = 0) and (p = 0) and (k = 1) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01462"
severity NOTE;
assert (m = 0) and (p = 0) and (k = 1) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01462 - only the condition after the second ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01462arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1462.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01462ent IS
END c08s07b00x00p04n01i01462ent;
ARCHITECTURE c08s07b00x00p04n01i01462arch OF c08s07b00x00p04n01i01462ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
variable p : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 2 then
p := 1;
elsif delay = 1 then
k := 1;
else
n := 1;
end if;
assert NOT((m = 0) and (p = 0) and (k = 1) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01462"
severity NOTE;
assert (m = 0) and (p = 0) and (k = 1) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01462 - only the condition after the second ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01462arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR
/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs
Wa/ntbD9A7gQTxiux5YljYgGyLOT/9s/aTdgKJoDOsqqUyUxTQ7SY+5XXQWupeCMuNptCUFl1pbL
eo8+6sdU2QlvHcKKxXnUej1F69sbqTfZYSXOCR3gJF4tJrsJszLIH8LO4HAbS24TJwNC+WZfrV5i
e0ymUF+FCnLVE7tiAh6mk7X3nIHhYF/Mj0cIuq0wRyjOfp61Nnd9xOUnELPjNvM0Ovw47MabhMPo
upGT17SKfeuLyEBSi0IRB05ViJlrIjcvA5J1+w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ss/YXNSnBDeKAHkqMWMBl0au7TJkur4GPPPBQgp4DOGHgNqm7epu6Veaj+9izoe1kUIoHW/cI0fo
rldl2CaEVtrnvyBOZHq5E/B/y+VfRkFLkqobLN6CVdCYSTI2zsf0YU2F+faYHzYI+wjtI1ItfssZ
aGiDdKo3Tu+ThXC7F/f8rStV5zGMiM5YgiAwKA7HSRhOQkKKXCvYYb0GyY/DyYIWi5UYyPfsTclh
2cL1VJimb7mNhI0zC//b2WxC9bo7/dDpJPAwbL/kb3fE0gQ12PtNg1+FfOpkmoDiEA6WgRzMr/8O
pEUMiMNYVA/eYnW82bTzp7XYvL3lxpVY/C2f5A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
HfF0P1NdmPyToATiwr9GlQXlEuTl0731HxDRMl9UNvBfImykEW/n9a6KRO68F8GLrcimAqIWDGMq
pp0Bul6xe6+kHCj5XCgqAj6kzB+Q/m/uxysXzD4QDsrfKG7p6s+U7RjsJmG6gkxBCaGBkt/izSHy
cD8AD2EKaq4iEznEur1XVhCVCZEmtvCV0zLjeNFZzKHx2rXnKfdF0hDPemE4JcaI2YYyiWqnl4G3
xMUwnJEKEFmFA0UR5XDJ6gJFr1sauhaetPtJBcr7GpgkH3GHk+Y4iA1VGJZ47KMdfGpzdlaMVK5T
7LcLb0yWecwTXyw7gfAyBz608j5AwyXBxPm3F91RRKfnNCSnzifM5yx4s634TfydAphdpM4TvWNn
t8eq3+C2lXhjKvEhrU+2LTuTSSnIYk1Bg5y0kLw47fXV93By3Wh9iHFEJ3bthuQN54NUbmGzHE9k
cmBPRJ9+9t4I4heZD3KAUcDQlEGkPrpa8c9tJ66eITwcFv0Q61A30n/M5mvoeFn5y0KUtqXmruDG
aIswrgcrw7mV+bPzhmCZfXxH9rN3gXmZdvAcCEFXytWUzqzCq71d0qIX+H7p5RQEU1NwtaFiM800
B8gY1AtJj7RgBGq0qpK36YgNdkd/vIaOoG7Pyx7Qz7vafVXuXWs38PezYAqvy7g6U/B1BDW7JQnN
Shv4WF4ZxAkqjd65wMdS7xs7zkUvwdAtuM+ZFreVzzt9WGJOuPwHZ0yb/jUsDwKXUNZ+l4qvhMt6
HqYIsCA4MiX46kltZiweP5zTVz5/mtlnBNOH5Rvls4r5RQ+qgG1U31gB3Un7fbwSPru2SJdfF1t2
axfMrVbMTh2yxDu8pv9abJRBZgu2PXAG5Ed6h6/De7Q3gR4EFUKMkhgSFdPQWzdUTQt6zQPoiWPo
Qi4SsPDfIDFpMpcWqEb15LV6d51Bq2NBWegfCntYWGhWhvIeyb/gZCCvkiZAnvSMc095Ai9bvMr3
a1JWQ3A3S1S8wDWGBxaXBUhPC/Ivme6ytsUXYMHiMHZ7IZOSPNO0m7meINDHlsJ4RebsLyVPn82t
CTUJiEX3iZ00MKhNUQ1QaK8RDyvum+JE+sH+6cbtMG3OwP8dBLT4KhpFP2ba4jw6C161nLy2ebzv
2od/tcyfmer+KiNP12XNrwUFwieM6mON/y0imNeMlDpnTy9GyuVmhhqgwU8yluGtC7qeLUND1iwi
GKk2NxGgkqvS2Lcb1l888wqG1pM3EP4EBXCcFSr2rpH5vLG04cghcZQ7g1WWhbV/GPNUUSsoj4w5
VwYYr8OGJdbnj+Y4f6JcQkeM+CNpS4t5f34p5KJMH3EBmNAabImfCUtsOZCeBgzUYnJ9NbTLdryV
9mlsNrXJCM8Ryhmt/OwqHa5V1t96iEgMBo6eFpH0emB95b1bVllcVmc88Y3a0qY8By9m4cYzpwUt
TcvEtMrQqzK3VcySiGf28H92H6Sk0IVsipT+27/9EWwKKYParVNJq+8YeUMfnFNCeSYMR6c/pyZ4
Pfw3Qn7fEuHAgW6WHiYFFO3DphHrs30SLT3M+PXo9eGM0lEP/JQRdPL+j5kgA7PvBi8E3OKvrQ5X
E8Iq3OtRGrAGGTpA5TmCI8v/mguzvJWRlYE7MFUwV+/HB69dm/dsWJiAkrn+nqxOTLTcPeaV28II
zWAObR6gALTmoFsO0E80P4y3WLy/eC2R/kdqIclXJctQJtZ6eOjCR9ObeGhK+1bRvATq4xgBtX3U
L5q4FoCuHmpLc2BJ7nOeo4T6q8f2sY/7L661cvBUIixa/qbACu8LL/FT/h2SLQa729GRaDX+g5Cd
xXd2drba6Y+30VZmQaqTTeZKiEwpgE7p/5GbQ002yL0DsxnmZomkemMwar6w2H40w9hcE8zQnH4u
n8FqQtlT83ZldpoCS0oqo0hvH8YNyGP5Qrf5NgGcRlNyb2mcd/qAchkwhGuQfsdYNBD6lVHIswfn
dU90s9upNdhfQniiOBCs0qDZwiSU23GZMKfmgtAWL7pDRFp1l0rHEtus+xEF8f3zL5wKM20lhH4G
AlIy8vV3/xiCyJSyrOAoXxutRnR2tVUgcmqKsdvcqm1OdnvkuSkqF+wQKrWGBR84ofRCubT2ZuYO
VIpPjVlNzl98v1B+10tRA9oALRIvUhqHBQsT4tV2609SVugYjbsJyIC71jjoOP6DhrpP0CeRA4OG
oH3rAZOLsOR4aEaEGrGoUM1pDqRikeXwjhzAGvaHI7M4EqycN0/qvRUu90A++4WAb7boAKL5lz3e
LFdMgg9Zcf1WJAzp00ydP9W8wCdCWAv78r9ddkowv8a+roXU/q0LacgcuXoN7Pgde3Qe/Ola0qj0
TK18fGC6wHP0h+KWFGqqt6Y54Hd8XE0AUxrPuG3mpsfGKLDQIBLa3DBU8wOAByGRSGUWEsvmvsHO
M2tyHpjSfcDB/4ZixqcfpMA7FV6jHi7X9a+AithcL4KWndZipM0TVwUO9oYIccqF12+/CZsy7DTS
kvA1eOySWZv0rWdr4VMzq09+VYpW1kW+TTFsl4xMC2mAfR7/t6s9/h6MBfd+euFSoau+Uv73UvS5
8pd+LgUEqDVokVXLCNRmix1Cyda6Dmgw2O0DHctwhklPikjjHVx3iM6hu8qPU3ynxosYVPPYUNAb
dIVYdvIyDjOOT1WkF12bbbF+q/TCch2lZpf4U6ApCKiNaTVV1cN+3P3QhldokmkplPW/VZPV+iLk
Ob7gn7sBiHLUq4bQ8Vbk990GKmfbE8a1rOJ8yDLHrztTCKqUG542RcOtaVqHw/XF7q4MD19dLtDY
LAQdXMiT4Hd3lE5LqYeYp/kfvvLC9XnnoIkXWY1SdURL0cLBp99MGeOptIbodTx1onuRMCf2NlhA
gwaWOFO8SLMUCMdR6BRXJJHnbagjB9ywY/sQZf5mK5x1Xlyd3UMo0LifYleQPEHGEZ2jCC5q2VeF
KJTtQ3Ph6D4e5lBRKsd3F4l5u+9WZZLQs/d/F1KLoBNGtcHsItgv3EAhiePESY+bf/xV+0R1c0eS
5nlAraVMrreGf+qnqAPpixxLXLuXB5I4b8gQdogCQ0lfiXs2FG9cgWTt8oQczW+Tl4/0Jb+AnsV0
d4nrcVWgqpfmUzjSqqYexq3jvGijSy4NEF5JD3s3QVySPkN0dTXOnnvtC1Di2wKSQVltRp0L/6Ht
1PwjJClWpVpFywFbkW7VyRTvpPK3PFVzq9CUvM+Laret6nRuG7221jRpdtcXJkrDH/Hv+qGPbcSA
MG7OTF+4H6wLmvd/nIyPeG0ATkWvnDb8orfBA5NLkeKHhkPfT8ack97bCdWOpwcH4oQPiCIAuOy/
h7FKMuxr9i3BBoAUT1Ngpw6JE74MGA0ldUsG7QChCcPJNfrLv3Udm9AM8nV0EP8V3P6Ihk0d9Rpr
7kurwSYTFfauh2CoCSdjLjaxbXVeATyORdARNEdXmSuguKVfawpPbALC7iXNuLhdNoRzNJNLZNX1
jyRVRVbxga12oeZgLRcFhhutVmSZjKh1ltv3wN5onrm7+r4D6H8dEg/WSZHQ25RjEQkmqzcxtyyk
sgxXfHUQjkti5oteydJFYTJRxNuK1yFZqISjWpwtRUf8Z+Xk/D++BBQorBS7N18fZGH37srom2Ft
gUZ1YJjvb5bQxWzex+CbYVsCSvHvNB1jZG5ctdU3AmUCNnRU698bIPEyysbNhW1Gu1XgTWs0BFhd
It7FjZC1cuPK3LeD4ub7og0c2gsBJA+F0kW/XEpEzgNv1RHi+h0HHt+AAgirMoBMW5XF2nNfBGWl
JyfsjKExLX4rzliLB28esXPN0D1ivJTrR9fstNOnMiDMcw+wOhyWe0Eo82EFoGC0jiP1D7U0ekeI
3yrb5VoO6FZVj9I0igxU16G47gWYGk50kuTAaEbyIvr3Oe0bEDH6kwTr+tnkrHkBWtwA9gJdntjO
D8FXlfrL1EXDBq6V943fEsHLqQfEU06sAOwzg9hzhW4yKlTiebu1oXEMLh4VhDvG9gcr0Wyvl16j
Hbz/U5wGNSTIIer5oP3qgCyv2qUk7pJ18exdLXdojphYEOptFYQfjQGUVyM/ex8DCZ3YcEsyDMx1
kqYsxpv2qjnRFrScMIC65Sa6tu7NzeqYqrLfo/YnXO7QDHaXVhpcxbokQHaqpyuPGldbr7QrupAq
jiJAB/CoXBYJXQxlSVTECthHPnJDpfftDPI/HXHUbKDSkGDN/fZHiasSkT4cPn+q9Hr8ZWm5pmFR
OtUPXwCj8RSBo94JrQhpJgXEkmGpIpo1QMsPjmyFOyWcBco2olRYd2BThTsFFXlLjAeGNIoVGmLn
OQuxmPKpTWMjjiSp93dk2XfK4q1WaVA8VajaOh7FIWU6znO2WPv83sZwVcbPueEw0uDfgZyp9rXS
87Ym1CeBm/EOZX+tl0RyUe3vd9Vf3Y8kZjD2qhS121rKBSjoEbAdK+EuAnEPCjFeWjh2qID+R+Aq
nbhTqYYTsFxyCHjDymCvKLZqqX+8cw5gCEfIw127+KMBZCaMm0lE1o7f+jCdbFlCkDj3LUJX5ACF
jgoR5x5bKRWbQK0lFBP0xLQF2hKHOsrMgwKT7TGHdPnAJiBCtLHdoo8m9x76YBGtoIuXQsMOpKd8
0C5cr8MgHT64Uu9naXok3yypCfgbz6iqqh3nyYusoMPqwkR+SyGeL7AU6RPFZe+zUnoQMmuwhWHL
DFekgK5LJSxJPlpfglmlBEl05byMPkOovUUWeo7w384W4JVkzSn5Ch271cyGoW8J1CfAOZMKI8qu
fWMhYzbvbLN5wT93pvj4eZZJ1tGEUsdC+1F1tbFGmJmEJn897tEangKffNchmO+jLW/boXLPtun1
ievO0uz+AjxBiAPhKoy+AkUwFZgEq6yNo09rpxYrzfRonQNuwZDaZHeUnbi+CAcYBH+Y9IH6yuDX
Q0m4E6LbJ4GYt/ztIT3AIZcxtY/j0GpKP08hU9ZZIaR1j5sCSqCUmJDhS7EQMa60MOMPXRNR8e1T
zwrFBgL5l+OieC2Rq7bwt2pqqQb+aYs44VTBFojMhCOlaKCToJvRbjm4xuqsgDspEOcN7wT9+AeC
aXyoOC9Dcwq7hRUp/UXOklPzrt2Fom+M0G05/CoBM2J5Ay4fFjuwnGAsomdvk1MxPVyCfN4JN16A
40XtcqtrLC7Ix95uc9Y2xplmNZ65e+W3GT/A+N/YC0TC6EjF+ICUpdvG1LXOraE6bI6b5/oPNgKJ
BYihlI71lIH/rZK6X/3CodLBO6lwC+f1WBYK7oDPw7ROl758cw7ZVg0MfMo4eR/krN935kce/ByJ
5alFoS3rmqW66llEhligc1FUephHbM6ZOEXLGzUMlhq9KmmqXoTzme98
`protect end_protected
|
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
|
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
|
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
|
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
|
entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_ibea_entity;
ARCHITECTURE fir2_ibea_description OF fir2_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := not input3 or input3;
register3 := not input4 or input4;
register4 := not input5 or input5;
register5 := not input6 or input6;
WHEN "00000011" =>
register6 := not input7 or input7;
register4 := register4 + register5;
register5 := not input8 or input8;
register1 := register1 * 10;
WHEN "00000100" =>
register5 := register5 + register6;
register6 := not input9 or input9;
WHEN "00000101" =>
register2 := register2 + register6;
register5 := register5 * 13;
register6 := not input10 or input10;
register4 := register4 * 16;
register7 := not input11 or input11;
WHEN "00000110" =>
register4 := register4 + register5;
register2 := register2 * 19;
register5 := not input12 or input12;
register8 := not input13 or input13;
register6 := register6 + register7;
WHEN "00000111" =>
register3 := register5 + register3;
register5 := register6 * 23;
register6 := not input14 or input14;
WHEN "00001000" =>
register3 := register3 * 26;
register4 := register5 + register4;
register5 := register8 + register6;
WHEN "00001001" =>
register5 := register5 * 28;
register2 := register2 + register4;
register4 := not input15 or input15;
WHEN "00001010" =>
register2 := register5 + register2;
register5 := not input16 or input16;
WHEN "00001011" =>
register2 := register3 + register2;
register3 := register5 + register4;
WHEN "00001100" =>
register1 := register1 + register2;
register2 := register3 * 32;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_ibea_description; |
library verilog;
use verilog.vl_types.all;
entity altstratixii_oct is
generic(
lpm_type : string := "altstratixii_oct"
);
port(
terminationenable: in vl_logic;
terminationclock: in vl_logic;
rdn : in vl_logic;
rup : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altstratixii_oct;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
M97EkI6FhFz4Yo9U2K8wRigNx57fOt8lVFwA+PXfyNL8UGSMupnT7hTMt0ju4oDTMPXOS5gETSpL
9PU25LWmng==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AMVIiS9DwkcMnAPtd9qYYC7sZmD8LBW3VN3FgxDycsSmKhvE4eadqAZNup2akZhDeGMY5EynH4YS
bpsmoGoAc4x95hwDPsGRuJwLaDvRRqCtIbHF6oDCj/HAR9KfosbqgEc/5q41XQC9BXrGgMyyyBgR
9e6/PlPx0UNQ5YXPHOA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
p2fWngAziDA7L9sbbXdBKa3pCTwKU0nYubaiDHU5CH71VmlJ5/3TydfkjEICoY8ZHgnkXAKiGO5i
PmaCnLk+H8GtnKa2CPT1gXVdWbSNu53kEiyg3tw1CCqp8CcX+MjpgC0kWJPlRgz9SX5dgwCErSOE
3xq/fyXb3UwyRBbdxsNGUlXZEopVrkVWEHm/crcwigJdZJKJkJ9wmAnciNeqI1geZhJXpycrDNEf
EtYzKLCjEdfK+wnLcgcqAStyaAieMFAYBPCywsZDb4GWNeCgrHX8ytNy93jJqh4wHp+2QEiaMIv6
tvZNykrTdO+rG29TA8FbVrUjlkg3qyx0CTeS0A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vcpZLaqvZH+X4BLHyO7alungV2YZ+1iKd4zFRS1fjy07JpH5sXGU31gyM07MnIrlUGsD2ADfNJjb
ptgqsEd4FxrCZ3yUXQRz2g2mvTq2qsGVLj8GQL4fk9oPs6eG6p43ZrWdED3llXrT3SXRFCm1IWea
wIhuF9pGQtbd0RuW57s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dGG1Du+0IRTeMcXCh3n6bqowdN1ANgbqVK3g14LZbzBALXCADSwxcRvLTiF4D8Er0+fGtcOYfPUm
MJkpHFc9R2h3FsIgiXT6sVEMzHbqh+X8JJ8LiF/e5l/2mKyNShAsMAipYUKaIkdTf8JEKKP0e3i8
w7P4Qt8UfvtpX8jDD7ufpvYxbckWfW2aEHKDxQ0InK5ddXdBiyAaYa+rpT/VgWk2h7WX4obpP6tu
oxXv3/vDdIYk3QqZVmMi85PdAwE4A+ZTMoQF7io8h47ecYf3ayQI4raNg2M/tf+SET+t+KwBhlVB
IfJyaFiP7Yg7REMwE3DB+HjmfQJJmpFYcPKfaA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28448)
`protect data_block
hqQtCvtyNAIRhohqqEDKb2xQSxEZ0zwrprsYBq+DyZ5pyFy2wx2jJGgbdQ5hFVoiZ2QMCDMg15P0
NeHLU0i2dmHh2rDSZ0XHpZ0rfCESSGzEJos0UxvuixA8LMedoDf+Ym9FCG8u4XvTNC9IGGeY+R67
fID26unjuHwfzRu2Zku2OF2cibiDqmg5Pnx7G/bnxLLCvh4evsUnO1zwnqYRI1k6Cm+2oxn56Ul2
SGDqQwZtLeuKWoVjG2vyFgPH3UXoG7guXFiWJ2Q3uFqQ+vCeSZBGnLP54AEylM67AerYVciBoI+h
FNsd3SMWmUkEsAeeMKHlSb+3PCKcTt7UH5iyjq8yTApBmQRAyFMx5ZNrMSgH/AyK3SmUT6JDAxBa
3ex+7XXfGDpqWswEVangc4dqlHqwvWK2z2Q8GahggN9oJa8C4CyToVSD8rqnOoWBRszgljPbG6Vh
ZNXZ8djOfFke45FP5AnVEHMHbRZlCPIMRhjayIy5YD+cfTgAcejD3vvdbAitqKQuGveaosXV06FF
5YFm7bAe8GJnWwc4cBp6hm7Z6/w4XboFSaVgKXDRmv1Ou6KsEp0NLBwy41/kqfr8rje7GZ5g+J2x
EE5piI2mTidRXn8cqBFAomsz+qnwZGUQXrpXjKx34ctPTR25BSxdF3mVuPogI312bSy5GE1GKyqL
WlXQfn6cZvgvPBaZwnWM4qsyVrSQZPlwNY+c4WCdF7Kl4aChghKrOw4PfilhuGAzNJGHBiQ1QB7t
opmxKvn5k56XpKOVxBLdqQaB3btDsb+p7N1rP1haRXRgz05ojZqWEGSHHRhAkLjKqQx1DqsBnps/
sXLegIGHipEGmrkp9B06PkluhhKA50FAhE862ZJMmLjrGU96NZJweeRAfHczjiNJ61Pa+tcISu8b
bs0tlrGZ2EKhV5P+IVcI9DBGz9QWIXRwQRPpQj+xa8qEw1I9DOx+GC9K4wl84fYv5HBjbU8lKygd
ucu6Xfhu10YKnsf246JB2NHUc6n9UJ7PIk4RqTR+AYgqfyDBz7tiIKJl7LiBO2g6lVHMR1jw8dEe
GAmkqCFc0IuozTz2aXZQmPWaTlFMmX43hQcuYVFhaU+klTxQmDAF/YaBFx6aJoqdw6eu32Z6IEFf
hxj6Aeo6/OaVmdibWTP5MWFHj5+mjgfGhl2rPa5U4QHcOeW7edeIVfUpa85kWn4FeOkaBBY/5Swo
9FvNneLjciPTbV701+Z7REOs/9FOdS/y98W2nnHNfIzwpMYed6eDNcOZ+8WZnw8WLnNZDn58Z4WG
Evg5aXkBZEZ7PsCfFjSN3MfT9jyKJobHDXKuR52SoyKVI0B7R58ISFIO89Hacj1nQSkn3ZK+z88X
dV47nCW8fz5BaW5gOZzVfMxWOL9juAzBcuQkHGyLC94a6Xx8sI+R1YScX/t8ynL+AA5kYNrIg8pW
hqOCBHdmqQ6nqROD5WmvfcVFJmff7ljd7k5zBRwVrVVT1I10/JWCPE49OLiFFoqT8AS5yAMzmk+4
I7STMVa+lJ7qAnpuhAeKhQl5cKeqlPtLFCsGF1OtssLECs2R74/ZrSdinsktMJjRjEcVFptK9LsJ
7/iHWNS6JhOPpfICzaVmYM8HWOgXYxeHs/ZeBR49d4RnzyOV32242zbump5uD17mMcOdjPHeAXPi
6U4waJBgOlvOQuXQRvq+DH16iOesibr1aU0Qe8zpTYfYnuiweemU/ND3kH8YNxg9NUGMpBcYRxS4
A9doi6EXyxUVX28bdxwfVg3rMjSUg6Hh4ysTSjkgNMv3ri50xhTiALT+wXdZ8CYwA8bHSl+ftPEN
0g372dXjN08c//G70g3+MLarWEYD+aeMsuRKit+6M7Trb1FZMHh3fGBD9gmOTQ/iuoGpSlA10ZDJ
lQARxilFs/t8h4WdiUY89KK7UZ2W53KPvgUkaU8T4jL0p95SWVMQkCjclJJswHjkWehn06s9pmNn
R5T4oek6P2gS/CzCeeVb3SAPguatOeDATsMJAGYfe0e5xvizzszqLCuvrJKxDwydk1M9AWjxuCIf
seLqmg+XLMtsUZIEi8qpIY/K/PlkQV9PkPFLo3JMhhQ1SGC3GsD+I822Xactkqwmevvkj3IcpgRu
ZRtKGxaTSmQ9vYk+/dron2xnoH3ExeqYrh9ZktZ5rXjLw+0uRNUMZUQyLF6UZ1Iu12V0vF/UzU+S
vy/qyGj3ID9eUJNZlVMgSV8t4GnGLicmeRjauTPA/xRzTgjPdv21UhykFGmd9IfFEc94EUf5M2Gt
a9sYl5a8/FLbmf0d0kGjrby+/JlrpmVhIcad0isOra/ztNAf66I7uCz/xtyIQF/kpipzqnAr5JVY
YjlqQfERIsZL3USLC0hyxZded/nbQcb2Q6sxy/uhHDr2XkUq6Y+1FSuL4eE99F9bBEWIMBG3kjO5
1rGp39H0nrqpsZ0wQiarYTKLklPqRzSZlA016IkpPRaAR9RtOMwI1Zrz0hHXm8moZ0X2dYDNcOze
QDorApOApiPmMoTP1eQ1DW23g9dP2cWxU6qlst0Da/LlqzNhoBVSYhh/BPNu2Rrq4Ixe3yxN04He
mtC9Ya1JoMlpGuu3Y+3094Q53r1F1E1CWODoDtxklJ3/mpqM284iccX5cmCtloICHV4hR+/b7mt5
dMSHGd51SE1iq7BCIBaYPFt8AIXWYx7zGTrInX45e+vckQ2fkVEa8cKXmucrweVzlEgDoXnZUk9H
pnBjzT/fHzwR/UYbf24klk/vjd5otmj15k79VcqJWCg1/SGluSVJAirL01Q2sshbV9SHVI+1mGN6
Co76zwfMbaGZoWVGTLaxlR4N912fIqdLemaJODrRsgVHje3WBwpHYFEBeoN5vuXZiImOEMB566L8
Qq/zdnR3oij3eKVpA4f7qzn/kbmnjZZUjvZfbZY+8lpSperplcgwV0pTPRmNqqoHndyrscG0pj/a
qGBNv09h5o9Q2AA5tFWQ4wZlHyIsWrRU10KYQ3YFKiSR658i1w1DsUhQWCt6RlVuo9qWRtblCvH2
x7LKMfHhpJkVIAA5vWRaYwLgnp6kqTjFXo0jhdJUXSDhsfTNnCHhv0mgBp96NB4QPigZk1476jwh
t9PnXWQclQJ7D0oXa7aAMksy0HvPOc6WN23SM3OXJh83VeY8Djsz0bnZosfyD0rmSifHF0sfaUU2
/SEiVlF+hFuAMl4SHzScw12zaIpiBjFUZWemcF+ipNJtK/PJ//ty8WwEmCqqdKZj35yYPCh1DcrF
Y24f7XVF80R2hxsS6oJu8qS2O6e1EIXNWh/qaEDlDI5IYwZTUHPZWMHMPcq5eG8ImEglPpbpoPoF
mbBTJOFEHPuAWPBBr14x1dFVYpuEDQvObbKrxQfKvLy66oIbyAUDj9RMWvL8a2ggmuYv/ORwToB4
wfEPjFJqzVAWWqjGdVXdWi+aYbYCg61M1wrnpKDvLe70ug732RdJufACtFO72vlhNQE6mz3olEvC
8n/P6INTg7y4ErlVCjqYfFtA4s8qeErjQrI/mU9qWj5f/s7IeecECElQByzMOwnCT8qHqGxW62T8
cUOzWC+Y2A4mz5oJ41ce0Sqy1hWI05UHIQ+Mcp5EDeR/P/ZSCpTqH7GzaCsQuUpIXERxVNhhU41M
cRsqjyJOkwbKv+AbzPhEsGytu3CsBmX7Yd9v0yoPCbb0d1OuAOHZ5ZpF9t+T8xEbRTmJawxowRhd
yicKZvk7vhDF37Kwusd2h9sZNneaKgEtfYcgrQ13EZBWHyoxFTccRW8lo3FQ3ly4ZWMvOdwZbShh
22w5in9okkKMysIDPP/pulCIYEMwo93yfP+qs9lixv5IoDAhIxPHotH1DvRiTNeQfOuhY6CtQ6Qo
q1WvLYXN+YfJNj6HnPSzG+doOFoVAkZ06f/8b4rW74PJynOQyaAFsXxebHUrGV8YPJDdxP6VmmBs
pC65FtsAJxpOUQ771o1p+PW8QTnOEIdaFpT6xmqEzmEFSN30w/wuf9tH5Lzi9iNIHm1mx8c9cCYI
3I8I5RUHFb2UXMNZvv1lfl4CoE+z3L7lrFbe5+tRZDdokFoYsnBNMSNpCHhTp23J0Q1e2gKr8ioB
ZZR664YPL8Jm8IEp06kbi2+Tyf46QkyUEpv/ZgNXOcVCsBE9HXHa4soizIYtbY7fDTE5wApsDMux
ixHi5i8CXDHyxSRvf+o37Gl6ZQvnVKpCrYrqrta4fA9pJptKaY14dkCA4BmqhsIU27ktkWeU2Zav
xypKvEkyPxt2frUJXgFrs/RNu29AiGf4r82NQtNCMYZhOi9xY+LHj52Me0MwL09GNGtOWejBNr0I
+1uKjTEeIaZEkIUAKskVYTSnpP/YaQgICBsXJF/0CQe3Qn4OpGcv99YZEdmjWK1FsznGT4l2z/ch
GSdY0C1V7UUuRzV4iAKTGtY9wBFDELydFIDb4OdA1XDlp+y9BCZXRcXsucAVh4NrSemhoT6XT3k6
cNvmfwhlhSnfbcuGDu5RR1ImwBDtYdbfj8nyTiy8NMZgSRumxBQyEufLSeDezegb0ZUIkrUkxcpc
9tabX3Q8b0pTklJTLtJxwiusLSyXEUuaz72OMU45yrEvKHcjxzQPnsnHb1CzD5H7LRRFz1eg2RWO
8USw5eeYesFNrZ131sk3+RbEFrrPptGZ0vGM9WNMgKKndEglHGBY++0cyliNk2DRhi3Nmjkh53Bz
kRkSWpvTh32M9EmepB00vaJsYmDgRd3cRBiJb9R+chMDugb7Rmto0ZU7o5vFQSz6Iyzz58yzkYUH
oNjXEY13F26jHAhdC98hCrvILAP5VkocDZO6/UPeVCkZ/1//1+Job+buj7zZit8l/vj5yse4rBes
pwBKhrCv0nudw4CCETJcVDe4P3AjAg3UrKiJlN4B/d3J/Uz3t13ELwXVrQVnuIVQSZB1Zuutx7ry
80Uhk8AJx7dCOTf9S6AHpv3yjA/i8cWUz8vUUK5RCUeLnCFIKIf9AJytq0CCu5EsV30WiUmTxctv
zB5FExPG4l3VOgrdConcrwPPvL74XaEylH5HSYKBFY8TvYCaX2SOVHMnBYXNjHQgPqv12XOkgfXv
+5sCscMb/B0t+z1Vl5CWOSiTL2pHzeDrAINulKeVrCb+02E6c7uZaXxnkor8riPquSsqFTl4IBBT
1pV20VDu6yvKSyCPxwuBFU9Glf8fq8PkBMIasPm3dB9Tp0inzLQKJJ9PKk7t1sk/Z+faLKb3qCiJ
mhm2eQaBh8v/Qvhbp6A3XlraARX/sqfmWOPFA7eUiA+NRkYKqj2ekHJ87E6JjAXGVtVu2M/Uwc5L
RXSFnQntjZr1kh4RpYbruYX4cNoB+wvu5fEEOyiwMMqcKcU6ZOvbb9O3i6G4xhBS/Uh1xomBIAtx
jXzQjQwPwlFfWnyaQeAd310Kybcj3sBPKgIilrTab5/FdaD9aB1B9mypnTIzD5/sG9RNBHaIf3B8
WZOENiKU1QDzUTGgYngLMda3mGpZLz61E46nmU2UGzuHzx9nsrxIVpJaKbJ7WKReGjBURUevUKoj
80R3exRyKHr2w8GZvKSfeb0hm8I9SRk6cUVYj2DwhYui8zw1XCFSXHqtbDuRwZzFYv9evg42wHE5
YLDYuKadYyG0JknY2YAZxVL0hlK+2bRawZ4AFJp1T6821nXiZRbgAgHbC1e0cNzdCbRCFuMK1aTE
eK8b9iZkcwTEOOQvHDYvNJWtP8qlRoJwUNC/chIlyJGLdIRfmYknPqoljznqQw/C9GNqZnJvWvaC
2W/0Eeq0wK3EnDsXHXSSavW3TJhuC9O7kDVjtTWVp7TDMBwAXNfy1/19zb1lJcuniSPLAfKEoRlR
OlN7o8ldP6ztOhAfqWLKZq9muDdULHj92+yLAaR9MslXGXPuPZS2Rxd0fAqNtu1p5qhJVgnaUtp3
Nny08dx/Gf6bdAHxRZyxMfNwwZqD3/rZFRp36UZsGubcy13T7ZXTQfIfvMBJJmDBtgUWhpgVB3GT
cLkIjn1oH263bro6T//ovLMGKy+LK4MbRRm/Rx/JdL7S0SNqIjgRU+Lq/hJJT0YPhNE21yNtqPmx
el5CjLZg1pwsaJOwGAXhjBu4TuUPR0iVvnqTYriTRHAMtLY3BOysYDjIIwthZvN/9oZAmGKsRBYI
fo0glOrMHNUYs/OqexSmJIChwxD6DDumfek3Emo9aVAQeihhA81jk0aOUwOn8Yp+JMb3iC/3OpOz
v+mCs6ZgOAHtdGG2pqmu0cTFn1GzG3xUKCvwHYczh8bhXqcdzsc75vX4lPWEWtw1ZbNQvBiTpdhj
tb6g4X9tZ2UIjZyypIUjE2jmCSZlrFGc0VxNZS7yHEVAf3mDzkrzws1/daA04w7NzmogOKHcP/rk
Pi46PGlBnJiEzJMdt/J25PRbgZZrIDugOWKP76J19n5ujZXrWgoyoyYBt7ABViGS0MlaMa0mvswt
UqtH+i4vk7y6q+wDj3tgKA3rG0MFp+NU4sxf2L7ALCTUx1a36eZ5lbyDaFG8i99pBYvegEP4HBld
mnyAIuRROf/XymaQFMIdUqpMVrzKfTWO4xdUlvZuHdScDb1glG2WYkoYyLuA1fAxKqLluqIyxMz1
2UC7gy6Er6tZXeBy+96tWwhbuAUAuBZjBHnI4X7IqVCaNj1Oe633wLZExRtJTaaybStrhG9zNWZP
z0pl9G3dD1t9H1KE5lxipfMnVv/YD3JCh5gyziB+7ixKrVdvER8vrnxBD5Ss5IakO0UiLEPouMoj
uEO5dNsdBcTZXXQebfz8TWAFF0one5cTF3GIxgMKlAm+KbwyN6V3298DVl5vxznFfQBKQZt1aiDw
wRRgFR4y2Nb2aDRYADMAlpI7i1rdqStYQRMTHa9zQIXOrcQ9+t+HLI/WU6306TcQucIbtwLWRBOR
/dGQtP2hSk6Fo65Iqy6UrZ2uAJxEGKazAzO/0O7ezo1jR/pNrSz8AmFIb6VqBIwTMyvSD2TTWMcM
nE5bfkoH6U+znzNB4y+e9OboVSzor6GGdpOgtVfaljujo0gITmWltSaB+Zc9yxsq6fL664BAU8cN
aFfUIscSAIwyK3FkFHU+ecO+4hLmQJnAHSZKxhXG9qzvhBaubdEjdkD+05STPVHXc+h0vxnEeti/
kW+OztBoqQQ3d72iNV7Yto8qaupT2X2LIiHXAytXFRuhWx99mnW3htOQ31RbxA/9PyQu7ACpsENn
ORobpjiiSO9ImK5l/0ItUOF70cOThGIlv/9w1QPQoEENRiyUMi9a+UZ9i2uMz107R73c5ZMxjvh4
9jOmVf8VXaxAz42SaDiwH/5h7fBo57ApsP17cgpm/Qk1m+dqU2N1N7xGy5TilCbLP+0DgI0GfHgo
Dzz5vBUxPOEZZzTeKs4xtWF9RkRDa5T9vZFVm9ZOqEnJijAPiRC4qVpGdNiKc7rbaLsUKF6PIT9y
F5ZyoIUngiozpk/T+pkouTUGR5+TlTwALYkpaqqew9UZ7wPsubz2lMDx13FT/dgX6ogO4mRI0ljG
mCI/Ear38Pum/UpSW7ruXr65o4dGUQH0JCjOIkXwcHAA77/iMQdnZ2yKVNsi/LBFYYN4vs2rE4EZ
6raHAfy4fTszBRTeEJl5TkWDganKlcwsF4E7h1VoLTOSNUQKXvpYG4g2h89WL55f1kzRRSiBV8l2
OqY1V/cg6WHnXLQdM1Ie/Ou7wSgnVqfB5Ymy0uxWYqprG5libiBgJA9AJD0x3fJsWXNjQM6OnknC
RzHTOIH/gNYXRJm4UGnwXXFqs2I/h3H65kgG3z+u1WR3oPEroC3i1IOcSYX044u+vDCyRe9DfNsw
TNPhXIVVfrcInnV6hesqFUCI+kzGfY6Jq5TkWq98MU2iy3/aQH1VTUqUXcEhh+cpDwPdvaBuXy3E
ecHaQqkryKEAvNCeRnYowu3PYUMagwSqY5GkFxWg4D8fPiZhVkgcBjwtZaYQH5jZhOEKEUTxFnTx
DehPW4qUTPJ4ON8ciC67XuGdbvuYYl2SLOJF0e2FDT4FiwXvTLJZK6iM1uKurmIXqjWPTk3ApMGV
RyvjqUQqfB/3yH3xc59/SCchAalb9zuyPAS78MPVceltNawjzsDYdrqfIbUCbcJdlAG+RSSgVa3u
BkuvHaF31AdqsLtk3EqrcomR88jA6UvLtQ1jO/zW81Vre9jyOtCQmiN4z6guKH80+H3DQVZmwIZ9
JjDEBYeibfb3Q/puektWDZpyuEnFQP9Lkr2tEAXzMXOviF/kVCFDfBOSBw8cTHouWnXPSyhCSueZ
QgvmdnC5ElLHoQ1BqjcOFVIsyMz+NBW2lf2/mj4LdG2meWwkTtaeFWoYmNIKWNjNZ+8cEAx6CSPc
nMlIwuVUKB560XZZyjOk/U+vbpuT2CWOX2mxaKG1fy1qCHnbxNCSMfWXIvdbkvxM7GZKEbymh/Qj
IPzIUCOYdC18unfthsixN9hmoEJ7v7dQVACGnkHQzgYgdP0wDkkN/WgJwxTdGBGc36i9sOW+2a1Z
gynpiBOo3+az1RQrKaSrRQRVLLvZe6q9gW02UcTlxVa4V5e4Dw3FTLsAhGXKoMglMsf5u6K3Gfvm
uDHH46mTVa6vRXhlMLK7F+f68bwHBdfLa4ao16+V0vmUZYRKNUvFDcsEAOUs+VcOMbc9E/6RXIpL
jKFInFUmaFEMjLGBpstNLzp+3z4b7Zr0LmciwjKaBp/C4kh/jjQ/zTnqEfFRV/XFf1pFye83+r2l
j/wOqsddDJ/CzBgpscsnlREmvu5N+Bk41WTSO2UAxDbGJpGE0O+OVRBdb04TUyTZ0yWrSlMVg01/
ZCJ+il20wq/zgAOUNG4OH0rViK4cjLPoKL1hnCxuPFYnU55+hKyaG9ffjZyAIhF5bZPHB2izHRbp
Ho1HHG5lNcDVAIiopEfWvBJ6Wn+drri4yGSsYNZNzF4yL9OlRhfpUqEMN9gkyD9wiZCkF8vynu+y
SUzT+ywwwSBcpxrNaLgom0po546VVCubBU3EzbsTkW0uCzx9XAgFMi8H3Vs+/H77Rm1mE3iRGVrO
ZHjHVkF5xg0qJLDX1+c8p3TSldHV00yauz4NYf7J+ebZW6SWpm5O23u27NJwfkmHLIsRlswTWa7g
5AYpDILYLj9KA+clmm7Dd56P/oppsinKvqvsaWQxbBa2OyZ5DCmwV8jB27ELRGrOhu0gBYjeWH2m
NhwIGmmMOpSpcJQ2ULI0kjGOLU5wLhjXJgoB0+xCXiKUeajmK8Dz+B4MrF0J83t07d/TWkhBfSdf
sWTZ4qhwZomW22FTDPWdhjTAhiDvYmqyRjWAPPhtLmnDT4yxKHye7tcvUR9O9dU7TJWOFLe+0FRp
y+j+KyXZogVXkyL7uOVFQOyAea3JxgKUX+03e6Wo/43CkomnA2re6SiSof5R7SR74CM788p23owh
eSNz8utz7dkaSxto8nmJO2qI0xTXOIisqPXpt7Gc/D1LI/wHg4KulvzAecEOUtjN2vwaQbVmsarx
kDqbIzOY+AUj0EppDVdXmziPyBA2dgB+3wzZDx+ml3Pdx/QUKO7v5VPJBO5/3JBCrcBW6y3yrc2p
gK3hXR530VeYRrjRMkOqU1zR/lDTySjANwZF+Atkbh6ftffOrb8RoFot6eZiZM2qedhSmkoI0lW8
I71NYb/5ASL0FTZTeIQCI8fLfb+9md5r9REo//6YjwP5ugRHb5okB3Tu1+9UgAj2dbpA2e2CxWgm
aIxib/H0EsSzDbvyzNXfL9ktew4sAKY/1DwqDwMj/fSJKaZnYDyfs/k/UXbHC0u1YOPtVAg+/4y/
jLNB/6kfCltRed7C9MlKBFb9HKd19SVtysHHzQ8f4Id56PibzfF7JHTqsSyMX02yIlBqLcUqBrmn
cnyJRoWY+pwsNYSesEu+AcRJPJh6rYHXn21DPIG6X4kPDoBh6aATrvjXK0HVHApCTentmZUsb/QZ
nI4/94Hp+Bq8KLvpwROQleSELGVKtEC3cRZlJq3+Be2rTLZxWtB2/cZ4BwbFXRhQzNoqNlNoiHYW
PlyQBck+WUP3vLFK7UIpWru3VnragxZtzNWQyodpIhmvYCcDsNpzf5Fv44AW4btSjroHkxCwmLLR
emsCUp3MLNUhM3Wkbs0KPgs1G+R7HUgpz+zhLuiErWEM6wJJcqw73tRVVeZcDMGSXSsJiosHzOxq
kg392Zks//4RrUzuuxQ1gVjyh02Yl9bW4KgTjkXmDWDZwl9JufYNiAPYKCf7USWpZrSDPsy33hOD
yqEEJXA9I4yE+EVFF7kJcthkGdei/NekmFLnJgD0REyxG5Mmi61BzdfUOJ7imEusozAoZ+zpigMM
RrLqD4qFT2agrQwkNjAgSu4MXl3IhHmuK7lKeVCjnFNmCAMG5gm7/PdWoRor+x0u6bHpgzoB4cMs
qDDS1Wq9t7M7zc3uhe9bptANy9y5VwI+sqtlafZb8E5tHDwCSa4N1/4eL+MapSNKZ7eUwJcW4Rz2
d6D+o51JjQtXWqMCvW/9ErvsaPliBNvIrzpN7dVEPbU629g9TbvJrT3k+abHeu1V5Hvhb84PXFLS
ebQPGenLhlO9jKNcT/dranHHE+6b44JKI+t89snWXVN1vaoY1ctwy5ATGmC0Bp8YmIfmWnYjR3/S
Pv5uoMDQO9nHyzroDgT6ZUjgEcOw7nAkSZJFjn16yq3T96up8+OnYD5+9sevmtM4dFUZehNqSrD6
Z9Ujquhm5ghLy6CBtpR/KoQESpYtn0wSyVARHgloJs/Oi/q7OuXm/DGIaXh26GtQ6tjMUCBc7YlP
Evh5UU+GqyWLR58nR/VVK8bzPVCvNoO1hNt1pDUlqO2uSeNZq6mWj7NFjB5KaMml1RmKRXc92FBf
YEqdR+XjjLAkYO1H+M+qCtORwS0jtff18Vz/R3scfh2UADlGxPYMqHNvcRcpdsnHWH9xphemO7dF
R4XaJfJZxGompFilYc7V0qc/dyeslHYroYQ/yGlfsK1WRGpXtNXMFn3i3kscWnMzTeAQQvMB0bC0
nret20zhdIBaLawqnX9LmAVcL+ZIcnU2h1uaim8ZmCCpZ1u0ZsDqwFa5bPM16ps23COGN4G6BEbF
A6bDmYklanVKnz0sEQ7Fz+WV18G817SRnHxnwA4brmBFub0EIyTrIvamc1BE2HRyDWuqgYaXG453
RtFpA8rWUgTcUCww0atnyvLLAkzBSo9JmMht8k0s1WdTbXTfjQtrcO8yHPHsKa5+/iR2HOjrJCnB
kCVAnGvdtc+D6WYLco0fC5Ajs9pWx6ZOjVJdXP4uBI9LNvfU84fYDbusRdeSLvOJnF/6FKcMLXI4
4nz+HZ6lxhQ1HvK/GeQEyEpNJp3REooCx5IfiYUZgBFZi09X34Zv5foAgJYrdBnrSYnd64Rfjg0g
j699WwhkWL1syT29gAocyhXp4Dg2twuo6cZsQZD3b7HpDBVVxfdAZvFjprrzfSrnO67LR3l6mx3M
wYWzHi4kEeX7aIPj2NJ+CpfYNI5YB1kf5eaLrSqLrlnAyj6t6JEVrPd2I39kZ0hV/Wcwh74NMKPE
4kFGw5Ic1NLi/EsmqJt7lmY5iT053md/40Ry46boZxeyQqQB1/BK2qsQwpig+HN1NnWnjvt3Kw+s
y/RDN1M3R8xipKXfII52dqIvJSIq/9+um/IQpXD4l2/BOPeC6Uz5mY9UlY4RU8JWMKlzS49fEHuM
dSLkmjBRZIJ68FwTGo3HyhWb+H5QgpnwEfl45Etlq0PvQ6HloiQgQtRsuIpmcIuem3LVlGGtxWNp
YvD4KSP1X5uy1xFk5bus/BLvBvuuS7DywEDVbNZQVY4/QgM9MHOpUEhYVnAk9V4ZGab/rAbELJmt
TuRS/ZWpQZPLRDxENeco0hTJWwe9zBfXYsp65Q5zHsamtwr1Xxb/JUMr5BAcwa5hryPEdmQ9fw+B
FRI/xMyMJVsnsEG1AnnQDEjqagpj/Lclq1Fp3shWiwqZ1Zsfozc7Vit3dEUuvqywqRe/dGfLYjct
fNl/BQ3wULlId2vVV9fkFHgoemnpTdW6B7g/Nizjbykm3muU6Kr2LEbEtHSSeur5vrVljk841T42
ev74fB/D3uwbCIMP5JWMXdFXCdhHGi5UJsybX5fkaW9wD2r1VM9kDPjKlJ1djUFZmYBHwTO1iCUv
Bax8XQ44AtNQPlaL9iwA9bxBev62NphL0cxN5I3DMvuI6SzL50+hpjMg6B9gDS46z9gB4Gm7cJqT
T4lx/2ar/zdJ2djgEoTZyG83bMStR6nasoVh7f8h+m72VXh3N56chCCUT2OlZqoYuuUuLML3no8C
O3vSWtwxqvdXrJU8cGC6fieCHHG7mZMxb2XpjqFDkmQ+uanedgPae1jtk8d5iS6pDQL14PPqgGUz
qNWjLUqj17ICf+LbF/qxpabsdlTAoG5y8Pqrvdkfe1fQftgYTi/eN/Nf/+lvGz5GWryrcZQdRaEH
Qoyl2tGOKfW+Pa7/nyUPCKOvRA8xgKIkAi07Vq8YCCAszzpPanVrhgkQ4sh/4d7w92Frdin43+zf
Q0BtobcObh+KphP3yiuYIdhRB5XDo3BGXa9XOCdenIiHQfBTwNHZFJTbDB1ZEDYCixpNSlFo6GFj
GMLjBtyuV0Meuj39n/5kB+BtRyMxGW1JygWUVs6lgOJ9akDNcy8KSX4RNYN/2DymhXfuJwFx6uGW
YV2A37dHuil8UErcb3gkg2NR0nXgQiZ2YeVhgbLcOLCRybX4Tyy1nkHJRvl52UBVc4pQ/6I7VmEY
HqRHoM+Za3aWdh4AfSEQT+AtXBZK3nzHwlfG++zVmeNQ3nIGQS780JI4GWq5sS1BEWW4Ct7WDrrc
l1OyjhqGLJll/bhpKM6oDNVGP1huqc4WUsCVNK1OfR5Zx3biMNf3D1ni6Ne8OMg46GWqw4QHJGPs
nm9O7e79eQHG3+cuZV7VG+mwEH2ISV1nZa7qS/wf2l4xyrsjMtw8iIjy7dNlohEeRkLMO1qCUh/l
l413M2E8V2ehjqpjoSt5Wz8uPDglinskJOMh4u53Dv2mZ7tjVRzBd/nEK953EJ3dBvKpsbqS+F8X
JnSpIgUnTyxNYXPwTzUXfCKbdYdO6i7/37dlUDlH5jLhCA0Sg5qxhQAYq4dP7c9f5cFCRGvh61Kz
unsxsDcAauDsD6CKExV5widtIOU/emBIOgJsMM6PsqZsiulklh4GaO4IElsBJHp/cVdIdMdocks8
FpV3ln6DWfcu5CMpd62T7QNWy7au1dPpaNtijYueVjoZzXJ7vxqto9A/mNLKL/WtCqC31kmnG20r
oyi3dmjvwuLHmgSzf136rfSI0mkVTnDBP6BhGSf6615Sgv/W3SNWdwnQzT6iZI2C63EHi4KZM+zK
ArKI9ajS7iRGLrH75bo9p9kJiOqF0QpbFIsE1nb9NIaFmryxBpMK8WmcsCNV56/glwp4IfhyP2YT
DdwWUbitUNqAPyKPkUK5Kpxi0DnVqoqGhrkf8vICMbtGeojjXq+ASQqx26qvwAdbXG6a0fedlbvK
t/S6rCsdmuiCHy0HYB4C6EiCNdLCYfAdd5VDgOi+DDzWg6jXwdQOUyhiOo/TE5WgEqcL5+aOKfYl
IKvNGoiVXvJVR9POoVDRzWk3tne0fRLfvoPcgl32/315uiXMjx08ehGPm3rGtYKhPrAFZe7tJt8F
5cWuQ/2PhgroctAR2FTgAfck+fClB0lZsQ/cDd/sAr5dU9kFn3FLtkdueTlOjAfns8Cm/zwtAIvX
1evjfP5cD+ExBfx1g/klpjoBBMIvzQBKjzBhclhf8X6dLno2JcwvMq3v06NtefyAVTKZc2VKPQc6
wBcM2abX1xBfB3xukvIMdE0a5QfRybS7sl5Q9McD849IG3rCnyey9cCh8Bg9Z8HIHjd76oPihoX5
oRpZTVc7awm74wGMgLRC3ORYt1KFbylOlEVWcLFIDKI7vwLO8jEIB0bzFzHa1V9T7Wq0Vb+fRRRP
TVQhpAgnoKtajJW9pfqkX/nGSU7Ea50CCzF566M2pIxrhAPOaKuv1aEIcPolyZnZ9AEhoBdeesrh
mMlR949koZ+fKgvpi9HnknnA3M+bn4Ly+Nbeor9pF0ID2VNyrCA4VOaTSLvnklMY69aPAsHJOyns
nwuAlKPz4KULt185Zdxeg3HipGR/w5u9u3SFGNPYEM4e8v/adCntkRrffTrsx7BaLE+tS+D5f2Zw
6uG1UuPiZacDGz1fc+Xyi/oTL7VvRaBn/fQskUhjPNiWUjCqN8C+iJWqZm1Xjadyn4RsN+YEX8d+
HWFAoUwmABMl4Eu4lsIXqNkm0OiOfdcLjjX8FWxuKsvGi59qlw4iXthed/R8munQJygaII+5OCJ+
HZsnOr6muIHvW+TRqi4gkDy4WgR2N+wnsgOmVcfTMM7lfo3rdlwmsLWik7s4itWs72LtSXsfnNbc
o4st3+IR9Mg6KbR5m+GJQDGteCox4HFEjqGcXWKjqfntQ3sEJZknjBVrpWymWtG7zETpjGLb4xRd
vfjPS2Ta7jS5ULYzpe4v5RVTbxuo9c+kgmLV6QVlRaBtdt/deqVcB6YurksSMzKkW6bH3/Y2MXaL
2Dc5l25eSZBlcdncSfXnolVdNQHdzpW7XH4CJNMhDKGSF8RINgCLMPCBELbT5sXpf1ZZ6SVWN4AR
GPyTPdx50XDi21g/e/82OWPm8wppdr3Pzb1jUSsQJZKOigi4k2S0VEQfi8izMSHZ1KixpwIKr+lf
Zljpymb2HPhKJ9PPEgmgNPoxF5j5TuQ9xm4T4DBV576Qhhy/U/N7CZgmXn4IuTaBcCoBfirRQaM1
pJYuZNkHaB4sOH7KvwM9BiCJZdbzh9Fd3ItO7ttFjoGUZKwAtUg3CAzmMhpiU7qC+Fh/QdR+kB86
4yg336LBF3yjbUMPtbTEALejqvxa5CSGSDr2GSyMv1lbSMiFTErX/quRAD5R9ej7le0JJRBilQ/1
03e42yrxRoCA+phGBucuAxYJCuJBUiGMciEBjsGgn9TdNAxvvtbRKjBv3+r+humefYBylEPZBkkh
irGyoIW4hUCijDlziK/CWEdaDt5Pd73zpvZuFISV+5BHCZFMr7jhEzWv5ojoWMrmEUEiddXpGWYJ
9GrBpvb2WO3Wwg5P6hrD51WdXfDzqYjusXXPreLkeqCATb4wtLGILKRfySXSKZoK/jPBh1GjgzHf
fTvAPRVvZpuRuBoEMxHEuFceBKa2AGwArjC+nvBPOAToPKwzOGhRQ/r7KRBXZMSiI+oUjuzgP+9/
VgqIXqBmB2kAxHPLmLkyPMnYeaOwGxK+Ihoir+Rau3W4uGFKNVmcAmh91UJEE2j+3h0DBCvsli7j
5L9c9Xc9toDLYX6EW6G6VITs60iNBzXJSnX/5Xw1a8lqF399hPeH1uJoE3e9CJ0ztTPeKlHNZrOO
4ELm69j+bVcBp97WGZ0AQBEJBtk8XtDvd9BiD3P92BlLkfXo9WluEPX1WcfhVPjqxTwiRxiuh+IZ
rrkE+jX2FZo/owTzvjepz181ujBMDdF65npdDR/KLXCpKbAvkmU6p/it6pOjHw4fsj7lWiYmPQSp
ysiE68VgYsQFT3zJjUOGa4EjWqk2ulkB3CmVqBQCQYzWwitn0As2+q8WA7J/6K2HogxWeXK2rjj/
eJnuJXgBq2FzhzVhf0CYiImaLJymEHTMzHmFFADqCSIBY5YWp3Rn2h3WhwAaqenLvCtXxq4XiGWv
Sc1hkrB+PGwYBysrGtlgMaq/Dy3g9MYpjm7xsdeAzg2utWx0s/XxOnKkZN4GkgsDIGLQ9+0x2NAY
6PoQvw3lADx6Z94xyoO0+wcUZT+eFDMdPEtrRiuDScAJtikBTz0OM31VxXOy5mbspQx+4iUrQ8Q/
FrvVx1ubbgiS7xRjZ+uKwogPMxUkdSIU9GaN37AKQr0kx6W9yJMwJg/5QHzV7nN97kya+vZyMjoL
hUOIjYNJz5+SKztjePDaZWvOaSBZyA6vtJLVqyOa1s7sN4u5xOhP0XnsaPZTaQBxxxqV5XnNtzfq
85EIDmlurvv9AgjflQB9WBiAqprQFBVDVB4lW0OU9C7qbwvidSp6B8t1bzDxtBguDX3HPXVLDnnz
uaouoAbCScMiqkAfzHNgzj73d6sw1NwGxh3RaMgnWfIlNZoqzBYZNl0Z+ykSULuIN75gDWEzxw9S
rMaqD901j3Is51gW84FCLeLQj1AQDfuFotdvU3xDlK2hFKMqI7nXaVaNS0+oYdpaXi5MfwfCcWE8
joFgFm1f5vSWu+oyC+Rit4Wak9k0NH/jv8/1h7/6vAObIBlA0YPMGiKW1+stTLCOSeMpjxXMcqyY
+90wy1byoK4KPWfhwD9skcO+nH9uZI5XB4RbE1P82sXmEm4xAtDUOPFfYBQdloq3RzUgQ5dGC2bk
M0bYsTV+9iX64FiiicmQ7MiorH/ZgxdQWQByqhnRv4JkU3cqtQw90UQRDof43jBuwGJpjNX/9BsK
w3aqnHE0UadpCVn/5cizEw5/plEG+Gge6iPAw7A44/rdgXhqrtvE99jDaPiDcC44CMMxMh04/hIv
GqyKfoxSE5x7x7O+NcORz2MHrrK9wMX0/kQ9uu+hfh6HeubrPAwA0yWVWG+rzonsWdLTpV53eK/F
K1Gmx2eOD4hFCk+7zefOLGUJdJQ/NB6yU7KSBHF3zHEIT6hgjcMBgwCCIRt2RBLtHHWe7Q8W3Jul
BycUIu38DJ3dasmrQDM9ODRr7XExO24UhR/2d3AXWMJAuiUk822Sl1v6QETVCRp4ec8fWfhm1hVW
IKFBGFD87KIbShSBK9OPUuebx1p3T/jF176vn8MhUWsNgFQ8DpOotLfxFH8f4h1K6gIOZyy/a4+b
4jj9NM9+sZukNt8YbRKlRXwYqytLiza+J/gPGq7yr63mDsgWIdOh5XTUzyxbYs984/dp5m2HikUl
PCM4lx7Kj0YEoPNEjBlLvQj3k47G+VOPTltIvOTlgx9V8PmDGlCfhSWKRXPhDhx+1w/oZTFABhhO
pZDAb9q6TdVg7Bm9q/+xsei9DaEbkE0aBq3pnMOgPWYUJw2HSJgX8orRb723JpM/P9JavCD/Iq9W
7y5wsq3PQLBt8B1Jptajncw/3MhA1p4F0PKBSK1hGx96xEuoszlbz/08GyFwXEDxI0HEka0QK+8m
0jo9SK2YQ8OunDO0SbiuIqpkAeViDprcYh7zciCiFVeYT0aU2L6j187xinmL92EXVOKy5EDvZe9w
6KXDbR0eXdeqPrLuwUxFKlAbCEqjaR3GtSmHp/gVdSvfgbpsl94lk2a//7s+7gBL+lYvIs7x7/J1
ScQLy4vs/DZxXaNNOa4fzTYjXS9Es9hbpA9xEn5jKeH7omaSwTCvcPJpDglPEN1E9dNzHcOceozS
NVLRlvQT5unavP3NAamW/535EU+td+fiwilLpWwbZnAmvky0zSmNvFijQ6DifUB01N7ZVjaJAzwl
HptWv+VFifemN2CJyYEI22WGPsACfjBF3ED0o5sTDv7rvCZ6GAKKTlvF8XVffX4etReA61mVH4Lw
otHWu6t7XCn/d7DugRV/QTCcniQyGVy/AVjPUX5QByUlpiSKZbQOpuVfbbodYdpIySvpcr1Sksqi
8RQXC7PwmmNH4C99tQ4oKrtzkXBAU0QHpyuki984pIlFeTv7/nW9u+ZRJO5nbujw98cAAX5kogS7
5o4ks/qCBAVZeIspylsfK4lRJSZ2XgToCRIZjPCu4c6Ry12g/JV5Nrb1cNShVnI76keq2g7K3Q+s
Mz+UCIgd8qP+zGvsapEXk+mishpnfiWjdA0M5m5OS/nQsWR4qOjgoeEZOVz0ZqsTO7oSXTCshdl9
gYAuROTHyQ+pXgkvbaggxXQIkcVUOFYjnxqbKGD7Yh3W+LzG8WdMhTySha+31f0t+sMshJJDO3y6
eX5IrYh13OPPLxtDI2nSTk81gEoQ+tcHppAiOupQUCZMNDYhlFhdRhp0tVCaOtGIp7kn0glxyrXp
t+1fqxbqQqvy21wux8Ie4UxBY2+g6zOPtoNEgkJyl3jXolbiIwBbsDFyxNu9qykcqPCeSn7B/TfP
YMNSz+kBXWI8f8bT/J2HNcuRpaSLu/cFWSiYmGIGnzO37s2CiMfn5klAdDJ1wa1vtiJ5qtfVimAV
uOOQKC6ku3UnnWLyGdRX0/uKtovAuCCXeNh0DRUVwTHq1lEt12Hx2Bq9a9Geob5EBfQR8onMnR6l
Lf17MB+qEQcfw1PmhZpBWF60vxB55huffNhHGd3OKpwKWl92K7jnv9GeOalcqVbmILZtfbtYN2RT
+Tkh0lwVsSlgPek2BFSgjvtDtuR/A/EB+IZwmlvnGxLsVYN+7k4/HU8vOWbYAo70ZUEi2icIVDIq
NaRrSG81jUiRr8iSgiWvp9w651d0KjIzFEzFWCeyLD9b29FI55SgfWWC3wioLQ8QejUF5V75TDGG
hzkLj1XKh8f9etXE30rtSIUt4OOmIDCmZ1svXld6jEaQ7iaoXHgzZLAVgbTtBb8LqMn84Siq8ypE
2MiRGJFBNf/1wNwEnAN6kqThXWyi6IhR3cF5I/q35vLZLSmLBc2Ohb6jGknmi425M3pa2t5RJtPG
lNZCzo+6laxrH5V8gmnlrfspLZ7Rb2w7gTrQC0IbPyLI68J1z23DKqie7Klz8i2r+fma9Y1nzAhf
RV4/fQdG6GNK1jMzt1w4pgeaqjmTQ1RyOeCq4AjVtBjpe4JWvNuXu4XuDfE//Uzt0sBkF8lY0/sr
VHSLHzxyM7rZGDEL/BVXUvL+5F8l5PDKj/WPOMgCNCqlJ4g9oh4PhkDT9ExkawGIN/DyodxhoNCG
MaGxxNZySABIGtOgQ32wBmC4+NQvGKXVSqEgmmlFqBNM3q0kacMT32Bg8Zpu062IfCW+by+LYFHL
XZtj1CB71/wdMAC+BeovQNvDolZpXe/cnyALdQ5SLNRMJSB4RpRe6r2zRcWRyE5wWg6T+MBDwiaU
eskybNAnM44yoqCbcxEK9IoSC9kF6WrUw9aVKfDOMh21F6M+CpBebhPyJ2XEeGfpH48zjQ9yAtO7
vTiSDbMpvWTcJx9LOgv/Y6MVrRUnLn16+xLt3LOMCoZyrzXuJ8vyYEhKgNBo9kmzit/b4OWasOoq
FuZYrq/Rs4CHbliIZLD81W64P4gDcfRGuEFk5+v2KFDdc9DLWzCNlSpWk5Nv2EOf0QrwoxYzQzOp
is2WPexX1vHXJkl27I7XED2qQsi3N0Ztvm0rzlIkR5woTvPVi4YpvESBJBU3X+1zhFCKiPuVOM9T
p9nJ9/swsdMRMNBclQqN4aqEfCNTMbcRP6cBGRmUVqLccwOiS/dXXz0re5NpdBL6Taj05Hw1HX5x
wRpqCQkC5j7RyaEfW/KtxuUM2W8gRBEPjXfr3LqfP2jqUF0M013+hW6Dkm8/RoJqbO+IEcXRctFs
5u4DremZAnW9uwAoFYR6b7Q+11GHz+qXIXz2NonItW3eJDCTyLXtOox70vXXRV7c0g4UkM7szrMA
YabHsxR+cBo63hxE3SMkRGMczfyUe1hBV9Z7CrrnAqfZ9Hb5oXQ8vj+aAM3Oogjl9z/KbxwHMGAr
zL6+3hDahzt6v2L5sjDk6lGgiD4OQLtRN2f+tbw2LFmlrZUmHSQzSuylxXUPSG3KsI6E+K6jDAPn
oveDMSHrR+DjO0XPZFKlGaw9RlBkwutjffr+ieXuMcfqlU9KBEJhpvgLkBaRjgWUy7Zcjf12hVXM
I8ioHDZ+nOJxzz6CcAgxQ72CoEaLYjeAPxo6/r0+KAQqVpUxJJdVJPe09RfKXidyG1yv4eIq9OlW
ESH6OWRcGYfBf9XUpc6VefvSpMq5zpl+0jWoe22NV7zY/HuTIRhrjp/yXJTW8vspwCOOsoTo+3DN
aqAuuLiq3CVo7SxeHFWasH39tQwizjxNNnsaOgRlzEZpWApvY1XiXHPhIkEkxJCxqh+mKYjSIb6T
8Dyv6ZmxV711J/c3QjbMOLbOwzP8lyVT2xJajcWb6tjEJmgwnfr3DadGgtjp8ItewSVRP68sk3pO
TsSTIk1ZtGCuqNqXMUqzHCn0DDNJRtzd4odrAyF4OIIp4cYQh/c18Nwam2gfWxjV8XYoJ1smzTVW
aU5vSn7W9BOc6nWaG3QZX+potI0DnmDfg2RNIgg1rYZzM3Vum9g0QwrEI9OgcuzriWaSZTu/zlZ6
FnGgiQ9La4vDbtSPj3RkoALOVwq1hrrlncIxGH22BdAQNga29V6+NmOurl44zXbrkYOtAlb1XmAo
I8kjTs30LPNQnGTFRYNf7ubHu/ayY6J2HFTKjX7OA2RxhAe4A6H/UGwpvQvq390ysNxllOD070H+
Y3iD05EAiislvlNKg+EqqWvsMmvUKzMQtDhEQIHNxJKdAn5NYMuBNNPCVkGQtuk05WDoT0mDvWev
BnAoQgjTr5Arv3/LOu+KMlwlElKsmYJ5qGWjYw/8zjukMi2JIJRJtpZ3SwGuxoWEntl0qNnKxYgQ
/mw2dju8DJgDzirvgq4HocwLbrqU2Evv6BNENW00+BGOtMGI8FfXt5Yjw0y74WiWobCnXiFHBHMf
swYjJ4zLJ7TKwG7PSfvqbmf525I4o97CLc7MGwIIhTWRuLhiOr5GUlUV1WCXc+KoioWKcQpkQLDW
kgF6AUeflecJugVL/J6fo/Su89rHmXkLi/53AKY7POHVGakng78DK+qq2+4/X93bEuU3rQqDuRbe
514qWXqdjWRBKL+AJB8mGETxkhaDxLEOjdGoUpdDoe81aMMGi3+OhAeK/s2j+aJCQtPg7xGjeZmh
/n4Pk35Qjh/17e4h6y6ofewVWvwaIjge88/KBfaqJB5Y/0mfvOJ+7Gl9TwJVhzCS3ntu2rrJHfP1
qmi2fkksabaa3I7dRzAo+EVlgu/ALXnybacf0GOGYWTObWc9Y65ENtf8FRJ3u1dCBw/Vf0oobsKB
3F41pRjCycRuo3K/fwyiAZorm/NYiVz5+VENpjUhu8k6W7qBINeBwca6qVallS56GHa/LIfoVECR
2lQDLNRszIWdH12CkIjxhWWGVEsc6eTedtk2CazraYm7aeSpmvAcOd2tfdkML0db1IA/pRe14Xsv
c85KZEYduj9zp5Cas89mNcmrtfCQwwGk5BOGDU/tufaTPq6s9JTr5uDilCJcDYVxFn1VIWFMLxDv
6vDlb037nmQuMqmyDmgFOlUNAEJNNp4xsJMq8X6s7eVFoJYyrdScvkQCJELGNp/7ekTzs/qJXi6I
igK0W7oIBxQmShSqWtvmS4TH0ursSOaBnuj4b5t0CpwmmPQZUekkPMwP+pzoN3rqnSPG1hBhU/3t
RQspd40DF6rrmGao1CeCjJYpQridVucUEhKfPdIP+ud/QYvwKurtGdkXqPoiLkmN4HhDmZt+ypI1
JU6Q2O4J/Aj40it/0ctEJxq4EXUe7RQvyejtDsqRoDXPjT+8pPM8iqh4h7Zy+SpVEeV2hBkmtpY8
3tfb2WXtBSqmWSuGP7VdAX0BTEGnwFROVgWnxV0Hx0JufK7aSpX5Q33eXF1SRHYhi5TugZAR+4QB
DoMnQEjabyixcNOoUhHDcUga21KBk71VpoAiMGdCdIvwoCvikMAQeDIqOcqN5hAgXgKztDuM+tqu
Oj5CxKjebMIN/XTQ9yovS1LmHP95tZ0wsVfFlqVFPGiSxNLsR88wOOp9xx5seCb2jOpfqo1slSdh
yYaQBb60Zj+zAUSqfkAf6gyLh7VCFLafRtmWThVVGF1I06HlZ5cuOCIUlZqgJVBgsyqTRClkBpdT
Apny6KmgpdP/HfLzQaVKq8gVSlX8tB2gAE+dnQY+dZIegzx7TKWRX9VdAfAG+5ZYw502Ty3EXF5h
pK4fW4k0fuKSq5oV35LRVeAPbAulyK3nhI8Q76V+bhi4GT1z7kPmjdO6wzjKpRml+YCxCsKNBgO6
oUqLKL6bwt2UAht6gfUgzL2HXzwD+NnhjfmrvXnhVJ/fZn6HFeyHJ76W4UiHFKeoa1/dIikIbx1n
GfelB+0OV8hFJqnvLJaA4FOH9LLTuJcpYEDmr8w5oz0t/dJWk70a4gGouhbOknKg4Hp9AmBF6zvW
CDa50u2jCmNd6wja6wRQDEiy4lUPaMSkMv5ISAGA817GLTvKA56rwIXsvUpQnEoIevJVbWTX1HGa
cSAU5y69qOD3h8DG00C1MO61VirOBb0q+O8OYmJmBg6xfAgNbNKkg1YAU/QoYvjO/8ADWJnibRCF
C9sOUmfikLVARHIbtnIZh70Rgdnxd/6UZU2f1SF/HKBZljUl0TwvBOxTeOGeWDmu4gqKNrfznUZs
kRLXGRQZIcCdlvLxI40sCCl9wUoReyywrMNc1hvtUs985iRR+Pj1RjhHGlbN8Ij1pj5t/353r1M9
ioMa++lXeczxkgCfBRqI1X0cI6G4/Vol7Pg2pRhB0ON26m3KzaGgrPNdGG7HzhwluDcSgz+24ATk
wXap689sxt8yMbBj4/2azXPOFABOtIs0EOnLsX2avs5WCD5en/Zqg+q8ObEhqaBR7EDeCjE835lp
7v8y/RAL+mm+dwCThCHYhITSoa2LxtFdLyFnVrvnG0k5Bx1joPaKen2MwRlXkq+QKTEy6Av7t/GB
qcRozEfHi6lN8MRExlrNDcmOE7H7lalip8PVIf2HE7naAl1GJ65dRNL8R8yjfFABjie7nXgK0DAs
p2dlLJQUtMBwqT5sLhAz66zf4c2tVp2PdOjQL5kkg9vYRNbrVocz3nobXDazcEgXQbeD2mObg+jT
/q9hmVDN2LJXr3EsLvUQWmulA/P+t27Cyj0+sHFADpSKByTrHo1md7KUNz9x+nHzO5rtcfNlV8kY
CNu4QmAvN4yki2LEMDEQA+YK2cHFs7kl7/fK+otdaXjPeEza7sCqTSJinzfB+x7+Fdh+4XZMxQ8I
uUYgRaOrSAxv1JG3iSoyMeGjGgnyItA+p3Dz5Ebm0Iu21wBBFhKDWwCeoJaAq6u611KZYUVrZ/k2
3PKwTAGDIC55r+6Eld2HKPVjbYsBZfwCNP1H9aK7Ni2yfRO0HpcFsBetZptYuK5qDuuUfdsMyIfR
XG0WET96p+vy5n70mk3n0zAi7038SJykhKT028k68bt6JstsiN3oZ1BSDTohShZgaha5EfHblyOv
gHTNjwupiuDCSfC4arEa5mn+66u2EICBrSw8lxE0/eLNBpSQKJO9eCwd/mkADlOoO2QNCcMVq6ND
CZ0/uVE+mLL/JSE2OLgqasojEzjAXntHs+Pv4uAdDg0Xfw5FU1yu/IsahSw/Ikir6RcSeLILhHb3
JNRVoR9cHawuxeG958N0Ez+LbtyyL7IgP0HPjv9ULC8yd+755ajrs+euPFl3RGLvs8I4kQBjXC92
IY+/uQqPNAlOoHEn7qrVqIRAr8j41TxRxYv+74cOfGYyWIvNqTQED1bOsvfCqh+MbtCRvn93eq86
RZ/4i6z0V18jqkdmlSpH9htieZ5OZubGI8Si/G/IjxIGBvwobcgW2tVpBHOI3dpCmnbHJO0EWvB/
Bw8glpw1sDWKtkpfVmAR3IxLd+CtrC6Exo5CE3U1FEzNAEIyJ+2Q3koGY20nWVVu2NR5bzU7wTw3
FU1opc17e8dDBzSNa5JclK2dehDPssCUViHHZ87taUqQa2zuN+/gF6jfNhYPCR/NWFw4aWPJWCBm
HqH3/7kpK3zTNQsAtLHJJ4/MuHV4LqvNq+B/TPZ2vWQ0t4dKecZsLYmFwq3FUJRYqvHAaMKcEHvX
DksexiKCHoC/CDBLzrJOcT6dzGOx4ZMbM9Nr6KDirjkTajvPH+0ZONpZv8pd4TcwoVodqeUARqHj
dXjZnmLMMdge2RlRSS+wGLqDavBPFDhYJqF2MX9anA95TdNKv//Mwf10lmp9Nz1uL7BhqRiJticJ
SG7wiTuJ3MqW/D257hsuyblhwn1aL2F3jWBFUJmxv/pzjw905y4GVV3LCgyE9uDGNJ9VQrawrZTx
Kd5Bm5/2etBpogERxfKjICssEHUsovAhjsAvW4VoZPo3pQTNmBI5V65PTziy7mByee0KB+rJFgbx
4DzVsjq7Ey1AfmJ3K8/uiJcmmR1tryTQ3fGs3kp++SpePx8Z3Ah9Ip7TvstX84CSXRoybmSULvTy
BvNVLdpbDu0oifs5mzSD96H4R2qn/iHYMrs9d3o20MLkY71Nqn5WNtiGj6FQrGCm3yyVkncfRAGu
NJws0UbQ3BiJetJkxalL3b/CK3KCT9UuOOqAzK0lCcd9fim7gdhbThqKQOG8VdG6qSTWPnYk7UBd
V7kMR1QazXK6VsMCHrHM5LcPueQSGv1SYI4J+pYH6uqa7kLMPrxMRdqz6chJv4hXMw5+z1yFvmPo
8CNjM1JU31pabrzCz3k55fBvPVo+b21wTUOmMsynURRtdqccr8MGfKJEzwaZIYqCPWPzkcTnXhDy
06kFY8BytK5Wyx+yilJ2GnvDBA0JWDuEVuBSwnQSf8YDartG2ZvMHq91ctMN8uUkgpiruh8DpZRP
TiRtxxA1Ck6ctsIj9zJePR+qBzk/O9WB5/LoSwKxaNVf5WMGRS36XaqzHLoIACLRMMSZfxtv6a21
kO3SmB+HOaBEpYL8PILHKO+pywa0ZFhdGx7u86i0FXfB65J+fNSZI1Gok4jlqkR6MgEUEbc2bUW8
NNw5ys4tu+vPROdHCykN2EVrVkpYC3iAy4XO6q4aeTX5J8IIvw9MOIk0ZPHiMs1pznTZ2JeHtEM7
0PU9/oEbJwWZ+JTziwJ3NzBQMFcEgNEunNP31h/hvMsIMRudlTpBPTChFPb1phWg4DQnDDIJFPGl
JjaHe9yVx9LKTsTjr+9mFtl5lUItTiPbFQsL4TsmB37Rc9Rg85HXWkVU+SEgRX8Pf1nnYrTuhl9W
g1EsXL1zTFFxaGgutayLBhoGYsJO5S6YGFBm92XatVXxkcpZonG3JyYac8e01/7v9I6Rkwfmept3
5Fvk95tkRdYyFH9RGaotcQbfR16jv40Tr4+OkpBymi3GHHaduA3pbW4ccgNYdULsKBc2OPBOyO37
c234epsAlVKyHKWpZRvcCOm2GVkDrd5qyhXpjjs5p+AhblydntRN5QrQn4VSzR+UX4zFoRcTuUmI
Dmmuh6x2t9KWSywi8b9d4BsQn5QZC2nkXGbQK4tV+Pmpz1TS9uwTEO0+U3UjCTMd51YUfa5F7xg3
r9BouCZJanlFWT6YRgbgzQ1bSTW0WUBT1vApnWH2K+nB7QNkZ1uIFYsF/QfNHWnqGppkTpGSsZR2
cW9wiatDbfPnV+MnHbfsm4bEFDBDBe9abqDJecpIOozlmZNoye7HkMFKhJ4Dh2QoT8o0PZc4xQTl
SIxfQgTlpOlPucpl1DcQ4/0saPrdGrIbhBZMzgMeW3SP8F/s143Z5gQjgWONcylvnVFUFvKI0zQL
9Da6o3jB2CtRjbSS2t7IoZ7ZgkbAuOs/i7HWUQQgmYsFS8VLiG5y11Pm4KE7ncAtMhycxUFxH5zF
WDT6J23VPZceZ63kAvIY/+vNxC1dbFPvNgHBdik47/B7tNh6PRytntbdgF5z9pI4UjeqffY+bKvg
9DlAMIZCp5sO08apwnqsLV2pvNgc26shrUIhH+knUnpnj1MFynf4b9JjIHq76SgMhZP+xEQiKHhg
w8oLC5FmdMsE1nG6EUeBkciggALWZC+QKT1k+XoAu1Hzqx0VkhBfYSk5heJL9arYxxVfetzwQEPe
RyYCy9R4GFxPD34qqxtvhy9MPK/Tx5rj1OYtsU9AGeqPj3Kp9nWKMr8VGD8uuq4+hHZkcLbJxnA8
O5XAPNkAq58ZoCDF+3YfULbIk64kWwDbHu9ppfcVkI3mWGGIQGcfxy8ioTAC6LdF/yXC0+NfKyVM
jfr1d7eK4ax165+cigJWuQ0jaHwNlifOHSS2QrDO3YZFcg/cYu70+tohKsfD9bESAWWwDYDGFOHT
eRmwzA3C/Q+WGsqQ4c5+DRSXFSYejH7OU366US5VBLuPkAz3YPoGCCM/QQFKPbD+dG+UBINQVKck
vLjgRGbAu5W8QNDGIJ5pNYiRG7JGgoNKRGRCYoZ4x5dX0g5sR5aGpCsAQf0IYzDktH72SNv5BVzL
f4VbCBvcCAyzNDg+9p0DbSOJDYiPpARP472z1Qe/7n7+NyHAWYuZHbUDXu/Vp+YTGqUBxGJWviTS
0WChMfbyYOPBZAdxB0kSU5Un8A2OSz2uE96DG3coVQTqQZ8TtxpWBQXhrYhPwV811Mc0M47mfe1b
i5/jOlTpVm+NFl20qIKX4dRHklyMp87Z8iT3QkCN23LJcvPgUFksWI/Igs2q8T9C4yDQJ1c+zrNm
PdRdQxglh/QeaHwVAnny21Swj0paT1sWARwGoDBZlGO94v7azd8KDr9FeoYZenEi9Miatw40EzCJ
VjLvb3LHumjWkXl2oMYsgTABLs/v92gR8VxKqPtDOmZgjogzg1rWDBX8uYrVU66dxtgYRbRqLl/E
wKRbMCbnPUgdptikW4pP691vADeiUuZv4RntgwgNUq4usbtfrv0CBilwDgckeOjQGbXbzGMPx/cF
U/rFm86cTzIGSNPSEk9G56/9ewjux1ikhQW7ok53Cozi6yV8VNdXIwBrdYd7oJSp8qnYYerYLDgx
cBzw1mOtHmQ9dlGiV4vWe/kwilgqcNRz3tCsnzdb6k4LyGliKDdTP+qIkoleuyxQbprlZzs7bZ6P
gqR4IY0Ke3N36rlBBbZ7Alpa7SzMasbb+2cmrvWbYQB6JGcltE0zd6jqElkTdbD6pfxVVvKHnMuz
OzXpoXVXBVEs2cpYnxGk9pVuemmS5Efw0/fDKebkeaavJNTa1f9ymJ/3NQ5C4A+b8DFPt49QlAca
iGtE6aEJgFMXdTKN6kr5EofAvGR4/v7AbD15aM5zwe6+u1W+QYVtZ6f1zB2bKQHyLg9dUR0sH0le
pLCg0f3gM7LZGPdoMw9MwE4kVeXnU3h87NNFd+pOUIP+ImO0wms1MByGzsjTGpLMFLI0bl/TFgNu
VohG0MtopBnCImI4nbdhaWC5nM1q1WFYoVR22wdAFy0hzy9P1r+j9oRPwuu2wf0COAZ6Y5l16YnV
Faop/BsO/ddNXfwa8epfD6iaFhIOFhIWIvsDuXuWE0+ydK/pY+QSmVRmcyS2EFSznHankFzjbrrq
lKNe+pIctfVVJAzIUm6+hdS1wu31H8s1oj6NyxOOEX2yE33UiIzDfMw02C4bw0VEspmv5WI4VmTF
SWQlOzW48bc9EIFO3Mmf/09BOWoDpCIRvxDjOwpUOEkc0O3xBIu7JBbFJY9Z2TolhXnyKlTEcZ6q
lQtCvR7HxudE/NHUwTAVXjBiNAHdBOhSdSdpGr/R3iYbLCw6kd8pS6nd+P5x8HZGO0pNzD4GMrn1
F9ZrEy1VhtrCEAjgZQliAvJx8sUf55tY9jEWFge9WFmWK/onoYRSEKNXs03Eaj/T2SW7Hk5rc4Cx
lIgcMVHLMsQ0Hml4REPyOXtjsxgQifiV5aXHt1Ka1vwo5jkFZcha4iW1ODYLGaTyjGFz+Sk8+0m/
+4/KOG3wfCzjLsN/JBCsAZDBpaKpeQxTCLcr60vsig1ly/oJVrhFJtbkGRsHQO9KVerChtJ25qov
0ffY9mnkfwfClXs+QqOphHPwo4okxCI+VbeTyjnZZDTPDt1KZO7lk83AW6oMIKppudeiLsLHmw7h
hNdiruAyOWGsAj8Nqk6pk7aTPKCeOsJccT9GmgZWpCjHijKcZZzKcXT+GgSiDSQWNL3vrDd8Fgw3
gGyz0qxqwF2VOvSZu9ZujSzxpYyZ8xj9EHxgS3x7frHzDcIGC+t2wdZa66qxhGwFfDcU2/1fgK3s
BKJ9hC4P0hP/UuZXuhbI7KXKJ0r7uS11+JLPfIUCD6LUTlPGW0Uu6zDrvovHu8Oe12PdX4Miwa3f
i/UgQevcHVGmWEbM/IAA5MFLkSa+GQqdOaRbwq6SFzCu5UwGgM7TVto0Fwy86orEiLERL75ggfcu
crLVzZkE4cWv/B88E1x69b89gW/FoRT8SnYsI4eXREzxAAsUStcXLecZoVEIE6K/696E2Vd3PNkg
Y6mdTjMZCA34/fCIseoxiM12U7mJ+DL7o8GUhpgQau1oUCAEssOyNuHPp3yhNO8r73Jh6FTRPGMa
umU62vYhdYExcg3t7Ur4UFA7l0hUag5DgADQCdZuYnNFkxhD3RUa7mbMb6x3kje+5O512J5XJSqA
TbLHq+LDtLDhh4CEjicxA+9q78RC3QAIad5eNKKXKmshYrg22ro6B2ObVOgek0sENBkeHBxlWgT7
PZ3sBdKI8MpobkI0niUgOjjLYHr3sJH11F17Ro9dvCZMl1cBHZaEvqnSyn2YOljoOznFrFI/kX4O
VDFQMf0NBlO1U4IVZbbbf3Z599sgp2bUW2AsyrNJ3rmdxLs/QN7c3X/FqoFd7ZmyftNC3ZXEgFAM
OFDPUXZD0GYdMXBB28OJMlTj3MjhEwF6B28AstHeVgZXjS8TuAhcbZzvQ22N1jG7Fbk6iUJyepWu
t0cIlL+Dyb8yiW33Vn65BJDSH0AxyyTf/yYsUs3eHW0YZUA9JMzOLsGv2MvN58fZV+KDAPw4MjKD
lImAmw5qbjqeTtjZycmLG0+sEslfrOiN/qGGQf8Hbnnxz5y+ITw5Xat75UxxBNg9w9tavfl2+mAh
8ajs5VS+y9i0JmTsGsrAxmxJQuVQVbW9AwheQCwXUWAuCnueExdYMUo5TFDlMzBV9xxMbgSCmEtJ
WXXGFLeBSiL8dfIw+Fvr3MYwHlR1O8B+iEc+OKpqN22Lw72rfDKgE2Bodw4qqV5I0MrE7w4fRqBH
MvmFcHe23zJZd0vMtXyr+msRGGFVjjqGSmnGSMusWtjCg5uRhq6KjWiFxXdpnuW97o7CKtCjbzpT
KwSVZlsLADdcCoOV+AVrCNWuwDbSNXYzR0hjb6MLEDtUy7qO6bCWGgA+qq6oTGX0pHJkaVicTxm7
nILTWCCcBBr/R0HqHr5gQQn7k/Tl4BZrloNjv2kH6Su2fJ6H2O0FXOEJP1qsNNuKwk+9FYAAMW1b
TgQGb+RaoInpMbrFmLXshA/UPfpashnbvba6m+iC0g9Kf0WAg6fsNM+Uu/s96V913Pd+amQjpPGp
upamTpi/n7/mHwIu7J+TssmzY6ohuqlFrIrB/ZRvj1g0Ua8HxDKglG08OKvxDcAY+dS0q9Y+LEFH
9f7PizRG6Usiv8Prg+Zel/s/o6KC0GXMo6RJQ+0f7ckAKefluczIKqdTpJCGKoesBlyp5Lze6VnC
PJi4C0d1x0xalUR4xr5VzMjT4ZewxG/ecJ1EfsVfIigcfzUbUoG6xxKR0olqP8oRQJnqyowveRWJ
LzCh/4SG9WQ+Rk+Mi5NVIm8TLEHR493rfT2rP1fOm/AQmeF9qbS0ezwxcfFYTmKHO7Di/6//RPvi
xJn1+wFx9VZtn62AGimYMuy2sTbOYYGma4Z8E9wuFaPYBeClZs+KYFjZUZu4iKZ4vJo/xLq3wqDc
XzM2G76TdAbJoeje2t/zz9X+pDVi1U6tn1Br89P7wdTgyuDq+o0jKWpQS/XpDbeqPALrXRe9MqXD
/gZNFzHZXr2KIUEyCslE/kHZm3PeFkl3g8QxkrUvPABPEPk4/EqALcT8pWM0x1lu6slMi3Opr2Kl
9VK1wlL1Eeeq91uRE/eQiCuDEmQ455O9kkVq+cjrJqqAaNy0airjbPLg2NdLsCq0HzSsz10eOlOi
NejNNUHjr7egYm3gCMpwCilzg60gR+RON0eeGf+cpBgt4N36tKnAaj2QAXSTanxQIj44nnyLBIPk
ZSr3h8IoufEY2Nc+PFA472+KQmoOkhvqlflofnj/iqW/2/1c9ECs7WXDjLv3swathg4rYEclN6y4
7NXtq7CKGG3N3OHiUyLH2PNH/CAICF7/X161ppOI327QYszLqqh+TOkq0PaXGHkvXmGHtml+rIWU
Lz8V9xvio7EG4l3M7iDEsa0fJdFfzwXpX9NUO6fsXBBf0AKIg6OG+mfahBh3kqYAjywdzSEz0Iel
oglAeyx/P+vL66+wAUlNomRknhZ3D75FjFxOONMt+rCvhwcOROpPqeww0nuCwrw6u0CJftBEtCq6
jq8LYJEl6nsq+UtE9Ysgl7yCZUxwg9XPFWrb6W1EjYIskkAGyp9Ymns9z7b+RUP/YmzZYZSmy36q
FcvfxCEefN6jiyMT8QLGlazKIGMu+jg5s3VabWnmOcTHDrvfJtxqej8FIkquyS4htOcLh5Jpku+d
eu2ZHZnBSK9+QGc97y9pQFKfXCnRSULwFlyth+3haJPdSt8rDlxqDHJkGEFSv7RPr7w92WYOSwvL
79iXx1+qel/j1SNOZxOz/4X4HlgDtV31LhUjsZVwLSgLfvcE3v34VDgvFfamsaR1d3rw10J37k4n
QHMGeyvSWBI/PTOOspbRKcqykLE3ZpoGpJ9EBw8nCVfQtTR/9z7zxKVZ5U1IBqcorBlfEyKHrs7A
cHGQfouTjNN3yOXC4QwEu7ouubFIkiR7aLotEGf9sO35z+bnDku4+Xmpq3V/yOasBSzfp2WUziJh
YUxp6iL6VXy0WIb9TtDgnzjTZZb+lr+RJsCI/dbl8kOov3l52iU7AKjCV8WA+ghTIMj9UA0x0xLS
WKng9xS+ZJHKDcCZ6WIIKZW7ET0H8ohmjSRuLVpRIR/3ss9R4u7R38RP/moUr8FqZ5CVIM1dlFTd
Dx0MZTIomzR+E7rEism5MzmVffwc4xziRwibIxok2HUc0P4ZiHPKTvoCucbFGYOSPJSHydnW3uYM
Yui054yRPk0gD9VorwOUaC8OGNgpgsxNn+9B8o9raYz7d1ebXZ2d0vLWuIc6crGLzwXJflse0pdN
6GAkYsziG07TV8xZzO4hjL9KLg3Mj9qe4xlhuOnmOCvKoGFcBK/c5kHTaT/t9106vFzv/bT0c7jf
9WPyiAF9cBss1a9vMhUR0ftv8eK3VuozJf1g9rp+aFfoBn8tROslmf8b7FTDSVnv/vcnr6IZJkKe
IhJbuJKzH84avU/us6fKkC+XA+pGp6FLy0NTXkdNn+V3P8pO6d+bcvV3gD4JtFIRudM8UQSxEGkG
rWolr6BTpBWmRjLkjOugUJDALb/PnzHxW579o9csTtVStNCoX5DVJDCZvS2yUrDi8WpKmODeY63g
Li4XX00R+GMFs4dY5lgvlw7RongEw0UL8CSMBEsxlXTMY7uHrSHWpfgQmwLYH9ic/qFpmxeGbO+k
soQcW9ftt6dkIeA0y1jwAq3Rwmm8EJy3FmusHzLmrzXda8ALjyLcgDAdCTaMZhXFrfdvIaiEcPgP
3DWxy/lzNayqyB26euaTB4kBivGkq3lPF7VaWHYZvLpuizFhRXK80tmzl5h5XMSb2lUxF4ER5lge
3DKf25IQjYtMiFcRifmVEFqc9WbfDSwVM/VLBde+3OPZhByOAeGqfK6vUCx6Y6UMjCD/XXpC+yUQ
AdrbiGIFPPpDNPfWq4uak7srLXToEPO1rASly8G5MSboMKH0BfYz27vt2kT3phBPDp4VvIc0tPzD
aApzsH3sLx2KmBm1RavPTN2iKIbpPyDehR5tQsiH7FCgBERtnHKmGBcEErOex19GVZaO5OtcmC/+
Af1knp+j2G7TRSgZYdxtQiKXJuKhWIk6fGB0DEozBXhFDLQSZtbRFOE0HH5jIzzPsizcjNihv8iR
EQJXR0GlS2y9GUcIU+4A80aMnVrFhBFk28WPAryZ8uJ58uhF9fu6Z+/TT7eeql1ZTLgJ53A+tsxI
u+gh8zKKD0e/+ZDmUhcxTatISnuuTHmRPly0c32anrnMeMjZYEoBH5O3lP4VoVoFptAFNesC3xa/
dzaDXL4MTI3PY4X0M7TPJox9In0L+5WKiY1OPz06ydv2L086Hvlu8aafQ6kqzinOQLh+AIEqmFB5
1hfx9qKisMPr1uEfVsGU+JwW3GdRkWEjOL0l4N/Q1E9cSQX680kI7ygaKFWBb6/Kx06h8Izomun1
7aw0ctukBUSFtwpz8HTwEm/yPpvbqwmAfcHGnnkW6Gjw803l+ys8wsn9hJd69Scnmd28yVppCOfE
gnjg0gd0Ch0hXZ8OHtYy92js3LXJaMEtqbhGoWDJ+Uc3eG8/k+xPVjT2jJ2Ye6ny7stqGyE/7Mu6
3msHwPdBc9XffHpvYEkUnBFTbKX3I5NnedsS0qIbbhXI6EJSkptccWLiooVATPpU6eIkYoZYAhKB
kvuXf0RZcbMPMtxCGQBuINwZ/4pyX6EYEsIeqc6pxZUOjDN3G++T8Gl0zphq5Qvkqp8qWtiEL0kq
XgmGNJjFcATBKdcLaMQEzbzM0LA38l4PQgG3OoIBaN7Q7zoAFT3lGz51hCraO1T+0SfWYtoa7/FV
I6fgKFAWtuQRfNIz62xfHgC7wXSlQWzV55mN1FM2FhCq31GZL4IxtYzC6HYjC2KTcaICz1+DtjjC
Cbfz0jiZEkWE/fqJHtqK6DtQUEjQoYJ2JCpfQhezHVSpWG5FL1LUbkSKYLxt/isLaocM042tkoTe
T3gwBZUU0oK0Iz/Frye3cMgIIRrW16sivsW8iHGrCFA8azdn5lDxv9jXgNVCLSwsNHczrxyWOORg
8s088uL0+oEc2RD8Kx68K/Vv9SdRGNo36VzDf0VeE9ClZGzVhbjHGwI+QFINxSquoGwiqIfFsGs5
z636HJN6UJjp/P0OikIwXNkXtlw9MM3fFfnq/rKgvN6Py+M8dslsrctrxVUl4m4luu4uU9q+XVT5
SLEojft33dRJNg7PDLEi47+tTeYajuqNGJWlUJTUbnTqnuHFJgdQXYfNNeSQMX+fXZAiX+GTEm5t
Q6dNwS0qEFq3CEi4sLGI698e9B8N6EH0cFhkXr/x7i4mMlazzn+r/W7c7PR3jnoX9NJoiBaDjEJC
0R+dnxyO2AQc1OzQqqNJ3NUYH29X/BBBcolHo8/Wll0LeSCQ8J9gvttuDBjIjzkRihbcGQlnST21
TwX27XMjT1FBpVkHWJT+1TXnfDZPI4IGed2NMokBqQl0Pchzmr6hHLNuqoN4oN4mkbvoQ46ixbn3
7KKXPk7PxwBII5KLC1pFzI94bU8RkmgSgqRzeQIf3Uh207+y/PfEv5W3WUTfONafL8gAftXExywp
Zftsj2NEF+djvludjP02k8MnbMxr6dh/vcTaQaIgWqXKjB1+UShjGAXszHbGOJPbdFhSrL0TyWpt
r5TO9zM45yCOPRlv1Je+AdlIqM1oXKGpXtJsveC1lX98/S/M14XnT6h8eX/G0dF3vs+y3fESxeyO
IidztPupnH5oPLXEbDeCaU1nMiw5DdPIoVmM8xgru+0RDgNtoPtavSDcApaFHXrE//puOkDM3TZp
wvf1qMuiyAjBUpu4wrb7ETfqmw6l4noRdbK4Q6nBRH5+Q15ueA3AtGGs3AI7OxPkbelIw3ryc5NY
fKoqdM3awLZPIkOZYcAIvPkS+Q8gzyBmUzc4+lN9s6k546xx06AUM07/esW4iKseK5BvXLLpCPaz
IaEKFHeZ9NLF8Os2VyrOitvu8c3j9z0nGlO2e7eElWep9hTVN5jhs4gfOPtIKnzwG8G4YH8SYFBS
68GhrPt7fP4ll6SWX1OR0KLg9xUedEtmD5sQoGreP1H20nzK3gCj9rRxydUsg5QMO2F27BSeEcJM
//RVX2Q8Y1BjEmvjsxdkbeJQO20jJ9h1RZOCuohy3FzjyzS8YKiAwwvCA6LRO6JcmM+5ZyIyJtVS
VSYBCOGcvlfGDaG80squJZZlDdJCXukcNwDIUvK0ewyQnkRO93NaGtAGA06VFTrYzBzDOTBapgVJ
o+743iJRh+Ga3AMnW560duI7U1E4jTU7BLzCBKBcSHwCQGaWRc4fgc/14TaDMeZbdZIyiRb2S4Ra
Pn9fKhpy1+f27tAGY60nx+T6no8x5466uS3AfVx8Fp9OICaBjzo+MS7ggd3rchwE1DQED6Co2q1K
pcHY/OR3Fi7zZHF7R6e22pj3OkKlNWFlDFj0Tzc0AUT8jpXjjvDcCQNjvapHy8TCfGeNZZGFd327
2cL84hnkiIFrXmzyo2g9KNKV28XSaC+qdvmxHvMcX1RJYcLckplvLThBu7DQ8zpxRUJLVSrfDzS+
LCXtOnk9j+ABhGCVDoVNTdptaRF7SzUR0bgH0Rji+3T5V2csHqT1eaARUv1I/Tz5qhWi6/CHhTy0
yjkddIVFOflsS0D8jV5GjnepjE5Kr+1U1/JpwSJpZaqFc/p4ZOZFb5V2h4kl1C7TIfNMPEm3C2TM
djq53rxhSMFHcz1PCkYqyb4hzn/m/f6rWbRbN5vbCt4lQiCpLNxV4x6Adq/llurIj4NOH/Mw39mi
fkHJDT6vOFGPOJLnAdFzVtFxghkY7dfuoWW1BqrAZHqsK0j37aRGwetZJvvxq/vUFQYtDo26boSh
nItBy1fI96Z5ja1WcRR66zyiJ2H+swur16s9X8dtm7DUBwmIFOZ+dNSP7G7F68T+WToGPEVhg88d
uipnjF0QFPtgbZlX06dTt39VCuxPlJSH6hP9ovG6jlGv14n2XMN7RCotngzuRsmDHOKvL1JD5YfT
P4XonFhznd9+C5pxlckOBhTG3iX7+/FMI45UK/W2DqJxaJrZIafcJOwd8ZWYfOTv2LJCQsKbtQU2
gFFMUSzPhq1b3z61R+43OnMRJf1MBy/O5ekVBMHVn7fMeqVnBT1fJ0JUYmdCWD7Z1ru/3Mlz2MJg
SwgLiiMpLqN6VWtVmGoXVGpP9n0WmfPfjf0U5PE2S+SGFZWNLbsrH2GADunIS2HV3l6RFW/AIiiy
TZtKesGPzuqO1y6LLRbkZu3XlhtXwZ1InlpNAFKJI6FzHIXUsgpFAHPmka5OLalmxJDmd0VGNuMO
KW1bCIWel4EG5tO285McqE23FWgiT9DYJoR62CBSkj7UhBOoNpHb3Rw0LrlwJqtaaXAYUYSkOWvC
+x/0vy/E330zggiDjEvqJGeyt2XZQjgp1x12px3bwav+17o/Y9mRdDeddqnizppmH8EquXWEYny7
+SNI5KPosNBqkeA7KD1gfU8MrSFj6FlIA0WR7NQy2LE3zjgbIxZ0WT7ldpwDcY/E4r5jQqu4i2O3
wcS310jW7tcGBLiBg4zqeqrJRU7yY+Wy0PJek01B9fjUZ82sTA++54nxyVI/DAPcwuvz2TPCZ7DE
Pb3VE5VCVjgpxRYgWM+2Rqdr504ppvLqQIOuerCY3boT27HzooNeL7k8kSEMkef45TnhNtCtU44H
ueTEXQbaZD1BYcYfVfy6IkH1P8IFeP9wGDwLJnJcntPRbInD+nX4kLYvvwyH7GL86AoEXGsqZwN+
Mc+95NP3XbK4etn+mBZEIT5BmU9uGC3xdDqLyhXyhMIoTQCOyaY6evGCpXmGx4vTqK/CBz8E2OrD
Tx26ls4L6Nqipmkdoo4nT99dTC9yfgYMrDhosTUlVPpa/NzJhTMYhz542+rMrrmQxIZ4wEg1u2Yq
Y8z2Z8DugNY/KIhs1wpH1V1vuex2jYOstjRoH1a3+g+h9sIw4Z0s9A1taz5Es7aBQrKGu7NDuSY7
Pp2E4jkYelC281JYj+dFWrlC7DiGhyv+E0J+HiygMg+KmX+ypq6Q1E0TLjjxV/IQbPbjBXpXZX0A
jwj98RRy0PHSyj0fSuvdrihRepJlJInTgtzFsUBIm6RtDH/jgyBU0UvUxypDun6uWUL8ThOYkti6
ZSiUHakZojH0lF/voCKetRd+The5GBjgFe2EaSzNHHetczUeXR37L7YLJTMkd7mKuSMABShRTbH3
/sQiyVNt6J2oe4JoA2fjUDP5EG1uYEnZrax1Ru2S+k7cePtjDuG0ySeObBvs0A3/Xv1va6/6dnAq
VXBnr1FHjNQcH9eZi7Wj20f/CLlqw9HYwjyRjM0pFLRgvNhUDg8h2XHfx6AXXinJnSJxSqT9GVF/
S0wYhZlwQ7AaEghgyF70rN3r/X27Nx5A0vFX0kWErF66e02P44UVueAVgYJ39FKeYMjfcs5KsYPV
1s9Vr3QHPe5UGbrHUpiBOK2Zc0omC0l0g3JyRngjgRSoc4zqBrumfRtOrNuEjuVSG/ItUd+9a/8Q
A/ltL/3QMLNj8hMf6o2ZiikOBY/t88LTUVsdHdSEtdqyBei3jIIgRDAus3EjrjvQqTYSsxd9w9SL
D/2Y4z2lCWcu3tpSVwUo/7DQ9VG4kHovnyhnA64QzgqQFmSg3rNgsjBV+/pm8/eY+JPaHS57fsyL
UYvQVsp1iiNVAVZVszPDmex1f5V9+U9p391pg4muz9TRInomY7ND712GDHlEuTwUo2+Y0L3USbq4
rgerWZrCnkzDiWz8n0MGgxymwPC2itquyy9UtW4zceEx6NbO6g4XqIxFgrgrbd5ST0sqzRU2Qjti
bekjC2qRPkMzouqfib+UByWfDQMfQvomd0HW/ZR7IzCBkZFOZO5ciu4hAe2wjZuT9F3IF3Lb4/7a
U6XtqCGQgRM8mxW36EmRJOnmWJLmLqM8oj/XzwdGUDVTHkfNNjAc1jS9VxeyZZvOR4nuzByGeae1
A0UtcoiUU0jz5O7G7Pzvf/SN6CYYpP5kOLtNKATLhW7ZSQSVq0/S68Iyr4zfRYgISbnhrCfiAEpq
tvGmxwlxA/92umI+JQNv/IWmZxjo208yVFoBD8emTiha4y12M9lJYmEmLFfQEShH1TEQcEk9pTY3
zx8foZA60VEJ++6jgMDRquSsWY09JYLcRb16ZURSorC29x6SrY+R0hWu0ZO/IsYqulZeSGBu2es3
kPryfkvpUILCpOGuHbP/FcUIRUhTHonSP0h+bRtDj/7cEwyqpePD7DiYxs9jeav79L8IyHGx2UKU
iLfSWyglxQMfxWEWnRbYFZpfQRA9vWrMo4MvSXeAVTP2OtEVWEFFNx6rsreQ0dAzmCYVb43qJyQl
eOqGQNGt4PnvnRvAy8dX3ZcskaCaLppv3C9S0ocLGy8l2Qz1Cfoy9WlrCnbIO7yddoneHXOeChVK
Ymwzp7IPoIJQT8q3wmD/wnfkksvetN+2b1KIwe1HK2q8X5kyt6n/LhPJmNTPnWfprqU0DoAa5Bfm
lUTi6XA9x+hR7YjNcqpY2wl4gNi5ocBBTjTT5Se47dayGNBaJl2ZiHUUzVw823RITHTFEH4TsnYB
yfBPTf/+Ec6HE/b/ia1G50a3h78DRTeUFJ21C7GpgcQYdtSmUYouedogaw2U9/fCOuDANNPoL+fo
lWwOPEat3/TZ7nZ6gnWDFJCCOHbLcYw8GRBSEjX0docygbufO4MFHyusBbc9NBJ6qO0pZ+vfWiZ5
7gilEkduBpGcW/qSwqL6Ofpml3cW6miD32Af9pe3JCwXsthKDOt//Nnfwxp9KD+EyXvYKEXf/BYI
95vgtZKhymPUqaFlJKQaQmyV7FFDudfdcy9v5YHPjNQRkEWqQAcFawPs0KZXkR0IM6RoNn7bAoIq
wH/bBzU/A6WpEUAFLOn+v7bjPAWQ2tu6zzNGAvXmCfPu3EyXLukl5VJiYT6UGXMWTVOC7CMxWHYT
uUmCTasuGtjxkXjEyeij+Tzn760WqtJRBvNriX7IYjhUPEx2lVN7IJYMS81+ESD0kd/Q0MMq7P51
zSDOxSgB2Kd8l0rEw/yYputULjlqSbXnKChuJMmEO7Rizasom6J0dpkwx8Qy7eSGA/mPUspmfHZX
MUqhpPI+2c1jESWfzoa/q0dYq8Ctr8Wvhw9FfBzSzmUCOZiYi+rqq1LOo71GzlMcvj5grYUSt0HJ
dp64HQLzeINA3of4Ltamp5Uz2Qhk/t0bCj25xB3rrfMoORMPiU4xKder9tFQIdzbn4F+kjY1XTS8
Wq6N8B4=
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM is
generic (
WIDTH : integer := 7 -- that makes 256 bit combinations
);
Port (
CLK_66MHZ : in std_ulogic;
LED : out std_ulogic_vector(3 downto 0);
duty_cycle : in unsigned(7 downto 0)
);
end LEDPWM;
architecture Behavioral of LEDPWM is
signal counter : unsigned(7 downto 0) := (others => '0');
signal ledstate : std_ulogic := '0';
begin
ledstate <= '1' when duty_cycle > counter else '0';
LED(0) <= ledstate;
LED(1) <= ledstate;
LED(2) <= ledstate;
LED(3) <= ledstate;
counterProcess : process(CLK_66MHZ)
begin
if(rising_edge(CLK_66MHZ)) then
counter <= counter + 1;
end if;
end process;
end Behavioral;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library commonlib;
use commonlib.types_util.all;
entity asic_top_tb is
end asic_top_tb;
architecture behavior of asic_top_tb is
-- input/output signals:
signal i_rst : std_logic := '1';
signal i_sclk_p : std_logic := '1';
signal i_sclk_n : std_logic;
signal io_gpio : std_logic_vector(11 downto 0);
signal o_pwm : std_logic_vector(1 downto 0);
signal i_uart1_rd : std_logic := '1';
signal o_uart1_td : std_logic;
signal i_uart2_rd : std_logic := '1';
signal o_uart2_td : std_logic;
signal i_flash_si : std_logic;
signal o_flash_so : std_logic;
signal o_flash_sck : std_logic;
signal o_flash_csn : std_logic;
signal o_emdc : std_logic;
signal io_emdio : std_logic;
signal i_rxd : std_logic_vector(3 downto 0) := "0000";
signal i_rxdv : std_logic := '0';
signal o_txd : std_logic_vector(3 downto 0);
signal o_txdv : std_logic;
signal uart_wr_str : std_logic;
signal uart_instr : string(1 to 256);
signal uart_busy : std_logic;
signal uart_bin_data : std_logic_vector(63 downto 0);
signal uart_bin_bytes_sz : integer;
signal jtag_test_ena : std_logic;
signal jtag_test_burst : std_logic_vector(7 downto 0);
signal jtag_test_addr : std_logic_vector(31 downto 0);
signal jtag_test_we : std_logic;
signal jtag_test_wdata : std_logic_vector(31 downto 0);
signal jtag_tdi : std_logic;
signal jtag_tdo : std_logic;
signal jtag_tms : std_logic;
signal jtag_tck : std_logic;
signal jtag_ntrst : std_logic;
signal i_clk_adc : std_logic := '0';
signal i_gps_ld : std_logic := '0';--'1';
signal i_glo_ld : std_logic := '0';--'1';
signal o_max_sclk : std_logic;
signal o_max_sdata : std_logic;
signal o_max_ncs : std_logic_vector(1 downto 0);
signal i_antext_stat : std_logic := '0';
signal i_antext_detect : std_logic := '0';
signal o_antext_ena : std_logic;
signal o_antint_contr : std_logic;
signal iClkCnt : integer := 0;
signal iEdclCnt : integer := 0;
component asic_top is port (
i_rst : in std_logic;
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
io_gpio : inout std_logic_vector(11 downto 0);
o_pwm : out std_logic_vector(1 downto 0);
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
io_otp_gnd : inout std_logic;
io_otp_vdd : inout std_logic;
io_otp_vdd18 : inout std_logic;
io_otp_upp : inout std_logic;
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
component uart_sim is
generic (
clock_rate : integer := 10;
binary_bytes_max : integer := 8;
use_binary : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
wr_str : in std_logic;
instr : in string;
bin_data : in std_logic_vector(8*binary_bytes_max-1 downto 0);
bin_bytes_sz : in integer;
td : in std_logic;
rtsn : in std_logic;
rd : out std_logic;
ctsn : out std_logic;
busy : out std_logic
);
end component;
component ethphy_sim is
port (
rst : in std_logic;
clk : in std_logic;
o_rxd : out std_logic_vector(3 downto 0);
o_rxdv : out std_logic
);
end component;
component jtag_sim is
generic (
clock_rate : integer := 10;
irlen : integer := 4
);
port (
rst : in std_logic;
clk : in std_logic;
i_test_ena : in std_logic;
i_test_burst : in std_logic_vector(7 downto 0);
i_test_addr : in std_logic_vector(31 downto 0);
i_test_we : in std_logic;
i_test_wdata : in std_logic_vector(31 downto 0);
i_tdi : in std_logic;
o_tck : out std_logic;
o_ntrst : out std_logic;
o_tms : out std_logic;
o_tdo : out std_logic
);
end component;
component M25AA1024 is port (
SI : in std_logic;
SO : out std_logic;
SCK : in std_logic;
CS_N : in std_logic;
WP_N : in std_logic;
HOLD_N : in std_logic;
RESET : in std_logic
);
end component;
begin
i_sclk_p <= not i_sclk_p after 12.5 ns;
i_sclk_n <= not i_sclk_p;
i_clk_adc <= not i_clk_adc after 192.3 ns;
procSignal : process (i_sclk_p, iClkCnt)
begin
if rising_edge(i_sclk_p) then
iClkCnt <= iClkCnt + 1;
--! @note to make sync. reset of the logic that are clocked by
--! htif_clk which is clock/512 by default.
if iClkCnt = 15 then
i_rst <= '0';
end if;
end if;
end process procSignal;
io_gpio <= X"001";
udatagen0 : process (i_sclk_n, iClkCnt)
begin
if rising_edge(i_sclk_n) then
uart_wr_str <= '0';
if iClkCnt = 82000 then
uart_wr_str <= '1';
uart_instr(1 to 4) <= "ping";
uart_instr(5) <= cr;
uart_instr(6) <= lf;
elsif iClkCnt = 108000 then
uart_wr_str <= '1';
uart_instr(1 to 3) <= "pnp";
uart_instr(4) <= cr;
uart_instr(5) <= lf;
end if;
jtag_test_ena <= '0';
if iClkCnt = 3000 then
jtag_test_ena <= '1';
jtag_test_burst <= (others => '0');
jtag_test_addr <= X"10000000";
jtag_test_we <= '0';
jtag_test_wdata <= (others => '0');
elsif iClkCnt = 5000 then
jtag_test_ena <= '1';
jtag_test_burst <= (others => '0');
jtag_test_addr <= X"fffff004";
jtag_test_we <= '1';
jtag_test_wdata <= X"12345678";
elsif iClkCnt = 7000 then
jtag_test_ena <= '1';
jtag_test_burst <= X"01";
jtag_test_addr <= X"10000004";
jtag_test_we <= '0';
jtag_test_wdata <= (others => '0');
elsif iClkCnt = 10000 then
jtag_test_ena <= '1';
jtag_test_burst <= X"02";
jtag_test_addr <= X"FFFFF004";
jtag_test_we <= '1';
jtag_test_wdata <= X"DEADBEEF";
end if;
end if;
end process;
uart0 : uart_sim generic map (
clock_rate => 2*20
) port map (
rst => i_rst,
clk => i_sclk_p,
wr_str => uart_wr_str,
instr => uart_instr,
bin_data => uart_bin_data,
bin_bytes_sz => uart_bin_bytes_sz,
td => o_uart1_td,
rtsn => '0',
rd => i_uart1_rd,
ctsn => open,
busy => uart_busy
);
phy0 : ethphy_sim port map (
rst => i_rst,
clk => i_sclk_p,
o_rxd => i_rxd,
o_rxdv => i_rxdv
);
jsim0 : jtag_sim generic map (
clock_rate => 4,
irlen => 4
) port map (
rst => i_rst,
clk => i_sclk_p,
i_test_ena => jtag_test_ena,
i_test_burst => jtag_test_burst,
i_test_addr => jtag_test_addr,
i_test_we => jtag_test_we,
i_test_wdata => jtag_test_wdata,
i_tdi => jtag_tdi,
o_tck => jtag_tck,
o_ntrst => jtag_ntrst,
o_tms => jtag_tms,
o_tdo => jtag_tdo
);
flash0 : M25AA1024 port map (
SI => o_flash_so,
SO => i_flash_si,
SCK => o_flash_sck,
CS_N => o_flash_csn,
WP_N => '1',
HOLD_N => '1',
RESET => '0'
);
-- signal parsment and assignment
tt : asic_top port map
(
i_rst => i_rst,
i_sclk_p => i_sclk_p,
i_sclk_n => i_sclk_n,
io_gpio => io_gpio,
o_pwm => o_pwm,
i_jtag_tck => jtag_tck,
i_jtag_ntrst => jtag_ntrst,
i_jtag_tms => jtag_tms,
i_jtag_tdi => jtag_tdo,
o_jtag_tdo => jtag_tdi,
o_jtag_vref => open,
i_uart1_rd => i_uart1_rd,
o_uart1_td => o_uart1_td,
i_uart2_rd => i_uart2_rd,
o_uart2_td => o_uart2_td,
i_flash_si => i_flash_si,
o_flash_so => o_flash_so,
o_flash_sck => o_flash_sck,
o_flash_csn => o_flash_csn,
io_otp_gnd => open,
io_otp_vdd => open,
io_otp_vdd18 => open,
io_otp_upp => open,
i_gmiiclk_p => '0',
i_gmiiclk_n => '1',
o_egtx_clk => open,
i_etx_clk => i_sclk_p,
i_erx_clk => i_sclk_p,
i_erxd => i_rxd,
i_erx_dv => i_rxdv,
i_erx_er => '0',
i_erx_col => '0',
i_erx_crs => '0',
i_emdint => '0',
o_etxd => o_txd,
o_etx_en => o_txdv,
o_etx_er => open,
o_emdc => o_emdc,
io_emdio => io_emdio,
o_erstn => open,
i_clk_adc => i_clk_adc,
i_gps_I => "01",
i_gps_Q => "11",
i_glo_I => "11",
i_glo_Q => "01",
o_pps => open,
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
o_max_sclk => o_max_sclk,
o_max_sdata => o_max_sdata,
o_max_ncs => o_max_ncs,
i_antext_stat => i_antext_stat,
i_antext_detect => i_antext_detect,
o_antext_ena => o_antext_ena,
o_antint_contr => o_antint_contr
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis_input_tlast : out std_logic;
s_axis_input_tready : in std_logic;
m_axis_output_tvalid : in std_logic;
m_axis_output_tdata : in std_logic;
m_axis_output_tlast : in std_logic;
m_axis_output_tready : out std_logic;
s_axis_ctrl_tvalid : out std_logic;
s_axis_ctrl_tdata : out std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : out std_logic;
s_axis_ctrl_tready : in std_logic
);
end viterbi_stimuli;
architecture behav of viterbi_stimuli is
type fsm_type is (IDLE, START_STATE, );
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(32-1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => 32,
seed => 242)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => 32,
seed => 324)
port map (
clk => clk,
rand_out => rand_out_2);
in_A_r <= rand_out_1(3 downto 0);
in_A_i <= rand_out_2(3 downto 0);
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
m_axis_ctrl_tlast <= '0';
m_axis_ctrl_tvalid <= '0';
m_axis_ctrl_tdata <= (others => '0');
m_axis_input_tlast <= '0';
m_axis_input_tvalid <= '0';
m_axis_input_tdata <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis_input_tlast : out std_logic;
s_axis_input_tready : in std_logic;
m_axis_output_tvalid : in std_logic;
m_axis_output_tdata : in std_logic;
m_axis_output_tlast : in std_logic;
m_axis_output_tready : out std_logic;
s_axis_ctrl_tvalid : out std_logic;
s_axis_ctrl_tdata : out std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : out std_logic;
s_axis_ctrl_tready : in std_logic
);
end viterbi_stimuli;
architecture behav of viterbi_stimuli is
type fsm_type is (IDLE, START_STATE, );
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(32-1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => 32,
seed => 242)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => 32,
seed => 324)
port map (
clk => clk,
rand_out => rand_out_2);
in_A_r <= rand_out_1(3 downto 0);
in_A_i <= rand_out_2(3 downto 0);
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
m_axis_ctrl_tlast <= '0';
m_axis_ctrl_tvalid <= '0';
m_axis_ctrl_tdata <= (others => '0');
m_axis_input_tlast <= '0';
m_axis_input_tvalid <= '0';
m_axis_input_tdata <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity viterbi_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
s_axis_input_tvalid : out std_logic;
s_axis_input_tdata : out std_logic_vector(31 downto 0);
s_axis_input_tlast : out std_logic;
s_axis_input_tready : in std_logic;
m_axis_output_tvalid : in std_logic;
m_axis_output_tdata : in std_logic;
m_axis_output_tlast : in std_logic;
m_axis_output_tready : out std_logic;
s_axis_ctrl_tvalid : out std_logic;
s_axis_ctrl_tdata : out std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : out std_logic;
s_axis_ctrl_tready : in std_logic
);
end viterbi_stimuli;
architecture behav of viterbi_stimuli is
type fsm_type is (IDLE, START_STATE, );
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(32-1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => 32,
seed => 242)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => 32,
seed => 324)
port map (
clk => clk,
rand_out => rand_out_2);
in_A_r <= rand_out_1(3 downto 0);
in_A_i <= rand_out_2(3 downto 0);
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
m_axis_ctrl_tlast <= '0';
m_axis_ctrl_tvalid <= '0';
m_axis_ctrl_tdata <= (others => '0');
m_axis_input_tlast <= '0';
m_axis_input_tvalid <= '0';
m_axis_input_tdata <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rotr00 is
port(
clkrotr: in std_logic ;
codoprotr: in std_logic_vector ( 3 downto 0 );
portArotr: in std_logic_vector ( 7 downto 0 );
inFlagrotr: in std_logic;
outrotr: out std_logic_vector ( 7 downto 0 );
outFlagrotr: out std_logic );
end;
architecture rotr0 of rotr00 is
begin
protr: process(codoprotr, portArotr)
begin
if(codoprotr = "1100") then
outrotr(7) <= portArotr(0);
outrotr(6 downto 0) <= portArotr(7 downto 1);
outFlagrotr <= '1';
else
outrotr <= (others => 'Z');
outFlagrotr <= 'Z';
end if;
end process protr;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end rotr0;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity scheduler is
end entity scheduler;
architecture test of scheduler is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity scheduler is
end entity scheduler;
architecture test of scheduler is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity scheduler is
end entity scheduler;
architecture test of scheduler is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
|
-- file: timer_tb.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity timer_tb is
end timer_tb;
architecture test of timer_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
signal COUNTER_RESET : std_logic := '0';
component timer_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : timer_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT);
end test;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Feb 28 11:50:03 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
library vector_heater_a_v1_00_a;
use vector_heater_a_v1_00_a.big_register;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
C_REGISTER_LENGTH : integer := 10000;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
--component big_register is
--generic
--(
-- C_REGISTER_LENGTH : integer := 10000
--);
--port
--(
-- clk : in std_logic;
-- rst : in std_logic;
-- ce : in std_logic; -- clock enable
-- xor_sig : out std_logic -- xor of all register bits
-- );
--end component;
-- signal vector : std_logic_vector(0 to C_VECTOR_LENGTH-1);
-- signal vector_ones : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signal vector_xor : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signal heater_active : std_logic;
signal ce : std_logic;
signal xor_sig : std_logic;
signal register_xor : std_logic_vector(0 to C_SLV_DWIDTH-1);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 7);
signal slv_reg_read_sel : std_logic_vector(0 to 7);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
-- -- for active heater: invert vector and write number of 1s vector into output signal
-- change_vector : process (Bus2IP_Reset, Bus2IP_Clk) is
-- --variable result_temp : integer;
-- variable bit_temp : std_logic;
-- begin
-- if Bus2IP_Reset = '1' then
-- --vector <= (others=>'0');
-- --vector(0) <= '1';
-- --vector_ones <= (others=>'0');
-- --vector_xor <= (others=>'0');
-- elsif rising_edge(Bus2IP_Clk) then
-- if heater_active = '1' then
-- --vector <= not vector;
-- --result_temp := 0;
-- --bit_temp := '0';
-- --for i in 0 to C_VECTOR_LENGTH-1 loop
-- -- bit_temp := bit_temp xor vector(i);
-- -- --if (vector(i)='1') then
-- -- -- result_temp := result_temp + 1;
-- -- --end if;
-- --end loop;
-- --vector_xor <= (others=>'0');
-- --vector_xor(0) <= bit_temp;
-- ----vector_ones <= std_logic_vector(to_unsigned(result_temp, C_SLV_DWIDTH));
-- end if;
-- end if;
-- end process;
--big_register_1 : component big_register
big_register_1 : entity vector_heater_a_v1_00_a.big_register
generic map ( C_REGISTER_LENGTH => C_REGISTER_LENGTH )
port map ( clk => Bus2IP_Clk, rst => Bus2IP_Reset, ce => ce, xor_sig => xor_sig );
-- activate heater only when 0x1 is written in registor 0
activate_heater : process (Bus2IP_Reset, Bus2IP_Clk) is
begin
if Bus2IP_Reset = '1' then
ce <= '0';
elsif rising_edge(Bus2IP_Clk) then
if slv_reg0 = X"00000001" then
ce <= '1';
else
ce <= '0';
end if;
end if;
end process;
register_xor(0 to C_SLV_DWIDTH-2) <= (others=>'0');
register_xor(C_SLV_DWIDTH-1) <= xor_sig;
-- for the active heater: invert vector at each clock cycle
-- change_vector : process (Bus2IP_Reset, Bus2IP_Clk) is
-- begin
-- if Bus2IP_Reset = '1' then
-- vector <= (others=>'0');
-- elsif rising_edge(Bus2IP_Clk) then
-- if heater_active = '1' then
-- vector <= not vector;
-- end if;
-- end if;
-- end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 7);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= slv_reg0;
when "01000000" => slv_ip2bus_data <= slv_reg1;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= register_xor; --vector_ones; --slv_reg7;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:52 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: portlist_i_e-rtl-a.vhd,v 1.1 2007/03/05 15:35:27 wig Exp $
-- $Date: 2007/03/05 15:35:27 $
-- $Log: portlist_i_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 15:35:27 wig
-- Changed case of filenames.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of PORTLIST_i_e
--
architecture rtl of PORTLIST_i_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--
-- Parameterisable N to M mux.
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ParamMux is
generic(
NSpikeSources : integer := 32; -- The number of spike sources.
NOutputs : integer := 16; -- The number of Synapses in the neuron model.
NSelectBits : integer := 5); -- Log2(NSpikeSources), rounded up.
port(
SpikeIn : In Std_logic_vector((NSpikeSources-1) downto 0);
SelectIn : In Std_logic_vector(((NOutputs*NSelectBits)-1) downto 0);
SpikeOut : Out Std_logic_vector((NOutputs-1) downto 0));
end ParamMux;
architecture RTL of ParamMux is
begin
--
-- Convert the incoming select signals to integer so we can use them as an index,
-- then use them as an index into SpikeIn to make a mux.
--
process(SelectIn,SpikeIn)
variable Sel : integer;
begin
for i in 0 to (NOutputs-1) loop
Sel:= conv_integer(SelectIn((i*NSelectBits+NSelectBits-1) downto (i*NSelectBits)));
SpikeOut(i) <= SpikeIn(Sel);
end loop;
end process;
end RTL;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 1;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity firstrpart is
Port ( Resetext : in STD_LOGIC;
Clkinext : in STD_LOGIC;
Adressext : out STD_LOGIC_VECTOR (31 downto 0));
end firstrpart;
architecture arqfirstrpart of firstrpart is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT NPC
PORT(
inNPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outNPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c :in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Windowsmanager
PORT(
cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0')
);
END COMPONENT;
COMPONENT PSR
PORT(
nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC ;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
c : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
signal aux1,aux2,aux3,aux4,aux6,aux7,aux8,aux9,aux10: std_logic_vector(31 downto 0);
signal aux5: std_logic_vector(5 downto 0);
signal aux13,aux14,aux15: std_logic_vector(5 downto 0);
signal aux11,aux12: STD_LOGIC;
signal aux16: STD_LOGIC_VECTOR (3 downto 0);
signal aux17: STD_LOGIC;
begin
U0: NPC PORT MAP(
inNPC => aux1,
Reset => Resetext,
Clk => Clkinext,
outNPC => aux2
);
U1: PC PORT MAP(
inPC => aux2,
Reset => Resetext,
Clk => Clkinext,
outPC => aux3
);
U2: Sumador32bit PORT MAP(
Oper1 => aux3,
Result => aux1
);
U3: IM PORT MAP(
Address => aux3,
Reset => Resetext,
Instruction => aux4
);
U4: CU PORT MAP(
op =>aux4(31 downto 30),
op3 =>aux4(24 downto 19),
ALUOP => aux5
);
U5: SEU PORT MAP(
Instruction =>aux4,
OUTSEU =>aux6
);
U6: MUX32 PORT MAP(
SEUIMM => aux6,
CRS2 => aux7,
OPER2 => aux9,
Instruction => aux4
);
U7: ALU PORT MAP(
OPER1 => aux8,
OPER2 => aux9,
c =>aux17,
ALURESULT => aux10,
ALUOP => aux5
);
U8: RF PORT MAP(
rs1 => aux13,
rs2 => aux14,
rd => aux15,
dwr => aux10,
rst => Resetext,
crs1 => aux8,
crs2 => aux7
);
U9: Windowsmanager PORT MAP(
cwp =>aux12,
rs1 =>aux4(18 downto 14),
rs2 =>aux4(4 downto 0),
rd =>aux4(29 downto 25),
op =>aux4(31 downto 30),
op3 =>aux4(24 downto 19),
cwpout=> aux11,
rs1out=>aux13,
rs2out=> aux14,
rdout=> aux15
);
U10: PSR PORT MAP(
nzvc => aux16,
clk => Clkinext,
cwp => aux12,
rest => Resetext,
ncwp => aux11,
c => aux17
);
U11: PSR_Modifier PORT MAP(
oper1 => aux8,
oper2 => aux9,
aluop => aux5,
aluResult => aux10,
conditionalCodes => aux16
);
Adressext<=aux10;
end arqfirstrpart;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
subtype mmu_gpsz_typ is integer range 0 to 3;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
--# fault, todo: should we flush on a fault?
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
variable pagesize : integer range 0 to 3;
begin
--# merge data
transdata := (others => '0');
pagesize := MMU_getpagesize(mmupgsz, mmctrl);
case pagesize is
when 1 =>
-- 8k
case LVL is
when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 2 =>
-- 16k
case LVL is
when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 3 =>
-- 32k
case LVL is
when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when others =>
-- 4k
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ is
variable pagesize : mmu_gpsz_typ;
begin
if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
else pagesize := mmupgsz; end if;
return pagesize;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity uart_testbench is
end uart_testbench;
architecture sim of uart_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
constant UART_WR_BYTE_COUNT : natural := 13;
constant UART_RD_BYTE_COUNT : natural := 9;
constant UART_DATA_WIDTH : natural := 6; -- 6-bits
signal clock, reset_n, reset : std_ulogic;
-- UART registers
signal uart_sent_bytes, uart_sent_bytes_nxt : unsigned(to_log2(UART_WR_BYTE_COUNT) - 1 downto 0);
signal uart_received_bytes, uart_received_bytes_nxt : unsigned(to_log2(UART_RD_BYTE_COUNT) - 1 downto 0);
type uart_protocol_entry_t is record
cmd : std_ulogic_vector(1 downto 0);
data : std_ulogic_vector(5 downto 0);
end record;
type uart_protocol_array is array (natural range <>) of uart_protocol_entry_t;
signal uart_wr_array, uart_wr_array_nxt : uart_protocol_array(0 to UART_WR_BYTE_COUNT - 1);
signal uart_rd_array, uart_rd_array_nxt : uart_protocol_array(0 to UART_RD_BYTE_COUNT);
type uart_state_t is (S_UART_RD_WAIT_START, S_UART_RD_READ_LOOP, S_UART_WR_START, S_UART_WR_WRITE_LOOP, S_UART_WR_END);
signal uart_state, uart_state_nxt : uart_state_t;
signal uart_cs : std_ulogic;
signal uart_wr : std_ulogic;
signal uart_addr : std_ulogic_vector(CW_ADDR_UART-1 downto 0);
signal uart_din : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_dout : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_irq_rx : std_ulogic;
signal uart_irq_tx : std_ulogic;
signal uart_ack_rx : std_ulogic;
signal uart_ack_tx : std_ulogic;
signal uart_rts, uart_cts, uart_rxd, uart_txd : std_ulogic;
signal end_simulation : std_ulogic;
signal heating_thresh, heating_thresh_nxt : unsigned(11 downto 0);
signal lighting_thresh, lighting_thresh_nxt : unsigned(15 downto 0);
signal watering_thresh, watering_thresh_nxt : unsigned(15 downto 0);
component uart is
generic (
SIMULATION : boolean := true
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end component uart;
component uart_model is
generic (
SYSTEM_CYCLE_TIME : time;
FILE_NAME_COMMAND : string;
FILE_NAME_DUMP : string;
BAUD_RATE : natural;
SIMULATION : boolean
);
port (
end_simulation : in std_ulogic;
rx : in std_ulogic;
tx : out std_ulogic
);
end component uart_model;
begin
uart_inst : uart
generic map (
SIMULATION => true
)
port map (
-- global signals
clock => clock,
reset_n => reset_n,
-- bus interface
iobus_cs => uart_cs,
iobus_wr => uart_wr,
iobus_addr => uart_addr,
iobus_din => uart_dout, -- caution!
iobus_dout => uart_din, -- caution!
-- IRQ handling
iobus_irq_rx => uart_irq_rx,
iobus_irq_tx => uart_irq_tx,
iobus_ack_rx => uart_ack_rx,
iobus_ack_tx => uart_ack_tx,
-- pins to outside
rts => uart_rts,
cts => uart_cts,
rxd => uart_rxd,
txd => uart_txd
);
uart_model_inst : uart_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "uart_command.txt",
FILE_NAME_DUMP => "uart_dump.txt",
BAUD_RATE => CV_UART_BAUDRATE,
SIMULATION => true
)
port map (
end_simulation => end_simulation,
rx => uart_txd,
tx => uart_rxd
);
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
end_sim : process
begin
end_simulation <= '0';
wait for SIMULATION_TIME;
end_simulation <= '1';
wait;
end process end_sim;
seq : process(clock, reset)
begin
if reset = '1' then
uart_state <= S_UART_RD_WAIT_START;
uart_wr_array <= (others => (others => (others => '0')));
uart_rd_array <= (others => (others => (others => '0')));
uart_sent_bytes <= (others => '0');
uart_received_bytes <= (others => '0');
heating_thresh <= to_unsigned(240, heating_thresh'length); -- 24,0 °C
lighting_thresh <= to_unsigned(400, lighting_thresh'length); -- 400 lx
watering_thresh <= to_unsigned(500, watering_thresh'length); -- 50,0 %
elsif rising_edge(clock) then
uart_state <= uart_state_nxt;
uart_wr_array <= uart_wr_array_nxt;
uart_rd_array <= uart_rd_array_nxt;
uart_sent_bytes <= uart_sent_bytes_nxt;
uart_received_bytes <= uart_received_bytes_nxt;
heating_thresh <= heating_thresh_nxt;
lighting_thresh <= lighting_thresh_nxt;
watering_thresh <= watering_thresh_nxt;
end if;
end process seq;
comb : process(uart_state, uart_wr_array, uart_rd_array, uart_sent_bytes, uart_received_bytes, uart_irq_tx, uart_irq_rx, uart_din, lighting_thresh, watering_thresh, heating_thresh)
constant VALUE_COUNT : natural := 5; -- amount of data segments (four segments for each sensor + one segment including all states (on/off) of peripherals)
constant SEGMENT_COUNT : natural := 3; -- 3 bytes per "segment"
variable i, j : natural := 0; -- loop variables
variable segment_cmd : std_ulogic_vector(1 downto 0);
variable segment_data : unsigned(SEGMENT_COUNT * UART_DATA_WIDTH - 1 downto 0);
variable item : uart_protocol_entry_t;
variable segment_value : std_ulogic_vector(15 downto 0);
begin
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- hold values
uart_state_nxt <= uart_state;
uart_sent_bytes_nxt <= uart_sent_bytes;
uart_received_bytes_nxt <= uart_received_bytes;
uart_rd_array_nxt <= uart_rd_array;
lighting_thresh_nxt <= lighting_thresh;
watering_thresh_nxt <= watering_thresh;
heating_thresh_nxt <= heating_thresh;
-- assign sensor values to protocol
for i in 0 to VALUE_COUNT - 1 loop
if i = 0 then
segment_cmd := "10";
segment_data := to_unsigned(150, segment_data'length - 2) & "00"; -- replace with lux
elsif i = 1 then
segment_cmd := "11";
segment_data := to_unsigned(300, segment_data'length - 2) & "01"; -- replace with moisture
elsif i = 2 then
segment_cmd := "10";
segment_data := to_unsigned(271, segment_data'length - 2) & "10"; -- replace with temp
elsif i = 3 then
segment_cmd := "11";
segment_data := to_unsigned(3000, segment_data'length - 2) & "11"; -- replace with co2
else
segment_cmd := "10";
segment_data := (others => '0'); -- replace with peripherals
end if;
for j in 0 to SEGMENT_COUNT - 1 loop
if i < 4 or j = 0 then
uart_wr_array_nxt(j + i * SEGMENT_COUNT) <= (
segment_cmd, -- cmd
std_ulogic_vector(resize(shift_right(segment_data, (2 - j) * UART_DATA_WIDTH), UART_DATA_WIDTH)) -- data
);
end if;
end loop;
end loop;
case uart_state is
when S_UART_RD_WAIT_START =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- save data
if uart_din(7 downto 0) = "01000000" then
uart_received_bytes_nxt <= to_unsigned(0, uart_received_bytes'length);
uart_rd_array_nxt <= (others => (others => (others => '0')));
uart_state_nxt <= S_UART_RD_READ_LOOP;
end if;
end if;
when S_UART_RD_READ_LOOP =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- increment counter
if uart_din(7 downto 0) = "00111111" then
-- received end command
if uart_received_bytes = to_unsigned(UART_RD_BYTE_COUNT, uart_received_bytes'length) then
for i in 0 to 2 loop
if uart_rd_array(i*3).cmd = "10" or uart_rd_array(i*3).cmd = "11" then
segment_value := uart_rd_array(i*3).data & uart_rd_array(i*3+1).data & uart_rd_array(i*3+2).data(5 downto 2);
if uart_rd_array(i*3+2).data(1 downto 0) = "00" then
lighting_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "01" then
watering_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "10" then
heating_thresh_nxt <= resize(unsigned(segment_value), heating_thresh'length);
end if;
end if;
end loop;
end if;
uart_state_nxt <= S_UART_WR_START;
else
uart_rd_array_nxt(to_integer(uart_received_bytes)) <= (
uart_din(7 downto 6), -- cmd
uart_din(5 downto 0) -- data
);
uart_received_bytes_nxt <= uart_received_bytes + to_unsigned(1, uart_received_bytes'length);
end if;
end if;
when S_UART_WR_START =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `start` cmd
uart_dout(7 downto 0) <= "01000000";
--
uart_state_nxt <= S_UART_WR_WRITE_LOOP;
end if;
when S_UART_WR_WRITE_LOOP =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
item := uart_wr_array(to_integer(uart_sent_bytes));
uart_dout(7 downto 0) <= item.cmd & item.data;
if uart_sent_bytes = to_unsigned(UART_WR_BYTE_COUNT - 1, uart_sent_bytes'length) then
-- last byte sent
uart_sent_bytes_nxt <= (others => '0'); -- reset counter
uart_state_nxt <= S_UART_WR_END;
else
-- increment counter
uart_sent_bytes_nxt <= uart_sent_bytes + to_unsigned(1, uart_sent_bytes'length);
end if;
end if;
when S_UART_WR_END =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `end` cmd
uart_dout(7 downto 0) <= "00111111";
uart_state_nxt <= S_UART_RD_WAIT_START;
end if;
end case;
end process comb;
end sim; |
library ieee;
use ieee.std_logic_1164.all;
entity RAM_T is
end RAM_T;
architecture Beh of RAM_T is
component RAM is
generic(
-- øèíà äàííûé
m: integer := 2;
-- øèíà àäðåñà
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- øèíà àäðåñà
AB: in std_logic_vector (m-1 downto 0);
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0)
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal AB: std_logic_vector (1 downto 0);
signal DB: std_logic_vector (1 downto 0);
constant CLK_period: time := 10 ns;
begin
URAM: RAM port map(
CLK => CLK,
WR => WR,
AB => AB,
DB => DB
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for CLK_Period;
AB <= "01";
DB <= "10";
wait for CLK_Period;
AB <= "10";
DB <= "01";
wait for CLK_Period;
WR <= '1';
DB <= "ZZ";
AB <= "01";
wait for CLK_Period;
DB <= "ZZ";
AB <= "10";
wait for CLK_Period;
wait;
end process;
end Beh; |
----------------------------------------------------------------------------
--
-- Oscilloscope VRAM State Machine
--
-- This is an implementation of a VRAM State machine for a digital scope in
-- VHDL. There are three inputs to the system, one selects the trigger
-- slope and the other two determine the relationship between the trigger
-- level and the signal level. The only output is a trigger signal which
-- indicates a trigger event has occurred.
--
-- The file contains multiple architectures for a Moore state machine
-- implementation to demonstrate the different ways of building a state
-- machine.
--
--
-- Revision History:
-- 2014/02/23 Albert Gural Created file and updated with VRAM
-- state machine.
--
----------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
--
-- Oscilloscope VRAM entity declaration
--
entity ScopeVRAM is
port (
clk : in std_logic; -- clock input
reset : in std_logic; -- reset to idle state (active low)
cs : in std_logic; -- whether CPU is requesting R/W (active low)
rw : in std_logic; -- whether CPU is requesting R or W
srt : in std_logic; -- display requesting serial row transfer
RAS : out std_logic; -- row address select output
CAS : out std_logic; -- col address select output
TRG : out std_logic; -- trigger output (active low)
WE : out std_logic; -- write enable output (active low)
AS : out std_logic_vector(1 downto 0); -- address select
-- 00 = low 9 bits
-- 01 = high 9 bits
-- 10 = row transfer
-- 11 = col transfer (0)
ACK : out std_logic; -- send acknowledge back to display driver
BUSY : out std_logic -- busy signal to CPU for read/write
);
end ScopeVRAM;
--
-- Oscilloscope VRAM Moore State Machine
-- State Assignment Architecture
--
-- This architecture just shows the basic state machine syntax when the state
-- assignments are made manually. This is useful for minimizing output
-- decoding logic and avoiding glitches in the output (due to the decoding
-- logic).
--
architecture assign_statebits of ScopeVRAM is
subtype states is std_logic_vector(12 downto 0); -- state type
-- define the actual states as constants
-- bits: [RAS][CAS][TRG][WE][AS<2>][ACK][BUSY]
-- [type <000 IDLE, 010 READ, 011 WRITE, 100 REFRESH, 101 TRANSFER>]
-- [number <00, 01, ...>]
constant IDLE : states := "1111001100000"; -- idle (can accept R/W)
constant READ1 : states := "0111011101000"; -- read cycle
constant READ2 : states := "0001001101000"; -- read cycle
constant READ3 : states := "0001001101001"; -- read cycle
constant READ4 : states := "0001001001010"; -- read cycle
constant READ5 : states := "1111001101000"; -- read cycle
constant READ6 : states := "1111001101001"; -- read cycle
constant READ7 : states := "1111001101010"; -- read cycle
constant WRITE1 : states := "0111011001100"; -- write cycle
constant WRITE2 : states := "0000001101100"; -- write cycle
constant WRITE3 : states := "0000001101101"; -- write cycle
constant WRITE4 : states := "0000001101110"; -- write cycle
constant WRITE5 : states := "1110001101100"; -- write cycle
constant WRITE6 : states := "1111001101100"; -- write cycle
constant WRITE7 : states := "1111001101101"; -- write cycle
constant TRANSFER1 : states := "1101101110100"; -- transfer cycle
constant TRANSFER2 : states := "0101101110100"; -- transfer cycle
constant TRANSFER3 : states := "0001111110100"; -- transfer cycle
constant TRANSFER4 : states := "0011111110100"; -- transfer cycle
constant TRANSFER5 : states := "1111110110100"; -- transfer cycle
constant REFRESH1 : states := "0111101110000"; -- refresh cycle
constant REFRESH2 : states := "0111101110001"; -- refresh cycle
constant REFRESH3 : states := "0111101110010"; -- refresh cycle
constant REFRESH4 : states := "1111001110000"; -- refresh cycle
constant REFRESH5 : states := "1111001110001"; -- refresh cycle
constant REFRESH6 : states := "1111001110010"; -- refresh cycle
signal CurrentState : states; -- current state
signal NextState : states; -- next state
begin
-- the output is always the high bit of the state encoding
RAS <= CurrentState(12);
CAS <= CurrentState(11);
TRG <= CurrentState(10);
WE <= CurrentState(9);
AS <= CurrentState(8 downto 7);
ACK <= CurrentState(6);
BUSY <= CurrentState(5);
-- compute the next state (function of current state and inputs)
transition: process (reset, cs, rw, srt, CurrentState)
begin
case CurrentState is -- do the state transition/output
when IDLE => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
elsif (srt = '0') then
NextState <= TRANSFER1; -- start serial row transfer
else
NextState <= REFRESH1; -- start refresh cycle
end if;
when READ1 => -- read cycle
NextState <= READ2; -- go to next part of read cycle
when READ2 => -- read cycle
NextState <= READ3; -- go to next part of read cycle
when READ3 => -- read cycle
NextState <= READ4; -- go to next part of read cycle
when READ4 => -- read cycle
NextState <= READ5; -- go to next part of read cycle
when READ5 => -- read cycle
NextState <= READ6; -- go to next part of read cycle
when READ6 => -- read cycle
NextState <= READ7; -- go to next part of read cycle
when READ7 => -- read cycle
NextState <= IDLE; -- go back to idle
when WRITE1 => -- write cycle
NextState <= WRITE2; -- go to next part of write cycle
when WRITE2 => -- write cycle
NextState <= WRITE3; -- go to next part of write cycle
when WRITE3 => -- write cycle
NextState <= WRITE4; -- go to next part of write cycle
when WRITE4 => -- write cycle
NextState <= WRITE5; -- go to next part of write cycle
when WRITE5 => -- write cycle
NextState <= WRITE6; -- go to next part of write cycle
when WRITE6 => -- write cycle
NextState <= WRITE7; -- go to next part of write cycle
when WRITE7 => -- write cycle
NextState <= IDLE; -- go back to idle
when TRANSFER1 => -- transfer cycle
NextState <= TRANSFER2; -- go to next part of transfer cycle
when TRANSFER2 => -- transfer cycle
NextState <= TRANSFER3; -- go to next part of transfer cycle
when TRANSFER3 => -- transfer cycle
NextState <= TRANSFER4; -- go to next part of transfer cycle
when TRANSFER4 => -- transfer cycle
NextState <= TRANSFER5; -- go to next part of transfer cycle
when TRANSFER5 => -- transfer cycle
NextState <= IDLE; -- go back to idle
when REFRESH1 => -- refresh cycle
NextState <= REFRESH2; -- go to next part of refresh cycle
when REFRESH2 => -- refresh cycle
NextState <= REFRESH3; -- go to next part of refresh cycle
when REFRESH3 => -- refresh cycle
NextState <= REFRESH4; -- go to next part of refresh cycle
when REFRESH4 => -- refresh cycle
NextState <= REFRESH5; -- go to next part of refresh cycle
when REFRESH5 => -- refresh cycle
NextState <= REFRESH6; -- go to next part of refresh cycle
when REFRESH6 => -- refresh cycle
NextState <= IDLE; -- go back to idle
when others => -- default
NextState <= IDLE; -- go back to idle
end case;
if reset = '1' then -- reset overrides everything
NextState <= IDLE; -- go to idle on reset
end if;
end process transition;
-- storage of current state (loads the next state on the clock)
process (clk)
begin
if clk = '1' then -- only change on rising edge of clock
CurrentState <= NextState; -- save the new state information
end if;
end process;
end assign_statebits;
|
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0 report "TEST FAILED" severity FAILURE;
end if;
end proc;
begin -- only
doit: process
begin -- process doit
proc( 1, 3 );
proc( 0, 42 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0 report "TEST FAILED" severity FAILURE;
end if;
end proc;
begin -- only
doit: process
begin -- process doit
proc( 1, 3 );
proc( 0, 42 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0 report "TEST FAILED" severity FAILURE;
end if;
end proc;
begin -- only
doit: process
begin -- process doit
proc( 1, 3 );
proc( 0, 42 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_distance_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compute_distance_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
point_2_idx : in centre_index_type;
distance : out coord_type_ext;
point_1_out : out data_type_ext;
point_2_out : out data_type_ext;
point_2_idx_out : out centre_index_type;
rdy : out std_logic
);
end compute_distance_top;
architecture Behavioral of compute_distance_top is
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type data_delay_type is array(0 to LATENCY-1) of data_type_ext;
type idx_delay_type is array(0 to LATENCY-1) of centre_index_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component dot_product
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
result : out coord_type_ext;
rdy : out std_logic
);
end component;
signal tmp_diff : data_type_ext;
signal tmp_sub_rdy : std_logic;
signal tmp_dot_product_rdy : std_logic;
signal tmp_dot_product_result : coord_type_ext;
signal data_delay_1 : data_delay_type;
signal data_delay_2 : data_delay_type;
signal idx_delay_2 : idx_delay_type;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH_EXT,
B_BITWIDTH => COORD_BITWIDTH_EXT,
RES_BITWIDTH => COORD_BITWIDTH_EXT
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => tmp_sub_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH_EXT,
B_BITWIDTH => COORD_BITWIDTH_EXT,
RES_BITWIDTH => COORD_BITWIDTH_EXT
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
dot_product_inst : dot_product
generic map (
SCALE_MUL_RESULT => MUL_FRACTIONAL_BITS
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_sub_rdy,
point_1 => tmp_diff,
point_2 => tmp_diff,
result => tmp_dot_product_result,
rdy => tmp_dot_product_rdy
);
-- feed point_2 from input of this unit to output
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_1(0) <= point_1;
data_delay_1(1 to LATENCY-1) <= data_delay_1(0 to LATENCY-2);
data_delay_2(0) <= point_2;
data_delay_2(1 to LATENCY-1) <= data_delay_2(0 to LATENCY-2);
idx_delay_2(0) <= point_2_idx;
idx_delay_2(1 to LATENCY-1) <= idx_delay_2(0 to LATENCY-2);
end if;
end process data_delay_proc;
rdy <= tmp_dot_product_rdy;
distance <= tmp_dot_product_result;
point_1_out <= data_delay_1(LATENCY-1);
point_2_out <= data_delay_2(LATENCY-1);
point_2_idx_out <= idx_delay_2(LATENCY-1);
end Behavioral;
|
--
-- \file bram_wrapper.vhd
--
-- Parametrizable BRAM wrapper for use in burst_ram.vhd
--
-- Instantiates RAMB16_Sn_Sm blocks based on generics.
-- The genrics G_PORTA_AWIDTH and G_PORTB_AWIDTH must be set so that together
-- with the selected data width the RAM will hold 16384 bits. That is,
-- the following equations must be true:
--
-- G_PORTA_DWIDTH = 2**(14-G_PORTA_AWIDTH);
-- G_PORTB_DWIDTH = 2**(14-G_PORTB_AWIDTH);
--
-- See table below for address width (in parentheses).
--
-- Currently supported generic combinations:
--
-- G_PORTA_DWIDTH (AWIDTH) | G_PORTB_DWIDTH (AWIDTH) | instantiated BRAM
-- ---------------------------------------------------------------------
-- 1 (14) | 2 (13) | RAMB16_S1_S2
-- 2 (13) | 4 (12) | RAMB16_S2_S4
-- 4 (12) | 8 (11) | RAMB16_S4_S9
-- 8 (11) | 16 (10) | RAMB16_S9_S18
-- 16 (10) | 32 (9) | RAMB16_S18_S36
--
-- 1 (14) | 1 (14) | RAMB16_S1_S1
-- 2 (13) | 2 (13) | RAMB16_S2_S2
-- 4 (12) | 4 (12) | RAMB16_S4_S4
-- 8 (11) | 8 (11) | RAMB16_S9_S9
-- 16 (10) | 16 (10) | RAMB16_S18_S18
-- 32 (9) | 32 (9) | RAMB16_S36_S36
--
-- RAMB16 generics are left at their defaults. No parity bits are supported.
--
-- \author Enno Luebbers <[email protected]>
-- \date 09.05.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bram_wrapper is
generic (
G_PORTA_DWIDTH : natural := 8;
G_PORTB_DWIDTH : natural := 16;
G_PORTA_AWIDTH : natural := 11;
G_PORTB_AWIDTH : natural := 10
);
port (
DOA : out std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DOB : out std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ADDRA : in std_logic_vector(G_PORTA_AWIDTH-1 downto 0);
ADDRB : in std_logic_vector(G_PORTB_AWIDTH-1 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector(G_PORTA_DWIDTH-1 downto 0);
DIB : in std_logic_vector(G_PORTB_DWIDTH-1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic;
WEB : in std_logic
);
end bram_wrapper;
architecture Behavioral of bram_wrapper is
-- derived constants
constant C_PORTA_DWIDTH : natural := 2**(14-G_PORTA_AWIDTH);
constant C_PORTB_DWIDTH : natural := 2**(14-G_PORTB_AWIDTH);
begin
-- check generics
assert C_PORTA_DWIDTH = G_PORTA_DWIDTH
report "PORTA parameters don't match"
severity failure;
assert C_PORTB_DWIDTH = G_PORTB_DWIDTH
report "PORTB parameters don't match"
severity failure;
-- instantiate BRAM
s1_s2: if (G_PORTA_DWIDTH = 1) and (G_PORTB_DWIDTH = 2) generate
bram_inst : RAMB16_S1_S2
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s2_s4: if (G_PORTA_DWIDTH = 2) and (G_PORTB_DWIDTH = 4) generate
bram_inst : RAMB16_S2_S4
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s4_s9: if (G_PORTA_DWIDTH = 4) and (G_PORTB_DWIDTH = 8) generate
bram_inst : RAMB16_S4_S9
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPB => "0" );
end generate;
s9_s18: if (G_PORTA_DWIDTH = 8) and (G_PORTB_DWIDTH = 16) generate
bram_inst : RAMB16_S9_S18
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0", DIPB => "00" );
end generate;
s18_s36: if (G_PORTA_DWIDTH = 16) and (G_PORTB_DWIDTH = 32) generate
bram_inst : RAMB16_S18_S36
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "00", DIPB => "0000" );
end generate;
s1_s1: if (G_PORTA_DWIDTH = 1) and (G_PORTB_DWIDTH = 1) generate
bram_inst : RAMB16_S1_S1
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s2_s2: if (G_PORTA_DWIDTH = 2) and (G_PORTB_DWIDTH = 2) generate
bram_inst : RAMB16_S2_S2
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s4_s4: if (G_PORTA_DWIDTH = 4) and (G_PORTB_DWIDTH = 4) generate
bram_inst : RAMB16_S4_S4
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB );
end generate;
s9_s9: if (G_PORTA_DWIDTH = 8) and (G_PORTB_DWIDTH = 8) generate
bram_inst : RAMB16_S9_S9
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0", DIPB => "0" );
end generate;
s18_s18: if (G_PORTA_DWIDTH = 16) and (G_PORTB_DWIDTH = 16) generate
bram_inst : RAMB16_S18_S18
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "00", DIPB => "00" );
end generate;
s36_s36: if (G_PORTA_DWIDTH = 32) and (G_PORTB_DWIDTH = 32) generate
bram_inst : RAMB16_S36_S36
port map (DOA => DOA, DOB => DOB, ADDRA => ADDRA, ADDRB => ADDRB,
CLKA => CLKA, CLKB => CLKB, DIA => DIA, DIB => DIB,
ENA => ENA, ENB => ENB, SSRA => SSRA, SSRB => SSRB,
WEA => WEA, WEB => WEB, DIPA => "0000", DIPB => "0000" );
end generate;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library altera_mf;
use altera_mf.all;
entity fifo_com_rx is
generic
(
DEPTH : POSITIVE := 1024;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port
(
aclr : in std_logic := '0';
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic
);
END fifo_com_rx;
ARCHITECTURE syn OF fifo_com_rx IS
SIGNAL sub_wire0 : STD_LOGIC;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (OUT_SIZE-1 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
write_aclr_synch : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
port (
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrfull : out std_logic ;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
aclr : in std_logic
);
end component;
component dcfifo_mixed_widths
generic (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
port (
rdclk : in std_logic;
wrfull : out std_logic;
q : out std_logic_vector (OUT_SIZE-1 downto 0);
rdempty : out std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
aclr : in std_logic;
data : in std_logic_vector (IN_SIZE-1 downto 0);
rdreq : in std_logic
);
end component;
begin
wrfull <= sub_wire0;
rdempty <= sub_wire2;
FIFO_GEN_SAME_WIDTH : if (IN_SIZE = OUT_SIZE) generate
dcfifo_component : dcfifo
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => IN_SIZE,
lpm_widthu => integer(ceil(log2(real(DEPTH)))),
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
port map (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
q <= sub_wire1;
end generate;
FIFO_GEN_MIXED_WIDTH : if (IN_SIZE /= OUT_SIZE) generate
dcfifo_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => DEPTH,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => IN_SIZE,
lpm_widthu => integer(ceil(log2(real(DEPTH)))),
lpm_widthu_r => integer(ceil(log2(real(DEPTH))*(real(IN_SIZE)/real(OUT_SIZE)))),
lpm_width_r => OUT_SIZE,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
port map (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
q <= sub_wire1(7 downto 0) & sub_wire1(15 downto 8); -- inverse bytes
end generate;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity mixer is
port (h, l : std_logic_vector(7 downto 0);
o : out std_logic_vector (7 downto 0));
end mixer;
architecture behav of mixer is
signal t1 : std_logic_vector (7 downto 0);
begin
a1: entity work.cmask
port map (l, t1);
o <= t1 or h;
end behav;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_13_port.vhd
-- /___/ /\ Timestamp : Tue Jul 23 14:56:51 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_13_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0);
CONTROL4: inout std_logic_vector(35 downto 0);
CONTROL5: inout std_logic_vector(35 downto 0);
CONTROL6: inout std_logic_vector(35 downto 0);
CONTROL7: inout std_logic_vector(35 downto 0);
CONTROL8: inout std_logic_vector(35 downto 0);
CONTROL9: inout std_logic_vector(35 downto 0);
CONTROL10: inout std_logic_vector(35 downto 0);
CONTROL11: inout std_logic_vector(35 downto 0);
CONTROL12: inout std_logic_vector(35 downto 0));
END chipscope_icon_13_port;
ARCHITECTURE chipscope_icon_13_port_a OF chipscope_icon_13_port IS
BEGIN
END chipscope_icon_13_port_a;
|
--------------------------------------------------------------------/
---- ----
---- WISHBONE rev.B2 compliant synthesizable I2C Slave model ----
---- ----
---- ----
---- Authors: Richard Herveille ([email protected]) www.asics.ws ----
---- John Sheahan ([email protected]) ----
---- ----
---- Downloaded from: http:--www.opencores.org/projects/i2c/ ----
---- ----
--------------------------------------------------------------------/
---- ----
---- Copyright (C) 2001,2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
--------------------------------------------------------------------/
-- CVS Log
--
-- $Id: i2c_slave_model.v,v 1.6 2005/02/28 11:33:48 rherveille Exp $
--
-- $Date: 2005/02/28 11:33:48 $
-- $Revision: 1.6 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_slave_model.v,v $
-- Revision 1.6 2005/02/28 11:33:48 rherveille
-- Fixed Tsu:sta timing check.
-- Added Thd:sta timing check.
--
-- Revision 1.5 2003/12/05 11:05:19 rherveille
-- Fixed slave address MSB='1' bug
--
-- Revision 1.4 2003/09/11 08:25:37 rherveille
-- Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
--
-- Revision 1.3 2002/10/30 18:11:06 rherveille
-- Added timing tests to i2c_model.
-- Updated testbench.
--
-- Revision 1.2 2002/03/17 10:26:38 rherveille
-- Fixed some race conditions in the i2c-slave model.
-- Added debug information.
-- Added headers.
--
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
entity i2c_slave_model is
generic (
I2C_ADR : std_logic_vector(6 downto 0) := "1010111"
);
port (
scl : in std_logic;
sda : inout std_logic
);
end i2c_slave_model;
architecture syn of i2c_slave_model is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant debug :std_logic := '1';
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
type std_2d is array(natural range <>) of std_logic_vector(7 downto 0);
type i2s_slave_sm_type is (idle, slave_ack, get_mem_adr, gma_ack, data, data_ack);
signal state :i2s_slave_sm_type:=idle;
signal mem :std_2d(15 downto 0);
signal mem_adr :std_logic_vector(7 downto 0);
signal mem_do :std_logic_vector(7 downto 0);
signal sr :std_logic_vector(7 downto 0);
signal bit_cnt :std_logic_vector(2 downto 0);
signal sta : std_logic;
signal d_sta : std_logic;
signal sto : std_logic;
signal d_sto :std_logic;
signal i2c_reset :std_logic;
signal sda_o :std_logic:='1';
signal sda_dly :std_logic;
signal ld : std_logic;
signal acc_done :std_logic;
signal my_adr :std_logic;
signal rw :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
shift_reg: process(scl)
begin
if( scl'event and (scl = '1' or scl = 'H')) then
if (sda = '1' or sda = 'H') then
sr <= sr(6 downto 0) & '1' after 1 ns;
else
sr <= sr(6 downto 0) & '0' after 1 ns;
end if;
if (ld = '1') then
bit_cnt <= (others =>'1') after 1 ns;
else
bit_cnt <= bit_cnt - 1 after 1 ns;
end if;
end if;
end process;
detct_proc: process(sda, scl)
begin
if( sda'event and sda = '0' ) then
if(scl = '1' or scl = 'H') then
sta <= '1' after 1 ns;
d_sta <= '0' after 1 ns;
sto <= '0' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; start condition detected ");
end if;
else
sta <= '0' after 1 ns;
end if;
elsif( sda'event and (sda = '1' or sda = 'H')) then
if(scl = '1' or scl = 'H') then
sta <= '0' after 1 ns;
sto <= '1' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; stop condition detected");
end if;
else
sto <= '0' after 1 ns;
end if;
elsif ( scl'event and (scl = '1' or scl = 'H')) then
d_sta <= sta after 1 ns;
end if;
end process;
sm_proc: process(scl, sto)
variable rw_var :std_logic;
begin
if( (scl'event and scl = '0') or (sto'event and sto = '0')) then
if (sto = '1' or( sta = '1' and d_sta= '0')) then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
ld <= '1' after 1 ns;
else
sda_o <= '1' after 1 ns;
ld <= '0' after 1 ns;
case state is
when idle =>
if(acc_done = '1' and my_adr= '1') then
state <= slave_ack after 1 ns;
rw <= sr(0) after 1 ns;
rw_var := sr(0);
sda_o <= '0' after 1 ns;
if (debug = '1' and sr(0) = '1') then
report("DEBUG i2c_slave; command byte received (read)" );
elsif (debug = '1' and sr(0) = '0') then
report("DEBUG i2c_slave; command byte received (write)" );
end if;
if (rw_var = '1') then
mem_do <= mem(conv_integer(mem_adr)) after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read from address ");
end if;
end if;
end if;
when slave_ack =>
if (rw = '1') then
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
else
state <= get_mem_adr after 1 ns;
ld <= '1' after 1 ns;
end if;
when get_mem_adr =>
if (acc_done = '1') then
state <= gma_ack after 1 ns;
mem_adr <= sr after 1 ns;
if (sr <= conv_std_logic_vector(15,7)) then
sda_o <= '0' after 1 ns;
else
sda_o <= '1' after 1 ns;
end if;
if (debug = '1') then
report ("DEBUG i2c_slave; address received. ");
end if;
end if;
when gma_ack =>
state <= data after 1 ns;
ld <= '1' after 1 ns;
when data =>
if(rw = '1') then
sda_o <= mem_do(7) after 1 ns;
end if;
if(acc_done = '1') then
state <= data_ack after 1 ns;
mem_adr <= mem_adr + 1 after 2 ns;
if (rw= '1'and mem_adr <= conv_std_logic_vector(15,7)) then
sda_o <= '1' after 3 ns;
else
sda_o <= '0' after 1 ns;
end if;
if(rw= '1') then
mem_do <= mem(conv_integer(mem_adr)) after 3 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read");
end if;
end if;
if (rw= '0') then
mem(conv_integer(mem_adr)) <= sr after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block write ");
end if;
end if;
end if;
when data_ack =>
ld <= '1' after 1 ns;
if (rw= '1') then
if (sda = '1' or sda = 'H') then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
else
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
end if;
else
state <= data after 1 ns;
sda_o <= '1' after 1 ns;
end if;
end case;
end if;
elsif( scl'event and (scl = '1' or scl = 'H')) then
if (acc_done = '0' and rw = '1') then
mem_do <= mem_do(6 downto 0) & '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
my_adr <= '1' when sr(7 downto 1) = i2c_adr else '0'; --detect if it is our address
acc_done <= not or_reduce(bit_cnt); --generate access done signal
-- generate delayed version of sda
-- this model assumes a hold time for sda after the falling edge of scl.
-- According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
-- with regards to scl. If the data changes coincident with the clock, the
-- acknowledge is missed
-- Fix by Michael Sosnoski
sda_dly <= '1' after 1 ns when sda = '1' or sda = 'H' else '0' after 1 ns;
--generate i2c_reset signal
i2c_reset <= sta or sto;
-- generate tri-states
sda <= '0' when sda_o = '0' else 'Z';
-------------------
-------------------
end syn;
|
--------------------------------------------------------------------/
---- ----
---- WISHBONE rev.B2 compliant synthesizable I2C Slave model ----
---- ----
---- ----
---- Authors: Richard Herveille ([email protected]) www.asics.ws ----
---- John Sheahan ([email protected]) ----
---- ----
---- Downloaded from: http:--www.opencores.org/projects/i2c/ ----
---- ----
--------------------------------------------------------------------/
---- ----
---- Copyright (C) 2001,2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
--------------------------------------------------------------------/
-- CVS Log
--
-- $Id: i2c_slave_model.v,v 1.6 2005/02/28 11:33:48 rherveille Exp $
--
-- $Date: 2005/02/28 11:33:48 $
-- $Revision: 1.6 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_slave_model.v,v $
-- Revision 1.6 2005/02/28 11:33:48 rherveille
-- Fixed Tsu:sta timing check.
-- Added Thd:sta timing check.
--
-- Revision 1.5 2003/12/05 11:05:19 rherveille
-- Fixed slave address MSB='1' bug
--
-- Revision 1.4 2003/09/11 08:25:37 rherveille
-- Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
--
-- Revision 1.3 2002/10/30 18:11:06 rherveille
-- Added timing tests to i2c_model.
-- Updated testbench.
--
-- Revision 1.2 2002/03/17 10:26:38 rherveille
-- Fixed some race conditions in the i2c-slave model.
-- Added debug information.
-- Added headers.
--
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
entity i2c_slave_model is
generic (
I2C_ADR : std_logic_vector(6 downto 0) := "1010111"
);
port (
scl : in std_logic;
sda : inout std_logic
);
end i2c_slave_model;
architecture syn of i2c_slave_model is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant debug :std_logic := '1';
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
type std_2d is array(natural range <>) of std_logic_vector(7 downto 0);
type i2s_slave_sm_type is (idle, slave_ack, get_mem_adr, gma_ack, data, data_ack);
signal state :i2s_slave_sm_type:=idle;
signal mem :std_2d(15 downto 0);
signal mem_adr :std_logic_vector(7 downto 0);
signal mem_do :std_logic_vector(7 downto 0);
signal sr :std_logic_vector(7 downto 0);
signal bit_cnt :std_logic_vector(2 downto 0);
signal sta : std_logic;
signal d_sta : std_logic;
signal sto : std_logic;
signal d_sto :std_logic;
signal i2c_reset :std_logic;
signal sda_o :std_logic:='1';
signal sda_dly :std_logic;
signal ld : std_logic;
signal acc_done :std_logic;
signal my_adr :std_logic;
signal rw :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
shift_reg: process(scl)
begin
if( scl'event and (scl = '1' or scl = 'H')) then
if (sda = '1' or sda = 'H') then
sr <= sr(6 downto 0) & '1' after 1 ns;
else
sr <= sr(6 downto 0) & '0' after 1 ns;
end if;
if (ld = '1') then
bit_cnt <= (others =>'1') after 1 ns;
else
bit_cnt <= bit_cnt - 1 after 1 ns;
end if;
end if;
end process;
detct_proc: process(sda, scl)
begin
if( sda'event and sda = '0' ) then
if(scl = '1' or scl = 'H') then
sta <= '1' after 1 ns;
d_sta <= '0' after 1 ns;
sto <= '0' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; start condition detected ");
end if;
else
sta <= '0' after 1 ns;
end if;
elsif( sda'event and (sda = '1' or sda = 'H')) then
if(scl = '1' or scl = 'H') then
sta <= '0' after 1 ns;
sto <= '1' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; stop condition detected");
end if;
else
sto <= '0' after 1 ns;
end if;
elsif ( scl'event and (scl = '1' or scl = 'H')) then
d_sta <= sta after 1 ns;
end if;
end process;
sm_proc: process(scl, sto)
variable rw_var :std_logic;
begin
if( (scl'event and scl = '0') or (sto'event and sto = '0')) then
if (sto = '1' or( sta = '1' and d_sta= '0')) then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
ld <= '1' after 1 ns;
else
sda_o <= '1' after 1 ns;
ld <= '0' after 1 ns;
case state is
when idle =>
if(acc_done = '1' and my_adr= '1') then
state <= slave_ack after 1 ns;
rw <= sr(0) after 1 ns;
rw_var := sr(0);
sda_o <= '0' after 1 ns;
if (debug = '1' and sr(0) = '1') then
report("DEBUG i2c_slave; command byte received (read)" );
elsif (debug = '1' and sr(0) = '0') then
report("DEBUG i2c_slave; command byte received (write)" );
end if;
if (rw_var = '1') then
mem_do <= mem(conv_integer(mem_adr)) after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read from address ");
end if;
end if;
end if;
when slave_ack =>
if (rw = '1') then
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
else
state <= get_mem_adr after 1 ns;
ld <= '1' after 1 ns;
end if;
when get_mem_adr =>
if (acc_done = '1') then
state <= gma_ack after 1 ns;
mem_adr <= sr after 1 ns;
if (sr <= conv_std_logic_vector(15,7)) then
sda_o <= '0' after 1 ns;
else
sda_o <= '1' after 1 ns;
end if;
if (debug = '1') then
report ("DEBUG i2c_slave; address received. ");
end if;
end if;
when gma_ack =>
state <= data after 1 ns;
ld <= '1' after 1 ns;
when data =>
if(rw = '1') then
sda_o <= mem_do(7) after 1 ns;
end if;
if(acc_done = '1') then
state <= data_ack after 1 ns;
mem_adr <= mem_adr + 1 after 2 ns;
if (rw= '1'and mem_adr <= conv_std_logic_vector(15,7)) then
sda_o <= '1' after 3 ns;
else
sda_o <= '0' after 1 ns;
end if;
if(rw= '1') then
mem_do <= mem(conv_integer(mem_adr)) after 3 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read");
end if;
end if;
if (rw= '0') then
mem(conv_integer(mem_adr)) <= sr after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block write ");
end if;
end if;
end if;
when data_ack =>
ld <= '1' after 1 ns;
if (rw= '1') then
if (sda = '1' or sda = 'H') then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
else
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
end if;
else
state <= data after 1 ns;
sda_o <= '1' after 1 ns;
end if;
end case;
end if;
elsif( scl'event and (scl = '1' or scl = 'H')) then
if (acc_done = '0' and rw = '1') then
mem_do <= mem_do(6 downto 0) & '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
my_adr <= '1' when sr(7 downto 1) = i2c_adr else '0'; --detect if it is our address
acc_done <= not or_reduce(bit_cnt); --generate access done signal
-- generate delayed version of sda
-- this model assumes a hold time for sda after the falling edge of scl.
-- According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
-- with regards to scl. If the data changes coincident with the clock, the
-- acknowledge is missed
-- Fix by Michael Sosnoski
sda_dly <= '1' after 1 ns when sda = '1' or sda = 'H' else '0' after 1 ns;
--generate i2c_reset signal
i2c_reset <= sta or sto;
-- generate tri-states
sda <= '0' when sda_o = '0' else 'Z';
-------------------
-------------------
end syn;
|
architecture RTL of ENTITY1 is
begin
PROC : process (a) is
-- These should fail
variable v_var1 : std_logic;
variable s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias is name;
begin
end process PROC;
PROC : process (a) is
-- These should pass
variable v_var1 : std_logic;
variable s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias is name;
begin
end process PROC;
PROC : process (a) is
-- Test with different spacing
variable v_var1 : std_logic;
variable s_sig1 : std_logic;
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
alias a_alias is name;
begin
end process PROC;
PROC : process (a) is
-- Test with shorter combinations
variable s_sig1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
type t_typ1 is (idle, write, read);
begin
end process PROC;
PROC : process (a) is
-- Test with comments
variable v_var1 : std_logic;
variable s_sig1 : std_logic;
-- some comment
constant c_cons1 : std_logic;
file f_fil1 : load_file_type open read_mode is load_file_name;
-- some comment
type t_typ1 is (idle, write, read);
subtype s_sub1 is integer range 0 to 9;
begin
end process PROC;
PROC : process (a) is
-- Test multiline declarations
type state_type is (
state1, state2,
state3, state4
);
variable sig1 : std_logic;
-- This should not error
type state_type2 is (
state1, state2,
state3, state4
);
variable sig1 : std_logic;
begin
end process PROC;
-- Test functions and procedures in the process declarative region
PROC : process (a) is
variable sig1 : std_logic;
variable var1 : std_logic;
constant con1 : integer := 0;
file fil1 : something;
function func_1 (
constant a : integer;
signal b : integer;
signal c : unsigned(3 downto 0);
signal d : std_logic_vector(7 downto 0);
constant e : std_logic) return integer is
file file1 : load_file_type open read_mode is load_file_name;
constant con1 : integer := 0;
variable sig1 : std_logic_vector;
begin
end;
variable sig1 : std_logic;
file fil1 : something;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
variable sig1 : std_logic;
file file1 : load_file_type open read_mode is load_file_name;
variable var1 : integer;
begin
end procedure AVERAGE_SAMPLES;
variable sig1 : std_logic;
file fil1 : something;
begin
end process PROC;
end architecture RTL;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity syncram_1rw_inferred is
generic (
addr_bits : natural := 10;
data_bits : natural := 8
);
port (
clk : in std_ulogic;
en : in std_ulogic;
we : in std_ulogic;
addr : in std_ulogic_vector((addr_bits-1) downto 0);
wdata : in std_ulogic_vector((data_bits-1) downto 0);
rdata : out std_ulogic_vector((data_bits-1) downto 0)
);
end;
|
-- Copyright (c) 2016 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Memory access decoder
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : almaif_decoder.vhdl
-- Author : Aleksi Tervo <[email protected]>
-- Company : TUT/CPC
-- Created : 2017-06-13
-- Last update: 2017-06-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Directs memory accesses to either the local memory or an
-- AXI master
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-13 1.0 tervoa Created
-- 2018-07-30 1.1 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
use work.tce_util.all;
entity almaif_decoder is
generic (
mem_dataw_g : integer := 32;
mem_addrw_g : integer;
axi_addrw_g : integer := 32;
mem_offset_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
-- Bus from arbiter
arb_avalid_in : in std_logic;
arb_aready_out : out std_logic;
arb_aaddr_in : in std_logic_vector(axi_addrw_g-2-1 downto 0);
arb_awren_in : in std_logic;
arb_astrb_in : in std_logic_vector(mem_dataw_g/8-1 downto 0);
arb_adata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
--
arb_rvalid_out : out std_logic;
arb_rready_in : in std_logic;
arb_rdata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
-- Bus to local memory
mem_avalid_out : out std_logic;
mem_aready_in : in std_logic;
mem_aaddr_out : out std_logic_vector(mem_addrw_g-1 downto 0);
mem_awren_out : out std_logic;
mem_astrb_out : out std_logic_vector(mem_dataw_g/8-1 downto 0);
mem_adata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
--
mem_rvalid_in : in std_logic;
mem_rready_out : out std_logic;
mem_rdata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
-- AXI lite master
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(mem_dataw_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(mem_dataw_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(mem_dataw_g-1 downto 0)
);
end almaif_decoder;
architecture rtl of almaif_decoder is
constant sync_reset_c : boolean := sync_reset_g /= 0;
constant dst_axi_c : std_logic := '1';
constant dst_mem_c : std_logic := '0';
signal dst_sel, fifo_dst_sel, access_success, read_success : std_logic;
signal fifo_data_r : std_logic_vector(4-1 downto 0);
signal fifo_iter_r : unsigned(2-1 downto 0);
constant mem_offset_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
:= std_logic_vector(to_unsigned(mem_offset_g/4, axi_addrw_g-2));
constant mem_mask_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
-- := (mem_addrw_g-2-1 downto 0 => '0', others => '1');
:= not std_logic_vector(to_unsigned(2**(mem_addrw_g-2)-1,
axi_addrw_g-2));
constant mem_width_log2 : integer := integer(ceil(log2(real(mem_dataw_g))));
signal m_axi_wdata_r : std_logic_vector(m_axi_wdata'range);
signal m_axi_wstrb_r : std_logic_vector(m_axi_wstrb'range);
-- All accesses are unprivileged/secure/data
constant axi_axprot_c : std_logic_vector(3-1 downto 0) := "000";
signal m_axi_wvalid_r, write_load : std_logic;
begin
------------------------------------------------------------------------------
-- Direct accesses to AXI or local memory
------------------------------------------------------------------------------
asel_comb : process(arb_aaddr_in, arb_avalid_in, arb_awren_in,
mem_aready_in,
m_axi_arready, m_axi_awready,
m_axi_wvalid_r, m_axi_wready)
begin
mem_avalid_out <= '0';
m_axi_arvalid <= '0';
m_axi_awvalid <= '0';
arb_aready_out <= '0';
access_success <= '0';
write_load <= '0';
dst_sel <= dst_mem_c;
if (arb_aaddr_in and mem_mask_c) = mem_offset_c then
mem_avalid_out <= arb_avalid_in;
arb_aready_out <= mem_aready_in;
access_success <= mem_aready_in and arb_avalid_in;
else
dst_sel <= dst_axi_c;
if arb_awren_in = '0' then
m_axi_arvalid <= arb_avalid_in;
arb_aready_out <= m_axi_arready;
access_success <= arb_avalid_in and m_axi_arready;
elsif arb_awren_in = '1'
and (m_axi_wvalid_r = '0' or m_axi_wready = '1') then
m_axi_awvalid <= arb_avalid_in;
write_load <= '1';
arb_aready_out <= m_axi_awready;
access_success <= arb_avalid_in and m_axi_awready;
end if;
end if;
end process asel_comb;
-- Common signals to memory interface
mem_aaddr_out <= arb_aaddr_in(mem_aaddr_out'range);
mem_awren_out <= arb_awren_in;
mem_astrb_out <= arb_astrb_in;
mem_adata_out <= arb_adata_in;
-- Common signals to AXI
m_axi_awaddr <= arb_aaddr_in & "00";
m_axi_awprot <= axi_axprot_c;
m_axi_araddr <= arb_aaddr_in & "00";
m_axi_arprot <= axi_axprot_c;
------------------------------------------------------------------------------
-- FIFO to keep accesses to local/global memory in order
------------------------------------------------------------------------------
fifo_sync : process(clk, rstx)
variable fifo_data_v : std_logic_vector(fifo_data_r'range);
variable fifo_iter_v : unsigned(fifo_iter_r'range);
begin
if not sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
else
fifo_data_v := fifo_data_r;
fifo_iter_v := fifo_iter_r;
if read_success = '1' and fifo_iter_r > 0 then
fifo_data_v(fifo_data_v'high-1 downto 0) :=
fifo_data_v(fifo_data_v'high downto 1);
fifo_data_v(fifo_data_v'high) := '0';
fifo_iter_v := fifo_iter_v - 1;
end if;
if access_success = '1' and arb_awren_in = '0' then
fifo_data_v(to_integer(fifo_iter_v)) := dst_sel;
fifo_iter_v := fifo_iter_v + 1;
end if;
fifo_iter_r <= fifo_iter_v;
fifo_data_r <= fifo_data_v;
end if;
end if;
end process fifo_sync;
fifo_dst_sel <= fifo_data_r(0);
------------------------------------------------------------------------------
-- Select response to direct to arbiter
------------------------------------------------------------------------------
rsel_comb : process(fifo_dst_sel, m_axi_rvalid, arb_rready_in, mem_rvalid_in,
m_axi_rdata, mem_rdata_in)
begin
if fifo_dst_sel = dst_axi_c then
arb_rvalid_out <= m_axi_rvalid;
mem_rready_out <= '0';
m_axi_rready <= arb_rready_in;
arb_rdata_out <= m_axi_rdata;
read_success <= arb_rready_in and m_axi_rvalid;
else
arb_rvalid_out <= mem_rvalid_in;
mem_rready_out <= arb_rready_in;
m_axi_rready <= '0';
arb_rdata_out <= mem_rdata_in;
read_success <= arb_rready_in and mem_rvalid_in;
end if;
end process rsel_comb;
------------------------------------------------------------------------------
-- AXI write, response channels : drive m_axi_{w,b}* out ports
------------------------------------------------------------------------------
axi_w_channels_sync : process(clk, rstx)
begin
if not sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
else
if m_axi_wready = '1' then
m_axi_wvalid_r <= '0';
end if;
if write_load = '1' and m_axi_awready = '1' then
m_axi_wvalid_r <= '1';
m_axi_wdata_r <= arb_adata_in;
m_axi_wstrb_r <= arb_astrb_in;
end if;
end if;
end if;
end process axi_w_channels_sync;
m_axi_wvalid <= m_axi_wvalid_r;
m_axi_wdata <= m_axi_wdata_r;
m_axi_wstrb <= m_axi_wstrb_r;
-- Ignore the response
m_axi_bready <= '1';
------------------------------------------------------------------------------
-- Design-wide checks:
------------------------------------------------------------------------------
-- coverage off
-- pragma translate_off
assert 2**mem_width_log2 = mem_dataw_g and mem_dataw_g >= 8
report "Data width must be a power-of-two multiple of bytes"
severity failure;
assert (mem_offset_c and mem_mask_c) = mem_offset_c
report "Memory must be aligned to its size"
severity failure;
assert mem_addrw_g <= axi_addrw_g
report "Memory must fit in AXI address space"
severity failure;
-- pragma translate_on
-- coverage on
end architecture rtl;
|
-- Copyright (c) 2016 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Memory access decoder
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : almaif_decoder.vhdl
-- Author : Aleksi Tervo <[email protected]>
-- Company : TUT/CPC
-- Created : 2017-06-13
-- Last update: 2017-06-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Directs memory accesses to either the local memory or an
-- AXI master
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-13 1.0 tervoa Created
-- 2018-07-30 1.1 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
use work.tce_util.all;
entity almaif_decoder is
generic (
mem_dataw_g : integer := 32;
mem_addrw_g : integer;
axi_addrw_g : integer := 32;
mem_offset_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
-- Bus from arbiter
arb_avalid_in : in std_logic;
arb_aready_out : out std_logic;
arb_aaddr_in : in std_logic_vector(axi_addrw_g-2-1 downto 0);
arb_awren_in : in std_logic;
arb_astrb_in : in std_logic_vector(mem_dataw_g/8-1 downto 0);
arb_adata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
--
arb_rvalid_out : out std_logic;
arb_rready_in : in std_logic;
arb_rdata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
-- Bus to local memory
mem_avalid_out : out std_logic;
mem_aready_in : in std_logic;
mem_aaddr_out : out std_logic_vector(mem_addrw_g-1 downto 0);
mem_awren_out : out std_logic;
mem_astrb_out : out std_logic_vector(mem_dataw_g/8-1 downto 0);
mem_adata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
--
mem_rvalid_in : in std_logic;
mem_rready_out : out std_logic;
mem_rdata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
-- AXI lite master
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(mem_dataw_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(mem_dataw_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(mem_dataw_g-1 downto 0)
);
end almaif_decoder;
architecture rtl of almaif_decoder is
constant sync_reset_c : boolean := sync_reset_g /= 0;
constant dst_axi_c : std_logic := '1';
constant dst_mem_c : std_logic := '0';
signal dst_sel, fifo_dst_sel, access_success, read_success : std_logic;
signal fifo_data_r : std_logic_vector(4-1 downto 0);
signal fifo_iter_r : unsigned(2-1 downto 0);
constant mem_offset_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
:= std_logic_vector(to_unsigned(mem_offset_g/4, axi_addrw_g-2));
constant mem_mask_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
-- := (mem_addrw_g-2-1 downto 0 => '0', others => '1');
:= not std_logic_vector(to_unsigned(2**(mem_addrw_g-2)-1,
axi_addrw_g-2));
constant mem_width_log2 : integer := integer(ceil(log2(real(mem_dataw_g))));
signal m_axi_wdata_r : std_logic_vector(m_axi_wdata'range);
signal m_axi_wstrb_r : std_logic_vector(m_axi_wstrb'range);
-- All accesses are unprivileged/secure/data
constant axi_axprot_c : std_logic_vector(3-1 downto 0) := "000";
signal m_axi_wvalid_r, write_load : std_logic;
begin
------------------------------------------------------------------------------
-- Direct accesses to AXI or local memory
------------------------------------------------------------------------------
asel_comb : process(arb_aaddr_in, arb_avalid_in, arb_awren_in,
mem_aready_in,
m_axi_arready, m_axi_awready,
m_axi_wvalid_r, m_axi_wready)
begin
mem_avalid_out <= '0';
m_axi_arvalid <= '0';
m_axi_awvalid <= '0';
arb_aready_out <= '0';
access_success <= '0';
write_load <= '0';
dst_sel <= dst_mem_c;
if (arb_aaddr_in and mem_mask_c) = mem_offset_c then
mem_avalid_out <= arb_avalid_in;
arb_aready_out <= mem_aready_in;
access_success <= mem_aready_in and arb_avalid_in;
else
dst_sel <= dst_axi_c;
if arb_awren_in = '0' then
m_axi_arvalid <= arb_avalid_in;
arb_aready_out <= m_axi_arready;
access_success <= arb_avalid_in and m_axi_arready;
elsif arb_awren_in = '1'
and (m_axi_wvalid_r = '0' or m_axi_wready = '1') then
m_axi_awvalid <= arb_avalid_in;
write_load <= '1';
arb_aready_out <= m_axi_awready;
access_success <= arb_avalid_in and m_axi_awready;
end if;
end if;
end process asel_comb;
-- Common signals to memory interface
mem_aaddr_out <= arb_aaddr_in(mem_aaddr_out'range);
mem_awren_out <= arb_awren_in;
mem_astrb_out <= arb_astrb_in;
mem_adata_out <= arb_adata_in;
-- Common signals to AXI
m_axi_awaddr <= arb_aaddr_in & "00";
m_axi_awprot <= axi_axprot_c;
m_axi_araddr <= arb_aaddr_in & "00";
m_axi_arprot <= axi_axprot_c;
------------------------------------------------------------------------------
-- FIFO to keep accesses to local/global memory in order
------------------------------------------------------------------------------
fifo_sync : process(clk, rstx)
variable fifo_data_v : std_logic_vector(fifo_data_r'range);
variable fifo_iter_v : unsigned(fifo_iter_r'range);
begin
if not sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
else
fifo_data_v := fifo_data_r;
fifo_iter_v := fifo_iter_r;
if read_success = '1' and fifo_iter_r > 0 then
fifo_data_v(fifo_data_v'high-1 downto 0) :=
fifo_data_v(fifo_data_v'high downto 1);
fifo_data_v(fifo_data_v'high) := '0';
fifo_iter_v := fifo_iter_v - 1;
end if;
if access_success = '1' and arb_awren_in = '0' then
fifo_data_v(to_integer(fifo_iter_v)) := dst_sel;
fifo_iter_v := fifo_iter_v + 1;
end if;
fifo_iter_r <= fifo_iter_v;
fifo_data_r <= fifo_data_v;
end if;
end if;
end process fifo_sync;
fifo_dst_sel <= fifo_data_r(0);
------------------------------------------------------------------------------
-- Select response to direct to arbiter
------------------------------------------------------------------------------
rsel_comb : process(fifo_dst_sel, m_axi_rvalid, arb_rready_in, mem_rvalid_in,
m_axi_rdata, mem_rdata_in)
begin
if fifo_dst_sel = dst_axi_c then
arb_rvalid_out <= m_axi_rvalid;
mem_rready_out <= '0';
m_axi_rready <= arb_rready_in;
arb_rdata_out <= m_axi_rdata;
read_success <= arb_rready_in and m_axi_rvalid;
else
arb_rvalid_out <= mem_rvalid_in;
mem_rready_out <= arb_rready_in;
m_axi_rready <= '0';
arb_rdata_out <= mem_rdata_in;
read_success <= arb_rready_in and mem_rvalid_in;
end if;
end process rsel_comb;
------------------------------------------------------------------------------
-- AXI write, response channels : drive m_axi_{w,b}* out ports
------------------------------------------------------------------------------
axi_w_channels_sync : process(clk, rstx)
begin
if not sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
else
if m_axi_wready = '1' then
m_axi_wvalid_r <= '0';
end if;
if write_load = '1' and m_axi_awready = '1' then
m_axi_wvalid_r <= '1';
m_axi_wdata_r <= arb_adata_in;
m_axi_wstrb_r <= arb_astrb_in;
end if;
end if;
end if;
end process axi_w_channels_sync;
m_axi_wvalid <= m_axi_wvalid_r;
m_axi_wdata <= m_axi_wdata_r;
m_axi_wstrb <= m_axi_wstrb_r;
-- Ignore the response
m_axi_bready <= '1';
------------------------------------------------------------------------------
-- Design-wide checks:
------------------------------------------------------------------------------
-- coverage off
-- pragma translate_off
assert 2**mem_width_log2 = mem_dataw_g and mem_dataw_g >= 8
report "Data width must be a power-of-two multiple of bytes"
severity failure;
assert (mem_offset_c and mem_mask_c) = mem_offset_c
report "Memory must be aligned to its size"
severity failure;
assert mem_addrw_g <= axi_addrw_g
report "Memory must fit in AXI address space"
severity failure;
-- pragma translate_on
-- coverage on
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2016 11:43:23
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
done : in STD_LOGIC;
stop : in std_logic;
start : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type type_etat is (init, inc,finish, calcul);
Signal etat_present, etat_futur : type_etat;
begin
process(clock,reset)
begin
if reset='1' then
etat_present<=init;
elsif rising_edge(clock) then
etat_present<=etat_futur;
end if;
end process;
process(etat_present, done, stop)
begin
case etat_present is
when init=> etat_futur<=inc;
when calcul=> if stop='1' then
etat_futur<=finish;
elsif done = '0' then
etat_futur<=calcul;
else
etat_futur<=inc;
end if;
when inc=> etat_futur<=calcul;
when finish=>etat_futur<=init;
end case;
end process;
process(etat_present)
begin
case etat_present is
when init=> start<='0';
when calcul=> start<='0';
when inc=> start<='1';
when finish=>start<='0';
end case;
end process;
end Behavioral; |
-- vsg_off library_008 process_012
library ieee;
use ieee.std_logic_arith.all;
-- vsg_on library_008 process_012
library ieee;
use ieee.std_logic.all;
-- vsg_off : comment
entity FIFO is
port (
WRITE_EN : in std_logic;
READ_EN : in std_logic
);
end entity;
-- vsg_on : comment
-- vsg_off library_002 : comment
library ieee;
-- vsg_on library_002 : comment
library ieee;
-- vsg_off : comment
library ieee;
-- vsg_on : comment
library ieee;
-- vsg_off library_001 process_001
-- vsg_on library_001
-- vsg_off case_001
-- vsg_on process_001
-- vsg_off library_001
-- vsg_on case_001 library_001
architecture rtl of fifo is
begin
-- vsg_off comment_010
-- Comment
-- Comment
-- vsg_on comment_010
a <= b;
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 14:24:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_stub.vhdl
-- Design : system_affine_rotation_generator_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_affine_rotation_generator_0_0 is
Port (
clk_25 : in STD_LOGIC;
reset : in STD_LOGIC;
a00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_affine_rotation_generator_0_0;
architecture stub of system_affine_rotation_generator_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,reset,a00[31:0],a01[31:0],a10[31:0],a11[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "affine_rotation_generator,Vivado 2016.4";
begin
end;
|
entity test is
constant a : b :=
foo'(bar, baz);
end;
|
library work;
use work.opcodes.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
entity i8080 is
Port (
clk : in STD_LOGIC;
addressBus : out STD_LOGIC_VECTOR (15 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
sync : out STD_LOGIC; -- not implemented
dataBusIn : out STD_LOGIC;
ready : in STD_LOGIC;
waitAck : out STD_LOGIC;
wr : out STD_LOGIC;
hold : in STD_LOGIC; -- not implemented
hlda : out STD_LOGIC; -- not implemented
inte : out STD_LOGIC;
int : in STD_LOGIC;
reset : in STD_LOGIC;
status : out STD_LOGIC_VECTOR(3 downto 0));
end i8080;
architecture Behavioral of i8080 is
COMPONENT RegisterArray PORT(
clk : IN std_logic;
selector : IN std_logic_vector(7 downto 0);
dataIn : IN std_logic_vector(15 downto 0);
load : IN std_logic;
dataOut : OUT std_logic_vector(15 downto 0));
END COMPONENT;
COMPONENT alu PORT(
clk : IN std_logic;
operandA : IN std_logic_vector(7 downto 0);
operandB : IN std_logic_vector(7 downto 0);
operatorSelect : IN std_logic_vector(2 downto 0);
carryIn : IN std_logic;
carryOut : OUT std_logic;
zeroOut : OUT std_logic;
signOut : OUT std_logic;
parityOut : OUT std_logic;
auxCarryOut : OUT std_logic;
result : OUT std_logic_vector(7 downto 0));
END COMPONENT;
type stateType is (
halted0, badopcode,
fetch0, fetch1,
decode,
readDirect0,readDirect1,readDirect2,readDirect3,
readImmediate0, readImmediate1,
readRegPair0, readRegPair1, readRegPair2,
dad1, dad2,
lxi0, lxi1,
mvi0, mvi1a, mvi2a, mvi3a, mvi1b,
stax0, stax1, stax2,
ldax0, ldax1, ldax2,
shld0, shld1, shld2, shld3, shld4,
lhld0, lhld1, lhld2, lhld3, lhld4,
sta0, sta1, sta2,
lda0, lda1, lda2,
inxdcx0, inxdcx1,
inrdcrmem0, inrdcrmem1, inrdcrmem2, inrdcrmem3, inrdcrmem4,
inrdcrreg0, inrdcrreg1,
aluOp0a, aluOp0b, aluOp1,
postRotate0,
daa0,
call0, call1, call2, call3, call4,
jump0,
ret0, ret1, ret2, ret3, ret4,
movmemtoreg0, movmemtoreg1, movmemtoreg2, movmemtoreg3,
movregtomem0, movregtomem1, movregtomem2, movregtomem3,
movregtoreg0, movregtoreg1, movregtoreg2,
pop0, pop1, pop2, pop3, pop4,
push0, push1, push2, push3, push4, push5,
pchl0,
sphl0, sphl1,
ani0, ani1,
ori0, ori1,
inout0,
xchg0, xchg1, xchg2, xchg3
);
signal currentState : stateType := fetch0;
signal readMemReturnState : stateType := fetch0;
signal pc : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal regSelector : STD_LOGIC_VECTOR (7 downto 0);
signal regDataIn : STD_LOGIC_VECTOR (15 downto 0);
signal regDataOut : STD_LOGIC_VECTOR (15 downto 0);
signal regLoad : STD_LOGIC := '0';
signal tempReg1 : STD_LOGIC_VECTOR (7 downto 0);
signal tempReg2 : STD_LOGIC_VECTOR (7 downto 0);
signal a : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal flagsSign : STD_LOGIC := '0';
signal flagsZero : STD_LOGIC := '0';
signal flagsAuxCarry : STD_LOGIC := '0';
signal flagsParity : STD_LOGIC := '0';
signal flagsCarry : STD_LOGIC := '0';
signal aluOperandA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal aluOperandB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal aluCarryIn : STD_LOGIC := '0';
signal aluCarryOut : STD_LOGIC := '0';
signal aluZeroOut : STD_LOGIC := '0';
signal aluSignOut : STD_LOGIC := '0';
signal aluParityOut : STD_LOGIC := '0';
signal aluAuxCarryOut : STD_LOGIC := '0';
signal aluResult : STD_LOGIC_VECTOR (7 downto 0);
signal aluOpSelect : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal intEnabled : STD_LOGIC := '1';
constant regBC : std_logic_vector(1 downto 0) := "00";
constant regDE : std_logic_vector(1 downto 0) := "01";
constant regHL : std_logic_vector(1 downto 0) := "10";
constant regSP : std_logic_vector(1 downto 0) := "11";
constant regA : std_logic_vector(2 downto 0) := "111";
constant regB : std_logic_vector(2 downto 0) := "000";
constant regC : std_logic_vector(2 downto 0) := "001";
constant regD : std_logic_vector(2 downto 0) := "010";
constant regE : std_logic_vector(2 downto 0) := "011";
constant regH : std_logic_vector(2 downto 0) := "100";
constant regL : std_logic_vector(2 downto 0) := "101";
begin
registers: RegisterArray PORT MAP(
clk => clk,
selector => regSelector,
dataIn => regDataIn,
dataOut => regDataOut,
load => regLoad
);
ialu: alu PORT MAP(
clk => clk,
operandA => aluOperandA,
operandB => aluOperandB,
operatorSelect => aluOpSelect,
carryIn => aluCarryIn,
carryOut => aluCarryOut,
zeroOut => aluZeroOut,
signOut => aluSignOut,
parityOut => aluParityOut,
auxCarryOut => aluAuxCarryOut,
result => aluResult
);
procloop:
process (clk, reset)
pure function regToSelector(reg : std_logic_vector(2 downto 0)) return std_logic_vector is
variable regSelector : std_logic_vector(7 downto 0);
begin
case reg is
when regB => regSelector := "00000001";
when regC => regSelector := "00000010";
when regD => regSelector := "00000100";
when regE => regSelector := "00001000";
when regH => regSelector := "00010000";
when others => regSelector := "00100000"; -- regL
end case;
return regSelector;
end function regToSelector;
--impure function incrementByte(v : std_logic_vector) return std_logic_vector(7 downto 0) is
-- variable newValue : std_logic_vector(7 downto 0);
--begin
--flagsParity <= v(0) xor v(1) xor v(2) xor v(3) xor v(4) xor v(5) xor v(6) xor v(7);
--flagsAuxCarry <= and_reduce((v and X"F") + 1 and X"10");
--newValue := v + 1; -- todo fix
--flagsSign <= or_reduce(newValue and X"80");
--flagsZero <= not(or_reduce(v));
-- return "00000000"; --newValue;
--end function incrementByte;
--impure function decrementByte(v : std_logic_vector) return std_logic_vector(7 downto 0) is
-- variable newValue : std_logic_vector(7 downto 0);
--begin
--flagsParity <= v(0) xor v(1) xor v(2) xor v(3) xor v(4) xor v(5) xor v(6) xor v(7);
--flagsAuxCarry <= and_reduce((v and X"F") - 1 and X"10");
--newValue := v - 1; -- todo fix
--flagsSign <= or_reduce(newValue and X"80");
--flagsZero <= not(or_reduce(v));
-- return "00000000"; -- newValue;
--end function decrementByte;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return result;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return "0x" & result;
end if;
end function to_hstring;
variable waitCycleCount : integer := 0;
variable opcode : STD_LOGIC_VECTOR (7 downto 0);
begin
if (reset = '1') then
currentState <= fetch0;
pc <= (others => '0');
regLoad <= '0';
wr <= '0';
dataOut <= (others => '0');
status <= "0001";
elsif (rising_edge(clk)) then
case (currentState) is
when fetch0 =>
report to_hstring(pc);
if (int and intEnabled) then
else
end if;
addressBus <= pc;
dataBusIn <= '1';
currentState <= fetch1;
regLoad <= '0';
regSelector <= "01000000"; -- default to selecting the SP
when fetch1 =>
-- wait
if (pc = X"0A9E") then -- DrawStatus - ix3
pc <= pc + 1;
end if;
pc <= pc + 1;
currentState <= decode;
when decode =>
if (not ready = '1') then
waitAck <= '1';
else
-- once external memory is ready, take the opcode off the data bus
opcode := dataIn;
aluOpSelect <= opcode(5 downto 3);
dataBusIn <= '0';
waitAck <= '0';
-- work out what to do with the opcode
if (opcode = opcNOP) then
-- nothing to see here...
currentState <= fetch0;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "001") then
if (opcode(3) = '0') then
-- LXI instructions - read two more bytes
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= lxi0;
currentState <= readDirect0;
else
-- DAD instructions (double add) - 16 bit number in srcDReg is added to the 16 bit number in HL
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- regSP
end case;
currentState <= dad1;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "010") then
if (opcode(5) = '0') then
-- STAX - store accumulator - contents of accumulator are placed in the address in BC or DE
-- LDAX - load accumulator - contents of the address in BC or DE are placed in the accumulator
case opcode(4) is
when '0' => regSelector <= "00000011"; -- BC
when others => regSelector <= "00001100"; -- DE
end case;
regLoad <= '0';
case opcode(3) is
when '0' => currentState <= stax0;
when others => currentState <= ldax0;
end case;
elsif (opcode(5 downto 4) = "10") then
-- SHLD - store HL direct - contents of L are stored at the address following the instruction,
-- and the contents of H are stored at the location after that
-- LHLD - load HL direct
case opcode(3) is
when '0' => readMemReturnState <= shld0;
when others => readMemReturnState <= lhld0;
end case;
regSelector <= "00110000"; -- HL
regLoad <= '0';
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect0;
elsif (opcode(5 downto 4) = "11") then
-- STA -- store accumulator direct - the contents of the accumulator replace the byte at the address following the instruction
-- LDA -- load accumulatro direct - the contents of the accumulator are replaced by the byte at the address following the instruction
case opcode(3) is
when '0' => readMemReturnState <= sta0;
when others => readMemReturnState <= lda0;
end case;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect0;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "011") then
-- INX - increment register pair
-- DCX - increment register pair
-- no flags affected
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- regSP
end case;
currentState <= inxdcx0;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 1) = "10") then
if (opcode(5 downto 3) = "110") then -- mem ref
regSelector <= "00110000"; -- load mem ref from HL
currentState <= inrdcrmem0;
elsif (opcode(5 downto 3) = "111") then -- accumulator
if (opcode(0) = '0') then -- INR
a <= (a(7 downto 0) + 1); -- incrementByte(regDataOut);
else -- DCR
a <= (a(7 downto 0) - 1); --decrementByte(regDataOut);
end if;
currentState <= fetch0; -- todo
else
regSelector <= regToSelector(opcode(5 downto 3));
currentState <= inrdcrreg0;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "110") then
-- MVI -- todo
readMemReturnState <= mvi0;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readImmediate0;
elsif (opcode(7 downto 5) = "000" and opcode(2 downto 0) = "111") then
-- rotate accumulator instructions
if (opcode = opcRLC) then
tempReg1(7 downto 1) <= a(6 downto 0);
tempReg1(0) <= a(7);
flagsCarry <= a(7);
elsif (opcode = opcRRC) then
tempReg1(6 downto 0) <= a(7 downto 1);
tempReg1(7) <= a(0);
flagsCarry <= a(0);
elsif (opcode = opcRAL) then
tempReg1(7 downto 0) <= a(6 downto 0) & flagsCarry;
flagsCarry <= a(7); -- todo: verify you can do this as its used above
elsif (opcode = opcRAR) then
tempReg1(7 downto 0) <= flagsCarry & a(7 downto 1);
flagsCarry <= a(0); -- todo: verify you can do this as its used above
end if;
currentState <= postRotate0;
elsif (opcode(7 downto 5) = "001" and opcode(2 downto 0) = "111") then
if (opcode(4 downto 3) = "00") then
-- DAA -- decimal adjust accumulator 00100111
if (a(3 downto 0) > 9 or flagsAuxCarry = '1') then
a <= a + 6;
-- todo set aux carry if reqd
end if;
currentState <= daa0;
elsif (opcode(4 downto 3) = "01") then
-- CMA -- complement accumulator 00101111
a <= not a;
currentState <= fetch0;
else
if (opcode(3) = '0') then
-- STC -- set carry (carry to 1) 00110111
flagsCarry <= '1';
else
-- CMC -- complement carry 00111111
flagsCarry <= not flagsCarry;
end if;
currentState <= fetch0;
end if;
elsif (opcode(7 downto 6) = "01") then
-- this covers 0x40 to 0x7F for data transfer... also HLT is in here (76)
if (opcode = opcHLT) then
-- who goes there?
currentState <= halted0;
elsif (opcode(2 downto 0) = "110") then
-- read from memory address in HL
regSelector <= "00110000";
currentState <= movmemtoreg0;
elsif (opcode(5 downto 3) = "110") then
-- write to memory address in HL
if (opcode(2 downto 0) = "111") then -- a
dataOut <= a;
regSelector <= "00110000";
currentState <= movregtomem1;
else
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= movregtomem0;
end if;
else
-- register transfer
if (opcode(2 downto 0) = "111") then -- a
tempReg1 <= a;
currentState <= movregtoreg1;
else
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= movregtoreg0;
end if;
end if;
elsif (opcode(7 downto 6) = "10") then
-- arithmetic from 0x80 to 0x9F, logical from 0xA0 to 0xBF
-- operation already connected to alu
aluOperandA <= a;
aluCarryIn <= flagsCarry;
if (opcode(2 downto 0) = "110") then -- memory
regSelector <= "00110000"; -- load mem ref from HL
readMemReturnState <= aluOp0b;
currentState <= readRegPair0;
else -- register
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= aluOp0a;
end if;
elsif (opcode(7 downto 6) = "11") then
-- from 0xC0 to 0xFF
if (opcode(2 downto 0) = "111") then
-- RST -- todo
-- opcode(5 downto 3) * 8
currentState <= fetch0;
elsif (opcode = opcCALL or opcode(2 downto 0) = "100") then -- conditional calls
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= call0;
regSelector <= "01000000";
currentState <= readDirect0;
elsif (opcode = opcJMP or opcode(2 downto 0) = "010") then -- conditional jumps
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= jump0;
regSelector <= "01000000";
currentState <= readDirect0;
elsif (opcode = opcRET or opcode(2 downto 0) = "000") then -- conditional returns
if (opcode = opcRET
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
regSelector <= "01000000";
currentState <= ret0;
else
currentState <= fetch0;
end if;
elsif (opcode(3 downto 0) = "0001") then
-- pop
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= pop0;
elsif (opcode(3 downto 0) = "0101") then
-- push
if (opcode(5 downto 4) = "11") then
-- push from A and flags
tempReg1 <= a;
tempReg2 <= flagsSign & flagsZero & "0" & flagsAuxCarry & "0" & flagsParity & "1" & flagsCarry;
currentState <= push1;
else
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when others => regSelector <= "00110000"; -- regHL
end case;
currentState <= push0;
end if;
elsif (opcode = opcPCHL) then
-- PC <= HL
regSelector <= "00110000";
currentState <= pchl0;
elsif (opcode = opcSPHL) then
-- SP <= HL
regSelector <= "00110000";
currentState <= sphl0;
elsif (opcode = opcOUT or opcode = opcIN) then
readMemReturnState <= inout0;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readImmediate0;
--elsif (opcode = opcXTHL) then
elsif (opcode = opcXCHG) then
-- register exchange DE <-> HL
regSelector <= "00001100";
currentState <= xchg0;
elsif (opcode = opcDI) then
intEnabled <= '0';
currentState <= fetch0;
elsif (opcode = opcEI) then
intEnabled <= '1';
currentState <= fetch0;
elsif (opcode(7 downto 6) = "11" and opcode(2 downto 0) = "110") then
aluOpSelect <= opcode(5 downto 3);
aluOperandA <= a;
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= ani0;
currentState <= readImmediate0;
else
currentState <= badopcode;
end if;
else
currentState <= badopcode;
end if;
end if;
when readDirect0 =>
-- wait
pc <= pc + 1;
currentState <= readDirect1;
when readDirect1 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect2;
end if;
when readDirect2 =>
-- wait
pc <= pc + 1;
currentState <= readDirect3;
when readDirect3 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg2 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when readImmediate0 =>
-- wait
pc <= pc + 1;
currentState <= readImmediate1;
when readImmediate1 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when readRegPair0 =>
addressBus <= regDataOut;
regLoad <= '0';
dataBusIn <= '1';
currentState <= readRegPair1;
when readRegPair1 =>
-- wait
currentState <= readRegPair2;
when readRegPair2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when dad1 =>
waitCycleCount := 0;
tempReg1 <= regDataOut(7 downto 0); -- latch register array output
tempReg2 <= regDataOut(15 downto 8);
regSelector <= "00110000"; -- read hl
currentState <= dad2;
when dad2 =>
if (waitCycleCount = 0) then
regDataIn <= regDataOut + (tempReg2 & tempReg1); -- add temp and register output and store
regLoad <= '1';
waitCycleCount := waitCycleCount + 1;
elsif (waitCycleCount = 5) then
regLoad <= '0';
currentState <= fetch0;
else
waitCycleCount := waitCycleCount + 1;
end if;
when lxi0 =>
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- SP
end case;
regDataIn <= tempReg2 & tempReg1;
regLoad <= '1';
currentState <= lxi1;
when lxi1 =>
regLoad <= '0';
currentState <= fetch0;
when stax0 =>
addressBus <= regDataOut;
dataOut <= a;
wr <= '1';
currentState <= stax1;
when stax1 =>
-- wait
currentState <= stax2;
when stax2 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when ldax0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= ldax1;
when ldax1 =>
-- wait
currentState <= ldax2;
when ldax2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
a <= dataIn;
dataBusIn <= '0';
currentState <= fetch0;
end if;
when shld0 =>
-- contents of L are stored at the address following the instruction,
-- and the contents of H are stored at the location after that
addressBus <= (tempReg2 & tempReg1);
dataOut <= regDataOut(7 downto 0);
wr <= '1';
currentState <= shld1;
when shld1 =>
-- wait
currentState <= shld2;
when shld2 =>
addressBus <= (tempReg2 & tempReg1) + 1;
dataOut <= regDataOut(15 downto 8);
wr <= '1';
currentState <= shld3;
when shld3 =>
-- wait
currentState <= shld4;
when shld4 =>
wr <= '0';
currentState <= fetch0;
when lhld0 =>
-- the byte at the address following the instruction in stored in L
-- and the contents of the address following that are stored in H
addressBus <= (tempReg2 & tempReg1);
dataBusIn <= '1';
currentState <= lhld1;
when lhld1 =>
-- wait
currentState <= lhld2;
when lhld2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
regDataIn <= "00000000" & dataIn;
regSelector <= "00100000";
regLoad <= '1';
waitAck <= '0';
addressBus <= (tempReg2 & tempReg1) + 1;
dataBusIn <= '1';
currentState <= lhld3;
end if;
when lhld3 =>
-- wait
currentState <= lhld4;
when lhld4 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
regDataIn <= "00000000" & dataIn;
regSelector <= "00010000";
regLoad <= '1';
waitAck <= '0';
dataBusIn <= '0';
currentState <= fetch0;
end if;
when sta0 =>
addressBus <= (tempReg2 & tempReg1);
dataOut <= a;
wr <= '1';
currentState <= sta1;
when sta1 =>
-- wait
currentState <= sta2;
when sta2 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when lda0 =>
-- the byte at the address following the instruction in stored in L
-- and the contents of the address following that are stored in H
addressBus <= (tempReg2 & tempReg1);
dataBusIn <= '1';
currentState <= lda1;
when lda1 =>
-- wait
currentState <= lda2;
when lda2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
a <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= fetch0;
end if;
when inxdcx0 =>
if (opcode(3) = '0') then
regDataIn <= regDataOut + 1;
else
regDataIn <= regDataOut - 1;
end if;
regLoad <= '1';
currentState <= inxdcx1;
when inxdcx1 =>
regLoad <= '0';
currentState <= fetch0;
when inrdcrreg0 =>
if (opcode(0) = '0') then
regDataIn <= "00000000" & (regDataOut(7 downto 0) + 1); -- incrementByte(regDataOut);
else
regDataIn <= "00000000" & (regDataOut(7 downto 0) - 1); --decrementByte(regDataOut);
end if;
regLoad <= '1';
currentState <= inrdcrreg1;
when inrdcrreg1 =>
flagsZero <= not(or_reduce(regDataIn(7 downto 0)));
regLoad <= '0';
currentState <= fetch0;
when inrdcrmem0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= inrdcrmem1;
when inrdcrmem1 =>
-- wait
currentState <= inrdcrmem2;
when inrdcrmem2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
if (opcode(0) = '1') then
--dataOut <= incrementByte(dataIn);
else
--dataOut <= decrementByte(dataIn);
end if;
waitAck <= '0';
wr <= '1';
--addressBus <= stays the same as we're writing back
currentState <= inrdcrmem3;
end if;
when inrdcrmem3 =>
-- wait
currentState <= inrdcrmem4;
when inrdcrmem4 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when mvi0 =>
if (opcode(5 downto 3) = "110") then
dataOut <= tempReg1;
regSelector <= "00110000"; -- HL
currentState <= mvi1a;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn <= "00000000" & tempReg1;
regLoad <= '1';
currentState <= mvi1b;
end if;
when mvi1a =>
addressBus <= regDataOut;
wr <= '1';
currentState <= mvi2a;
when mvi2a =>
-- wait
currentState <= mvi3a;
when mvi3a =>
-- stored.
wr <= '0';
currentState <= fetch0;
when mvi1b =>
regLoad <= '0';
currentState <= fetch0;
when aluOp0a => -- from reg
aluOperandB <= regDataOut(7 downto 0);
currentState <= aluOp1;
when aluOp0b => -- from memory
aluOperandB <= tempReg1;
currentState <= aluOp1;
when aluOp1 =>
a <= aluResult;
currentState <= fetch0;
when postRotate0 =>
a <= tempReg1;
currentState <= fetch0;
when daa0 =>
if (a(7 downto 4) > 9 or flagsCarry = '1') then
a(7 downto 4) <= a(7 downto 4) + 6;
-- todo set carry if reqd
end if;
currentState <= fetch0;
when call0 =>
if (opcode = opcCALL
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
-- push pc to stack (high then low)
addressBus <= regDataOut - 1;
dataOut <= pc(15 downto 8);
wr <= '1';
currentState <= call1;
else
currentState <= fetch0;
end if;
when call1 =>
-- wait
currentState <= call2;
when call2 =>
-- stored
addressBus <= regDataOut - 2;
dataOut <= pc(7 downto 0);
currentState <= call3;
when call3 =>
-- wait and set pc to call site
pc <= tempReg2 & tempReg1;
regDataIn <= regDataOut - 2;
regLoad <= '1';
currentState <= call4;
when call4 =>
wr <= '0';
regLoad <= '0';
currentState <= fetch0;
when jump0 =>
if (opcode = opcJMP
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
pc <= tempReg2 & tempReg1;
end if;
currentState <= fetch0;
when ret0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= ret1;
when ret1 =>
-- wait
currentState <= ret2;
when ret2 =>
regLoad <= '0';
if (not ready = '1') then
waitAck <= '1';
else
tempReg1 <= dataIn;
addressBus <= regDataOut + 1;
waitAck <= '0';
currentState <= ret3;
end if;
when ret3 =>
-- wait
regDataIn <= regDataOut + 2;
regLoad <= '1';
currentState <= ret4;
when ret4 =>
regLoad <= '0';
if (not ready = '1') then
waitAck <= '1';
else
dataBusIn <= '0';
waitAck <= '0';
pc <= dataIn & tempReg1;
currentState <= fetch0;
end if;
when movmemtoreg0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= movmemtoreg1;
when movmemtoreg1 =>
-- wait
currentState <= movmemtoreg2;
when movmemtoreg2 =>
if (not ready = '1') then
waitAck <= '1';
else
dataBusIn <= '0';
waitAck <= '0';
if (opcode(5 downto 3) = "111") then
a <= dataIn;
currentState <= fetch0;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn(7 downto 0) <= dataIn;
regLoad <= '1';
currentState <= movmemtoreg3;
end if;
end if;
when movmemtoreg3 =>
regLoad <= '0';
currentState <= fetch0;
when movregtomem0 =>
dataOut <= regDataOut(7 downto 0);
regSelector <= "00110000";
currentState <= movregtomem1;
when movregtomem1 =>
addressBus <= regDataOut;
wr <= '1';
currentState <= movregtomem2;
when movregtomem2 =>
-- wait
currentState <= movregtomem3;
when movregtomem3 =>
wr <= '0';
currentState <= fetch0;
when movregtoreg0 =>
tempReg1 <= regDataOut(7 downto 0);
currentState <= movregtoreg1;
when movregtoreg1 =>
if (opcode(5 downto 3) = "111") then
a <= tempReg1;
currentState <= fetch0;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn <= "00000000" & tempReg1;
regLoad <= '1';
currentState <= movregtoreg2;
end if;
when movregtoreg2 =>
regLoad <= '0';
currentState <= fetch0;
when pop0 =>
-- wait
currentState <= pop1;
when pop1 =>
if (not ready = '1') then
waitAck <= '1';
else
waitAck <= '0';
tempReg2 <= dataIn;
addressBus <= regDataOut + 1;
dataBusIn <= '1';
currentState <= pop2;
end if;
when pop2 =>
-- wait and update SP
regDataIn <= regDataOut + 2;
regLoad <= '1';
currentState <= pop3;
when pop3 =>
if (not ready = '1') then
waitAck <= '1';
else
waitAck <= '0';
dataBusIn <= '0';
regLoad <= '0';
if (opcode(5 downto 4) = "11") then
-- pop to A and flags
a <= dataIn;
flagsSign <= tempReg2(7);
flagsZero <= tempReg2(6);
flagsAuxCarry <= tempReg2(4);
flagsParity <= tempReg2(2);
flagsCarry <= tempReg2(0);
currentState <= fetch0;
else
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when others => regSelector <= "00110000"; -- regHL
end case;
regDataIn <= dataIn & tempReg2;
regLoad <= '1';
currentState <= pop4;
end if;
end if;
when pop4 =>
regLoad <= '0';
currentState <= fetch0;
when push0 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regSelector <= "01000000";
currentState <= push1;
when push1 =>
addressBus <= regDataOut - 1;
dataOut <= tempReg1;
wr <= '1';
currentState <= push2;
when push2 =>
-- wait
currentState <= push3;
when push3 =>
addressBus <= regDataOut - 2;
dataOut <= tempReg2;
currentState <= push4;
when push4 =>
-- wait and update SP
regDataIn <= regDataOut - 2;
regLoad <= '1';
currentState <= push5;
when push5 =>
wr <= '0';
regLoad <= '0';
currentState <= fetch0;
when pchl0 =>
pc <= regDataOut;
currentState <= fetch0;
when sphl0 =>
regDataIn <= regDataOut;
regSelector <= "01000000";
regLoad <= '1';
currentState <= sphl1;
when sphl1 =>
regLoad <= '0';
currentState <= fetch0;
when ani0 =>
aluOperandB <= tempReg1;
currentState <= ani1;
when ani1 =>
a <= aluResult;
currentState <= fetch0;
when ori0 =>
aluOperandB <= tempReg1;
when ori1 =>
a <= aluResult;
currentState <= fetch0;
when inout0 =>
-- device num in tempReg1
-- opcode(3) = 1 for in 0 for out
-- todo read/send accumulator
currentState <= fetch0;
when xchg0 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regSelector <= "00110000"; -- regHL
currentState <= xchg1;
when xchg1 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regDataIn <= tempReg1 & tempReg2;
regLoad <= '1';
currentState <= xchg2;
when xchg2 =>
regSelector <= "00001100"; -- regDE
regDataIn <= tempReg1 & tempReg2;
currentState <= xchg3;
when xchg3 =>
regLoad <= '0';
currentState <= fetch0;
when badopcode =>
status <= "1110";
when halted0 =>
status <= "1111";
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
use work.interfaces.all;
entity alu_tb is
end;
architecture rtl of alu_tb is
component alu is
port(input : in alu_in_if;
output : out alu_out_if);
end component;
procedure output_data(name : string;
i0 : std_logic_vector(7 downto 0);
i1 : std_logic_vector(7 downto 0);
q : std_logic_vector(7 downto 0);
flags_in : std_logic_vector(7 downto 0);
flags_out : std_logic_vector(7 downto 0);
file output_file : text) is
variable tmp : line;
begin
write(tmp, name);
write(tmp, string'(" "));
write(tmp, i0);
write(tmp, string'(" "));
write(tmp, i1);
write(tmp, string'(" "));
write(tmp, flags_in);
write(tmp, string'(" "));
write(tmp, q);
write(tmp, string'(" "));
write(tmp, flags_out);
writeline(output_file, tmp);
end procedure;
signal clk : std_logic;
signal input : alu_in_if;
signal output : alu_out_if;
begin
alu0: alu
port map (input, output);
clkgen:
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
-- gen_data:
-- process
-- type state_t is (state_read_op, state_load_input, state_read_output);
-- variable state : state_t := state_read_op;
-- file log : text open read_mode is "/home/stuart/VHDL/gbvhdl/testing/input.txt";
-- file outfile : text;
-- variable tmp_line : line;
-- begin
-- case state is
-- when state_read_op =>
-- if endfile(log) then
-- report "End of simulation." severity failure;
-- end if;
-- readline(log, tmp_line);
-- file_open(outfile, "/home/stuart/VHDL/gbvhdl/testing/output/" & tmp_line.all & ".txt", WRITE_MODE);
-- op <= string_to_alu_op(tmp_line.all);
-- state := state_load_input;
-- wait for 10 ns;
-- when state_load_input =>
-- state := state_read_output;
-- wait for 10 ns;
-- when state_read_output =>
-- state := state_load_input;
-- output_data(tmp_line.all, i0, i1, q, flags_in, flags_out, outfile);
-- input <= std_logic_vector( unsigned(input) + 1);
-- if and_reduce(input) = '1' then
-- state := state_read_op;
-- file_close(outfile);
-- end if;
-- wait for 10 ns;
-- end case;
-- end process;
--
-- i0 <= input( 7 downto 0);
-- i1 <= input(15 downto 8);
-- flags_in <= input(19 downto 16) & "0000";
end rtl;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Basic Computer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Mano is
end Mano;
architecture arch of Mano is
component basicMano is
port(
CLK : in std_logic;
MEM : buffer word := (Others => '0');
PC : buffer word := (Others => '0');
DR : buffer word := (Others => '0');
AC : buffer word := (Others => '0');
IR : buffer word := (Others => '0');
TR : buffer word := (Others => '0');
BUSo: buffer word := (Others => '0');
AR : buffer adr := (Others => '0');
INPR: in std_logic_vector(7 downto 0);
OUTR: out std_logic_vector(7 downto 0);
FGI : buffer std_logic;
FGO : buffer std_logic;
sFGI: in std_logic:='0';
sFGO: in std_logic:='0'
);
end component basicMano;
signal CLK :std_logic;
signal MEM :word;
signal PC :word;
signal DR :word;
signal AC :word;
signal IR :word;
signal TR :word;
signal BUSo:word;
signal AR :adr;
signal INPR:std_logic_vector(7 downto 0);
signal OUTR:std_logic_vector(7 downto 0);
signal FGI :std_logic;
signal FGO :std_logic;
signal sFGI:std_logic;
signal sFGO:std_logic;
constant CLK_Period: TIME := 100 ns;
begin
bc: basicMano port map(CLK, MEM, PC, DR, AC, IR, TR, BUSo, AR, INPR, OUTR, FGI, FGO, sFGI, sFGO);
process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
end architecture; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:42:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.vhdl
-- Design : system_inverter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_inverter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_inverter_0_0 : entity is "system_inverter_0_0,inverter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_inverter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_inverter_0_0 : entity is "inverter,Vivado 2016.4";
end system_inverter_0_0;
architecture STRUCTURE of system_inverter_0_0 is
begin
x_not_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x,
O => x_not
);
end STRUCTURE;
|
entity FIFO is
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
LABEL1: postponed Proc1 (Clock);
LABEL2 : postponed READ (L => BufLine,
VALUE => Q);
process_and_or : postponed process(a,b,d,e) is
begin
end postponed process process_and_or;
end entity FIFO;
|
-- niosii_system_green_leds_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_green_leds_s1_translator;
architecture rtl of niosii_system_green_leds_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
green_leds_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_green_leds_s1_translator
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end FILTER_IIR_v1_0_S00_AXI;
architecture arch_imp of FILTER_IIR_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 20
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= slv_reg1;
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= slv_reg4;
when b"00101" =>
reg_data_out <= slv_reg5;
when b"00110" =>
reg_data_out <= slv_reg6;
when b"00111" =>
reg_data_out <= slv_reg7;
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= slv_reg13;
when b"01110" =>
reg_data_out <= slv_reg14;
when b"01111" =>
reg_data_out <= slv_reg15;
when b"10000" =>
reg_data_out <= slv_reg16;
when b"10001" =>
reg_data_out <= slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
Filter_Top_Level_inst : entity work.Filter_Top_Level
port map(
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
CLK_100mhz => S_AXI_ACLK,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
RST => slv_reg15(0),
sample_trigger_en => slv_reg16(0),
HP_SW => slv_reg17(0),
BP_SW => slv_reg18(0),
LP_SW => slv_reg19(0),
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14
);
-- User logic ends
end arch_imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end FILTER_IIR_v1_0_S00_AXI;
architecture arch_imp of FILTER_IIR_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 20
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= slv_reg1;
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= slv_reg4;
when b"00101" =>
reg_data_out <= slv_reg5;
when b"00110" =>
reg_data_out <= slv_reg6;
when b"00111" =>
reg_data_out <= slv_reg7;
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= slv_reg13;
when b"01110" =>
reg_data_out <= slv_reg14;
when b"01111" =>
reg_data_out <= slv_reg15;
when b"10000" =>
reg_data_out <= slv_reg16;
when b"10001" =>
reg_data_out <= slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
Filter_Top_Level_inst : entity work.Filter_Top_Level
port map(
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
CLK_100mhz => S_AXI_ACLK,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
RST => slv_reg15(0),
sample_trigger_en => slv_reg16(0),
HP_SW => slv_reg17(0),
BP_SW => slv_reg18(0),
LP_SW => slv_reg19(0),
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14
);
-- User logic ends
end arch_imp;
|
----------------------------------------------------------------------------------
-- EPP Controller
--
-- Original Author: Chris McClelland
-- Altered for use with EPP periperhals by Kyle Temkin
--
-- Portions copyright (c) 2013 Binghamton University
-- Copyright (c) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.-
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iThisR3 when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-!V87
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-!V87
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-!V87
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-!V87
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-!V87
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-!V87
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-!V87
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-!V87
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_CalcoloIndirizzo.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo trovato in rete, convertito da Verilog a VHDL
-- e successivamente adattato al progetto. Questo modulo
-- converte le coordinate in un indirizzo di memoria
-- Le coordinate sono calcolate sulla risoluzione di 320x240.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VGA_CalcoloIndirizzo is
-- "320x240": l'adattatore VGA usa un pixel di dimensioni 2x2.
-- Ho usato questa risoluzione per non superare il limite di memoria a disposizione.
-- 320x240 monocromatici = 76800 kbit - Il limite della memoria e' 240 kbit
port (
x : in std_logic_vector(8 downto 0);
y : in std_logic_vector(7 downto 0);
mem_address : out std_logic_vector(16 downto 0)
);
end VGA_CalcoloIndirizzo;
architecture behaviour of VGA_CalcoloIndirizzo is
signal res_320x240 : std_logic_vector(16 downto 0);
begin
-- Indirizzo = y*WIDTH + x;
-- In 320x240 il 320 e' scrivibile come due somme di potenze di due (256 + 64)
-- e l'indirizzo diventa (y*256) + (y*64) + x, semplificando l'operazione d moltiplcazione
-- che diventa uno shift piu' un'addizione.
-- Viene aggiunto uno zero in posizione piu' signficativa per trattarli come interi senza segno.
res_320x240 <= (('0' & y & "00000000") + ("00" & ('0' & y & "000000")) + ("0000000" & ('0' & x)));
process (res_320x240)
begin
mem_address <= res_320x240;
end process;
end behaviour; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library pvz;
use pvz.pvz_objects.all;
entity Input is
port(
clock, reset: in std_logic;
click: out std_logic;
game_state: in game_state;
ps2_clk: inout std_logic;
ps2_data: inout std_logic;
mousex, mousey: out std_logic_vector(9 downto 0); -- 鼠标坐标输出
state: out mouse_state := NO; -- 鼠标状态输出
plants: in plant_matrix; -- 输入输入
new_plant: out std_logic; -- 新植物信号
new_plant_type: out std_logic_vector(1 downto 0); -- 新植物类型
new_plant_x, new_plant_y: out integer range 0 to M-1 -- 新植物坐标
);
end entity;
architecture bhv of Input is
component ps2_mouse is
port(
clk_in: in std_logic;
reset_in: in std_logic;
ps2_clk: inout std_logic;
ps2_data: inout std_logic;
left_button: out std_logic;
right_button: out std_logic;
middle_button: out std_logic;
mousex: buffer std_logic_vector(9 downto 0);
mousey: buffer std_logic_vector(9 downto 0);
error_no_ack: out std_logic
);
end component;
signal left_button: std_logic;
signal s1, s2: mouse_state;
signal x, y: std_logic_vector(9 downto 0);
begin
mousex <= x;
mousey <= y;
click <= left_button;
mouse: ps2_mouse port map (
clk_in => clock,
reset_in => reset,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
left_button => left_button,
mousex => x, mousey => y
);
process(left_button)
variable px, py: integer range 0 to M-1;
begin
if (rising_edge(left_button)) then
if (6 <= y and y <= 62) then
if (164 <= x and x <= 202) then
s1 <= SUNFLOWER_DOWN;
elsif (207 <= x and x <= 245) then
s1 <= PEASHOOTER_DOWN;
elsif (250 <= x and x <= 288) then
s1 <= WALLNUT_DOWN;
else
s1 <= NO;
end if;
else
s1 <= NO;
end if;
elsif (falling_edge(left_button)) then
if (x < 576 and 72 <= y and y < 472) then
s2 <= UP;
px := conv_integer(x(9 downto 6));
py := conv_integer(y - 72) / 80;
new_plant_x <= px;
new_plant_y <= py;
if (s1 = NO and plants(py)(px).plant_type = "10") then
new_plant <= '1';
new_plant_type <= "10";
elsif (plants(py)(px).hp = 0) then
if (s1 = PEASHOOTER_DOWN) then
new_plant <= '1';
new_plant_type <= "00";
elsif (s1 = WALLNUT_DOWN) then
new_plant <= '1';
new_plant_type <= "01";
elsif (s1 = SUNFLOWER_DOWN) then
new_plant <= '1';
new_plant_type <= "10";
else
new_plant <= '0';
end if;
else
new_plant <= '0';
end if;
else
new_plant <= '0';
s2 <= NO;
end if;
end if;
if (left_button = '1') then
state <= s1;
else
state <= s2;
end if;
end process;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
p4R1JWHBywIR2Fi307tEhr9AcCfH9rS9QQ9Gn4BYGXVnDi5tc0U4TddOAMr9gE8yykBWg4pRrgQY
K0OXjCbgDQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XpdYEeRKQw9nhEXq47MIVZAJ///qNkxaVka8Z0bcj1dT2+H0QTInHjneUzYzLu8YPqeDmQr24kbO
wkgGTZa8j+jdXk0pz4vE9NbRsDC50znZIbuStqJlXvLDnJ/XF6ziNA6WoWAO3cWAa4bsqPLtwXfn
po/UeNJy8O7+GL1p4GY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QlEoufHvgQ/PWb44YQWe5IepwmsJFwFNPYfLZcpYZHOlMPEIgEZevKk2sHVQVk+Cudv3UZoX79WL
wphYFfx/NXYY76bxEILY6xi8UJgE5OZB/8xho3WMAbxPOxsGqXVFSa4F6+5HKvUeUdbcUl/95i1i
taCNTGNc9QouczHLD2HfIK5Avb74SvnSU15xzo8LOLl2seWI7VZKF5Ns4Og8iM6hNW1crWWMg3X6
iXioKAGf757tyFMG9fXDyUmSXOeAXtvTLHdmvz8fM/AcTFTOL99uhrFOflDpodQp53l/B/4nQCYf
5hMPF0Fd+SSegnxrtOt2hyfAAMU8cw0vLo/b7Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jSuNs9ls5g8Squqzlzvp73BJDN7bzKFFmA49HhgojPxPxzYaKRChIZoBvExaRvIm8fkw+Xsaxf4V
pXJXDCmRgAtVE+DzE0vtomDejkX5UAtceGhLib8ui1WEt4tsGidgqZVFsHjKpZ2HK+KBVheABTVA
uqA0XgTtawsQjOjHr1Y=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
i2CJx9GA/gbChKzzIYauuGaOiMmMW9pUNzmVsTa9q9W4VNxlDN38p60KHDBj7s9mGZAB67hrCMjS
wmx4bZXeq6ZMuSJWvmZCCo5IWr8FtWcxCRYtXS2OIJ6O14JglpvAlqlv9DIg+a15jNL/XPABEZW5
8BNJFijY8MLQerMAP36AzPUNo10qiEUdUDDj399zz35Rntdf91olkJWfdhPGs9hn8YxNvESSyc2C
T+NTw1o34iOEmEIJenb7Ng5CV4ypuQ+0wZDmV27pYMlwM8aRSWT3CfYedgGBODzTVIO5Xpu79FHl
1dRNS0OeB7uK/ybKhyxOOEKlYeN+BvnecD4p0w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 68608)
`protect data_block
Ja4qVGj2zyIazsmhoa/FFqvgWGfYJSg/erEY3yo9UlzOc8YrW6XYEZ5J99cgNFa17BoagkgTfnsj
FTBfMJ/wM7HthToolP7vgG8wIlzl+1J2yKgLJC3PJXWWomjyo/LqMlxa/3TFKlBVam5eWTqpCVvA
Ox+IuZef9C4XMC3hXt0UTwiywmLw0cEaV9YMAOsvgrJJU0A5ruKhHHWtT2yiuZ35kJPfU9Vlt/BI
ZMsZ7YwdmBEPSrKAAJaqSSVYB18TpO0p1WXhCHcjMA48a9KDOa3Ppot5MKrytb2EgslP5kKtmhdM
ka3agHj9Xw+b8/pfjNqrjR+QexvPTdPh7+FlYVEq5yecHe2D8q5lW49j4XbJqItYHI0zBQtF6MFM
iAzNAbVYJw9WDcXhoQSkcWj7iEw/eEWof8ZlCfwBnAqxq0zLSWx9D/Pd0O/VgBX1q2aVZsE/2FFK
ftwkcTKipW6UBHX/Ln+Huhmoy6xOZjGfMdcflc+31UQHk/PQ4kzHJvdBOcoaHWPtXReBNHxAJyhG
pxAc98K5cG7iVemLCVNonSKLxhiNarbHoh7rWt1jxu9xU5teA1xn2s+Vk/Wy3dItsTafm9CVKOGj
H44+EkMGodJleLtc2MMRRyqWQDj3kam8tTyh58F9q76bnIgnGgxMHevipr2RZUF9PG+J/yzkazgK
qLdM6OhwTzVsWVByE40wLW0Qc8h6e+qOcEpw8N04PyvsWSgg3KVPOCQRmgc/uPWxqIXrWObEHs4L
LWHQJZekKybomkwAs2OQX7E3JLSeG1AaOWRxN7G5u0zi13HyD99oxrCGzgi9x6OJWsWq/bPg1rFI
P1f+i1trK3oOV5o2oIEC1okD94lIjLBtmxHLU6U8fgj4V49/IRoleMMcUk4tUJgpGlwL+tgQzJtE
S5lji3iSK2+mXB5hdWCvyRqDqSudS1fAl+b5cqpPgBDpu8RK92PTXuJSBNGFy8O0BMQOMQLyIeSI
c1oZTEZekxkpxaxk4VU1qX+U6iPWFRXN1wAnQvRGwQqTVDqOL7Jvz6OaX2vZpD7CuxKbM8SnCIDY
wdIbT7HXtvjdmvtqrKoKYRqgBKO3VuJPF3aF/GNnI2Iv4BeAw0C5L66ewgdJZ+Q5iwBVISdIE7S0
qU7ocG4XBQJHp+a57vxszU1EKhotw2ifgM3kByG6Mf6GpKV5uaPOa7rDD/8lhUpzYSnxQhFQq856
5kWrl24Gc1RJT+ZRdeAlngMpHSTzT7Uch9Z//r0nQbOBSrXFPQvF7GfqFCcenrID1VSvRyPp3pwP
M85fhzf3jA3gr4JKy3PCB8yzY5Z6Iz9LE7ElxwjRxgc6f6QH2nGaMYkinsDPGFeQs10si0MployT
zBK8Y57nxlz6Adhy9TFIUdTevAWTAnuB+AenHIG6Yz3YXW81jPEz5iD57dHvbIDOV536Q5ZyrJpZ
IJu+73cCMSoqEdtjbEIIGrV1ZrUAoj/wEtBNjKXTBa7WxAPpbp3nPj474YvTkJcBY3vkRMi1ucmC
3QeFsqPX7skJqsxB8oJnm2Q9QwpzqZ3OaMKlnU6zHxo7s0QgRKkGelsHeK7uQ0BYS8i6Ttiry7od
iGbB702Tr+E6pob5f713mZZ7fqno5xEl1vxC8sZ6SqrU+VdP3+h5CtatP1+mWYPYzDEc9YIsJk76
wUjhhgKAnhguImRGAW/gb4OAHUM3b+GvSMWZIj29olCn0CcT2ZPGe3x8Blxs3bAWLI5d6kqEBaDW
+bCwZVpoC4LNvlh59N9QgsTHBGtC8ynZ2U2O9Kah4dWRXuMyToolT5k1bFKL+bWN0drdeI+o+XEg
lmnHMsC7eK6nCOdV+TGXrh2uVTkUOseBHAwn28ae4vg9ED9bBCCfLOuWJ5N67wW2Uq4U6M3OC8QQ
vJUkPY3BMTZMVxnwHyPvdSbkbUscaEn29MOhbB012x59FDs5VcwWxL0iLHC4aFF5yRLY+QFiu5fg
GBxQp5A6il8L6/hM9+5eP4FOD400Yb7bHbPsLsLik8aHFi4zQ/i8g+Rs285ZdLU0iQCUhGM74yvJ
QgEna6XKaBUvuzKvCcdztLuQnO1KuIJforiBkErE2JTGeYQIwK/QqeZSLHmQ3s2LDTfWum/6QGKZ
zbWUa/SHnHn+dj0QS0iNs1GFRLumbqSZX4Uz6wgqWIL2YhgVRLJlqlDZVSa1x5H+XCjwetUgouJC
g32awYWGxVmyp6quGaFOL1onYGDKYjZo8stdVWHlkQijw2zWgEBixLGvKYLMv7F2897hiw/BcppJ
x9S8nk/7Mi8RmGBDeHJ1I/f+cj+L8upfGwlMJphaLCjqzOqWt5vMlKTn4r25atgN49l60MfxTM4h
09waQymCNjjv3oUhvsK29bFbBz8n0JjiQF0+ThNH2opE9nQRGqTIXcGfVgclpXgqWElREn6eXKAq
6Eq3DhbQHDn9ExoISmfom9IMwxEA0WIR2OafZxwVqCYLLeusARnp+k4hqmhTq+YYMcGeMk5boHuN
vPKoqy56WNc0TQxEX+2YI3uT6/FQguEiEsCzaBX8OLFOHwt8LOVceYuGPfghviSwPECBRlh9Pt7b
Tr8apapHGw6Ne9NxV29AG3wyasc9veHeqALGKqlekeHchhrs+hxPtquaq7cQjtrYTxdpPpGf3fZp
PG/mBCF9S9cWHv3+UXM5i3zqYB2yuDQVgq7hIkbjeAxIm4V7vIdmKZH9H2lc9YmYjWFfJc2y8bau
mp/IaDcwFFxDVpjGpeFq5GtYbtNXF0Yjt0FFXHQqYp6NK2y0cAs3Mcuz5ADRrPIdz9rYp2jVse27
OuwM9t0YWgJKSiZCTeWRYZyJAZOZF/fQFeXklCdcAnoOzv1PqZcCCxbK6IWuZNn/Rw/HzSZ2/iA/
lvCzZP7STGbllL41fLH1cpwNlWuWDQaobGfZQKc+x4NAwBxChbKKCbXALZA0/F+txAod4V8RmgRK
lb91Z64BuB8E4albz5/G8Wtba9FqxiipNFiTJI2OeALN3WDkVkiu/vr2PsjU6sKro7s3x/sZ+rQ9
4B12lV8HaSf5KAwtrTqV2c6oeFah5YGn46Bm6KmCs+tZ7OFLbDkYFAxWDkqKGXmmCHLOqlAy26tW
fpULE3xC6wb43BVei5PKI5lHOgyZ7pPCAmtgmuTDA6sgsDaRcOwA3wFxrNWq7ykqp/+xwPPmXJP+
UYDh1liJkiNE6P+Aw9izXR3wqDO1U4OBnIXF8mmpPyajynZlC1R0oAWG/NigU4ncPzLhdLXmYXAz
L5PhltlvWEbIEp+LEnxIJ1Ve3yJsJaJK42D+0fE/bilAk7WLC9QVKGBVR3B+Q8BLhrIeOgfjah8f
3hCgjIxQ9F5atms4ZqG4o29B9sbsvtN/ZG69PBsCB0dYHnTTgmPLEu4OHlqm3dfJjqteLsiSzCXw
NkR8ShcQMDeNaczM1Orvuxiljw5XC2UPeg/vn+inuUvjJoQzjDZR2CPUxS2rKbe3lRhluz39NJBe
n6XEq9inUWA2+Yt2TGjMgnpjr78SJ5WqWSelz0eQAZSGZcaLe/cthe/LwspzqYjeX8VZ3hX3V6e1
u6TAPPZDYD01u24jIojb/SBECtUPEJWCYrtQZx/a0dTSdK/KpjIKDXD0Sd5UFUyIRfIyCeMSO9px
KFs8j35smFkWa1Rw9HhmBiANPvnUPu7VaWqVEcbQEMKlmX32NVF4MEij7zpcmuZm6sfxtqRAFRDh
WDgg/T5qHIspbdN4rEusLtggHEKt1eIil1BPx/qPu4KGX24e3ZXEi1S/0A8W214u8roG4Y9H5bcV
Idrl+tBU1uT02qVblha4eUyqlNBMsljoCjH8aiU/l1dhd0pjDSTQUh49tshOheYN8azwnVaZeDn0
puVAP4ufZM8jUSrkm3Dilrdl8DudJYUVwRp5/wya63/v92IHQ7jMk1lvcy6OOS96H7EHJMCuqxT/
6oXtAolFh4kKxKMLpWIxZ6Mq6WVfA8lwZq/qjAs+lDF+y1fnRk2ykXwntUonHD2jDO6lgs11K/E7
lnBNAxm1MAQut2KQvcMg1swJSK31pQLgY0N6VUix6LNF1s1ixEuyOPNeQwNcc9nb1yfqYfAhE0bS
WSZK8H49mIwJms8e3Nxp7zvEmqTPrRpivck873wu+GA3rr/T6t5BaHNOS5zF0RAjwdr0mYYF9PV6
YQ9fovFVw3QVVsctZ0ewjYJ/7D8gk271Q2ox+uJnkdZqBSDPEGGEve4TgdPSO/0pSnU6RG2dzarC
55QD/B2jUFNPzpvLq9HDt7+UDXa39Cp9xcEe47h8L8Na9by6Mq5fK5OIv2oMvHgDbAvSLRgQq74a
zE2pbJHcNRiXBP0JWdSrEQUND9wMc+jM8Oj9LaWMEfwJQPLzAnxDDQbBlwEgTny/yrDoj/NAd8lR
fayRZ5lc1Od6A6EJlRpFBw+AaurKgZua3t9TMJ0+yf5x+cSAX6wmbElFqtkaS4LpnKkdRHHhUx6z
q0JeNNDjoTwBLI8ffgvf2YaMlnTXEUlru5ZboStpCcevuWHFOIVD4iBt7oEoYuREKVxrnbTQt5yS
lz2Nik6vQEEexJnRYF2Y217hlbZ80Ljk2beJKC2IvGxOtBrwf3Y8vix2g8PdcscOfvDCCe19ylk9
BPdNhnOp37er7KWrmIJwJstNAwlGbQquDrg/BhCIzSlwbJ8bRY4jVEVrIP7RndsGS6CVGE4FT7dg
33CIh2KeWgQhrX8hWbU2x+pD1DNOtj6zHzT2TqrHMgsRzYPDEyWo/QDUN5DlafyH09lniG5DvIAG
d6D4hJayGM3HnhrbozXo6h3J1fVK9R50uYI3PY0yxVsHSKAA9e51wmMvcxr+zTYHfDstlfhcL5Rl
VGinKv/jqY276N8m5V9nKYyCp9bWLN8UzO9KvuLlplyQQegRFNHsFncJbLeubUXfE2nmrgaRld34
13XnW6xBqiTHtTwQn4w+Twc0HKqQlHbt3o/r8UnpAQhKiUa1m/2kieG7DeI2JBk7oIdYzseCLyt7
6Db4Da00IlMjARbXO0XN6Vjgh2SN0PL2e+z4Hv9lBxwcB3XJXUbvMCI4WF0CPZ3vP1OQ35ZL3jyK
h/3rqf9W6cT9zuRSlVtTuDcaO4lJ8Xcw7BpW8pVFDrW+gQIWVuZbO+lphDNOuinHw+UybD0EO/AS
ich9e+O77iCXkmZo4v1JjHHvqdd999LPy0Mtv+2F8aEWXHzVh7O8TF7mZhjAB9TD9dHIXAnlxFkw
1DgXWeMjkfMt54aol+uVn5gcb4gtn2jrtOshV65WbWHGCqAa4j6fwQr7aHMQTculWTLlDHpWpbDs
2Hk+MQcsHbQ/Ug84Kr7C338VsuQ4m7I5DmfJj65KjwxCS8CrJk1kz833DT6SVnkt9VBOIAEpefBy
KASzNQ+Y7DRWxItdaSfB2S7B24x6GzYDJL4G7BuXC3jXplyQASYtIp4d+12QsRkmU5N3StcaO4A7
ZXkCaPdQq5zT2VaRCHBfeqxKIGLbcCNcLH1TqcBSL2CeCy8sFSLe+Exx9he4NOeO8hg6EvxuRnEN
aCVPhGzy1QdqIw7oiIu284s2wmvYIurlUVzvcn1nimWynRVOd7yZ1Vgrq2gpJsYzNFWC7yWanatO
JworXAoRxVddy1QZ1WSvpkC29pvRFg1HhP7Yvdk5uCTFjzr/2DCgLDOo//6DX+71ILzGFvQ4jCmV
qpP2y31nB0Ckc2raMuYVUUiv2RwaoY+XDLmSCs0yAzqo7/aGsY4gByEAspEiWqteK9vrZ/kkGBpU
ZN+EzS/M3J71ACZeapVM2X5ot4x2bgHHAGRRhJkVLhu19o4HcisN+fJkzeuCeOoOvjrAhvkiUQsx
TtWyOuwhpc9flziRk22+vSvq4RLqpF+RhRwrzFNz+WCmCJAhp6JMzoRO8gTP9avn7g0qg1QSWPT0
udmW7OB3NlpNTIcTt06xo5sxzkxZh80H9RkpUk2v0u8jhCOGCfUvFggb7DOblPPSSnlEpxwofJrL
ikw1BxN7TWMs8UbbvzdGg2aEKd1QSSxNwzTitvK0XDNgK5p5icY5/lf4M4ueA0cux+JYZSKg+JGx
kQJtSJtif3rEuT6FK3nWNywI4ZyicpH9jJrKYmx+fXNzZrpS7O6r5bfsIpvHcx3Envi8372I7YRw
t2IoEhd6gC+35OM4p3ggQNuJfxR5SEhzQghrcoNtAth3qD3XeqPaEMQf8Quk9wG7OtAVi/1TlBtr
R2IBSFwJkjqI272Zj7Z6CsqpwOKoBVBECAQZ90ZWp5VqzvisZAlVJsO1qKUudGbZuOwsyZgxz7xt
H4Sh5KYrx0hHpEzaVSvxa/3+ZY2kymJlFum0savSMVqLLtr7b6kivaXRR/Z84SkkK/yA3ZP455JS
GW/ODEtWtjLceZ3K7XKi1VtjLmsiacIEjCPwqA+jcYCAwzAuDr6S0/MBCHb5DB/nKXK261WPoZka
aCjmiknjUpijGTRUbum8bXMNYMfTy8vqP/OnVpokUCMLSIQqlB2Z8vFeWCI3VXGF4+TVY+YsiLtW
DYwT7irHiWQFETJAoBlex1fDkjEtbIX3FpAU8yg0OQscUs9zpDXAhKVmLD94L3BRYt98jlU4Z8Fr
DMVmSRLzm5PRhcWPzXJpub5XJ2q5l/52God/9HR3li2UYfcNBtZmBeIUpzMtGCkD7/L8e7Hgg0lS
bfaOaHaWyhGhKs7g/a0BgMeIkNkYdc0sYpBgMl2+Z9rwUOaXdREloenPQqrmsIL9Y2dy5Mah4zB2
8JenTrc8KCSH8s/bqt4YZJLbXYc2M1te7uzxYYhOMKOklMk4eju4GRZUJUzYiFxeXFpA/jbsYOdd
tlLR/es6H6IXfajeaURruz55eaxSvfW1qg1FqIYZp3Ws69sXOU2VNnMrRep9SVIp8fmHacOkL6Fh
CS6NU5AH4soqUBSl+vErtvKN9Pm7puE00HC7+geKF9+kvtsUrL+2aDR+r4EWk0RzxyxM8Gm4LX40
FQeFHgPIOiq267UyXKXfzF2AMtjCSYWqGEOxuzdKDV10IoVlBQMcr1lqUAAGB1tTGV3bbiI0zbrX
URdmYtRtQAwQC2vxivWtK4ygoMZRLEWPP1YBffQPSYoA4Yv3Dr4IlgqOfXohO/55PvJyg0no5b3s
g+w9YB7OfuJsk9LunzT+S1cOfqIB4r6WBRF9akdq+S/dM4Cb0xTW5flTfwNjwkUhvT80s18u+0oo
VwMHKDaRBPM61ZdgUQislJXa+8/43PKiRAtc6scFcyk8c4iihO53tANAdhlZVQ4u0nY0TavTNKz0
LMliLqt2LOPbpUcjISwvzwru2Yndmja7kB/eh8G3VOXPgn5W3c3ZvSBBrEGD/iMAxCXGTqJP58si
UsCQ065RTPgLbEvFpwqV97URTdAKKpvqu46ia8a6Er3TamCoZFVgwYd0TOkVN6MoU6yeeOe0+B3s
MoJCeeaN1HS/5SL55XfcWjXVyCmzgxaOf0k+XHHXTifzotzkb4tS4rJwIUeaLSuV1K+YbjVVsFuE
jQcyi+/W5a8p9vFez00/RULClbf4mD80pAf6Hwkop9JGvybaSIVL/TRftPjtsneyoA/LsDVeQyBx
177bctUYoYtNh4RoNFwwf+mwuPJuKWCfKDEbDwU8NrMbaxRBOT9Ag3CqMLH9mCtCqN8ERe+x0Hci
+2N970ETmpK5WZN3AmxVgFaNIvY/uhYNPIuGdnrDtZlMrP6zL++gsqZ0riIulX8P8fg6s/Q9qWsO
RW3ixsPqMmalIMTHwjfCm8ZLp83BHAaA41gArnFsgwI9xfE/SuK+42rc5cxiTI+OTNB/fFQpt2b3
oCrUDtu9KIJHW+yiM+9Av9bMNuG7q3c4hzHwXb5xHAhB5SterSjFO5C7KcteXtNQpwaXxFvaIqix
ouqwrFCFiGlqO8larTGt4F4dL14NeBgBick+lLraAt1kqrAX/1RIeKW3Yj5JA98qds/ih5o9BCNF
HAwxccErXxrF2ozmXLYSlgO1f3mH3TIyOiXAKOUtPJ8QI+Ka21zZIgH4BD57CoEwgUFwk81GRvPi
7hSvreP4KhstWhRSbt1eZcK9nCGZx4hcJHLX0320+emtYnatAcg6WbwVXNzf3lCNsqZHTWhfzhSS
nAejCXLmOBJ3RkjI0zf4uUxbCQlTZGz5dKRpPdklrY+ePItIg7pMs4ypLY3soBMCvbVBhTM0ABOf
i0THRB7hjKW924yzVw+lPP7ZEfJaEFwJDjwQyAC9Byo+wHm7iF3FlDOoG1MjApMURVDDwPpjQsdM
rgYvEx7ECe+4pSEEWpvn0cgZIWlbhg3S6Z+zjAnAz9SJ/VZRNF2+o9l2CXZbN1xKHnBc5r82Z1hF
O3nifR3aptVmOsVn/aY2LBo4I6sAV+M1v4gHI7q9bfwTgnnGjOZFGsWlOG5+1YM3vEbX1dAkZeMk
+Z1bTOMy3kcRv3+7gj9bXw5WMrvMdSfC51XGHS90N61Eg0NMGG1aHD6cNVCnj1xOUWpWV61Wwipr
WF5gTeJgMbRRtyTnlqs1rzeakiYIe0Uxts9ERkZtLSmsekMMpL1id3tj2PtPpVmNjHazEqcfhH57
gAzhCPv8bCNVPBsrHQ7B8VXYs9tlR6kn3W+ivepGHobtICgqMRitelflJ8z1U3c7QXwpt7ESWNpv
6r/yIB406tr45m/9uEmISoIqGEBOr/IiyczKs/t515AidfXogf/AK7mv5NhGKh9+DsBZiy41d8r6
0GX6v71fgUrV5bpfPzV9yBrfSNa9l7bsHOLAk8l3jT1sqdYzjzswMjYTaGNHwd3KpHhhAqulU/CT
sJ30qivLAObH0PiKupQm/Pr6mZ4rsrcPWivEuS99qK7wUJRCFe7unM+Oq1ohd3Zx81w9S2m8Skyp
Jpp0gf1eOIJr20aXxCENTaC4UBbC34+th1VC9dtRS9Slb1VQwbBiOb7/dGyOdgtNj2X1eR2YNfvC
dHAgfZ2FmZcXgp7NlHVueB/SkRfAD9Q6479vWqXI9ZXsJXjMmiy3/BxmwcVYOwdYpdyFptHNSa/4
Ax5Cm8MiYYwFdzK+RZE3qDSnPilcjdlDjtQwtMKJZhVyNeOX+wX4zes7M9Uo3FETfdpDFLitLAhe
9QaTZH+TKFtSNWUVAU/vFxlSqBFt8NyRAnYK2FdKV9IHzsCDjLDuQzxzdrkElUJjT9NDBjuypB56
m9Ag7Jn5O/GgzBQiso9VjiMLDdCjqculrSPqFWiAFVSQQHrac9WK+GDCdvz0DVRPW7Ug6DVVJ39O
r1cUaAPuFXNNVoHREdCl5VRQ0lCsuaLCVrk2osMJYlAi6jp+iHRoI29Epmqqy6iNtgwE+5hC0BjT
YF7uodwRqRze+Bc7H1uIVC2UFZJNuesScEKApdgG5fQwJAwn1NrS+D2x46cumNlbuwnWYdp16nVx
C18sWxoBthlot5W3uJea7ujgdTgSugT7ybTbS2oBixcEUjorXKrvtyzBgkPB1uFLFNK64gp5MZQ/
eVGXVkrlePSGsuP1FWVR6W39V9O98jxpkU4F0G0bxh0kfP/ycAq4fKratltlFmOkNVsTQl0bgOR3
bYJMQZLMrAE/cwgHm7FBRm82EHCaIBiQTeYARqWGHmXRT0VjW0lJkJrcnrvUOnp0foJFeizIMcVS
ooIK4lTH/hLbkfkd1p2Lm7dZ2PHffHaITdxbPIuwgO8yANdgTKvAqLlXsRrGOW6sQFBGdDLWzGDG
Hrcae5+xIRJx54cz8aYU9sJKJEfYoSg3swIBvF3Hj7af0viNPWjv0vyyIR/Mq7gvYYrtajTJ+vWS
yEfimEZlC7fJWNI7jSqIdaV7EdTbBmgPI6q9Ejy8rpwAtvFT12r3qEieyd3T9rLV86I7q5O6NH5K
UqdamYxpM6+8bQKzbVVJ3Qh6ITV5cj+ILtVswdv9mbuUmtEOGaFeDI8I5aWu6mL+smkpJ4iIUwhD
WE8a4V8c20I5ADMgrYRTdLVHq4OiEOYzm+EA9jcKS08ZO4WIBoAEd8zqGVgYmwi6CCEvHll9L813
5Zfu3ZUKQEyztfrKVjDO/VKgHOj+X53pexPOdb768CUk1Wl5+YelBdtirhISU8eCopUFMrlFpxO8
+pt6D47ubvTHPt3S+Uww86B0O2G1lrioAlzWav7tMZ+rAfdge/LmWBOVlb6SdNsH4aeyOFPX5GF2
Z8BmNoZt8OXCChoF2PavWhBrVniLYY2uz5tk+dqPohG2eRfnyJrzVzhqZd6+BazOzYUj23eK0VH7
630LiVYXR2YyaeoSMR798jxlXpmq61XkplXBqUU0EbHEcRHDXac2+akTvyaNAb1RK2AzD7YeOkNg
238qkbP9d8qORTsM3jWKBgs+ruV/vPEUq/eaQa563tgGwTM2Ktd5nVxd3SY8l9VfFivttsbIHOFE
pOhAYy0ddxIjVsx3DFgGdAuCwWh5yhp/9W5Wpzm6CfzotkR+fRNEGjnAWIHb6Sav/U41Is0DwYLX
LeuJjT6jKUBgkfDuebRw9Pru65Lye32jYzPGltJna9X3dGZQmItyP5QQLBLIknDvHLOF8FdqStoq
/P7cgACYdQBVNc9pPZJvSPXFCfsNJKopqV0TZ9b3hRhSiUv7AAEWvQbHL41FVPYtkfYJjle28XAw
nkKmQDvZ39/2763KIGgI9tDQgFjf1Bo2dkEX+xU8fx68GzQjy6q+KlKFiVf+50RPxEZLWWv9q5dS
SDsEG9/1VZPn8Pc8XJlLBg0cAKPj6khWdH8aGy4CBLCxT75m/FavTklkUkzCp8ESeHp2khYXIN8U
khMnnBTApHUNMGOlJ5Nv0YGYaR8h53hlo3a4OAWZKomP4bXlALeNOOh73qZd1MP05zGMcnbx/9bK
5IbusgJF4rs9qY7KritmYf0WVgxqbKxjMrqqUKM5TjkFN5fnl9adFQ3mZBrfuohLIFX6aNQvDNue
s0S01tF80o5/zvYTaZVsER/LypgYeod8+Me845/AsbQ+xmIPpeiD8hzA2I4uz9lhSg4V0PdvEPe3
4ml4sf9kL1GbumgG2y8WnGEspQzVdTtPWoo9xKC4d6V9HX2GoNKoH/ftRvfkR23zwYh+ui3M+Q0S
xpj8iydIbrzxrh2ClHn1TidzpvJ/NmzPGIYS89Rr31+rqbEbVpyjFm1IsZq0xckzi5DJk2o4WqjY
RIXFVpuZS0lXFJ/azLfj0t68RFkgnAmfyZ/Ab9T0SH+TXXjLuO3VLjdP6W9g9GP6cr0L/wVR3V2X
F9EU8bZDkRCBFzBVn5JdNm0A77SVHf3yAOv03DOZWVj3dmc4jaD0FZ92mU4bRlQ29GKZtGeVteV7
N9KOWEkAspJoN4dOKqVCUjEHRXHaWl1gr02H2UciLUeGxPLHo3QPOQ2hXE8P99L2z/dG1vb1+MOV
HdlV5wamh+D7LGDXet2cA3KCA6fGq8qL8A8T1+l4RFIz3hlxxFqMFzDz4bpD6adsAyVv3728x3Vr
KvcvyvPvjL1ygrO6y8NMpMOX6WbdeK/Funh42v2EERY4FpdYyrIHJI4bw7BHpwvEIEdU9Gs8ZwIi
+ekxbO/nKdRbs68aBwrJ4SkAfrQwyWyP5TTEcGQuG/OU7d4fOkkNO+jNRlLbuN7lNhGUNkreA5Od
gxO+3l3mETNB/DAhVFbxCa1N1/bwg3/pnoGRJYP52LYN3wNReg74yt46KHmHYoCtZiHA2ApMhhGI
CdQNfCptz7sE9ygshHKiO5J3pIYJpXDWSN5yfekt90RxAeIey4ggzfiw3hZq8we8m1+4+yYiGIMm
+18A0ORXWWTPmFrp0ILgmsoxzilRyKirnifwwhi/9J5Ur5Y7IqSJk2XUfRrcWbtTUvMjUZSP0T6d
gcfDRRQMFEB/9+bKAM9EXduNq98XIFuIw9Js6C8KsX//0jnQUCqSWVauh+UmzaV1ONzlZOC7aX7W
rwXnipiNOkUJ1udnTLwqMRjrNln5QGz4enNg5g1zD41PGVzNWHe95DpSbU/NKuEL3DKlGjsi8YRG
CJDQGu2lFQU/e3NARQWPLXFg5b4aI76SHRfafzhTLej4Bj2Z1cRWWQSXPDiYu7CZ0JSIcglGctpS
LGHKQPKRph+5oznURYLKqWtCwi55nfWtOCX2hMjhmPmVSBbUD25C4MpOWjDV9a98u39XPebh2uAz
HXLIhEh73dlm4l7GOdZXWyEkCrUxoCUigFfrwOnkjLl0bEHtGFNebvrgy5HZR93xa7ca/1gpYJY4
LmMPhyG2EODKTC/XEBLjKbCJnIwZ/p7HP2uoDs2rhMb4ipR8/NhOamvDTjqSsXnOIoaz5FJXPhje
ctxPGpSNpo76hftjcoM4jwp8UDZlUQqcqpedE9whmI97y5YTIODae9hCibm/96qLskFqRxw0gDYV
PVAOcIBQLs/3MHu2w16UdeCw2acHyy/h0KnDmrOF7RUiz7Qu7ixWl4eWdjN16DR8hG0wpG5pUX3H
C6VUGcKmlYpSgB6o00ezqQI07B8ONlVGcRqf/zioE0ZUUPoFeqq0P6vcxDTOWsRw2IkHVIxVMbm0
oBgHST4iyzSpbyfsHWiYNkbDpVbgh15Z2fbRATtdDVR8o3HQgc/Mky4zU7zMoBd7NcJTyoJ6zeij
fjAlXw06Fw7ESBUTudrl8N94L1iVfc2Aarr4vA22lEwyyDFwdf7Nuzs1BNXPjqkrfC3A28/RdKNa
vW7vGfBbZLaM8yyEsQVPzwKDNIFJJcZIxDZy4wS5waMLclzp51kCqLtYJJTdM5UOf3Gmy4JuVq70
qXaQHF+Xb358lTovtt71H4zlRtEYP9/6kcmCm61jpeIOlpMDXG9H6hFuf8bLKg5m360i/xhM99Hd
Fhx8dkTpy6J1Tq1ZgIAwgs4HEyOG7lgLTmVfFW5X8im3YpsJu0ck8/NuMD3sRcSrXgPAoeRMp0P0
KeiyjdOWbwXh0lKtfivI5/XhthJhVIfeXQzeodHwRaeUWjO2czrSvR5Tj0SgkYT4RN8jUIwOgrsC
hSrpwwAp4a0GQHhuVtVg+DyIcLvOVQ47ZuSfgIYKa14I3y5KtmcWkPPud121dez3L66Gsq9HtBQ+
FFW/uirxoP3V+nDgl1YX5csAArNcJKGMkf5E/+6i9QKPQJjSmhD3sgKaUhJNVf2fDxu/KLWAjYmo
0/chgvDdRHQAiY5xqsuNVBEIT80eZ2+ixpdNiO4dNph3tUoihhrQ2fuZvsfRNxy84OZH7oPoV5Lj
USx5ukdYTI03n5vlCnp+m9F3lk1DimvSsKIB4Rz0qBaSqJi0jSsKIZ6DQlgZ+L0wSjFW3EjQ+UJP
EWbURKVRMZ+/W+627Rf9N0n9RDReodaNfXYHinV7H0FyaVxXpfqu39UnB7HVf3JzdJ7UltN+B+y7
WElVDhbmih1KQ4ERykeG/Yb1nn8PwrJUTAVNmhW+nbqMILWeT3Zeue8Iw1m7Cjf4piqhxZ+qrPf6
OZ/s1aN6fsh7heN4OIa9X0MGiXRIvz86Gyv2dytU7WhIVj2Y4TfVeUReWTcBJswNtgkfOpYbaka9
HWgVx3ta6iui8M1i/xwxEBWHA7jinnrG7w+D74hwrgunh56cGrUrd/9kOc5DiUMFoXPvNQO3SGcW
W+hyzTfFdN6f872Gksye8KP9pfZmlslV3/8G4uFfn58uewkj+5nKMgG0MXbTnlk9+dRTKR/6M0MD
BiEKURGpMZpjw45sx3yLbBgkoM4QJOZxveKiO85lE7W12NEx73E6EfYSIkOC6Qa1ZeKSVazrppPn
ig3xf8Es4heb5fJdfBYXdPSHnI+jD4cJiPrVkwWlDawTemQukykwlLDe23j97ABtnLg3n58ENsgg
VHyRcyH7IhUD+fjL1/oL8FeXg9lkL6D3005zkSOWZPrlN8eqT6mF2J6ioLJyODhqHnIElmzcNwb7
s84rgKxdzhXX79l7gabzrfZgOYY3UcMNS/smSAXxKgbbbl6zU8x8V/hRqLPj+NJbLydlc8qYf6kA
lHixe0OyUZAlk7ud3RZd2DXUtS55AafYcAuUrWSJ1QZZjdAMd45AuctBoPsR4cbXgRgIxDS7cd4n
+W+Ybpuh7csTjMZwskQmInfa5upbBFTed6uXfIL4DBXW2BovJJkhUegNRaljyEHv7I5LY9LLDXj2
pCT+orJuP5NCksrfltDlfvJuqjFCNjcH6urxtgWOxShIAfooczQ3T6mwG+wOeyMdZglYD8PZTk2k
CV39HYeHysUyHrSh7on8SbnVf0NHt2ssLENBNLaGkSxiqDXgkDCaT2+FLFG45dbHcVrPMAQ0FHjJ
FtcBKzmIeR60yCNG5VAzHJqNZoTs0szSsQUo6wp1I7Xj3+gc8zCGHJCTIRChwk763KXeugKdUOhB
JKqDRzonWS/JrZPg48LaVYyZMZ28Bgbm+Nb0Eh7rWONbHgywH6Oy4o6EHwa9KBQ2Z4l5tzH+dgIA
MdaHNIfV7UA372/822SqMI2yZqQoQFjPf1l7jG8cLmIMJZ4hkwypTcVgmxKREiG1K/FMORKtAqiv
QZvucYCLtY6I6E/qmSJmhHgt9Gk/4mNUtKff9twwBdnV/vO6JNdx7fWxpb2vYflR77a3ui3rBniS
0Zl+5BqLtnYZYNi7qvkQjIEpcXMW6GN2XFPQuaB61OJm1DbRUE3pTQTKc5RNRRgF8d0EFrPdNWLY
pyZAj67xO7RQi4HJcKdrnDHGEqfB9UbA3YURkqSN7kagSWqjFbDsOchS4/CsYmu7UKDf+CS024rZ
gE7BAC67ZhOA2rURjUnX/rDzzjg5Ilr0msuifnQ11Q/0T8KPBkhsE3jtJZMLJzclxn5kOaZnqfEN
1UsB4vOWmnP8vUkYZOpO7LnFFQIpxzeuJ4V3kUYB/ZieJlEt0cywlOkDWzxCubQjq9zu6g40YFio
TTmywtarH2B6YX5Om33Ia2P7QCuYLoJ9RDvCW6ZLk3YWk7FB4RCBU27evRjWhZXhT4LBNuO1nEoh
UgObToSEiVrSTc3tfsUoXUzRifMgg1kRbVL2fKcndxgHyLWK3IqdwYxMwW2/vDZsXP3LwMZ74Xb9
l7ULaxmN4uUgZ7eYgU57vvhe2Tt9uzsFwI4ypAjjukaM12PWfAdHyBA8m/aCYBCxyiUisBtEXYK/
wDYOHMaiZlSh1l/5bLbUshBn3oD/oQbYYhb6byVz+PDHDxl3sGi81GbhfhgApIywMqMJEcNP/i5y
jm7t+4W7sBYq0xLE6v5Tf4lC0NUB7m02D9VgYshEoJM90XWockjWoN/5D02G8fRa3QkYS4gaiMtm
TqfCrhZdW3H+RX+6hfURmw4ZiI62+bkLkLEN5ZCE8/3Yz/iIsVqqd9o0uFLGQuPcxqs/o32z6uQ2
skNqfJaasBDfCC5BlT2hN7K0RswhJWpESyHLv6ECm3CrqR3maAgh/Myd4JpFScgBM1uItQRt1YEO
GH6WL3OGGxPj7z9+rsA35K0+hjLaDVp2ykRO16Ydt9rTYCZI81YkegnHqpsc6hznuq9l0cawIBc+
+kpDTry5v3eaPx6j0PxTJxQytgtsFFHnoC51yGpH6Gx3YrinfqWYC5vsE+FxrXCk5eYI+X+Fy59g
GGeIm5fZXo9Ed8dZDhnqujbDfFNtKIizZsZY2F2XXeRt1e8fNJAcmH3uPRCnLvZXgoW6+CsEM5yz
jK/DFdPIkNb/8rzN8m043yp9Btk4Iic75agA5LMdRjn8CzDo3iPxu36T11abiGiqTp5iU+/OQUUX
WStBw6PouNV6VDvFsDolCcfn4gumqhC/pbfQqOoY4p188M/KSptgpQ664TvjFrXB6FYLCDJc+TzI
CoC2r5Jaxcejrq/avIUlfOz7e9k0Vw1vXOZnLvJ54mHsqlJbHw/PN1KM6XxqOgAMAi8Xs0aIE4DE
25PLz6tBczoj8z/go+p9TgDAPZMng4hiTwHQ24M6m3p1arYbzo/QCQpk+r5NzCQctZyEEq0DOcU6
p0NMRBMve68n5sxDggXsfYH/WP8mPOLQoptoR73VKK6lTSGQM/xI6+I8s8yQkLeN8SrIARNXveO+
aPiFjGFe5FpNJhi8IC70sK++6ExPxbIu2HNiKro+dMT5329ziz5SDf196ra3DnygIHxHfTdNdjzq
FcHWM0nyTQk3Dld5euD3C30Z3SfbmmQ1nyUswQ4uB/aUM8SItdxXRKpAFKdjh8kXIwnzkePnbqtu
QufIEzBdrLpVlItdhm8LhHCLyduRSH0qGOesjFilaipx6KhEHGUqFyMqEr0bZY4hVrQJ8m9t777J
qmyu8zRCmSGy7aWE00PV61lWEws3UnDSJMFLCOMY807YhmEZvc4nQsaUGtWDtDgrYdyOO5ub6qKV
3wuGE92CQW/Gkg6+I2oOVDhJS6qiaLOnmPo3rirAm/0CPKMHFmYSf5TDH8TgoWv74OvL3CkP3Gsb
bI/0+adEnoqOTRx/+z7dii3qUtf3kcsau/XOu3gz2XBkarPOTwgHGkqtzUZCQ/58qKIqvvnalY40
RFPpeiRpzs3Y/KECLrNXHZxMhE9SHXaoSWpe4PiczSPK6k6r0WCKCSOrwSTBb+u/wAXTvUjQY16b
4xFK4lSnlutR7WVYfoVsREKZIqVO4u0PFWl06B68whITcA7PwTuubt+ZBocdfqIEwE9yxbnd0s1k
miO6UB90jN57wVTgeRSIB2fLbTv/S7FxZaRmfAbZy1Irg5dPc8ZVMQhVnSohlmGTCkUzbIEg9jD2
EW7W3YVk9h0sWdD+oBm/la/4mFFlAELzLpGPeGxwpcLAu5RLFCOCgGk7VpRIWUZ0B8dA+Ue/zsz0
Nfn6xkpwXv4UeSX73GVJcinMK58k/RlTyR97bSTk8aqK1DE9Sbpd6iik0Ll+02C9GPPS0v84XL6Z
3YGlWxDLv6k0Mbsd1+gOAcULjwd1PAi4CzxDM2jxsoxyPWKFn7DcnYWxW+0IX1I2Sq0dO2l7LaT8
jyxoWRMG1rQvQMoOin220Pdh00QR2BokcKNC0C1Uu2Y8HqZTdJmQ/aNPVb0PJaLaGioPWMIyqpMz
K2TJzAfU0AkC6LDKstc9wU4IxZYFVLU319XT3fgHDTOfOv4pQYb7Z3ZOlv+xBWASHVGG48Kxk8rJ
RRQ2lc2mXq7S2dw7IzGbVi/HjftUAzMmaMzrieG3+y7R/mYqy0tFwgEHTdgC3cZ8nPjvcBTNWnw/
rJyXEPY5tzvhGDg/NYpt23SXuMvdfqhVNb39OwOl2ZjjHEcBRVn2B2kEjX/MqLu2VWL3IbJGyymA
8Xu+WL6NrC5eB7Uh9qu3wOE3x2pR+JNgWI8GwuWH8N4ikzi+/mqYnvXQ9Z+rPry4PrQMJsHnA94F
usP7JSeM2uOH5kbZnvuNc+tNtSvv9lHTK7oafejfyIq7dwQKQbn+TH44sVD5U+fsGEDR/oO3i0kF
ulNNNuGGlDgdmrzmcEsf/QOcRrh56eoNGFCn5v4G3esmptQbSK8VSJVKifa8zE13fEM/KAQ06RAM
qs1xcCpQ6rPvvKowxEJDQdduPBJF5eJDseE+xvSFy6I6aEWhvZbY8aVnne3uYs5e6pw8Urop7nEJ
rb/tEhgLPwG3OlNnUFQXSLq+yRla3px35ZpDDgTTOOQodErhI4xnHEyDwUlwrAfC3tts8QwynCnX
hdpl/Qky5V1N7Gx2a+tpqIn9TqmyqZ3zrNFtu0GTlVZiQNm0etmeBjLR6Si1DcVyxjPBZDr8WlWw
BWiFUlAnYhP7zE9xiHgyB2CQOU43OLGhRG5PMARh44B+FM/vBsoVqKMtIBjfL3UKfhFRVesanWwC
9RKzHtiltaDuGKvH0EOcoBGzo7SELSDeXD8PQvbQt/vLOkbcJC3TDqAZ7maH4+A1m0dfTgPKw2Rv
IgNmOCavJNPLO58w9oToq8v1Q6zN07vqb0Bh74m5Zj3Maal2wCSyKqJpB+JTi/V2MteFA23p+8iR
Sls3DkjkPNWBkIeM0QKPsF9PHeEPm7XInNRvd6ixK52sQQ9d+771SYPVrDQLCAbwUFEChPyCGw9X
+f2AVRv0GbKG4shleAgt6DvF7k0R4bVhfF/+LV6+L0uqVdtUMcPDZPssZ/1ltxkmWnSYYTB+jTjl
1tBgF0RB8QQlYyqXMiDVAj1GL0fwAJYsgvrCXEO04NIPUEHEILE8NjQ9Thx3jVWXeV4kfXzFNXsV
fqm7px2x5Y5Mtv9Lqty41X0l+HE41jABrgax/x9WaxF/PcsPEHvcSXP1Xm5m4g30F+rfiolY26bx
5gXPQnJM9SHGBVBD1gE4f2t+R5OBEYlNMLwj2l5CB/8AqVmJbd2bj/glPYiT7MQ0q8hFNh8uTMBD
H62fNwtS4UZgwKbIhNDyAmJVlJ9gpjMwY8uhD7TMV3LE8c+s6dQgqMdh7r5JzRsFNkML3PN7sEjk
X7LkBo8UG4bmLNINil3KXChiax2lfyljAVULIG4+FvDa4DpdVg1y5JukHHIQP52tGjt1bjcX1bKR
hrdoO8Z/g+Hj0w28nzE3xO1FUgYGF1PdM5Tq7we8gsoZsH+/ybqnLvP5MPjtSb4afj42TiRIA0O9
YsxIEV4N5oyTPLlQjoPtLQAcT0rc+pWAgvu14ckwwmCIGYz6qfbVDbGeRNFPkU6j/UDbK09GSVEp
awGlo7n5IWnLKFY0qzXjx7G45tbE+yW0i2olz+KKFbwYpUPr/7oXOOsqW2Fl8vPnKwL9AMKFED9I
X/vBOtC0WpDBT2ysdQPgL1IWpzDLUAgTvaYpDiYfgoc03dLEroOOErva5qNK4jMb3LkHIP4gzoxD
fPanKWJ0s/fklzVmf5bft9hWdoYs7747+KEmO/ldQhLLAzkXjt6PcBjPOMZsrDOfPP4DJSbQ7PLA
lOvJkuP/FUqGvZru3+/YspKu6RNBDQWGPQtvG5ABzNVQ7Ql9D+5AU/WvsxtKW9bpc7tb308mecVh
4xmuQUYd7zF4ZFDk+NDRbrkv+voeWZEexOnzObkWyTnknvMs+k3liOkNLQVBLmHLFbPsRit5sTpM
DTTaG9bg6q/E/LlYXVRk0NsD57W43uFqX8L6AYOOcjRfI6+TaMq721b3S8uZzPHoK7D+pTc0I0Y4
V1DNJcLIn7t3O28gAQo8cASY7b3Bfs3oJhIQVwgb8FT1ninO4Ivpgx7jmREDKPwll3kLfbiCgtqJ
EduUgDW6ro+YonDMzX2r7W0ohFHSBrIAYWsU6LYpTsJ6D/hldNzTUBa7UTpT4Xazf3KsHkqeHMnm
Yyd2u5tp44K2H76ushZ5flGj2j6v4UOhWDmMEi30MmSeIs1Npf4JTlcXoQuHph3xQL3VHiF2G5D9
7fITQzdgqMjz9v02IRQmHMymVim99xghPm4qjkJHj8+Rby+LW/BopY7NiORuQBLgDJKnIiBHYSow
C4X4ZbCekNBs36pwwDRI4t9PVscC+E72KWVe7GE921LYQgjCGsGQaiRb2iUgEI875A4FbmCxIlIp
MHOupuzeoyW7wq3pfFtbOqWF0SV1ZbJxNKZZmwHpfeFMQwnC1C2h2EGtB5wmHNQpXuS8Hdn+WrKR
YzUpR5JHtfdmWIqsVe4ZKVnDOcTPuM3y26DePIPZfDTogxbU3acYBmGqqdKenvTcJx96NlaZyzFK
PIYGU3DVU6NwH7K2/4saQTNqn56RBo2jBL2HCO9YVa9I5wwnSVYNXsaps3So5FuDHz5qqk++N/T2
KclA5Y9tY92LxOj6ScktV6gplX5ybE33UKYDA9kBK10hr2Z8o4Uqg/C0bWgjDvod4Nn9Tiw4c2Nd
9e9GV/XUxv1KDLT9bgfPXUUMnZWc/N/BO3rTDi6gxKoEDkraSrGFbF7iaUV5yjr+tNnL75AF5vuY
fPDlkJ4342ZEdcRwrymjf1KDzxcqD1+lxU1yyoMaHvKy4mkMsG5dZF9e3sIgccOHkjOcm54ZKGMX
JS1m9Ak0NTt4Cr63f5WJqvyL+neJcE9F+vZNBgYi1lyBYP5k7J0vW9J7GCqjyAplM3vxqrnvQkiW
/L4f/AEXLAOIjrl30Bb5ocJ6AIdF9kGVUcOGoJvTugO9rVOyJhww7Hyn6zeQHH5nhR+v0h7vAtxM
oxnW1uXS7O1PpVWu+jf8ptBPmowUgi77Fw+EKCeunUttG/BK8UyZwNKWJ878w1E0FA669AgVkAl0
1psEwS/7vQAdJGOzEH1ygideY/Ah+nGeGQpePjDDC38OE6eQSlB7yX4RuHxLEeVukSlp7K+ZCKYB
FVSFH5kil5X8HarO923F+50WsSfSEYvmc/or0zRmdPviYSez7zPHi5kPb5m8wizxA/rhxH0fUMEF
3zQ3jYRB37Q5kMr6DSy5IjWCM7W9racTclAFDCDxqfKx/mTDxSKhu20PC2ZhuOiEca1o3W4wKxix
Bwqt/Gk7a7hGrcqT5pJ3fQ1NoX2E5MBHDumu5Xx0JuXulvpqSFKVBukqL1LLppxmPNdg5v6IjsP0
u4nprDZxV0pEDHJ2cNuLjAVdpWEgdWfNM7i2ngwAxMYnvA6q206FBpyv4HOlbKhHtMeh6ocZkUw/
EvWbhPNOJTuVGI6sslEXKxaPF7D3jppIOgu3Db5nSxEdN0leQNsH5/SGO6XVdncXIw2KjvADoIqI
/Q5Uked/IU+aBIhNyLAnRRlFxYO756+gu7YoRbTuC+rumKfBu4iDw8bB0ojmTjQU5hI1RH7ei6tI
frgIwopRvNugRLx1k+cLsvzN41xN12N7hphwt894lczvWt0VTfu6+fDrGT8Y+ENdrqn0z45S1eV4
+H3ihwkbkMjKJkQCLb290o7fvEJ3QCtcqyJiLrzRs6reaCw9kgjct+0zxOtzbrL9VzyO59pcp/2S
waTPfTehNyBC/YDxygmAYTwnotALfL6RuAYQ0dgSqzurRiar0pEwAlrx9sy6XdDiP1FjDzxQZydN
xQadbsj0y2bwf4GOKoeysCMkxyoCeZ/OADt1jQAMTNA28bWh3lJcPH5DU4daETxgFQILE7RXoiob
AjjVuN4w3tMjpG1UMXwBGdDA6PGWcOGLFqWzp8tXZvia9Ekhn5VDWSmimxT7KeNRH6hbgbk+8bs5
yOkTRDW7LOwvVzltOm71w+SJjPRdAyRBGHWcbj0LmJGtXdLrjVSN+XS/0jxh03YKabnoqciHSrHs
x3US77p4Au5M0n1cgS0hodPHmJYONmmYfDObkwh/hxA4Xdk8kfE6JS4kl7mqUF+tKPtiR6gY6KpD
oolTtnlU6YzI+uIU4ow2MkZT42iDOS/25WQZ/8kfe/AUzUuD9lKiJMQu0p+r+cwhpuW+M4Rt36cA
3pYhq1WS6OS/kRcAfGg7CklWS+A+5/KaCw8f0RV/kmtoaxGd958JGBTzDnK1moQ327+ShebS1EqL
Q5at+6A4cP3iBmJptIgGt9/pPtdSOi2z51iM686KacSMdHU+7TvqlIl3q552gdCcMdRsR/9HBxoA
Bj4aq4kFdW5fQ4DUWctwaas70dfoM3NPD+CP50VphrbwHqVDSVURBW5+sRFFvJIA1BZK3F+JVj+e
JL+nd+FFSKA8W2Co4OET5dcdRgsSXkp1+/GmskpAw7jdeYuBLpCjYtS/dMMhrX6Z+ARaz2kqbGnh
0W8xq1Kk/KQGfbuQ8yX+DbeKLIjGIe2sGZweIbpYzu68/ize5mAwFrXUG6M707U4qPqnHTYrv+vJ
blBG+T0xXRjfRsV1Qvc974isGh3ttkfZKvwAU/lms/Xk3av86y03Go0Y7/84QdVdbAvXU9Fm/O1T
+rJAA/2Q0XQotPo5Jn/7/pn0Hej3UWGOU/teUHSE+5SmVc0zqv53sEYq7sKbwlpb8LzDR6yatMEb
BuEHRJHJDRvDKZHVboB1Jl3TP6M6c3CvlO5xEUkqdq7qsUzhrgN9Neyd3vxbE5CH6tzlNMr8kIs7
a+q+Uuu6p239fpQ3S0dl1cZddd8SfK6qjemuiTNeIOfKAsjEfL9OMB0UZw7KfmbduN6IxlgCCTQt
H+NxxtVOYwl2QOIzVP1CT3xAI8J+94gfFcqrNqK+GF6VU1M68wIZn2VK2ggBmVOZSrvnjKD5c7R5
tsajqZACTrvoKH6PrsjE6/Y3OizBiDVZrxinCv02a+qz6cSWHWJpoyKDPQ79yGBlpQ/w+q4tvfV/
DpA3+RitNDzyDxisFeH+EGkTQaFn8S9EHG/dmabumiYddHiLzPAugcJo+VJkQgojUhBwXPeOf4ng
fkHnL9D2/ymqNy8FB+w1AMaxk8BHtsZYn68hy3gqm0dRf/EZQzXUJNNweO4Z7zEiPbxfXpnAolDh
2AtlEYLfGSrl/Y2/SPlYAdsvvDGSF/r3G9KLc+dOCFsnig7+qEsLFxPKJk0xQiKsmFyo7VLHOXmp
G7QWrVWs7c5CbZU25rS56bpVBEqD3L4epz1SYxCv/ZSrrOc6s17hVkUEXgLzy46FcKCzUIhTahdj
efgXIzSJMoKc4zCze6TpAytrXwxXASmOvdE8DSl7WSUJXLdGJ9gv0DLzMwvEN8mcz0C3B970Q1Oo
p9oqTRdtvWd6Z3gURT0OxNf9qw1W86Hc4K0/0FYj9QSHTaepRVyUCQCO5iPbesoEAEiwuxG5stso
SjexgG/ebitn/lXeYlCBpHQo/cXq2GqzW5skc+ZWwoeq2JhHFT07ghIan6JeHspGiZz/hX4layu1
CCZTomIyBPP3nM/8AOJGSBugjiNUNy90Sa8HQgjFO7p568fYlJIOTMhHRndEMLBcPWa3Rg0wQnPg
+wyWgQwFRXjUnOTSZiolt1sbmcPt5lHbaneow5m2ed7YDuTKOPJvIsFDMWXc1bK3imWwDTZEGZ2j
C1F5F5AdPraiHO/dFg5NNE70KxONhpY+BzohQC0WM488TPcOGKoBIXDQvlPpqWwpbZJZnoLyjuPD
jEkkF+QriELna2ojstC9h65Jf3uwWAPVzXruiJIlJ0F7hPvV9aG7uAlLhdQh3aaO46H5U7tllK12
r2hqabs0gFyG+Vr0EE4R8O9xZXcl+0ekjFpg7oaC24IkP5zkVoXL6G4nech4+pyDuO2D8o08G0jO
ksbjIFIIggnf28RHD4s6SMgLdqvJY9ebNzhQ0uW9L9LHLBBj0Exh2B7DOFg6Y3KTHkK2+XbsTq0M
n37nhByiV/P1zRKT70AqpyBIlibPaeYLZdLM45PlMMR/6AgKtnLhEWCt/cIQc72QYEadbQMsZFeK
PM0ZjLShiepzZ19z2GcOHEo+BM5z6RZjXHl1DwIzjNgkGxjnxFIJ/bVdswQl75fXzenGou5/YG/R
t0YwRnkrls32zzuHTwwO1GdiHxuGvXtnqyXJdk72biYf76twi2KzL7cbbuWFuRqlFGoMmB4gnoO3
Tot+6rmC3c/7us5NyBvXjSwAIg7jN6o463qgPf5HU6tr704WCckKw7NfZMOrEbr+DY7pCtUERIO4
kZAhDB6hP0mukfIlr0+d4nBs4glzUSrlDw8MnTBtsIdwCGSZfA55M81ZSab6HzN40cnN3tNrYVOy
5CZK9JSTOoHUnDsMn+nHrCiJC/jgFzb8Lb1YZB2ANYC1ba0RLnQ5YjLaflniQPKq0advSJi4NgqG
Vrlevyh0ByRtVp6kcwXvEwNekdgsrPZEHoST2ltji82DD/loLAspokY0pAhqBPbmVFcWHm6fzmW1
nO5YCV+18Rob1K2yRfigxnhmefqti1sgpksPnnBuRitfMJ6BFl6bMM74rPwG4hyWicrsXthRLXnz
z3muQwzPm+gCGCnwhvsKL1Yo2bWUBXOYEA7vaWazE2Q87rzkl5rcW7+OriLqWFJwSWQXaFdLuwwq
FF50lJqHfaZF9oNjgi4GL+elwrDUOt8jLn4rAX5ksE5d98WIlruC7v09BeL1xiu5v8lkP8t7h8fa
d2K5sdu8hU9x3mwAet2ZfNJIcAjZpxHwK4JwO1N/KcliSJW6Akge6A+DcGlrlyWUsHbCOqik2xoW
7xiztu2X31SZHLovWy3Hg1PnEYOAI5l1BoDI+LEreiOSb5m7WzMtae60IgRvyCxu/WT5DYe8w62n
reD3DlbtmbRz4jZnSwEttHq193wez+cQx2Oy38vzOpKWe+i9YXP+lobD8S+eCHLDRpMH7dXdMmcK
AGtuTvByTeNureCGg+1cOw5CVkjVHkNeKR2bpNJ+xy6tzmZW+6HDSlHqnBI+WTWEwt4d35BmZWww
M7eT14kSriVPxK2/2DTt/lNP0fqj7oJCkzb0DZzjyiRk2x7xXtxavGGwQkz5ZyP28Qe95JbEXAtb
EQFskOzk1/znQxb1KoVdLzZ1z7wgeddzTsYEHfqz6Z5V7BWDiSNf7c7RTwPzOMV9YSZw8UqBFQj1
3QkQCTlQ5hmij4VjcitXp1z4tTboC25PD3Ss0mWYptz5ayH02aNnx8Ru4sOejqBuzhX61ZzxPuWn
JucWGkqru6fVsjuTaMZbw6Mc6pt1lr1qtHHoTD0+EqHekDWWH1PbJIpkvW/LxAC+REFAXGO6Nq4V
O+/v0N0Dq6sEDSyLWWeS3RPS2BNEzRF4QVV+a1qruP12d6CedD5p2FMh1QwNRdyd7bU1wcexB7Sw
i6eZy3lJ42bnj5HuBIaan9vgHpa3Fi4Q9mMgykM/wCd26XAKbODOiEoJpRxwRo2+qgzaWHXHq++u
TfzVX/RjFUAkFA1t/k1NFnYjhPctUcJnde6C5m4g7nGnQ005ZwTHkQaxTt0/XDhIbaiEsRRlrTfu
reTcow5g5hEf52w9cywP0LrO5VJIlV+mzp+Cz1C9dbDqIGnvW/6pqLe19aTkR8cjih1fMIc/QVEZ
cFPI8H1WjBHLAeyWY4EOHRTdhhxTk0/49yE9MtH4nb7jCB5Mg5Go9zhoLDi0fq3D02EZpOCUJVIh
VdGmQHEdHaBOEa/U7Bz0BmfbjsVwnockiSiCtEdyFwmktLY2RTP9JCmtfmttq3DqwfFnQcuuTZpE
SqzogRO9TCTIw+7Hq7VANkTxbnNdZj2Qga8ambQWAujBYr9AsWNI7VTjElVTL7dxazYQr0x5P6ii
MpTgX40qY1oeDOnqBxyZnN9wM6NLMQCFLmJJh4MS5Z53lbs0NbduBi48vP7ZTPDm+MSq4iFrBzWC
HSJHGx0BRrh281U3r44jdT+bsXd4O2vaTw1amfx8KtwlQH+nDFG6XBy668TGBXsntcDoH1ABT2Ud
FbKtuHUyrsT+j/62I0iDTIygYbv6bnrYPbWD+Rb6ed0ldNfkWK5Jn5YRmeHy/F93t1YcZoUHwa4V
VDnM+Di9Dk50sImfT0UI0lXKBP5ZT/j2ENxXROxdQ60gLv7vS+2PnFBA3q5V5ZtrUWtsDbHnTE1I
Sex5EVCUbS9o9/gCN3lmiBt6OWEKCoj5km/nByUpQVWP+p3EFcAWiJZl9dZKxU06S4tG7vSdIDxa
qzy/DvPdN73P4x8jrwWeOzsgUwYFIc5UgneTSOqQr1BtaAQZgcEe089TGGL9OCLcB/cuvGTqiqcs
fCAa9RwFky5LcuSGIpVtw9nCPnp2cQfE33oYmSpGmj+9lDxq+Z3vsML5IcgjAhVGiRw+jhrCnvhu
EyK58o9l7UAQ+QRrlXBEX0rs93c9FbLylDW9h/GKVi2maRuHkmgYwgMojmL9gDjvR0TXrO7Nm+v7
M/zdWW9v3buhi2//6oYWNa0/I9MzCKbgdJiLrJ3GBkYnmohdaPBurAP/qBoR2OkIbxTSsSicwA09
6vn7Z0z3GJIyOkRc3yAHy20V6VZO4794HiclLZNCEdrnAtDCriPZSeyW7fqzmHScU8SlAlAk1Ey8
2CgU9rPFWZQ/V1UYqFgpMkZPWMHKGRJkaAP8MudqDl44DLwzCWrSTm50/R88skUsDuXYvZ2HmQPy
CbdmATq68GJAEICBTPq4Q2UWWJ0AIsZszp5jP9rG9xlImv/RCwkf5qlybRPC2t16HYb51cMyDHOh
rJw0ckYU+fTitQDaoKnkcXzUMuZ12ksk7pwHgLYSRmmWpEzpPAQuO5M81hsa3fG3iftvi1jlCXp9
fzmPOOBm8dElubphjutCv5WLWbD5eG31Qo6oGnqvs94n2cbtZMrDbi1EbW+om+ieQWKVXKHWqR1z
AWPUL4nFG7oL3neli7Lj+UNfjZ5r3l5Rk0bFHt2FANT8NNpBvpWmEjv7HMo/b3hfFrffJpehh5WP
SJbqS10K3WKxpCOtqq5VvH5tv+UGFRyN4oNcDkJZhQjYRyRq4WpcemYron8bNkNp94jRqHlMdpmn
GvBsMsbBG7W6nyLRk0+YbUMW9Kqks0JVn0jbkvTwpl/so1FTcc42HFuqXk6q04fjr/dF6gZvKLwd
QnGtZ9+Cs9Ts8zvyBZCXBvLYvh7D1JbjM/jy1rIVP24qRiIG1jTyzUyBgPTEa8XGMoHEmlz/95Nd
CWUPvixDC2YX6M8PIaicn4FjGNISATulyXRYg6frlSnH+j3o0yZxX/4PwNaOkT8S2NmpeaOg1DA/
j0P0+41LVftFUg/fZfy5Z6s9JAkEJOOwiNh/PPvInZ5oiUMcp/O38zyfkVMBZNwhnnTS47869tnZ
O3s4EPM6R1twQO65ucpxoGJJas35JgzYCXJrNtKaCbHRxLzlAUWlEUJc0EXCZRnjQNYZE3P2W8ur
8M3NuUxG9mziIH/k9Jbq0niXseWscmtXMXOh3gFI77B+mDiD+ukL0q0lWUNK+dr/mZ/hyxZxzjAb
mJqkBzIv5HnQ6he7jKVV/4CEU4lc0xh0qc/54ENDaz4jf3xzzUenKTTcAmTG5tF90CBnTuZt59nU
zCEDe/Dep24yjPvtvwjsukYSjjR8M9NIKH7vu+kc7tfqBXjBXInHlQaWQ4czd0cle+FpPQyZjdKE
0zJH1P12ENg4BvJBLnJ7sjSEtEQJPmtErEJok0trBNQZJfDR7SXIQstqoh6m7fbns55PrZb6xDWi
HbKDSEiJD62u5CL5MbPcIBfpVGUSELGBi+Gw3jb9zoQ82z+mubFZ2tD/FhmQRruVr4qHXfgYoiM7
+cHTiVpBBOdRB/ajD+c7aCSlbQ4F3hBqbNw+vuNXyxdB5VhNeTrPkYFlMkbuIZ6O61B+Srq4Sk3z
oiIRJTfK8tqiIwKclP0lcWJ2JT8uUBOvcA4hOKne9YYC0GxXvZklif0fxuqZKQdWdh3jjsivyCk/
jnk9HTPKCQ+UfrGzy1L3SJFTqCwcVbd+0sZkdGFQN5fs12ndfrUgG8zQW9v+G1IhzW5EzwwaFhH8
Iinwjp5Q1w1C8SMCoqHda9xtle0wOMStyAFv2lND4QnnhBIhomc0t3tKEd6XoUn8yXfaGZGUbDtK
mMNzGMGenxLQcwvAQeSbkZIH6CLpYaJoPutxDXI+biM7YGNFjCEQ0vdl5tvzWnRBkTx8VatBrWBS
0ekYz/Al6dwpLIy7pwTn/Dsiy5qEBG17SfM6IcuCLagt1IJXKsBY5ZQ2vzNC2maFzivihA/BxOVl
qntoQJW+VrW0uHsC4MgjaZZBqrSiWVXfRrI6KoulHKwsWp4FlhJio48nbFFWjvqPeyqprOyF1XHH
i/d82K60o4JUA7Syw5TMGZTlZ/ir3gLWPOGIZ4X2mUAMXDePmyAHQUSdWb8zejEUVVllaNEIoQeD
+C9mO25FF6WfzuFkbbzhkmAvjMy84uNOVJNfC6n3oA0rTWoliPt/ke8Ouv3YehtEhx4bwuFt6dEe
JXvFvlbJL9koMUJ14htlz39yrPfw8dyxRl+lgJIVQh53kXsXgzj1mYqCFrx2BZRfpXvEbvETCVWf
BDWwpMekxjADxvNOnLN3cQHNwwH0GTZDKwn0ZE1ms0xCII1y7hEi+6rbxevLFL0dOfZyPCvc4l5U
JNwCdwWuru/XlwGrFva/loDsXeqUb9h8Kd5X1LIzXw5UkidYbBmUDI3Ne4C3kDMD6LCPzZ9T2bTI
c6GxvQtUg4eCk5XrnHL7WEXCnXXMcyCyba6bHn8NRkYWevtn8DzoTSRW6xdKFWer8Z+30G7jIAaC
b0jrqRlsY55KO2LAehOiSWOynCNwcwlZhBHIW3x3i4Z9DsGzWbDvt5DKO2g3xitXHplbWLPQrgDa
e/1iJwfp4UhmOTDiYHhwIff39Cbgi3qcpllg3+Z/qVcbfsQfcSIelwab+SCNou7A3ujtQcmFYO7q
RT2Qq40MseKQXfeCp8FAZSLWeluWwyKOUyLUS87T/YLkHmSuSRWRjjYPONhTrQ3J0OO0Zi5HtgeK
9HwBax33ngpQq2fHnP3a4rJolxYNsCDxYo4rFge32SHmfnpPOkCy2Cy3CcLFIRwqMUMBHiHeTzvI
v+G9acXWiGoemvJU1Nq0S8/nsbeAr19osNjZ2GCqxZjh9A2iV1YadQ3anfh/sP0kjrxXSY6telT/
puw0pYndneBFDk79OtQafI7rOVLexyRj2N9rrghaU45kaUTptzPVmpyuZdfmRwXrxL0XqiXr3L8R
w1D499owLDTdVCLNKKq06WmtyAvirWdcRELJupQkVLbZc3oTAF+yEPVN30ZnEvPyRcdVUYY2oUns
kWsriyYdmGtVU1GDiTetN7X4dgD9nCFQl1CoHOXlQlT0D6o2Fnuvn3YQTHhPnQm1W3X0BNsxlb3g
DNWSZ52hli66py6mmTb+ChS7XS8alf0JFeK1DARo39BK7IttbZTv7yiDJkzPQ7EZWdVaHGAlLwZr
fq4i2XEZhWswBIXGdr8MNDq1tCbanIW1N2XTaYOD3XmX2vk8yxB/N1/uOcDqtbp7694N/IiapLaT
BwOC/1XYmGPEfQ5awLl68lVqdGl2WBwKUDKuPhUBZa46H+xqo4y6wBlQQvRKn0/uWshlCMwS/2in
fk+FypnF7wvug5lYvylNFDNCaw6A5tAbTI3Y9oJbfHC6stfCUYudhcYHGd6LFjgOQOm6DyQIX7mV
LeqUcqqGXYrGeeG7ORyKgIdJV4Oi3b6JsQl2HBIZy60Y1IwvS1Td8HBneMkL76LEZBgUp+yEaZfu
EEHv5Rm10g2GQTdnI1/pAzseC8/wDZTgcVS5NjK4ceeuT+wGROnscQULUlik+1VXWzeYM7CQJIaH
4eQr8mktvr9TcdEq3ywMcX0zQ2w6hdEjPfSnhqQPOcE5FGkvUUb80TarGVvVU0IpLvOS3kCEAu3N
oZzIidTjgshj6DAbOvmfJAUFcYn5P9VbvlDgnPBS1RanOHc9/2KLF5kQzFax1XeefAI0kIqUenGR
ZUEXdWsYt8hOCsQdORNf5pLCG2DakSEoAcXVLXoWWIq0//eTpglGvOr/+urQcP7qQy2HpCjYhr63
TaC4+Okec3c2Gn8Nbqb97WYz2lZiGnswCJkvq5i1tjxu/rjaW87jLBPqmAH8tTvr8JhqbAnDAlNF
3/kYRnF09CjBZHg27WRDixopCywpNPuSrY6QzSXrN1mimGe9qyd3UGhaohvaQRMJoIECnULkKmtQ
MtqlhKshLm5CnXR9l8MULIpZX27VF67WaSXNTEXqVVYUJBCE9O9jm9DuoETllEDNnmXpvf4eicOG
GHisUst2poUFLXCCh4/gm8lCE7qA1q6g/6dnnh0MwkC1d/mdEzyceQmUJ96KOzlJMvLQU81NklP7
zg4w9/u0lbH0hdhJms4FvrHfu0YIF8EsC23wZyHB5RhUfWV1ZzVrcnk4KILRy9ypRSfPyFyIj9MF
NPNpZ+Av2xnAyRVw9+GmQ+jygGmFw8lr+Zi1KqB+jrR5kifX5lD/2oYofhXCrHh3N87yPobPnUEV
b3hGJa5Oko/tI1v4bCvnhN0im0xhZ5HgfWk/sFBRhTphShCWm4gMLGKJZ6qBqBrjarbEFzU/l61Y
oqRk0qxcBbolH3RGxWXYgcvDjGu9pSHDt4zNJPItepg8li3zlKc3st9iglh18fuMJlLPiYIf5/gn
Ru6f1VjwgSCfdxToE4D8UMA1y/f3/BYaznxhOi3EiTyebThl+JqXal1jho0gLSH4TdEctqKqdjC4
NKeDyBWLtNvu+lzRf567ciMyT6AXLwApdFgKJeHTT3bgRkAE/3p++Y9MqbDOL1FkZYE8TF/VjYWA
kgSTY3tyxEnvt7Jj3l9eYgZm7SJwfQCLJuv/BjYPefTPnm3eSnfd7rgXuckZMxNphPQKaRO6pk96
PJn0M4nKcyI5/mADFMqw3L9VUJ7lizatLhF7ouB0D2Bb9qWP4Rz3aGYOjMrK+6dPCSxPDJexYjGP
eismrkqwElJkxU0RtG5eSqKHleFEJ7jf/g6b9mDBCG2r68d4kyhLw2gPrstwwAa2Eq4fDpLxzsgS
Xv8eLH21L39gvcIRjtlCNJj6iJzXu4LiBY7BmCTpYtX87qfL/ORHU6yP1J+OCj9+z8sOXbfrVMoA
5odRIZw+Y/9IeQ23WpJFf2w8E32Di4+I4Ln0Aj8LEVMEhJ6LBQTNvfNr8//1zF799HmqClbw2Rx/
iIABB3C7YJQPGEcj/k/VfFkhw/N8rvJgQuovrwrHia2cneB1WlXbyRPQYfujLKVzKQkvfPTaRHXY
zh+1F4LJAfZj303k4sZGqvD7MLYKRYV7mXUmr7Uwihjg1wtZtKwdgqehnGhl4nZuV2FRrL66peyf
rBPBCoJ0JyU+ZgU5PctkjtGAI+YCffXbOYanxm35TPNs1BL0eHMYWxY2IJihj83PjOa7TCVP+MOl
jA1+RkBjf9xnIuagQEQKmAU2pclEEFOPcfhHarpqxaf6aL8dT7FfWImCk5F6BYFV8KFLkcYE3WTT
qAha/KLXeZ76iKG7bLuHphLAHPWbVPWTLxHlvALX5PoMr5XKG2jsUTkRZF/t9RaYzIMyualiZwIv
8nS+V161CPdFixCmY7TV7vscg3iePXSJf07V6QjINUiRUvOMaORuNtSwbKXFPuTcE6Ac2iyJCrz0
/TGGcL1G45+E/RtzXhOze3wHxj+e3dnS5SDTFTpTAXZ1OQhrAnL832toIV04sLRh4rEnetrDwaIH
IHrMfam3pcDAe9j5Pl1uWyWtk0ufFBmwpCxpw7QF3wLFc66gKvMrd3el3IDKYsWrJU44pPCOfAlm
8TPqF3BcF37bIzmB1+N52WFXMzr4THD7VW9vU3yGv5meCyXVuDBj5cKpIMBDO/f8niytmafNCSnt
FUN8Yaa3nhzFBQzeCOiZ/6vkbqyZpYGUrMfSVoVceOnA87atp1e4YQOBXRH9tO753DB4lofQGM2p
BR6HlWcDZfSPmqFLbU8+aOAplkimYSbIQ1Ty4XSIU24V/swSrkw6e31PYHu2dGeM5CzL1z0qQMRl
C5UNgvAgeISYRXmsz6kIz9yuyaA33Dxvpv0Uz4n8WUmuDFkxZEycwPA4kaQL3OfIZcqot+9W2Pdo
6PGdeHDZOlcTC7arCi0FbtuUekCYgU5G44ZlHZEG+oBhX5NcAzUsj5fbUY0OG0cHsVgHlrDehE+U
CfC+hcYKTGhCRgjwivFaOiY/JyjlSeEYRTv2GbAEEVvPNQwepCJV5xvNqMqvarcj/bqtrXoXjIhl
N2mdd5Nz09Bv4rRSEwh6WcgzK/z39O/HBtGqR/exy0PovuGXLRkQlrc0GVnPVCQB0o1CFAL3C4EM
kfoWuKvX5zeFIHmZTonyutbIyS1xIvspEhKm4n2IHhJ8USTqpkI67FK8RHRcGnTbt51m+ycV4ImM
8csU/Q+YVa/fdIbREWGHWcTq9FLUDemh+yW1sbeYrClkwK4owecqmVYSn4alb+sFilk/E6DoJWlR
71Nb1IePI3+xFXLXnTiHWvhEDsIR7zKLCsJaajtGdw4zy6ZAIy78kQs5sbW146AWVUqMf8BfLhLq
aAksbA6lipz67B1JkcW+yULzUhOiDxDpRO61J9HejJ3HPjBTGHD6GuqSma8cP8dD0J1TFXGkd9II
djtydF+lvqfOfpNP9kxs1PXys0cE2iIgstPGprG8Px5RzekVo+hb/fNqB4q3hkyBRnUudNoIHxRC
9Q5Y4T7lKKkWh1asCYoJiPuno5PLHtPFtOxh+mEp5MybO/phXDc13Z9U4vL1X2/sjidEtXd1DKjj
sXd/vyvibYdhbW9+2DunFsVFDajZyfIg2qdAJXzclHNckQ5Wy1znbf5BVosiq4zODJh76Mrzf6UP
4rg1wHsKfLo8ZjgNN31grb/HvRkVynbKvHpH89mIaDNiyINTAFeNu9o32z4AfQvY5C49nrXFk/Og
T1ad4yUgdq7wn+YHybHBdBkk1gCQT0ie0jXGW/U01QaCQ4O8ffN0XyYNED9IVYSJ+v3he/XeyNhN
eQXOAnoa6Le8yTq1Q1MJfq8/p/4jwUovpXvEdRjOIiPzY9nxDmN6R3s5rmofFEZEC7bWzQE7YuN8
xG7fuEbEa2fCRYSD5STi6TWLQImgenyOspVxyAufsDEzikY9tpztliGI2Yuly/kbfY7kNrR/7uIE
C6miMs0tC3yRJNYN3n15vj2csdpWqpZUmFgD3PGOSJsnf3UJILuI7+tm22CI7kK3tE2oJVD1cI5l
Wtj+QTHFJwP0az1hDw4X2+upDWOAGyRDdkmjUxKosTIyjFutgklXiYxB+h/UOBWr79qcTbDHqeMa
0S2GcvTn0jjPV6U3sOtlP//1mqPUYOM9vcX6wgyzX50yZHdYV5HSDsRVDzlOw2HdI1Y6nmOPRt9b
dDDDoFWW8jD/pSawLX/9yYtY6nRV5Mj4Jg24ColR4O7jgQPgDfX7gYfR6vsa8QmmigFB1b8OSboc
OuSQWtNR4UexTKQVEd6khSu2cPoFj5Oz3vEmECFogyLechsIQLRl41isaSAiL6yTY0D3/tnaDRf2
8dtDUTczGm3AskBEAhWeiU+yudIdwo88gQDbRp9XLURBEB2PKos893kVWzx0rM+Ht/5O0Z8OX9zK
a/TG3qh3sE7zTSSZVXG8qd/Y91owgM0f7DqZ38B0f7khvl2SYoUDcGuVCQU7Pf3W0skai18zsG/V
XOgr+Ri6HQaPQfGtcAAoeK8oi6fGElwQigQOfKegAfdxxVV8PJJ/6wdAQVYcJvOr0H4K71RyJ5NC
4tosVeZtmuJX/jbBCP1Idxp4FPiS/Vfk1X4diSekl46/+TTKAp6QUp9dCyNaxibu2uG4l1WwT37f
G+aVgdSzOdcHgAKzZKAlpZN6rsmYPOcI7TYbpThC2aXaatnIi10F5S1r9lczD3tLb8OJFQvJ7GaG
lkOoMAkicyA/jcVwVd9J0MFj38GYkSLOEhNuRKVy37dihNuHhge8XIS5ndcN7Jz33VvB/X1VzYLm
FMnGD417fQcs02EjqM3M7OsskYNVKue2dH06G5k3Db1KP2HOwCd3cQGZecMs0APWPT3xYO9oxPmX
rLQrOj7ZAMgXHSFAuyAoh8QyPYjVJfcUfHPESfhVdrcZt89n0AP4hSGKtqnbvgvs/ApH6xk89jYk
+rzNawSnHILaiy2s4d0i6RwLEzK9X2WS3HHrWwfn6g/fwWtHooulIRB157fg24oqcD5GOqi0U3DF
gtvnsQ8YtBuwF9RZvskTC7+rTq9OnIwSx2qwYXJAboN+balJFLuMOi836vs7AT7+Rzcu/LRXqx5N
2F9re3CltIiJYUCoj4tT+Zzuznry2ufsDoFTgevKaBHlDwiszIVHQ+DuxGLejUXsZxH7aEsoeGUV
KPz+vkltuGtq28vzFBw6oRMfD+zZ8/1FUBxlHzBUf6n7jRLNCIxjdpL+FGRu9ob/x/U/VrHA49gg
DW5iowin7nQxuN/wzyOHPCt16GcLmegqzJ1E0vKg1zhzBXuTLHn2y3dBVtayp06ie9dd13TkeIVC
Htxh+pihUFFwhSU+lOBPSidZRLafi5k0i/ZqdnBGXq/I3TMnpoeZncIwKXAVqtWGyMG+eI9X+Oqu
qgOdW09c//8ejkg8cP7hMFLtgzMscV0WoofXDU7Jyv/9iUh4rPQAbIangb0tIb0Pe4UIJRWfWC9W
QT9VOO1KyFF19tBiZG6WKELQX6aBlQ98rmmv9YD6fNDxrkyDefnV+HUY8Zc732OY73zOXzQFSDAw
J4CMB/vfr8c0x2UFonbWiQlCSSv3IG3o/3R2IvTK87ZN+//U9+Y5vF315Wud7dFmbVuTAtDI1hSg
1lZo24iDHoCN5YX7EPdpE4MXKXn48R9a3i2CoFOlPOQ2wpi5JyoiOfa994j4RS4dxSxTdqoiCl9j
2+mwav3PsGRAGiaJ1qbQ5qy7zs1vQILrTkLEvrJA7cGWVRQQJ6o9zh9Z+K1wE/dMG9c46W1m7Rvz
Vf/dT7Z9Dtmd+jcm9rRVZw43Wmkl79QAygaaa9KzMe/O0Dg38i+ze2hu7hV2LBF6viwTqAi1+tjB
Knx/oy1c+JAjoJczkMMdZYZZ0xmOV5HBrT0sN1XO/XsJugyUbDlbfHn7PpjkpbP1bsedNpYspJYW
e3WQjauoJDm5qH+eJKWpMccWSmYxHZbxRslh87xbTjEy8wxn8H1G6Md9fndYnhMM/RnKJwY385CE
d4hEIUx7kXrdOgkxiREqrF/U5SjroXF1Ijynxv7s8C8RIJpba/dP3FL2Z40herQG/0sCLz0Iw4Jt
LaQtZGtmZD8w+ikI4Q3THqWGQ/VmxXnQUURFY7DWH/MYUWuNl8LkGG5Fm2QmpjW7seZdRUi3oMer
MBlaPcZWd394K4TX68WVHIt7IpK1YtMKrdY4uHp4R2OzIdTZ8HqhzocI/V3oH7TrE3rf724f5CE6
mALi0OMjSqDkI6USfhuklu1x7hqHtLaa306T7wg/QTWmfC3N9cQ4JETJ+yP0jxPMMkFD5cV5mDet
ZYlR7/Q9mqR8AtKbSW0zG2jr5oDXzSNKFKtLjrF48Am6GpB5quxpVkXIjSTr73jTpInrKSCXFvC2
ZvOvOpktmHj2siuFaigEpTOzckhZBzk7SaYLBch3XUqnFk7/tXvRmNehdFymqIBsKnK1U9c3tRE9
JoHZ6I2VdgjOhYcLddbQLSv/1iLRfkuJf/hlK2xoLsmtVeu5ElzPjtsNM/eUEDh6MbFF7QkPHkFI
m5q5mEnhS8qi2AavNksZPH6+nXyhw4jCuWpCIz1oXhc+257t2xm/5Jd2Yk4w+5U4kp/Dd81F5fMH
wQFSeV8eQQt/GkO4UF+wn1Gisr7GjcgGDWjiMIWcMR9Jwuwq+gtKZdSSplsVvcZUm0BzVArM9VhM
V9B04fGyq1KOJp04/IKwc1e4Gc6obnr5WEdImbtlgsjw+cSM8IW8nEEJaW1xZDXhIkL4Leoa3JBM
O+QF2GFATuOcyYqxWqH9oXdB/29HZitTMpXmq+FqI9fqnUzn+VVC3IJ8U2y7bDTlXC8maHn0/PHo
YbpEX5nH7+3p2WW6dftphSezjqoGwPIQtl+LOyY0E14m/qr8pTkGmPIGUqehhSORkwS7cds9tcxl
bhuA9q6Z8KzPvCoKbn7A1zf5bP9S17ESw9HltQJ77/rKN4MpycPivRokzjwLBpajAE2QpDAKLXA/
nsf/Pzm/xKKbjVyUZ/SQvHPrabtLk1fEzM15AvyTuZfqUCR/5PKxEMPnmYtYfVD5ObPirvVPi5Rx
oTVG4fpUf4VYn2N/llFJLEQv3o1VpCo/daHCmj0picfoZYvxBHYTxjYjR9AKQ2xG7RtLfTe7Bpbx
XabmaspVu7EL91RjWnngzAoZxfHvZcDvSb087cPp0BDuXZ3XtXSO9O09fYvSsITKfZa+YGOLNVSj
wDkG3TVha851xoOqrGE9GjTKFLWQBQZgSTFYnFxMcOcXnwG2LtwLXIEdGjsYEjMrE2RjnFjokrN9
adZFMZmhaehKbo17yCCzUxW+mlCFLfU2pX52baM2sKIycSBe6OAxldgzx9UuvwmMZAUCeJQwG3uy
T1rsSmU00Te/pFKBO2XYLaZkncYlw98dgAv4uDBi7saCI+2ES3kd7ZtIgfwni8GvdvxsBJ7p72f1
Pji4vq2Oc1DOsoNJZuRxCrhTrsXBkWkyhd/7RiUvQFvkd3BEzNJmQqvqWKIUjzxX40J0IX3N/dji
AiuLZavtJaCILaS9fYDe4GSqmh4Nn3EbtKr9/bmV0b1jkUUxMkAGGG1x0YGO2CpSIpKHlELpjNap
IAO4Fwd58Di9oUrYXcwkvtVksjpiKpyM1HZMIhKAnmYZ18WQYoVKquKP6zZ7cyBvoBu1cnlekwKN
ZLwrqkEnJNWhl/8Su9hBn4u+2Nk1oNUr6ZHBwu/Qu3EF32hLpeXUmQUytBtB0WmEUE4TdIUTDoFj
CMkD6aFVMoYYd4oBW6p868PEAdHleTIaGmI6nnoq/s8qIx5k3C7MCPQNx/qevTfheePVeCQdMMcJ
A8/ys1+UOpDEpIAUO4aChBEomcUwKYbPMX5e3wxNzA0eZhJ2ummiH5T+yfHbaMAgfhOPD+Ik3b2E
QuRHP35rlEJGbZlJR+qehscH7lPGBArC3d84DDLwzOzMnexzcfY5z4ZMwZi56oPYCPm71IX10fx3
dbfc7yGlkl3ypjA8+xVbmkP8Pe2uvnzHb7ZQPw4xDAI8kuA9y1iJAdZyfFlGoDSj7ziD/isr3c9I
MiwrzjSnSP/oI2e2UY2XUtDyUhTVzKSF91A7aR3OwqvQPvVNg0xxcjtIABuhX3b48LkAH7LuL6Lq
xqM9vLKuKCdr1Ql+2v8CUVShn4xO872khTC5hfqusLJKMoyOozJQ05S39gs9ZNAHpHfSvyiyERK3
Ffjn5Dz19xdAAdypNipkqQTQEKI7JB/uTCSOpwSzQAVdTI/Mzvfx6YWyWjF8NZ4s8Tx1MLSkwp+X
UHxhVlIkAsZeesYgugwfqovg4ilSLpfPz4dDmwAgxXqfAm4yRWDCFKE8o6gbP+vj6/vvs8tzc0dE
cFVnjC2L61bnRday7RICdpgKC8gZtpYqatQP7LYJLO20Lg1XW7pBJyxRdQizOesSXQL4ayBfkyKF
ysjUCA3mnXcGV5aLcAczbO3BrsUYve/tEafxBqp0CTEq5Q8Bcbh9C4nQ/6l2dPTF4szjECuauxtl
WpXkdxh52jZwfr+KMu7LsLQEbvi5pc5/ubNmpuqH5W+qMJcrXNbhMy9rDvMQhSTAqHNI6bxBXiTe
YRWPGj5HxOeQezsWSRUme+9yc3dfYkpUeikA0mkvh5Fbqeeuc1zC628GQezbW+BcIWVWxa1xtwVI
dF76XFbKvnK5pGloESlgrdM7mRZM4pyVlQD6D2rMPwGSnbXz8H2mL6Ycwrc4ONR+0Qfli2rFkftm
2Ga1vkEkxfKkUpFGxockHL7+cxLdexhWLc3hesSatcM1/BfJE1a0gLiN5atxeMQcFio635YvbMV3
yGFAxTDtBfEZOoLIcdtLcfGF5pomgRnTX45JhJMJZuYQ0o6dWnFls9wnAyFR0VzBziIEoHGljetx
n0cbCnNT9V8WE98rPa2CKYp8fopzHhxdRI6tSrNRWW77j51wPN6IdJP+2uG1uVqIKgMRWAXps1k9
iL2Ll+nFsIabV72vPVHLJ+Nc08oSZv1OjJ+5e7HCAU2KWfvrpLL2jmWO/GItS6/vueL5t+WyGytm
LesR44mwpggjibJBMC5L/H3t+4BEgEJ1eK+0q7bX8GVnbpT5gf2aPHEGJUA20VTUpaFu3H6Gfd+5
BpDB2xjKmg+ojqTtl3UKy+XekPbePOvK7ksUFR790TmLL3wJ5XY4UxyygxlY5aeBXZu/gfISxanK
3AQ5wJ3pyiiZkekUKGSHfdQVr6qHP5vtJXaGERlZFAmX3RoeQ0gb8Olpbl978JLnHezSuD9L0WOp
hiLCctM36tvL8FImWesF9T68i3o+hS7r6sRYfJCEdzRgVq6KZrtKfs7UXvCw+q5ZX6GJiAUw4jpo
0T9UWQn5YoMdZAIpeDbAl7hPmGoQVIA0H5SpjPH4YATHF7GvpHBlFJSJeBv+2AgS30zvTKCTZUIr
gdX8fH7h36n542F6VMiOeAxZg9X8JapBNRFQNSNiboryphVfeX8iUk8UiS3TNqJay1GZTypIS5cX
+bZ4CWTbSeNnZ05YoMqyLe3ydQrGpo+f4xx5A6CFbWG4po1qaCvlcp6s8oaPl+LHpqPnzKXEmqJr
b/oGPHzrGrw4xl9YVJj8LAmdKiSh7b7mPrZJO+Bsr3lWZ5pk3UHn4YkDf9+2Q1CpQa6VUl8ooMxd
tbfPDpxXIS/bw2kFIMSmq16Ac/ilgEsM7LY9Yd6M0AI8Jx9EStSCjaGFHGyUqjLM+zz6x8sl0GAY
1/DffeDf1Zw3A7qhBtW50K9AbT6gIN8GUJJh6hCjidmxnYCPh56Yc790Z7DBopxWn6joZkwKhQVe
09LxcfcWIRZd9RG50UFYK+w+amEkh1C5XOlko5hX9BEJaqalbNxhKmhS8N09WWjut2PuuQjICLDT
xbNC20NSQIuRDAc6aOLSjf2SNjZ5ej37VmPltNYHpKZTmvr8yDLqTsYyFbLgCM4BOamDWOF/ftRe
U6BM6u0nsAL+lVMe7k/zs+bMfU9ngP1evlSYkgsZp8uwRD56CMskfYhvn1uMvc1rwx1W5MaqQT/v
1pfoGq0DtcAKlW6PWryPScz7kHFVatZDxDGeIPXvnsGuVDmeCVrZVNF3hFRxxC8v/uofCP3BA5zj
cIGnKS3c1ncxpFA9HPgdN9xlZKk/iEupt+2qRTE8BsjV77EykzW9jeRoUWU1g4NsFAmGrouXQINV
Vyqv6li8gTGPU2X+B5KikIkSlaWm+QKZHbmIROpteGXr177WKi1Z2fLepJxMcBTtlXqJ5UGPTUOp
gnHf0qSWOvIg27CGGvPcFj6oTNZaKcMFxPxW7GJc+o0Jk+e5W0r1mzkSKBbnHz9JwXklTddKR8Zk
SHbLt9GCDL3Q+LpFh03/52vI75VGnx5cjzJp26ur3P7XZae6zrWhInEnC1sTSbiE45Ys5yfzqOkg
oBGpsScqmGBSEWDwrUrsW+5bI6DrMKZAy9WI02z+nYVsL7/nwesChlF5L6XoOLizRnzFysOCIqvS
bTWP6OjN1TGH6c+UKKC9UZAFjZAu/boYYRCWUNK8bz8XVDL+ODN8IG7CQ6n6PavSLo3grGGMiR5z
8XaPBIVJkcQ6o039yrS0T0MaiSO/ZdF+u9QSyeDqrssMC9OTZfQBATBsRz2FN4jgW4TmY0SV5gVa
B6/CzJbJ+Xg4yFi98Vo7QvJFybU/SV7YIhX991RyT7ZAu5Ln4/wosquTkbcM/AOn6j9iS3R/yfl+
kPeJlmHiS+uN44lW5yHMbETlh6sCK702CS3EsmwCgudoTOQInA3J79YvbxfLRZZnjQLFf46qBGNX
E2PmA2vvfQdNGjsTIbe5PulbP4Uv44iDsGzATX56sz+m96oYmjaDlCvEajPMezwlo1lEc7r/Y/Vy
4DIqb9YYi0DvToqONAn6ztanIgT2enXccmz9rvDWhWBrjuoEIIXt8K29DultjEHCo2NQSonZJXTy
oOIXYQ/Ov0jHNOPAxltRF2ouCbw6uKcr/bJNEw/Hn9xGCoXK0oaQHZV2k9poDPykU8ugkXJZcd/M
0GV3SGNSBNfQEavqwu15lp97iux5lil09zTsWgrRRcmJzmlSS6ZwkpaoKgZ9DfNBSIbcmHTagXfv
Z8UE1KM0+PH5EUXxQaVeSh7CfTFz6qarx+doJKTRgMvlO9ckhpBexSsu23rfAa9xSgd1DQLUEnai
t9OZnMDOtTch9HTAaKhAupZ61Jdcy6gYrypyffW9YVvQl0P2vh+zo9NJIqK7OJ1pc7ruaCPalWSh
TrTlVxw/5BeBpj5Apjj7EAPR7/CmvHRIzzG8rlJPCPG4v47YrOTY0b3uKmW8hJ9IjAvpDdaagIIp
uN0ZunJquctWJXrV+gTE78zMmPSLhHPdpfCjz8CEmg/oKMMCXHsel2EduyC3OLkjUBmXNOEs5YYm
DtWplsaVE7GqwjqapuAhSZuUhoBY2y3YoEDomVQX7jYGjLGKAvhwqU9xjK+uAYdQk9V47JRS0/Vt
xjSXrRMeKrS+j4UktTBgmYUqfxaf4kRagk00UM8YxNDdkq4VeIls3diPHw72x59C27Nz7aRblgmf
+LM+z9nRjCGfRMjDgucZ9ZJTynB7FiRlrD87u98HS+HjveoT9f6DYokhnGtUzIMt6tvZNczvgDIY
hbu+bQw5yNvWQN3BKk1AZBx94LG6kirjXNuHzrM6UcgYRPCWUQ5Cvm6LimMap+43ebmsS2s7bq1Y
7Om9Ttwo/pSAAucfUIYZiHx4rbf4fMtFm72qdfReQrvhu/dnCokKVAEzHfBFILPpn08LNatxcD6G
jpfEWXGb+K+8cio040m5CpeBsJ0+7xBe+9ReL4oJEsfRyyFWOHD1ik4QKg1FSPzTfcvGyRqFpcP1
8O+sG3GevyDwj3INvltr7PX6p9BodEye52WK8yXVOKRnxnseh6LXgc4ZGWSxYLHZViALkqxh4Xng
3U7127OQqR2tdFlkrVjT4MfE5G9olYzjwZdpkJQ+XgWUhD+WOkZSBFQQxtlOtq+v8Oc3WigSmK8G
8phHgd09OT2nh+QnMh5HH90cG3WmDCexVv8M/gsb7qEaHi9cPAE0e1KSCtXBqpKZgMYGvBYSkWT4
A0w1bqzW8LV8qpTJxgYCoWA61kMgOvH+9QxxSqA48qQHLFQpGv2MjecHeq91qwLpi6Ho7lSSHidV
hyGHT8Jbi7u/IxIjSdaK0WZb7cbeTvFm5FlH1w76OsIaHYxyqpso64MLRR6Xt9PglcH/1yH2ZRwB
irPekZ6QRJr2A0W2IaTpKLFMmDjVuu+m9WLqbyvMGdgNtVav/+IOwTXx2tdAeCnLmaXFiv5K2wYb
k7JgGK59IvCTvK482zTQk8MDDkrA+XKakgxHIY1Snpy4t2+2veZ2+n9mk+wX5R7KqN3hWTqd5tTa
IH+h/l1TNhtqQQilxGdQOP1ioRmUGLXWKvNLl3HCdIMErBsBw9WWAHG4wHAIcJwVsUFWlnzsY1b0
oJ5VSwMqrfq5pfCOXVbzRPIN4OuZW8uKq8nP/48x1A9dx2DMsJYnBKrYylyv0mhnXigoq5+EDGJw
+HpTQJ8Ej+HQjSbTIEJ6UOmPOembT/RcNP1qOR65bBnAT8xuC1y1Nnk6pRlydtAztUWaIQyob8cV
2lyLcscZAv6IZxm9m4v/XI1JtIlOSWI756lkViFk+ghhxkc05+fnslJD+6iXsrZL42zMAEmdbwwn
M2Y7qNxLDmWvDKCFq4Ttp6PCxw7Onumw1qDQgAz1NKQScxLaftwbrQxeborOn3GGabJOv1VARlpn
jnzi/FnmR/gNOC8EkJ+JunqV5D6pcdJa4OM6JLHwmBtmsM6+9Cuzj3FrdHB8uhmNopaOWfP8W2iX
Jv48PfnkqI7rJy+ksI5vCyYTekQqzjJ484CnIBbJrwf92Z6D/x6MQbakNjorFQ1iNMaPAdiQmLkx
3n9D3M1nQZ4rjQyCKMG5nF9bxU3hLOieQuSX4cCoZkaKLq+PeImRLEJJQUCxwY4tqmjYroyXjF2m
dCdUqSZPWwhE86FKOkmMgb+P1HJzL2dvStULh/WNKvqKqjBnzpUhwWrTaE0NuW/hLHhtyaOZ3poN
IcdSUzWM1pZT++otLsQiQdSUqh8b1pwIJN5kFLAAXOu4kjyKkszRxTkgxqAPOOn6bvrg27U6sEvV
6D4eU8UZqRjJQpGZSxg/AmKU7GxR+UAq8fENPaLupaQqKgBHAHOo/+wrkwAtZsubhfTePEUPfKdV
58wl/S5olcib3VtSMjde7+ovYFD+W6yvXAedXmZ9JnJk2JcvHr3vq07YgOE/VoiyJ8OzOKuW+fBx
+/UUa73tE9uyoJPs+HAP8i/NV928/Zm4mf0D/+WFdBfEzHhz6RlW/XZ5xF443jW2ubAcjvHPFtmM
7kROD8aCW0sA+/KQScARYONQ8V9iuhrF/jxPYd3oEu5IFuXA1RHVMoawrU6uRnVXmmpFbsyYjXbk
5MBkZ5vc+cR7+uxaBg+pUsAezXiLbU/t/EjYDeY0FRk1msKsHORGDlGdbXgUht7Vnu3WLijLRBGt
f4SQOAUvrtyC24KTvxP3DPo+6kSUIK/XNJ3n2DUE7qfr1+mZbMXPRORn8y2bc+f3QtoTypPvZjYA
Nz8ouQX5ElZ8laXVS56iv0jKSmM5krNSaB7x8WGabvBhW+s3sdJ0OcuJfuooj1UP59TFtiP3HS0v
ztUphovt+MpO7melSQWoKaU3kyPzWVf+FnSf2a94w/yoisxsKyTWaA7jpQutoa+tRVowEMygZere
OKL62WZgHNSmGiD2ugzjFODJ/mjC/fT5A4W2NiH7adAYLzVblGK4qL07+76DCL/d29l5eq9J6rd+
QokdQ+rkFL8OcgDH1EaVOZ7RMW1hasmBnXog7K/1JeUDCcb5hfY/sH72VmA1Cn3Tblc2+S8z9kUd
rv/HMTAN/n5YFah36p4g8U5JL795NSLTx43S9Llh7sTVB/e20fZWI9uQ4pfBB36UjFh+itBGyV3p
CWsPIGd46zVBr3K/7uN4EvjbA58eJOa4HUsKG1akvlLUjgSuSVZyBNnYaNZ45Bn49Bj05/aP8HDl
4WoqTXZ0b52vhlAOsJYcDMuLk/hmSwpSzuGmUwymMkPJDXbEEXzz4oVuchDs2HYbc0kRTn7IVnke
Wz211dZIhCNG2MF1ZJUrP5CvQV4n+MZ2T6QATk/SWNKeEzTtVr0SI+JIvLCAuhvkO2shJ43uAsux
SApIPcRH829iwMAMcpRT16NPF4E6DUIrrBbbR39OhVcndE6IZYAF+wWHqrdKQDCS9m03crkANpp0
YJNOj9k/D27AvgYGdGaE5C+Fbv4rMQPg+LnO7uhZq/b+GgvJofvyxqCY8XFmH3F6fBAtpmWqLglG
xsjZMqrc+rPgZCux+axkWf2EPJKkvyz72po7kwWEmADCVLlk77pAJapE/3GYJke/+JQHkdK7ElOs
wBpEJp55aQcqceLjIIaY/F/mNMP3otfKu5jhp8QAb1Y4X+bYWSGm27oldNOwH1tVA5iCdFiDYm2e
pnXXS66UjI+uRKCIVhBW781IqpuC675J2+cuFHGSNArFPZk8IAdUrRW8cubm5nzzk+NIRGny+25f
gyhuDP9zZFuypZ2aKOKwpOFRKxs10JElpP8C3FAOWuNPcOnZ3xopOM7Dz0X7BaPdYkDBr17Zxi69
Wri3pX3I5i6XJgqQLU7HSoEJeZ0UvpEocBM8lkqYYwji55YDr6ZAAN+Cup4D9mKH0PCTTvBVBN73
VxSH5wMXheJ4nCqLSaW8QyWSPWNA5vTYZEXpj3h71wDccvTwBmZj/0MVtXdOxgsmK5IL+RSYywYS
0oo/GhDr2QUY5hCjmxCA4z37XlOQLeZTyeQfYsoTndSg3yFHJQ/v2Y657NktNrddljEI50u7m0b4
UJHKItEKsqXq0nBYUtgVsXjhBy8VpRNfj9HOsjwdUyS/h5JUPZwX2popYCAFIAKrg0P09DtPFtvq
iq4VFktoIcFCpP948TnZd1lHNBEz4g/bVsWqI/h99iTQubFmgdiC894B+1hM1TswH1MBCpmZwX2O
bEqaVeC2GX2gtecVJGXSieykeU3G+vJZQVTqw3WOw/VVQcIACYGg17HQE4eeGCxASMP3Q3ApW0ln
c3b8KJ0CIMV8O4nDE4W6qF/SUwsFm9wDhsIPgF3Ra8xIDQvR08U1vH0rBTKAb0wcmKLBb5NoFVVr
mYG0RuY4XVf9kxZiGsZbdwfeSwClj2yaj7UOKcVU+nHQkLkDHRiYGHHb/+jnlLVH4YpClE83Cpu0
IpCW1UqicFinxY7E38DX3C2Zzq8fC41L4M8GAMKeliw7EaKbMDD9aTR3BBVORUXyGrbQGjjANBiB
jHJ1XGPOOmY/pyezjB88pexWMi3GKBSFbus9yo8szT6feZ55w1ne/MQy1GohXYwY4cyj/tmEJ1JY
7YAP0Bn+RydIgzrxc0+CKGBJcU+aCw7PwDMXANzDZLhmNUBnxagk5JrzUKET5n7Myuh0GEKSjHd8
NMdc5ZyvyaP0z3T0Zh7AxsoHTO1eHIXV1mRVA4DCAaQVj6UKb51NnWzJBr+zqlbZhBbUmkCT+G8W
prRc4WPFTpkTRkfzqvZP+yJ30c33zZYr1c8OxwmHoQt1GMrgG4H71Q1pua7Mce/LYJhqm23TAix8
GnVCiwoOVhvtBE7lwqKvzsi3sgy0xdO50fckQyDtRE+bJ1Ihw5XnL1KJe3u4AqwW+87lvbVpi2S5
3ysemJ0L5nKrZagkpuc9TKx8YG/dQJlOePl4CHLTvgPDINIcgSquqGpMHuO+DS4otn3oYwL5Rnvh
f7S9Z0STS63s0cfccXQqGnFH214lUr3Rx/xnJ+Y2cewNl5XWYBILk3yGONMk45/r2eK9XzCHq5Ex
Rvst5CZHWQhLPM8/G9grrqsRfNkjan/fzRGMtZ7PZSxx+lkhJ16GiQVRhaHqFJEffK4DaKutfM9q
LuJrJW8IaRkr17STNx4lE3YyKXziZotkJRUxpMZMRDmh0EZfJkiN+HXiyLMh5qoysY9C5fSZPg+S
AcDBIxT0VqYvnqovgfdaCDTkLZ8OelhwioEF46gpWmBaCI9iSqroVpCbhSZTWYVDTY44hnxRn7KD
HaBT4rStZ2fl5hXqqjO//aaaGAdA6NYNOCBAm9RHpmw3InNhCR8+WNtKJnf4/uvRmaeq8Oe7w57W
mSbf5vdg6P7XCLdGU3OYSb4V6tEUE59GzPdT0VbzV3O/j2072QayOBQB7AocD0b1pjcM7qlvOfw8
4IRzJQiAbWO+zSbu8HTXdpzb/fEEjG+QmZunsAbFbLwmNuE5d0spheUbNJ6R+piY8JCtRIxiLP0H
uyyTTHCJWwxAQongcj++0FHCfPTv4nEW2YZdLzM3hF/Bh3NTOMKeHHo3B1w6oEPk0sIWw+TUfzG9
qGemifM0yKaeDKCF/rtwnVHZWAiYWEtZCSdUKjWh+jMkrNrLhkoK57fMfa3yOp1uTis83r/8RlAQ
itg5xb4KW7UCdbxN5ABlufwu6FvK6E4qULb2fGkjJCE1AtTAe1nc0UQFGK21vN3mDTByfFPh3awZ
rcILnNrw2yQh2TBc4Z7JE/8mLIN4EiWpCSzkj6ttV455oqK6u0wY/8Z9IW35E05eIqXlOrZEWcBU
6lQqUcpInsO/1FhXkoUEKNr6OR4oTjeJ3x/iUBmTU6Nl7/Ztd/0W34lTsY9Bay7WJVLVH0EDoEf/
uVW448grJq19rHSy9DLLI/Phcbtxr6SDZdkt8KRLeC5ylMIuC8HFUU+eDIR9wPbltVzE6cJ0Szkm
ISUzMc430qc/nOAdNq4+A1lt4ejGei2jhgn5AKYLN5GFd6pU+AtpW8oBwb2UZhJ4ds5f7pLqPw50
bjr3kRM8B/C/+tfSvdFOoR7ho+71nuBKeHYQ0pf+QDbsy0/TNknuRkiZI1O3STXP5uGt5CEaEUAm
X48rmhgZgSAwSwCxE2ZpJkjkQBtOFI55aq6vrD2dAJ3i16j6WQnyMCx73W0yAMSWxOHo8n4ANe/Q
LNdppYORlIwugF6Jiy2p7/ZDaMQ+JpeTRsB1AL1KAX1r0rDpYeymCbhBTS8MmGKopII+bKsSNusP
63YBCKA/aHOk87mkIbaSw1nYLpX/VU3MxTrhykQnjkApkBrv/560ko/LKK5IsUletBPYyaBet1Qs
vkVa8519E2yRhJqB/o8lqYBqocX6sQVdBgHDeBuaZc42iBbbqUSR3uC0rPiSeXJXdCpmGl0ZYgjk
Y1T9mUcB1Zbdp/Glber35yveS9vw85YNjZMsFdYvclRi3chnGK/EMoYwEd55UlbSjYHu/EjFTfWJ
B+uv3mVriDqqb8vUZmIXU3UyQdwnzPRH6mjSM9lOtjWlO/0XFAetPbo9FrvlJH9t226nenoxxQSY
E/8MULupiylPZxKf680OEvV4vXQXIoY4IlIOP+sIBprN2zjs+bIlwCBKXpWPnaW33Y0hqC/W3c34
6/MODIDXstQOJdcFb9eAhLz6oxl7Br4KoPJzgdEC8sV5P703uphC8XohCVbmWG92zfjmdueU6/IT
hRy+tt6VVBNqrZe7sXdoMLQtrXzsgwvuNy2UrQRyjXfoXzqHhS547TU5ASd2GB46NGTKJBQLC0G6
2sNZx0JZg3WqQGAzS7g16ivo63RJIhuGKYSQhIAUYtGB5+WPktoLm48q3KAoUCwgjOf570iA4uwn
iGwKbVw4DEmlC/lm3Hk47mjFsTIqKh9ek6RKT2uFc5wIPsQhx/bpUvGBf3Yw5FugSl3JyjONVncT
vkJwM3Rn+8QXb1LkMuIvgAThRtBpHFhyYRHBAc57fn20l1EQq8DMlyUXgsY0LN07OgffgwxfeLMA
Nvk1iSESgrEm0kZLRPvQBkJ3x/OkEzIe3tqa9px26Bm+2mQ/ebvDuajNLgs29oJn13BuI3V0PbBM
NTcA+3ZyBVufKJC6zwhcI12h2MWcKIBtXNb0jSs9efoeMHnT2yOUQFsjItgiKFb8OD5V4D3da975
1yBEvBHzodrUexZN35z2u054FWjjEWq0taCNCMnuOAPrNaaE3kl3YMz2aBCSo8JnucX/jUcWpb5i
py7nSBKi1xz/Gap/Kw2K5b78gAjnOi9yvX5oZDGv7fMt3AJzxrDVsukztdtY3t3zR7RwRgZHP1hT
OlFchn9oP4mfCH2NccUxTe3wtdrLrekZTcYX0oSIrs3XtlbkaDkhp6LoHDtCP15LK4uEHUepYdYB
UoLru0fxCKZkIUn6aJVXgkDrDBpPJBM99EMSaZctRNdxyipRGMUZDvu7LE4Skhxhkym2Mfr5XUOk
J/BjrVINNfokxbgtaKcJyIBFqozdS5T1NNu464VGp/CGWdUQshGcjmFVcBtJp5tbPBi0VnYI2qJK
RC2G4nCBLPO4Az43EtDEc4Zxr+EzQpyHElUQ9alBe5HRQ9Lpud1c3T/3xccreCmy+IKlGsrNcbJo
YZwQnvioW7yLuGLBd/hxzpeLLoVd5igS5PO5mE2sULD1wFXojDBVNcNKFsGGX1j3fZe2C7xXGbcH
yEleToB6QWhyLTFfcj9lpUoL2Jner0nL7nrnwIEXo1EsiDQCl1nP6MB1IUr8ZMjGurmDgZsjPvYF
aT8PHBwODWuQExpfN6fIwF6+xJ5AZHB3eC+fdevfv/Ci+hXApjwtDiKttlwBtFcPBlXSbdZjcq9n
JbRW8gUE8wOF0Rjf9n+6ZoTRj/OkAktwn82hbKnhddSfBZYXqNNemYfcrNLKsT20z+2isLeoauis
9ZcsuzgXGC3pBXOLVND4kyHHGU1AlurC3AlDfTYA4/PNUTOHreAj1f8GSWLrcvw1gKDs0sX2+rf7
J0b4KP04nB7fhYCjssc8HM1EVvVG3uPa94YyQwS/pRwCsaOlDO0F0XgTCjg4waLuXFvRWXqLq19z
wqu7v83hfRkLXvr4saYdHkf8XfUM5wFU3yQRZQWOL2kbXRR7eyEGBOVYdsOMaClDAMZN04ky2uvN
96qEAAVbZAPYcLf5pmll8SkFnz1+gbNJiRWjNTPlhc/7no2KTCBi+mPZrxt/3WggG6PtIvpRr7Jl
DipkzqbJWEr/LyBmqkAz7EBM5oiFFyxQEdompluSmF0bRakeL06xbRH+ZOt5xyStmVg1InlcMYVD
jKsxCMM0YUN9GdVSwMvH0HLwufIQOpFd1dVNvEnRVeNnR+5JH7qQdr/weWi8SGeRkRzxvtfgiK8p
ymMNWB1mV5+voGpFVxivsZw1CiWOznUrX8k2Nr/W0U9JKN4rgX6UnhSIrscepFqUD8dc5wtUM3k2
0Hm/ulLqa6hBmpbcksg96Gm5sDJd7khU8uiT8yKOHh+Ua9b/j/jHHMSn6nKYVKnAjuKgQwZYn9DF
aB2Epk17jbokDpAAcu72HCoGGHzgWc/A45ed3Q0p4Zs3QVEySg/KySNe24qLvlEMbWfM4mH2PoQ1
Sdv9ljVxsW6YEyKYbki/jjpJjFSqkB0j5M5g2+/niC+9VRd5Q3SkbhUOugLpEtCFkoBVlYtvDYIm
m3HGAdWQbV9mz6VeT9XOxMbFZHnYO+6IF3Kwt66dEvNN4Q6qjTIY9nAtMMd3XEFjfsbPmmK89XKk
sNXV+LkVs7tEkTZcog5gn2cGSin+V4s10OYBOpizDmI+qPOxYMESkNXwtBHUjHBFaCzZZo/TTz+T
hZUXAbx917I6W9L4MBGOoABHe8Qp8tScqhsxfBQp544ThPytmd/NhrPV8wcUP63X8PhkWveSIzEo
2LNypFdVTwTLggOthcMzC6MkYmxlPBEHqfPVf2HrBYMLf/lxQHGgUkAVdQRYm99aiu+iYFsgX/2/
p5xQogEAG15rWqNLUapsSTc/wEsqexPQQce4hB0RORH5AHkURnrkicIrR58T4ZhwTBw45i0qYZlm
fmkPr5haHji/yC+AO0+2epb3B/fQ84uDemGNUvMZOwz2blXsKZpgZ/gFeIub83ZtdCk5sSjRhKN8
nK8QGqrr6k85T0/T7hXhjfht53SMCuwzbnXxC/KbbedhXEns730J7obk9JHyq2Ds8qv89x9dcOYW
ty/xM29+RBQMwc5m0LKkxXVz8mfEGG3g7lvCu6c+ZoaSSs16U4XCNwTfYGD6yorvTOKkzhD2AqM2
a3aWE3v9j1kHFQLuWnk4ZdfwI+ala6ZTzGSgbMT8Xu6D9v7wgr6UL2zM390dmX6v9go7XeM7KySi
o5CScz4bBPYwo/SSblK7kYkhz5Tq/j4vR4KGafkLgOIB2XlTUMbYbkH7FpshlXDe2JyVY3ai2kzQ
lE9U+U7SLAI8UpVzxtxr5pnvnFx/PKXInbGyvCQXMDfpI2D+Hj/EmwmwNicmCe6AXZBgbdK9O4Bs
FiPef7uHBelK9o2IxtwCLKlb397/H46GBQYU3bsNNBVh1iiExeAiYoltv+C8Cj+MEBxDg1dyD3Ny
1J59rCS4Jb+A2dRhTsiawB6iu3imEA/ucF75Fq1St9E7jy/7/b8EdxaFd4uzMIfCPsrOJlbaj+d0
r9Ri1D+SAY4QPZR6jGQYgL85roPC1LYQrYG3FD2Lw8ZnRImliXz9MaRMMVs2QmKvU5OM8bNEQ8ga
DQMo0zAsRA0rU0yHVU6synFIF+3Zc92AFN44skm2esIUayhO6KWuFMejOBn6JNT3zecrLizrepv6
D795FkqZp15naXphyb4M0RysQXW16uwefU6lcFD5+yu6Fob4TbJ8jyQSrzdT2eQbSe1qoQQA3EO4
Qtf04dS3FDjL7jYeNq/9/v7ExQphFZaLoGac66OLE+FLT41cR/itWJNO3WSw1029VjwCe1yIj4CO
uDQRd8xSCT4bVTiOxbur3i3aZocUKlssIk8PUHO0q4VwYf33Bvscbwvq9WcFzYGVeERwCxGvIZA1
hbqf+WIlX3X/mVmGp1GZHWIAkwsD6zb7H/RNLO1MJ16w/1yeXsBEjazcAytyngRgErq65MoYP5ez
y7zfB7pGNIa/DdsZOygLfRDZ3dMpH+bpLnKjHe0pO3MM49LNjEg7SkpY1xSZdX/zslGUJxmH1/eO
wYRzo/JF1yIll+q9M8rkwOXQ0yRX9cRHFL931x7pBNyvWCOVIPlwpISLFapqQf7pn+W7SurVFEYr
QzoTD0AL5Y57lnKVl0RECrU9auf2NApWL9xANK2DrVCeoWePpB0vyuKYnzpd2dReDsoyO/NEk2Ga
mA2U/luE6jDr3HmTDqY9l2eMIGQrJ5pxAEztjWihrhsKCtI70pIP4Iakt/RApYt65QZ8nEtuUwHs
YwYgUgS+DtXmw0elM63XdoKMJOm3t3aiIO5w+i6OTrbQKMyIHHNSLbIPBe+uXo2yEmx+eH5VBxJu
IBLzn3QMhq7T3hIDEVuAMOcZOiQ8sJHGw70O8B1nOXtnCnTXeSvCvP7qDL5aCvCCLB0UVr3lHVPZ
8fpMEJikDCdnaWmepWrgAleF7+iZE2Vyx5XShcCSzORE+ZT3+WuhUXlbLNnUSoE71qhWB3wTLZqV
f8le0YfUX05J93w+PABcDXqGoT6uZ1/O3wLnsm3kKtiBUIYB+GiXYaacEHU90ADgnq2V0+2XuDCk
A94oOtoBKBeTCi20Hm8LhUO8smC1FZrOZRPIRYW5ExG2HkU7XirssrE0kTr+Z7KMbiQ30m0j2EHH
EMQb/xqbwCoUSa6HuPMFBL3P8DscwvxLKoBwwIbP3R1lk/GtSYAUw+utc4dHNQYkkDTAT19zhNGb
+IrUFQxP5Kfuf6OowGfq1N7eWFlFQu8FKefqbiDib/2c52SZ5/FzdBNHgkIlTlMWfkFAHzN7GFvD
VC8gcL8MtmrdhKqAgQdm8YxXBv+vhdqArkjHf3Ir/VcQTqqFZoKxy42LNuovCXTqpWNGpm09Jqqh
wuVhp6fyWC+gdkimq8mcS/CwDf7LS/578eiYTi/LmO7D6YKr5lQMxPbFNxBRAG6Emqg10bIh8yxr
U/TylPaUDAe/KlrPC3CLkU1MuoXSLP0/hiVKRpPEhzFlyWykTWsnLGvLEnzZf21Tm+zJfnWTde6P
OiMs+eA8VyMN1flyX/+mvfF7DoQNT82474/65gMcJlcgDyc5kQhixxW5Kr2wOKNsGR1gzhLcaBZd
ia+Lqxjm5ZEMNZXECpy/g4KfucoGfMOiL1+zt+HHBhPNNKHLOf9aVuBaTCvkSdRJ9voV7Gx8YM1e
R6xhowKUB8zOqRce6eSa6tW9ofkIj+owfCli/bYzb0cnhKMy/SCoawfxNfK1mW16aGRVePXwhXcD
vWCcQtLhFTbehgJzWvcxx+L9qD1+fEwnmglXLg9+zOX1Q3Qj1u9al0EvZV1JYBbAyCrvsS03GTvz
t6k8uoVXQZwH7cHMbXGZBKIMP7cBQj9/8PUQLKze5V+RZIO6Aim4yGjJhD/ZaAChiTmISgvX2kS4
2ULyhLZcq+ZgfHHs+TXFdxDbpxPFikbqe8zsZck5hLz3BCtHAi0D3yEh+EXO8gyWaGHdJ+1Co3dW
Yp/354OfXzjdXTUrm2NtpIL+Lkk47ExgFXTGgWDHIzZ6jgdjmZZHSa8UKiClX1csZG0bRM4Stbah
ZhR+J8GXEJa1dX4+bVuQ9/jumebv+YbmgJNHxxLpd51Mea5kwSA7VObfagzGN494sIN3g0kcuh3q
MEc2vdrxIU6dm0dW8af/5b7GdDYPg0mX5YcgN6JZAgbxyMzQElv3TDhxWPypOBsVCGeinlbeHS/g
mnQbg1l4zCZ9erK6+JZyHcQ5plMmxYdEQ9SOZ2r8cG9MpSF5wbzRcuSTZajf4wxjxsxupkwWYkwS
mLqZsVWgqk71ko6hNHE/+iNKc4nX9WxB7++4x3sGz3pOB7euj2ppse/OLrjiLBIvoHK3QR91JHfv
KEgS5nARLQyvv3ciH1hcu+lF5mr3rlBaQdcbVhymWog9h/J93iAkIyqSOfXT73ZiQZWX+NEJdvS7
NuA58j9dLleFHrkJ7vP95tzYw++KV8cs+8EPUKDQc15u1EydJ4YPC0Rk11qrZNw1H7NS0kSOqNrJ
CMgcKxF8/bpcPM2aH8sCFJI0z+CdW/4NfPA7ejyjoBiIttE87yNaxBT2XRJzT5AvSY1tHdm9xNBz
+k0tDMMg86h8RtaDOV1ojFXmHG8lGmQwKGwYr4PKnVnP/YWfab8LGRcE0ZZR1p5XFqQ51TJnQRqz
Mo6U5C+3AHWHfc59vgS2VGVBKmF7IZ/CJmrkaBNhciMTZS7yXpgA7MElkIpaE7O6U8z2wrzxbSdy
KKwdYZill3bWWElKXQyNC7No592zkZWpoDA/7jrGv+DyOXxsg4FQCjXmqW7c2HyQ6UxNloVcnah0
JczSHJo8AlkNevJEOLNzUWLtlGdV1lD/VeA6xNen3wFCHIsCK1EVaQmuutqzy8Vw8mhv0ixl1/Ha
kCKvgg3pRqfNQD1eJzzwjGEGUUcrOsZSqJ30DMFxc/yfC04W/VKG+VCgCV8WW7DT+5fD0ZdX4SiH
u86ZCGkiv6SbBBXnHYM/yfwxTptphs1oC3NdcmxmaRs83Lp+EnWHapmNAPH7e2ZJQJdn/T7euldN
kUlrzHjFH69LwSslxwvGlMHobXhSwFlbmSzu099yHHianFcX2Cy3cCW9d1050RBoprtXClRHbqBZ
D8wtvsfDOrG4ab0JRMrhoy/7JANSLQUQYKRG6v3GnOldjnRXYAkBEYzAXHComjggLyi8y1+LQxgL
UR3PuLCBteonM6yB7Tm/hK9u7QAnLvY5L5exs7GjHw9q4bVeaUZEZyxaeNocD7vzqPP7b6mNPOF4
EP+NhYgJf4fWcYrmTwdx4GYpKZ1LAIiKcGqzT5+Sa4u2fmemvRcFQheQ+Glo8Uvt5e9KWreVsOmd
MuD6zpD4UdzXC+tWz0hYIXZqRBcXKrQcKLyQcj2fxfszPpOCaFpuJtn15/SwXKjEAO5isW3MqUgo
jlVfKBfNkVGvg83K2oJFR1LcQQH+EsNF+54NwtnVJ5ypCkeYvSac1P6ztQCZ1fvf2wabgdSHici6
70tHMCTfG6bxwDaN3gL1a/g40JHIj2YcOsrKJmhenDSfOKZjAVuil94ay57b53SxrI4bfjaU/125
UQTPK+T8x/os8A8AJEa4fg/L099VJCOnERkklWDTioQOyrZB/PuTR8eKkkspoVOujIQk2qpOmKo4
D1Lx/juDbUc3OCjdKya14wr54iiDZCz6ej7OQPUj6Eo+Qw36MjkyngjT6dpcr/rHZP1SLZPx75n2
PTrGM7RQ6HYITpOMepu3FjJe2EjhqgKnr1bOpIqZ+bKPRvG3J/cp5LBzM3V7h0Ni195WBwzSNAaq
beFNU6goRUwwbE6RZAyaw/8jf4MMo4poPEg+NUx/MWTWvZXtYuOBWCxjEmKMATXunBmE8jplUoEF
sN5LXazPSiIlvxk2u4P67XBOl3nfBOxbkUPpGz1ZIfKQSYOLh99VpPC+WkEobQOGbQ8BF2r7FuFS
1BOYATw4WEde3n5pbFTPyAH+aupaywqmibpGIzc+1LNDu5WVBekP0vazg7pjBgeWiz7qk2G7znlG
DTM/U6TzJe0WhZgF5DS4POCdy5eeEO23dUAUHNPNA2yhzhD5vIGvxA5I4S9hIbPr1Uz7Eqp8KbtF
Wx1CN3Jj33l2w2sZG3NUVMwRRi3sBE7krtC3cE/6l8L88A16rpnaObqQFLsdm/uVnVuSdDJNrOSw
ltG0BpRTvGAoIBW/dLo9gdYFEmTbgippxDTFj+Rns1WnvPMNc4sp21OD1+whp8wji/gkZhtgJLYO
hibKZ037NbmhAALO6CgH+SMRKOXB7qRDnjX3h3t0JxDLaVqnKN7GCF6HuLB+8pZGu0BCGZwYFL/x
tEvIZukvHTJP2tIo0NpZuMzBZxt6mNmD/2M1OtjBKeHQlm+CRBrBWQMounVrh2gW6fJXOrL54nSZ
BcSLGQBwVy0jTIbWQfe8MkhwqnuFNCwh91NKD465vfC7NiiDmiNyzlIIf6ZOcStwAoa4KWo91Hrv
1nAs6Cmnrxu0s+O0hpZYSxmN436mPAPENOCAKBcJUIUvgaNMYjVyOKAJXYHtSC2XcD2KU/elhXXQ
TEDZE85bTUKs50OpEV3JGQbUvvM8pke+4HS95AroomVgeI8TKgz8qPX2Bypd/KxhnHIktdQ+SVcJ
Vu/qTtQsulgV0g2vD1VoitL5Fab4yKhwk6yhaT+PoM2s+AUFlpvupobLhjKNA07YaJFLtRQa2RA7
7q4ycoR2RK/N+sP2Mr3QhH/HwHqe4NcTH+uk0cFWO87+jgsXI51F6JWmrxFuH7Wn42ml4aOruPOF
SwMDOYikfsRwZQsbEgTUgV0vhNfzYjVAJ5gIdDZVN8UuHd79Vq93Y4mrvSlgPzIrJ+lObgxuhQNP
JZOQPo7RTXa1T3jgCPjKo/8YX4Mp02d0HjEcAstoQhd+5TIvvn3LtdMJwntrIDlpcJXWoEuNITe6
+z9fFbDFIZ73T7+SMOIlGCajKw4J1J9fAgbVK59k/NoO8B+KXhK0tt3m9Imyl2QFVyLi/sl4Gh+D
dyociXGl73VrGBdd+h3+WE9hSmEgtU0YC1QfULNXAwAVnuUafYsovnlmqRZTedE9H2rbnEM19TPl
ncCboh6w4qajb5ozLHvdiXp7aw8pb0l5VecPIX1SJh+0H06civliyIUPlM3XPhX7/ewS470kioo6
O95BwjMW9hl/aa0iC7p/ti8xczPseg2ESUE2wrGpQ4UPNgklwsBRo1gRYJNsG3LKOUbQM1i5wXeZ
f+zDbdEbc+svilVQTVDc71yLMtVv9QLvcTtsQV6URInwQO4HVSYe7y54cmmR/ioEwoqyeTR0hHCi
8JmljP2Id87TbM+FnDXAd8xG/OpXt6M1WPkRhrP32a3EPBgKyt0ZGlALjQ5Asas7fDAD+kBAWPEG
sejnJo81KIvcr364zRKhnDfgIZko91Xl8BiCt5v3vn6jAru3Ql5ennfjbH+Ai6jPHyZrdeR/Yag2
GIQHaAqs9iE3LlNvQvQ1DDdZuigmLjcbmyBXD+aIk2JSYnKBpRYfJJPcF15gVwp5OlWXbXofpNqt
sjZEBfpe/QHF/X3MsLTj7c/7tzfPlqXy7lyecmLIKUzrdrNpV3p/iCT46+TfvOETGJQl83UOEj7y
wY5QvuxynorGjtBwCQw8LD3cDCzgFueh+4oJgAQXVWpHLRRqnEczXtHAsTHXO8lBsVCDSZeTI56f
LW/UIlvwTHcpmKY2sAvhMMZKjoXU359SNNiwaOhsKIaRzckGXAY5PAP/Vg3+w8aDGWCgiYNugadE
y2UPOU2GCLQkbCZjWU0Ruy8iJj546pEb40QCGde4UK6IyA/oSMgA3XM50Kce1VrhuD0lPHXXVwho
CIHoesq2w6gCUpRqxBytRY8OtF+vLFtf3ytTj41ALCrJ4o5JXEy4PmYbu77j/eCXAKTCHwrmJSZu
fW0nzoXFAmLTp47IjToOELuwkSbB+hYwPH6qNzxjOh0EvYdJ89RjGP0vwCcgeez3t5ar4Wh53VWg
TjNTfmqEE+QQX3A3hIIyAqHPhnCtOOwuaMv+ERe7OuFxCoEgM0UWpOFa/TmZkxTrEJEGgX8JFIib
TYUZDoJPHzRKC7YznHERD+AIu6W3xfR6wRXapcomQ10wTIQXkCB8YEy+l371+0H+Jrdz5iMktAZa
xt8hZ1ZtWX0i7z3Bvm6Utj8Whq/S5qpPlgB6y3OGXIB0AvTgAJlq7K/2GuZ5cRh1VdGZVFGDHmwR
O48kWXd3xMKsW3xszIUvwuuiEit0mfYB8kAZtuBDs5JPJHYFbJKY2g20YIrTj1WoRa/CCUKb0nzf
jMRG/b0ZIE+gQW3kAXZFL0oNnEVyyCkW8rqtfujmGR+8rjulL2YofGNXpcn3iG0VCneYBPR6uSXd
apm4zW232x5DCcX80zHQwHYixfqwparTjzbgBtz/Ai+H+KSNdKSATNwPEqBqF8j5sYUzST8tUpeh
OVQdwhTsuh+11H0xwsRi9SRTkcbg62yMbMZWAZJ6iGQJ2g9INo3Yf9TDsQJMF6KzkYUmlINXu1Hu
t0DwDP8S8JrDY3IC1Fcv4b31EDW5Hd5PxNaIhS4faPcip8brifdMtEuEDvMPBdF5+tI532GO1vO0
ciMgO2fyCqPNuc0i3aYzJJV9emKyBFDwC5xywTOh3Oxy92YF514Wj1q49yFIUnGomeovYNBnhQ9D
Fwr3aABgEF5zsmR1X4WBEUyuGhbIRE5G7286zCUvsHy8Jx8Rl2yyMVZ6/x6oYm6J+L0pzRduczld
rNtVhgF8rX8FbEM3WuT2h2XXZdh3TrLZx4pNDHLnkXRzBpMiQLR6FHavTTn9K+gRNbxzvDKDgDjT
+8xDIv2jztv1FmnMuCqA0OUU+khdyE+IECmwbDYwVftUED9zMloFpzwezk6Eff+cl5Zd6dLpcA5t
Wkbl8HDmZIBAWOF6qYjBvfWb6UZDxkowr1TE6AbbsOgMVcjkmUokaWiJuBLqy5r0r2rl2MYBmxKL
VnFdfp0p14bs29G6rwEUamE0Sr+12qoYrweK5Zu0ZH4O3J4zR50SVK+E8Vp3aGa88ht6y1D0ZMl8
Aqo/4cHUEHW1nFlo/Axak6mnomEMjlfj/rV1iHph2fCz5hs8g+dufrPxBFmdOVCAriOmYqfJiRgX
uJRCduaiA5iywefmQ5j8e4yR6/Jyxz9AJVVp5Vp0ivPBTqNeJG7KuMsDHweFiAl+iaIqHGIe6vPN
78VaDzGFivmt841i6qR1l92H5CfmCA6etZA0alKdexbb02f2OHhF1QbZbrZMK+Y2x9/rsNU7iOon
L+IFB8bzoMx9wodRywWijFFQljaolD/KQ+K1M9w3uCP3VJD8tEuHTOhKxwd2fZsbVPFYtFZNMRRd
n2LGKcwTgEmCY/a7w3MZcT/ddTraOvcPjnodvz8hB3Ttf2o8l2ma1ZFeqrP5DnPW6qgF+pZwZ0V8
Xg2WuCZJc53ujGrGfpYyoe2HgKj6qciIeAa2uSDQV6Q02VrHV0RaLxPCQgiv0Pl+k+bzExifWXd5
H8jIFeDbxrtMyKgQ50QSa7msBpFTYucGicz8FAyCnO9yTSGWX5m4YE8pgowGtvFs08mCzxj68biK
QVkcWlAxSYPQAwcHR1ol1aNeFgkWwW1sS/K87ELDBvDr6Ejhnybp2da4nScZgboVEodhDst7Vdmv
SKKqE+NYh4HuDa/zVrBnwpE8eaHkk/dDSkn/yR5aoVrZEpYow3mkJT9RPYRLec63si5iU024x5WY
ESsgqXr9yLmVkugOJD2ltBPBidmN4sSIsLN6ZVtGx7HXNTTPyqovpLZCsZZC/tAOpjv1MVL2Q9MM
CqB+m7uZn0M/NeLQ2in9St98HNH5J47rkxpf9iY1h8Qvx7GPBpLOYPnJn09sMBToHAK/arpSGRCP
Kunn+W8YfjYUOYhZrTzcWbi/2zdfZKe875aEJ4EBZLNUvxNxzt6NG7yGUxFPY2bAGYcBzvzmgmar
RLn4++d+bgljZfsAFYy7uumvjkMpa8y0u2UFaltvSL8+ECXpZ7NdzEEXw/wUTAKf+2OgA0QNmtir
hDTyITb3uzg6EvoeQh+mQQnEFe4p7VhVvT48slAs1/cHPizqcbT/I+PETFrUeW02nrs1xgEQwiIq
0QACxiEbt2w3xTvApBlwjRiGM9GR82mqd0VYVq4jgLL1c3ybpp1xxt9hifti/utf1yAOt2F9Ao9m
SIw3C6kMOhwQT/AwwwOUunDvEUJxu++r+fSQkuZxr5lRYo8FNPf2Lww0D3Zq3br6IGAYZ5uzVpRv
EzQHU2Zeb8QJndRRGFR9jmQCCWWBReUAWWMaGpbEZtTCJ92bY/X9663z20/MQ3/z+f7V6J2UT1g8
GpwoUrIcyZk8QaorOpeofjsRMbrFX4h/xplf/ro6aaMtaa0y2KK+z4Qz1GV0S8OdWaztQ/njqk3m
EYcxMMaYTd/r32YCVxizGOjxubyZzxBqyVF9QjiWUqHV1VDA7FzxdN7M1yht1vMmtC3C2dgM6gPG
Pg3ShlT7AYy3vD/W3V4l8et9XfQ4EVaMXeF5qd1Ar+ZT+1WuKDTI25lN5NrRWOQ1EOwd7yrduN6u
rGW8nksVD6+nZSHp+01QLe98rZeqjPShTODdGEHhK4Nb4ulbB3IrqgSA27aBOuFurorBdE3MOoy5
n9cR0OyhUFYufmNPXLKKR2uS9SbhNF+1gdJiJP1fE4XMlnjbA/EMWt+FwUUmNxLArj0CEsRGR9ye
Rk0MW2yTpCmhQ0HtsFUEADHPOSEt5t+zVCJsYb4xaipof9v4QvM2tqWC+2jS0n1G89ux86NFqoY5
47xSdflyptg29a0NoFjb4lfA3656G1N4XJdiPygqT+lgq8OGBE8aJ/Fg0lUDne/Krv9kTGzSd8Qg
XJS/6M+YCVPjNacZfKopdryKHfqQbsuub/A3/RLA2octxWn4qf1s+/VKPTKGt+Al7BF/TwSFxJtI
At2w+Lch4jU3pXbvLoQf7HgqsXODGfIZO+BALYPLipOTVBEvQae6OgBPfKJanjhE788i+p2mVDJy
5ZktToC5Y2H8wVliZOfmwERf5TWraKSt3sFyzex9F9I7ymp2aviD1aFrr3uo1Qv6HtBWLXw46Yhs
ERIaZeenfr9jm/aFc/lR7DJuoTxC0eYBDY3jMf4Y+R9wOfXofGKRyrzcTaLMnsdhie9dVOWYkVbR
yeG23PbEJTCHySD5hh0qu21vTndkcPF6lAHNcV1I7f9J7vDRF1kh70HYcti4b1NKac9MNCi6VRXO
EBOfN96f4XZubIrOPW1kZ1papZJ0/6UlXpw6Ax2nRLI4g+8Kg8ssGgl0duyKIVH/cgJevNddPuNi
2TtLZ0usP1vG5ijCHa9jMV36d1uT3boQQRB0UqNbPNCioVxeZjntd0Xb5DDezbgDKvAd7m5LEYC5
w9GDfiKHbXmrdalwsc498+W7csZQe6+OV/6EY1x+wPfmyWj8GvMpoghlh0hKlSGYEjAn97/BTKTU
bJ2n6Bj7oz8AA1XZUvKUuNrIKOJ9ARsg/4NQyRTLN2QYixxcI8RDihh4m+tUzMbOATSfqJq2hjW1
cQnlZu9zNJ+DZoz8RbIN9bjV7QLsft34c+M3hMJgTlsQWLx4HgeHafrXqJaKcCN1p2QRPuipFh1/
tl5UmJLlZ5+BQIi+ubXVs5GdXqUXMhflmEdH6nCWs7BoFwpsBpFsqgZBu1FQYMgLE4Jsf7XcpPHD
xnfC7GUB5/AC0BXCjtnZI6oQyhLGmmk3SbWVGW4kSlyYwtJji0T1hKieckQ8StEISX+f2SVebzbG
S/AtCMpaWrKi5RJjIit4bNHW/ww+28ZeDUy3GHtN8Ia8AeSd2ufmqX1UFuOaxNV5OW8bIy11hPp6
iMkZDxvn0wTK2s9QpjYagrHHLc3hzEmTXUKn6hcqKi3EB+xu61N23s5TSCMd3HTxGasBPV9Y9LK7
/G8tsUdp3XOuBibZtytDHUI90kHm+UqsacPdlhG4IhlHT8QnCbUWAy/BgddWtsmY0G+LQIBoK8yy
1YRtxAfzAvjf2mOjYoEMm7vQz1DoIO6njYCBF35grcFDwd/J7NwM30riKDGkrTpjc+uYngSziNNQ
gI+goWPWTOI6lE0MpPmEBPHU4xX/tvmxq4XtiEPc+S51PlXRJU5AbhfwfnsOtJ5Wq/Vv7EKu7B0y
JtqmRum5uwoqjIotvZizf8yE2v7O4yjhkcgpCqhFy0kRk8Z05+wxgmDDoh5fMlw9wDLjfUzWHa3l
/F+4OJ3kAvWINB+cGXMAW6Qbz2bo8zg+PHd4Ix1EWLqbYWk3vBrAKc2h0qvScNUv6upTDkoRICrI
9gcaXEKh17mJnFIUaPArdiWeYh4N3YAGwFSaIYjgiC0xaZOHfvUl0Zl2H4d5B1cevW4qQm25ZkGt
050qbzL5SOOjFVbV4SAqw7KjZrN7vHNTcvGPLSpsmfTItGPUiuHmSZyvcU1AyUMEdmNvaYxaKmyh
Vvz/gSyYAH1fB4DIjlbUDi2z9ZMvvc43rE0A9KjlMD7oOc3Y1z5exrMqzA0sfYjl1szSF5tvnTDo
+lF0mDjnAYwxAHYNkGEdtRLL2jZM+o3irK7kIo+ePTkCrF7NaDTTYJEYQF2YPQgy1QTOh3/SuVkG
CSP8L8lrfMcdV/YO43/lCyArYyQZjWS64r3mTa6lfHRriC7cjopnBwvmFsxWiarVbHWQw65cvjFO
YN0o6zVSeG0A+I6qnVmu9N/QAXQ9xa70N5EdWqtwePvea0J+/QdevEei8DSVcqDkPBs8WTPHb2pR
BOsU6NeLkCTN0BHzc2C/DdyUDmRtkRAfthOTJIgNHdmHJpaAkEee+nzGxUJX81q74gkTE5KJYAAI
03UkiYKsiUzOJz6RE4KbVmeQEW5ulNzvNJVhIHRjMRmEJRFp+tLrOWsTrVtyWzCYuIWOmup9NCY0
702LRig9/oZyhkxKITFwINVTTs9lbF/LqEGed2Ipg6NETZ/icR5NnSxQVoua5sZYyYEckJjS/V/N
W77mMYvrpvS5IEj+SX6grWN7BbfWGQfnFfxnhfUBi/FaMlWqiIWgrlsjSRGM6mDbjK3OmdS7NitK
jisN5OxkaITm960PCipyP+YmQYvFx4xzCdwr2mUmwI5QtbYiWna9Wt9ZE1NJn9G7SantePq9Pv5O
6oSwngclh/He53pcvUOhox+foSC8EXV0G90BVnrK8quOBhFlOd4EvhkPhF9+OB8Kqd9x6V54ue2n
pMxWJidhXmAgROF/NBHzYAI1uTMcG8hLlgfo7iGiI3zpZfuDMbO1W0AVeYzLOYobtuzU1UlUGiL6
I4fcVn5J1rOUwtC70R7KvGgAlT3JDnusjczNnw/TZVXfqtMeSy8NrSkp6QiafIve2XfX5pCdbzbm
WEc0VP+HfgbhL94tuo42BFfSisEAIyEoiw1uUaZxZNQiEeyiFuzVmULFYxIPjSgbtS18w561/xQk
cN03WdqWm9XPkyUa7n8kKakN4eZpCLJ9Vz47LZEM58w4Zpc7tGWPrE7yinLI0kfH0midcIhWtpBZ
V5j9stnyUxK0S7MYSBgJFJh0+2uErnhHUSxzYAC7hbgsfFmHTDIOy0PqhCIUHwjSxHvnwNlSj+52
8/XybRI9PmcNkBHnnWWx2kWlILX2RChrPOlsJOAUSU3rDx8b+TH/cqurfrAihPsDR3377wBYqaWG
mpalBBnVNh2xxUmqMwZo/qdl8uNv8BglSBALtxxO2UIRDF0Cn2bZ4TOTsPDrqF2EG0pDCCajPU2U
nr3DZEO8j6FQDOzAS1eg2nUrLVF1f3WvczBrlKyiz1vOkhqjNK24DzUFnSgfBCkVClctAMDlJpQK
HiGKTZ60Fn+EyBAwl+JbQ9w1d1ArmyZ2v5+XCHIHugD2vFvQ1SZsp5BtiITRopjzEsJHEoro5xtq
1jRvwp5LaeB5ask6KburZktQhpzomndeJ/lesxKq55LCEAZ9XVsQ3JpWCrygZNlbXUrrXt36lxC6
sOGBk0gsdvZALjCoF2K9cTIt7pY26aXCaEkWvIf8OXf0Nr9Bkbf6rLTQyGM/JuUBVSV/WCEcC1EB
syO+WAVoFJvzu4CCWTWkz+RCBvNKNel2DU6nqmN4jRdMmrt90TEZTHIeXgC+rreNXqD6RKp7iE1W
Vp8gLewLrpBkW1WTT+/OARTlYrOPv5OwsMftLj2TS9l3zWq99b/StmkrDGQJYMW+n3++xtLSBRp/
k9iR4DS+ef2NdnzYpch+STjmuikpP/ICbsSQ7v9+b38cTD49fYl2Vaoc40qE5SAxKhPAexN1GYAu
g6YOEHZBBn0upowN1Awld73oiCzmwcks0g7RufhE0hfFE1ZohANap2FiU9OqL0RiwirK7xBd0nAT
viGqwydcDmLfCT7TWmyyJe2w3L5l5/A/fMDoi3o1AOroIDykxYjtg04Vsj+islljqx17p0tLpyCc
t/r+pXIiykGx6H9l1ZJyY+kPXlG0D7nXiuDJZ4HaUAw+zLuzxFnDHDGwBOqKjo7VwroQcvwBZy3k
Hu0/eo3GrEh2tnakqRsRAc9N8Yn5VAwNHKldY/L1adpZokw1xFLdJp4MQuG4Am3wA1KZ82jhC3bm
T/2AwkLckA9t673wmL+TRgVSnOPGg/d/qdrIFH+viP4cdn/IuYAtzI2FK0P7PHjuSbdvNUDTesOn
VCvWlYZafkYe4W/ciGgXlBSmYDcFt9zPW3nct7xh0KjNT8FB2+L6J4DOcOGmvdriLazAqKxAOk2V
JVjyDv5L693e++rpOm8Nn/fjYFvgZvJY49aUopEEHJT4EkzjnCp+W8/A7rvofmUgQPhCewEvSRQj
QS+FgOKrac+7HNCy4jY9NTl0Gxh6mQhgjIiyKbejNkI3gMlboykZwshFMKiDQfVNqiBXDfjn3obc
knC0izk+Govs+XRUdEwUd28r5zRGph6y8ShkETqZ1xcSIQNPdPbIAKQuyXvslxoobUcpJYbQ0JL2
3BPkWBahqUvEltUceUdpDZszcjU3SNYWd0w3TqKxMFOddQ0Hk9JsUrj6yZzYQotatiZOhl8SN/fm
evosVrL1eT1ggnWO+Xi21lejeWgP5ALdg24DONhfCyUe9ovv63qsRIZCB70zBWHz5Bg0xEvRgLfe
E11Byn3kdDE8livrYIvaNBOLWMUcJzO5ZfuuUotNj9RBA9NNsK2BI6u9RGelN4I4WEaNvel9+nHV
iM4EIQRyUyHbffVd/HzgBE8b4d1YWqjSxEcd5KF8tl2QKVpOM1TPC+WGWo4wxYO3ZN3/iCjdrCb4
kvxLywCWjLCKyYEb9r0edRQKvlQVDYJSGzB0Ul13amtVnyoW/AHWZDkQuEyjCKb+Tt1/L/i2f0FQ
Q6c9ZEKX/8CfuJEw7fXbHMmYyQFX5lWCQbLhuPqsfR3+r3HZBufXC0WVS/drvAoOzgWOnG2JVRQ9
ea+/q71ncUyUZDy0TIoj3osWGY0YqI5jtdWBm0dzyovr+CmOqUF2iKimFvrW+1cR+zNGeAmt4ww2
pXLNeCKG6PxnzUKLxTAnF86Wr6qYlFQUbVKJ1+CFhcHuttgtcqMKS71NP04aSFGY4ejlxqiKa8dK
xpTXEjnp8sMOSfEVRJOVLYTXMii9oOsecseObDQfUw+hWP80ip/PUCP6ybmUmo+e/YDUa3Wof9fA
gHOj96Zt6+UHRMbQHwRxOJ8k4Nn5erZhidniuwdvUVHWdKjYkh5t61mLjhCyXlJJfwS+VuJNvwr8
XDdGXmdpzwx9o25g893DRyhyGNmWHiC9Gg85vATdG+nNi8Qt+Sd6CUCTewURE3+H67ft+wTU2bFM
pxRt4vrMcWIVlIxv4xGfRfWAiEfXt4hVU8FDVsfWNYk3GUDDOnwTQssgxDmWA4PVSyT2vTV9C5y1
hzDQh27I/cDveXre4uMpHHiLxjP7TkYDqqxq1ycPeI5LUDGiYxpJNFuEwo/bkNhKGePyhiDpyI9u
IMxA4EwYrvlLgVzG7clEKvRThHK74WTl3yxSM5EW7fRmcq/g8R7l0e6TL4NY7wyHc21LbW0b6EYc
E9+nWzzLq1Rfd/R1+Qf83cb66AHRPpvRBsvGOaMDZ3CH/XftbZ9cYsUVYrZSVaQHTRmKFyIrjlKR
mS3wEcCtWlp2IrfNawPs7UgEX54LUNglPXeuQ8rivrBfQ8HvmlMThXkzN+NW6aK6XnTEByVWAZbi
YItGMfdD9FGJq1MrdhmpIPdfRtRiFBRIFAmtrKVwTWoE0zf9ijHHtRSnotmAWH2aW/iQiW3PjkgD
qrgyzpSaYiJRWt1RUY0n4NAsXCIirH+B40brJdDnUqpRhzLGxSIjylifEL0adt78GAf34M1RNN7O
Z0rIFmS/iCb5DtOIehDmOgthlTsHPI4MPacx/md7WZQ952NERyq7IDaS2EwIGNRDD47JkRtYvqte
eW5ZgV2qWMGE/6+IcEoKLio32RPzvRvjt5buOskRiDwU3hCKFeaJaqnGbqnOWS5cJSX/GKf5hkVc
06DceM2F6yv45Ny4RTmuVNtHNu6gD6CmFfald7+43DDk/XcUqyJdb94wQI94+vaT8ExCLxi0bDpA
SD1hIIz1GuyTf3QQ9UPoDKX7qDYejsOr+ndGrCcwgDDuHjVeq/7jXm3NgCWWF3VEXynZ5qZ6UGyH
Aad/XsGTaGqsm7k6sk22EJWr3+VdhDEBYLAvR7Z5GUI37SbALh/Ju6HDd3edUKffdJn+Xkw9TDsQ
3jg6s2Ou2C5qHjhqDbuM1xY1UQUHgykdcikplYNfqmgFrXwDn/oW6GzGf9O6bEcIyXgSr8jA+sIk
EIFwn4NgPiPgru35CxiF0JEQxBbx703HrQcStAE1Dz2U9LVzHniSGQvgFEjAq/OPx2M9HUwUq8dK
fjBAWDBRFiZ6YTtE+bbBdIUdBOFyn7yb2W62vk1CAQ2dnmtjJ5+gK8bz15feYAd94iLXAsgvgaRm
r+mPLlO5PESYJ36mYct6RMmL8lFtms/ORwX1ZPbca2fCnPTvymZpNW5WFGQN2zBb0266cEhSg2FK
zYFutf/WzHSGjpJj1xcXqwTW+hu8hcY8WPboIBI810wgQ8es2IPDcknyfmJ/+y2sB8PCH6OMoAYq
/QXiS5iPZMp8VlUphRaIzUFJ9jEYo5k+zClxQ4dWrlmc0Pel+G0mxZQPEKQ9Lm4ZoP1e4sfDzkbl
jqf/es7q1V40VOG2sIyuUPf3igltS7Uu9aXqUj4J78/K3G+QSGbPq1Ltjaj1ygjQce6yVOdl8836
adw/z08qaDBlVXxzTkA4djst1afjUOYlWGTawu+LXlnGVsTnkisgermkT/ujU3fbyX8glsdiGJKI
xx+u9psiLtUgT37nEkNZYy9C53q+TOENpfWrMFpXutePjJKGw6KPPnQ23FSkDAlmb28PuELrzOp8
eDX4u5ruKk7o1YO/5Ty6piws4b380CVNFxWysTfuqPR1EHGmO/QnBv2HBAJ7IB9gVxvypCJ6iBpX
cP56uvSIjZNcM7EU08GdnzY/FS4xDFPIyDs8YgvquKLJFPXNIKcT6OsZ/k+Hbnhalnci2iPjp6wE
bL3UYU3/wxh8Meb+kuYoxTt11jKU/2z7Nfis+F76IsoYNlj5OMCoMv9JkUF5B4WL8xGhPDABoGRX
AwE2g/E0+jY8NH3DGC12PenLmpWSwXwAh5hbz2ju72XEvjBk4EnLldRZyiWkRsDMd7yX7axY5YJV
UW67ASFTG6W5T8f0U16u66iaXbW3pwBfWMPty6HBhcnjDYMCaoJnYPZNh/R9V5L8gl0Q6T2S3DnZ
Hu2AemhEEN/wbKEUYQezRRkO62uchvob6rj3M0sAV4I1scpnID8p+RAZefa2QK9zOvc3Bhhoc/Ki
lfol6FQXPHHIaKrvek9s98BX1pSYcs2ZKtdM9i8NteLW+n1MYzKZSGEZw87GgEGW1x2HKzgjvuDL
cMRb64eKWNcMFDW1t8EzJ3MIIiCW5OGnMMas5kRe5nm0ScLG7Fm8Uoku+w8ofcolX+sIECjyGtz3
EblxkVRiO3oyJu3oM+UvjavvB3wrbG0fnSEWFwVf0Qyv5CKnTXuaWbrNHU3M3U7hM9vuV7uVaaln
oDBpcl2K0cUt23sOfwDdB1fTH4XAChr8vPXqT7D7XHIumdnSjoRStLWElpyWI9BJ/jBMNXOvmvIT
e1uinYF23b6HX2G8MpOhIwqpZhQWqsGhveyH+TCnvWmwljU8+4o/7wCY/Q92b0bRhrmVEI/zi6JC
NNI0zCKI22Xpze1zrZAhp/rlD9bguQmoHtqUUMskQ18/lAyU3GdYwX+vsWO5YWJ3oZyPKO++7kWJ
ZZ+7iDi+Fx1Tdg6uHgDXuWROmp9yJ+slICCZU1WKzFp9M7lVbbtibB2Ni/Vfz3fLD0++niIdIJcw
Jsil7w2P0YKuqMhAM2DvWXkpIWLCR8TPWZ8p6VyS/bphkhf1K59+hmp/0OlWBQ/8d1B/AwOlSVPe
ChLPjBDHBsL/F2Goy8gVNQCSqcHBTzthuoeuZIHdtcBr5MzU1eI0eZgp7JnAPNQLS9aO20G3W+Nw
WgrR2Y/KPlD2AJ2moAMK3LnSgeuNKFu7bw+uPqYPAUAWCT9//0UIqadXrK+dqogsYZuKllwa0SoD
TNBrEHqiJyZYvmgiRdAVLuQxQmQKKeuC9DRMvV5xBb9h41/SQvuVukA8EeN0jVgIREjYeVvdJEbk
UuVa2smBtzdxDbm+WJZoaDVc4D1AW/Ke7sxIJpQlKAxLxngzHiFeRg0ofqvpnW5zZzP+kaoT2j0P
e1kvPhKGhTgvlV0qS0zuBapplzMOHmcmrEmrr8uF0Bn/ZnOXPH/eKBBlA0hqyZ/TaS0Ur1XW2KbR
gJ45boCyoAQQXUJwUQZP1xM8BgvZQO6fQML34t75hSuuZ1w7NTJ7HTLELJyJSeyO2S/iXag3Sjfv
WWvj7Kn227rQJZjeH1GAPsHR2o+/LHq8FUub3Rdhyl1wriql2Zas48w+8UTPd8yLD4JoBQOhyfLd
XIptPGvVIGVEZPfFSxg1eaQWLV7t6Jw33aX5/Du3KLk4zWvgCz6nIlz4SEYvpoylNPUrP1HPXRh0
4vTc8aGy5mQ1Cc+VXfAfopn02QDMMzV9NYhdp37tHyamJsSd7RFKVOYK+RHM5Ei0kF9E7TzF3kB2
ZCKN3U49VHG8n2+xXaKHpdQoq22848o+85DhRHfk9CF0ZwCdmvPWEh3yfecGZ8S7k9ns3c5q5Dws
zFc04nEhAQOWjgjx1gAa1F8czycqyl/kYrJNwmLJ1rcQp8DmWqhWS/EF4nwYHFmthhpbG5z2vKC/
l4RVediK1EHy/EAioQf6O6iz6kf+lDL1fxMPQk5JXvgf9GZdOxupqtIhtiJcR4iWagA4xMfC/SM/
cFa7ZTrYtblJgI52ykrnrIe55Epg7mUCvlxVDm/tDWg0lZI6GhbqxnkhAzvRJ+hhoxyKHtFGW3eZ
QQwA8ZtQuE2NLouJtNo7KZ4tEOk3O4KZWBJAeykufu9jY4GI/E9TP3/XwDLtvzDR02dJf0b5TFY4
UDcVEzHFnyPvPt2RTr1P4kPzkDK+3CtW8tJ4ursLrsOfqrv0m/M0D0D3E433PL6LqobiKdL0akyn
xV1mX5K71hAP7NqHJ+stci++ai7OjQ/PhGaBGB0SK8IRg9/W9uqmONvwi5b1pE4uqZq54u9L1CGe
16tPDjZl4SlOZ9YD8AVWoZ2/1tARxfGu9Aqx8z2lu1CZgtscsaO15MsF1t9KrOOdVOLaa3tFafim
yimjh/MeIYowKtSooZnM/muWsjZ8D//0/0ozyLlwHb0YIyJVIM6O/UgReywm+FCSAE00zfZvPFUM
su93ghsdRtKw5iXVXH9IBih+xuacBgUI2XcerWPzF9k3wLJW4LXxL0FhfYvb1Pb4PnEjx5cDFL2u
Vi2BIjgcBRK2ybmCRxv90yhTNPDqq1Ay72EVs5bLyJ+Xq1HHC87E92EiOAPCDFMZ9o/EH0LIHOKf
DVDCG8M1Im2sJNHBPqW4iT/VT2oAL+GpcszzzhHthv0DMLG9n6GDa3pi29Sr14Jc3IeOTLRegX/F
fWYT2fcpHPiO3pEl66Paga8rz5fYvp/cJ01WWLCpuaRHJ25k9FFDvM03rPjkxYBOcbql8d66R5H6
ZkDadSYIpHC6W4vZKnIT7LvV+75sohGRNsjujAwtLlnzLKk3Tj1RaA1Eosbu//xWW2aJHxD0UZEb
886jL5gWJe9e6hWQGiSZTP+2O30GzauZwroklpptSgW6ieeJVIYRFZkzAtAOuWJKm416l6GCNuVr
sr3tdFf5i1lCDy1+/JtUeTK8WgM3INBprNjfXAbO1w0pfbTiPRjlEZFCEpqwfP6zumQ1XaJ7T5or
Bko9G8iwG5w0hNrgyC8pg9vS4QmDVhpQ2vSKzfaO+MIfIpNVgRicfUR0+BCpdMY9Es4QwXYFx5mK
bCQHmPEAhpVs9wLA2QGU9vT2ocvcRqwTIleC6jyaidy8Y2h6GYHTfteeDcI2WV9uLa034im5nTGf
8fACxvRzX9DbidLjQBGN0gUPUShGBX50XJ8qhBOQu8I4D5UxHbB6o3JT0SxlQ+nNB6gNiJDUiXV7
qJNFY5ntfEC3HgW3PQYP7dzFvKtK970zy6da+BC+ZDvIcibVdsqNbMu10Hoc8IzxbaJfRyGy5yfr
SWbWlwvQh2wXz0LHNJgdi3Cpq77lZmx5ZtFZuyKVOjGBoFK4YvWlTUmLV41XtGObPCrwxNo/z0FE
tMRdODwZPM7NCdH3SBj8RVzOxRLL5m8SszXOjbrO4EAMvsHivpam+QdJXnzmF8htS5QyhfJ87G6+
OccW6S4oIqWVg1P5dY2XVTe6Yvxq2uBakS+F9iMsN4IvKGiFkq8Y7krumlU/KnXAJa8oU2j6F/ea
y31xoLd+dFpEGjK0fhSvqioZG0iJlVYro1Dim+zSAiGfGRZzV9E4P5xE18kDpQBQgtlaIUKKbdUP
/83nUUAEyBnSWk0yNgjquWcAVgucaL3P0+9NocYQnCmY+mipK5qs2UjWFjyGeS6pVOkwM8L//0Se
FgIyrAsZqd/ZeSgM275ud4eEJoCZD+gcFqHqKPrzRAJ5lBkqH8WuB4v87a0XdP4IrD+qjWI/7nCI
zOG3vR0agaHF32zpnqJX43MTvmI7wmTP7M4N5WqOMkR6dD9Xk2I6EBibclXnzbRenO8RyH4AX46L
U3OoqN6kghx4Q7NhawucDcHQWq8lHBT1Djz0UFRRnJUZBC32gKAxDX9HUa5QtIx0F2oNhav0bkdh
fIzEeb5CaRM4RRbgRgMgzj0P2GFHrlVuzxtD5McBon9E0/TbjXfVJtfcsmwGsS4O6OUUDFJJBwvK
0E6NIlTayYWPPbCagThZtxn5udoUZjz4I/9tVqkGJ8eC6vBh+rSQimYpTPoPxRaw55eiRBb0hb7W
qvqr6hcntV6AV/J5gBQtk8E4tnbiaa5dcB2qxsHYce7VhvhmJzAa/N+wuZItTyTmtOHkayVrM4QI
+459kGd6stN97E4a4IWHV5tiMFG1WMLCmKfNGfYC8PDcWrFc2j7oAxqdXAwMOSgNaXYzo3BR2bYl
bVhjOeURuUNhabfuWRY1lExMQJA2I+K5CfllWi04p1eG302SzC8X/M6ur3tZxnSwRdWrfmOpsvCc
hC1r3d3cIrH5xqktt3iJngtMg+0w8i7lPZFzGilX8MI50I+mTsuCjAWKba1lrm6yH0ACENf7rc7o
VX+nf8gvgFJe58DpMt1AnVS2ObFTXrpfuZ9J4hr+xa8EWWYgiVAIRn5Ql2wagD5tmPfOlntLt1ya
d2h4Xb0WHxlKOqmih/N2/n3C9QB6fTHNgEwCttCLyiDMQ1BfnHdZCbYz0NL/xW8aXGqL6W2S7Q6K
UJ9goMeX3geA1Kh3PwMlgPEKRfm/rtf4DUVXP+842OVBTphKHQZ0oCLxzGH98GuG+8daL1l5mcFj
d1MT4xkc5DPF4Tb+ZKrnL1KUK4VL2ar/AEzxkrLFZCcna49pndDAF/wC1d2F2fE+h0WnkQB5NNwz
1uhkzWGIZZz1CJmZAKn9NYLiz0TKj9n7rS2CNVYetdrxO413CuuPV1+nqyMB1/TmjoGQSWQSRsaA
+Q9aUFniLzP7s+evkIl8M84BkTRBtG2SHYi9LA4zDj9s6QCfpMIYjbNovH3ivgMhrRSI+p1jtk4I
CHVQURgekt25M2HXEf9aeK7u1kTbL47IkRjty3mcL+Ol7dJA4pP6yK/Fi1owjvtAeA1et6iD2GzL
v47SU+aZr5tCLKhtbxv+0b80JWqzdFEfEMPsXHZdP6ux9JrpI3Jn6Bi1zynf71gjYD8whf/PAr11
40+WocrzK4b72hqoAnfZ/gkTsiVvEaoOVjCp9DRAVXqrGw3zXNw8cyEfrurUbu+KXL2GJDvGNlJ0
QuEYYPBAK7ZkcTPuBO9/jObUKarTh1gn7pQ759tICIxb9EImHOoqM4IqtBDsHwTHY3G0nTxSdoHm
iqaZY0HogkzXayEkpgyivwlRcEjvnmWs2ikoSXngyAIpJbNwgt5le7NTKLA/C9jR0r9E2FvoQynZ
nhkRJd48FJtQyz0Z0vj4pTO1ixOmXkAp32HvZwJLNQnrvOMEQ6GjKnoUHsiE0Yk7khRl3UlpCwpB
q2oSGfb1ZBpeP7GKjVc+Wir++olCmKf1VLhloqKQDYz7U2UCMJYT8I0KM3z6tL3YZUIPlE62O7Y6
F0TIfRxSJ4capCInyEXj4w15CFhu2UfNj/SowCl24HezD51/4YnjtJuG8VRkrm/4AvBJEB37gjHU
/X7xpH0ZysynAX8ZytPZJT7ewBwyJE01ZGMPbsOCIcbSOGS9Uiz6R/5QjfcEjSfkr8P6UPBoByX2
3b89b+xtgy1iHL1+xQXuQfOAn1h6qenfrg1F3Tv3czd7TGRBHQT196wtaiPzH3sxX0hoOgdubPep
kFfyjzA/ySPlVEjRJVGjKN/gU9m0d980ie65+QV4eSuo/RdVY7SlYEair/zQe8avCOzx75SUDPZ8
rwOs+TnVgeLyN4B38tMaaKRiwIM0AXQlgy69Ho/RdIjKoGBrov2oDB8Cdupd/QGiu5l/WCBoJFXQ
X7r1jskETQ9qV7o1kuCuN0FJ4UnbZdqE8VQRMNJXoVbMpyvgaAc1hKn6WRWTBNAo7guCEXOqRsH7
qvkkEFAHBykKDtaWX9CMCoRMtKyXMqqzPsjDrfe6dRSGpj76n5Cgtr81OL5FcZg8g8tZav+ZVEDZ
wW0Wf8Li7JSeoPInbG1KqhJ6ADPhKvL9WcAECKDPgYKnwJTW1gP368nKbeQDdSOQyqCEHQIMdf4l
Vq48DONgtmR43yGS2YxrK7W6ouXr193pRRYPvdn7cY/IhATRIcLEa4o+A2Uu4yWj7cxsS3BWsVRG
7EbaNs9U2LzLWReFRuOn/eA8M1qUDzj1Fi9BNcqs3BsHWa3be7vgyMZ06higvI4rhPObFDMg2MPt
ILAwicnGtF7cq95i1gogoM2D2sEn6k8tJgZaVfZ0D2BHIAYG0/ulyX4E6BtHABUCNndp0mV6L2hW
zDnGtH4D6Nvg8cGSCPbjBAR090GOQPHkw3fPZpXLg/cRg7IuMoPEH7I4GlSVLzGeSQPJFfqn9hyA
XWelif9JyEAqRoGP7Ijm7ueYh2cVK0QZpGvp4YGUb+ABaepco99rSGnqwL2kJ4PIpr5tV30A7/nz
YzEUg7QlqR+eRUfj55RbfcxPCU3waufTydY19P/ftxNN5AdeZPLx6HvGxV9EyB3qOIV57WgxGhYv
V3ohBGQMy9MUe4vnPMfTSB8UX5wFNFV8RiMvIO7eNJoL3oaPZQhvQDIAkOdiyB9JMn7X+TMJFiL9
v6JvMD6ibX8AXxWwqVIg6z3ZmwsrkzE4e0f75ixoXE4MguNII1kv8qGn5LDcw4vx1+GI+ZRoyvvg
2FhLOgopRIgfgEZR1XTBybIDb8oV4jxGPnMS7aye8599h5JapjNsD247sr4zPVJK0aq2Sr08I8HL
1Ulp2JP5olpwIHNhxKDusQz9xQrA7UEIdo7+iFLPwgCEtBHpsugdbCSWRUBUEHSXJwkijslHLupX
L1fh84KaOilUdTltHXmVFbi5P/yGFVCF+aE6Tf+ut1zDOuuNqU0EobIthZcOkdz46Ifn0iW7e9DE
VwH0Ug1AM579esa89N1QetQYikh/KJRINwL7FwrV8Wzu76wjzqluYv/S61rsglt8JCynZzkTfjO9
cONLjJGAI2Z1+L8stLhMr5HUjUFggflPHotsPanwuPskWwAIiqAwhxYxuGWg2SfziJdrQ4B7zTpZ
zJ/iMo8ke6EgaqQPLXUMESeglaMNeMIELHkKpeFL0b4kexkLylRk+XaxEkNZg5GQX9I73zV/t662
d0CP4358PAw+SsosfvN5yGVhWPRzS1oerfPneyB2qipDSaL9KiTu1/YSuRG7hP5QLPkHtrk6X8iV
E1P01tQTQsqH7vKd6x3mRIdJmuiGoHu9/5oSwy1Goaki7QIxG9vwYXfNhm3JZ3fAwe5KRSuj6gw/
G2f/4TwMaAj3iCXn1zwpStflGiWDH23osSf5Y1hMp8wa7QJWAJlXChzVuStXt/4DfOJbAGYLgsLC
ZgA5Nh5VWnTIu++rUa3hNd5Rf+L/bxKGW8Ic9MMJjuvW5RoonnkanmeCPd8WC9if3uchSovvPqoR
KPfHhSU8Yuqcl3otYAmsjdDxxR+6NudnJe8w2yz+7jms75hU39VZj6A3YgAilPkrxC82lCilGNZY
/LzXJU5BIirz4Tgzw63axQcI5BxgCuMq7+s6z6k7bdGQq+H7GyeKLoOJVrtKLvL7HkTZ41ZldtyL
BgRCaPnl/QcUlnYlhzbrR35eOyqeGdTALmsBWze7ANtBiK3ipcDi9kiax9ovIKSjoynT6wjVrc74
nId1WfHXvxUroeLlAd17z6rHhOjGNLH2JWqcfQAAffFQjaoYsD9LgYyl5ETz/FDWWoclzfiMJP9b
Z82fZ1L8mE5vq9gE6M3jJ8YpVuYkME1BxA4BHkpXqi7oMqTICpUdxOrMgLWCeOs1S8iUWnXvUJa/
mc4nGdSXNUra1ceLFH1HMh6PJZhJw/F1iMTYP6/rUz8MviQSsAxXQ/xoluT2NPgjeeT7lbuQiWaR
vtHJQbpn+JVViLTH4YBdV3FHFHXVHoAHKeh4zy+rGc9wjWHPwGlTSO90iZjUdnKViI+LMDHG0iIC
Cy8C4W3iAs73ZyyoEHoKOBRia9vxR6bq5G7BkOQqGzslhZEwe1WsW+bV4/Ug5WsNi45+jn4pR+bR
57w8Klbs5cpCNd0miYhIDmAXR1/l8RDbJXqNtt5KBgT7+0u3RkxvVhDVwraWQ239E5gGM5v0Vccn
V+nVNM66YE9A90cR5Rtng2A+HdQgKzMNfttk46hpHv3vEwWWyFVLvnR7XbBV3i9q58qUeocLkYOu
vGUVP8X+pB+CpJUeN714Hn92sDQmgq5vCUQPEbb6WFOPqtnIGhJwUYLb/BV7U8CAsXPltYvXbbP8
AL9r6hnUCjVt2NNMGx/LJKCUmEHOeoQFCb5poYNoFku5iVw9g43MnBfaALF6wqfJJiHdK7zUDzjS
buVc/ZjUHs1pwA9PNdldWw2U8o0CvMP2wCgJd+jSHMzWpOFI2wjikRaLsm104ABymjbcMde8x2IQ
T2zFnZSIP7YVFtXEBOSdLY0mRPAS9yd3Hg1KqDL/4q/tS07Qtx8oTlLTaA20tyfA0+KjcusQ3+uX
Ze5ihVMpe5ulxdCYHjH4t3CUwiRYWVIUX7Yx2wLXYngmmbgPWXrfPXiY/jahV6LT2JV9ojcwq+sp
MXfAMrW6T2uL5ZBGNOBrgP6Ry4ZqpnUOc/QSTDPekjTQtzSaWrzxP3FZDTAmBEdQ4roVNWT2t8VX
E8Z7QTR9Mg8ONGbH7vA+9wuzX4B8CHEAMOi7i6mYHpSx7WlYDQz+dXujkAj9rmxKaDLk/qoyXqfE
E8uaYBNZfAUePbtcBOWuG8mfRgBeXUvu/q4Wlat2o+1siwVxmCyY5b/ZwvYYiM6l0jpgD5aAwXvS
b23NHzY9+I3c9L1tMGSS/1jZia1y8EzeOWt0PqZWAsdw3KNXnf9vQKpcTUK0U5oqqRL9FtPDFy2H
TSwhZgbttHenfSNrw5AZHz33Lb+WzsnyHVGqRk7Rmwo8vWTSzbJGu3JuLWP5O9aP8kRo6gt4Wu6Q
QuXK6lDSRJ5JZQhARSfDRUqqDaxylFjbScSgpOLAV1eB4qZRcKd2fH7lMgQNObMUpEXrrdhT6uGA
T1Hk/HHCuSoZrNnTsrirldBXhZj5/tZfWhWC/s8BWFW+98VRwapYjU2I/avrjfsMY1/+I0dP9j9F
r8EktSU3zT6N74F55P0rINOndBXuX+ExcqaZzAQBmDeR8LQRXzqlr8s9ALS02QG5kl1xsgxK8JTs
xlX9z8h6B7UWW/8gLdp2qPfAIDD8HDrfv/3KtXrnlhSgXRhrO4yPKYfkaDTlxBGTkHho5FN5QF08
suDmSbP9LsqyMYLsZExNWgLwR+DVj+W62noo4EOOISBx0WsAaJZEUYEwgLfV6tOq9ndwQRLREhMx
WT9GhdaisBSS+IA/c1WB/Xe3fC2zltO4Ein5Oiev1vfU8DO1RPmp0aJUWOvrRbpqtdUawdE5Q36m
r35r+3ZwjdeySHHWVIBp4DvSUKaqaOE7n4lIRJ1sWZUlBRlZPR/h9iNzZHFW/tvDfEEDJqtzWFMQ
EXlhmoXYl/Umnfs/9QeK115Qt41mIigXwKDe2ZN5bp7VQhzPw8ych4cpAJXvnSGveK7X89aXaGgg
JLGxoaShczNaqFO3ypI08hk5XZkVQ2v1zGi9vOQmLHUgXIuY+KA9+0zCQCB7++xx0V1Wr6fjLKHh
P7yctE0goLDaPZL4SqHpbOekfIWrqzD+tGBMwOLZYMxGL7OMQEo/WW4v6gAmlnS1W2ZFMmRHUkqL
7LNWjt/wmNa2a77Bb1AIfjxRjQTZrWZz/O0DMbZiO0a2dBLnb1ObwaDDANJ9V43HgA0B9zkCsiaR
TcW2RS4TXQrjgopXeXJ8IaEd6Zxo2kaOgAo/xQu7y1amBrOYvyvmTNmN29LkSugnywlR/TOnQhcn
RLytqBHXWvo+NX8HYyLRlENPOqTnYSkjj47ZWIgndxMOYFzwM92adLYk/Z/CB/yymxaw97Qm8/ZX
0eg993ow2QNezP1o6Jm2a0f3behoFDuFFQ8LYA5bPHcM7ZCYOKVr+UWUSDIaRke1kYA1pgVJ0n7A
h0eK1Hc4Ga6JtTC6G9lJGInx9RUrtXBHQKZLbCMg8zLXIbYmMA6ADExp75z0AnHWBdJDaWKUFrgJ
+Sh4euTeAcFOVc1gWoocxWQxySK1NhQE8sd0NZ1aSTj99HagPbGjYQcHxvrdprIxWU31k5uKMipL
o5ihYT8cGuHnLsIo2ZNq6asq1N9UxFm7n4lwXTfaeKlc0zwFXngF0uZgV8GIdw6ZEnKC0AAT5o5p
XFyYKtzlFo33UVgVD5WNETSPiN3+y8/RjPdmUxvCurLMpwlndbR4Lx1QOVH+ml9NkuLij3iQstXI
S18H4tzgi9VoFMWEufssOwaJsRPwvkltapu2maaJDly8DVQcUxzic5u2bTbOT95fFQT1qxh6rMRk
JRgte238t0kJq5cg1yZPaA/3ITdgzHrymCj4Hdz5eQOlNhJvtRg/Zw7QbZOFeeP5bWF1XiQ58Ln4
/fXsWqKV3IlfubZevs4RZMKVhX5fSS7L0KQLic3JwWZ7hPRoMy/u6NPMotGzla2kzs/FiMcVdml1
iTCaxWLerZ33s6IVlz49+AZJ/iAJimIj/wp6b4aLs7cTSCboBNfCNJOc13ehmx0uPDQ/UCJ3u1jS
3tFUILwpeDsCcumIzUHuw6b7/Rfq3jHO9pid0HJ8lYgd2KcjCyo4Ed4nPGM1HAjGG0Ftry4+ryjf
Sm9CW+gAQ4m6dfS8PZycmdlDo5mZjL42Dnw2PauPEUVxSbd4xF8pYqePoMDRD8dQr/LPSdgjXEU0
3LqJgShiGl9m4zPPN1uSi7gNSc7r2YQpCpHGmm/DEZ6s7a8NBzrZm6n90/BKHMpFScFl6BHLsnmc
f8+dEqVX3lvb0pWHCt8+s415mL/7jce3LiWEvBe4gg4s5ryph41DdBOKn2Rhs5X+1zKJXpocU3MQ
dnTHy/TuOEKKoRuqCh6eqiihme5AbP6uMekpB+2q040Fui4DJ9Kbv87/Ziz6yssdWW3GJ4m6Fhd6
xFGfWCW7cXr5oT0e11zKZFQ1gRKHeCPTLXMQafajBqTd0u3oyPy2BzZ+2DKgLYloDw5PEuk7Li7d
WEn6IUQ5EeNz2AMANQ5ySqAxOxuxNNI+QcrH3fL3lvYKwSgXNao/fXgYu8/bqXMKxppHoDdq7+d3
koHUX73gFUmawgroypMSzMsfX0ArRpLedWKjE1SEf/VvmdoaXM8sqEb6PqEAAR72KGdwSeN0/bZs
gA+vH3Wo8Z5AzHQ2elxD0UzavADqyzqblPVc/XfgM9mnEjGDuwwaQOPf4yjFZ3av8olgvzoYHxXA
Rjx6ej/Z669FS9dAsKJKws3sJNawrVOd8dIjjAyZ6rLyvTeABqaMAu2JaxpuY+eRkEJhqPstNfzx
kG7XS1I6J278QlC8AHT7rqXACEP3kLNv5D9lO0FcuZTaD28hJmvWuo3lN47cpAOVYq4e0hDEGezc
Cjdp3CDFjPtq2FhE4BvpLDqM2nwdiUedhRSLW88DxCyLKp5pz6YVNTkVTW9PgjwjMA1bYN1tz7PR
UhvFIvFvccw42PAB3Ck9ymJB+iYV2fTLkP1uJDx/Dh+dMQpu8A+YLxcV62qoiNDIMGJc7OM7WiaZ
pSRRE+dKCP7LsgY4hdqE1Yv0NQGY0XnEi0dUOm8tAoCyzBHtFMqhGqpBOvz7ILj67SNAzR/ClQzi
+fppJk1dGXYOtDpeavDUFDN9LuWtIC8SSG5vmImGJiAfdwsfpdK/5BlJH+GVI3H+uhCULR5IHK+a
H8GuulBJVTngUuTgse+aOFCjp4qi9BOBuBgD0abSmtpVB5zqRlktzB3RGWLumoc6RSnGISo91O7k
M2LrHNy51Dz53hsG2aFvaaHisHr0ZiEoW4uGD0ibLI/fUfw7NHKYY9T2oDG3N/Zapcy0yVoCIMUQ
esrWV18JoN3loDaRa0j0tIkSefsMhuoRxrNslaAtKxk7t7SunQaxTBnDD7gjYvlEuxnUrjSoWUn7
i54uxluyPEBqp5HB0mPyHfOTqoEeEndoZOWm42k9B6l/JHNaoMlEHhEXPNyDAIns+mvZSAs8QW/J
TsO5koeu+l80m+1/4HFQmQLEXIdJ7YmK5dC1L26csnvVY6LKZKU2YDtDMUdVQdqOTvCkJuNWgVGm
K6HruVqXtAPkG+TiKedOnUNE3bEhTiW/II8SdXpPjGKj+Y147fq4mPrGxrMknR2tiKVji+rfQTK/
g8Ljwd07uohdsKgfikOtFJfhmF7t3nqTTQOAArCEnWFHc+cykLmJSYeMZDZ++t4O40OwjXOcamdW
E8RIcijyDa2Qzxrwq50pG9y8MqeHCJ3mTB+btWgiOG5AkAUrzKJdfqMSfZ7JQGoFg3IbptayQ0ba
pAOxjuxFA459yJNFeUfxXm7eZEidXgBrnrm8ocextH2VF6djJRwBxZRdmS/6+m1k8O7cYBNkxL4a
cNQWGiZQtMc0faXU52nJenr2FP8rmuRkGwiK7OBMz4/JQxVoDYAY+qb4iglhStF+TuJoKgHosd88
wXypEEkpJXXAaImkqfvKV0yPMTQj9oK06+3FdRJjPTdVx4VicvF+Hpi16dwdkr1F2KK3p/vjRliY
NVmOkKt8CEuyBw8Y0tJUL34GcHSwMTEzIMVy2qk/bGjAUWO8gV/S7UWov+xVxUPpK6qmx+wAuwAW
FRlXlmAMHbLr8KeQQcJYPi4pCC7B7joTT4t7uIbcfHh873wKOknqfpzJWALcYfIYZk9r2f7oz675
uAuQdt1EFgYUgGkuT5ppFBvT516b9tgB0bmK+ahN8fyU0aB3ScStv4UuG6pyEkFbAdN81mEQEPar
Gmnadc4/Aw9HQ8k8Eot0P0SS36+ffTcb7Udm2uhJDgNftdRLe+ncoyog9K2I60LEveP+Q+H5elHn
ku4uyFawNTZtS2Zh5WWQf3h4+vfBCoThGIdCaxqrZnrQ56PbXX46sKVd4n2/0toSGtbAx3+eSKYP
IdgCZh9fgzn1vHaRKDSkqJ3ciXPjeiDUgTMKwI18LlpH+x1lbrgZiC05H6hR899IrY5C8BgeKF+r
sj0C2fgIycbWVpactLBLU+vxSVe5KeweHaNK5EphynEC5fjDGt6WjZB+WP0zoY9eAposUQ0dryo/
kBUxtAUTanpwI4+qQqGPfeN57ZbnEAqKLIgiWthfY82wmTTpQKtNrbQuW3XzsTynjmRDr9qcrQEM
JSxUenXN6XQ0ycFAFwtLCCL0C/P9I4p5O0nTYg0QOds+OOilFERV4O8caIMY8kHTjzjR33QHkOTm
BsNg7HvMkJTOuflDfgyPmSkHZYy+t7OL7j3vJmilKU0DEVk61xr1m8y2LS8z3NP5LeYNXDH0BHR8
d+yrwW1Op24vqHVsbs7/TQjyeneO1mVVVdIvKSx2k/iF/WLfp2E5U51HQFyqdEMjts7SXpnuN+Nu
F62+9ZMtab6/ZxPeApzbJac6PeEYQWOfruARBvgxv2A7dqC29QTOVRhw/IRE1i6JsGi6N6oNyfEc
gDPJeWd7FimrSz8PkZKCcN0amD8MhAQktL3m9aw39vfShGKWZn+QNwN1AlSvrza38hJ0spPHD0Fb
6iXyM2bDVEm89TTcXTj0PDUy1GPkQ8Hg3hgjgzqtm0jkboh1WSg9VvREUWHh+QiuWho+j3JzeJy1
EGbrarI+eCeSJj7gQ9+4PrC/6DDW4U2gYiGPBQ4i3wN6CR+YRQPzmvVlm5rzis4dUCdc7baZNhxG
fAmqsomMQW2fN3TgsLT9GYXdkApFHVmKZjm4bT3vASGOCcc6qk50YZcXYTw0VPRSyY0bjMCum7J4
KyOYRcfmWJgVmDkxF+dh1iBMH+oYpQgdRZZpQYVB/uiCoJAazZLfR+ATTKmuQdr7ePQunBr1ewWI
suvOo425S0vqpYQ9GNjmrG7TEhXVlbS0EbD3GPDy7E5TokseQJEmafVjfs+eOfQZXGnSo0zDMesl
rM/IatuvhdM4H3m0rpU4FCXJkFeq+LvXiaY/rMXEGKsamSpfeoNvEHjoAnPGgjewPbhAJgsTQHnX
NkuHaudryjeUajDIupWVbMhmuLTN3MpA0HPvvPA2kEzRM6YugPAlFiXg85nrYxX+PaB5hr8iNhqZ
RRm9xw+1Mf21KoDQhTCMQ3rzjunee+CINYz081r1/cKcSQ3Q1d37meBR8AmQgNvJztad2oUvM1p/
zWjfRyUonsHyrfTPbzYOEP712m328TqqO57h0jOQ2G4KCRaka6OTdIUD+S+EzvBMxDr7+loFSPcT
pbj3jt0t8U9Lz/sDcMBaq/MDfEmDBgqgGdtlZ1Hx5CgZPxAbVwintamnLqK1Cro3qn/M46qtFwFx
Z6E8zgiyKQoQd0cJpkmeGpHPPxnpL0J56EOX37aD60faUVOT2AQTf75EasCWvP4Kjt6BhBiefVlq
pQhIjxJibks517i0Z1GHGeoje75dvOSKxf6TBq2Ywq/cegxUH9vIfkUjZCulrgZoHWTCbjYKe8VD
/PZN10eCjh9eaXEjenxlDCLaIDGenaL4QVFrCLgfJ8LxPWu/XJiBB+iZmLzLfiKNCdK6Z/8YahE1
bTbSEtDCzJJd28A1F0t1x4mQp7jJCkyU19+uXW++ZrtRemTnfvAWPDRmRFh6Sl2UwdtugZQYOeMA
AYKRLptc5oNpCd+3/wTzWQodS6f2E0KuJFcgvEQLRcDDfi8aeAu3kIUmdQGM2qO4IqUCQN/Qvj5R
MGk0cbf7WvUrG8hcnzw1fvGmoXG0dTibGSboMbruDUs4XjhtRg75vTGphLPF02/R8+j8WNcvif74
1C2cb1oyGPvnyRp6lkmmk9P0203EOSb6Ql4gMKaw0bd/q6YAONLTILzrKwSP8yse4IBw3qRcrX5n
4J50U5Pnm8GfUFvQb6OYM8dvHA5OtLKQCbmSB9o+gAiiB3rnlx5B9LXeG+hD7P+fOVsA7yMxS5dX
58SytTBCb0syliEpfuG/l+v8lx279Bz4sq/LUYOZaFLTkQJLA9NobsoqeWJFx2tYLAgFHJzxMXMc
faBYzQ3ciN3ktKBstraYz8JhB+YuluxOUVJ5rEOsqQJyI9z0YI21eqto7waVhC6X6gLSDVUXCAct
eljj7rV+ZC6whb1ljw9iaRP2ObW9X93OxiRCVhTKJqRVegiPrAEOZQ8oZPNp7Hc7h/4JoiIoe8Ig
alF137iv/asv3LNKGB+vVXy0ug/CFfL2OGABu44FsDjt3sFQ0EAiaJwMoGr5q6qmvBxUCvuzfyuJ
Qn9TwUxhTYsW5+Vx8nVsYP8xl7PKzO3q2VEzS3X1UolYxm1oQyuRt9tDVNUiJtgZ2OXJ5Cby92B7
nwhH+9fyrE6Bmvp6mMgRiY9wCHNrzbxKwc3nYIS1mY4sKTeW4XSgwjteg2idjOUWSaF6TcDWLj0o
cekeRNt3ZgW88ssJWquyS1mecJGE8jayIXEXbmW2e/X4hcOz5tqvU2zSQOwSuBaZJgsrQxiV+rml
nh43xtxua+LhOMuzk0WLCeZcNTdcak84LgSNIqXpfUkR6p6WHmZMFfms/JWHb8MOo5ByoHK+BUpt
4bbTgjs/iHtRMhagP+IxmebMqGrf2S90YtQW/aA9FveQ+ZZRU6fMWZc0zTLbwoGW17jwncvnIKaJ
DpoZ/jSW8tFqURsYCuaQmCOWF6ftmE5lI5I628ODTqfcwCFRd+rSt2mwaSLv2RRN6CT+prdnNrmO
iu65BmeAeWQ5diRDApjwj2S4wEViFizMJQ8bjrCVpq9jioN5s4RONLwurMpZ333qoqbPhtxc8+FF
mwsA5THx5pVpR1cZbR+zbOBwHfKx6N1pMNPI5MxbPVUd34LWSzk5fGlNALfV4dctQBUnRCWXSpHm
MeL020HddeKUXt33SdKd/3/6C5fe3yJv71KGomaZ/FlAgZShXnNQbwfm0Cwp64BBAftSptSUQclw
+WAf7wBLSKqH/+48EanlzwTThFKGGUS3C26VhlFwjmPNF9N5Ae9tni79hctAf2gI44FcKFEBK8FS
DQhtSFtkB8k6Ns3ZDPnpR1OTLznTL4J42GIZnnxEeF2YKY2xtEN3Hp27OpUJ/tWda7caVOGhgFes
M/X45kbYBvTDdwts6frdMNTjUcVDC/tes7UBQW6K7wYunn2hscjcWtxnAWTG4o/WqFLF74Wk32C4
PrvtyysVlRkhXmbyn3E3tpRx2EqJoIt0ecPQhJB/SVmYnwodnuNC/NfuwOa62ulLt4Zo9T2hqcOl
kFVsh4OFr3LMCTtzYHhRsn5/JcTCjFEje5D6sI7y0Z+j8suFvsuEwp8JdKhRo9qGJObLuUPog/OX
AgwOUmf/jrwPZmkgfEwW+UH2IRxj4DTuI73wEIKlYpFHli/sLZuPse9G5d88WmjSXOgyU5bBEkT/
WceOXu//wHYQD3P/6Zul6y1iSQ7vcnLdR/JGHNBR5EO95QVUbVuqcn2JrSSk5YMkuFfN9hj0GNij
ix9DPF3RUvl4wizDwUZXzq/uccuTt5X2/MKXZtd3IlqDdE7XycgPeJRMKD34vV4aKGiK0IlLrmG9
ZU/De5WsMORJ3gqePSqmlEIF0bgkK086EkZG8kZYTr1vde/yu7k2O0YkttDj3dzDLURKcyIWcDV9
Q73C3DnaEWa/vR0sDutd/EXAfDJW1DNUp2cSq6cDf+RXYRA4kOCS9JdbxAoO+ME9vY00g4QtpKYM
CRztW+Dcejj3BfmJYVlt7U6c78tAIH9+eSm/UHCr1F1LQavzIAra+l19JuZfyyQb9r0nYLW3fTqx
T8Mjbh2cLNZ60CM9W8eVY7jurpZbSd6qv8kQ1Hy9qWV/iiwLs0Bib/rcSFpsiZg5ir/r/11Prrdk
8evrojFJhZtCju0g2nliTi3N2JF0Smltm/1py0d5sW/cZ51yLt05vElA7tbq+GF1qhyUnT9lUK1F
oBMOvrDwEsJ+Go0YSEOQ/V8ldxlCrCNef4bIv9kIJdgCxVyKny2FKXRl4w5O2k///qnB/1MDI/zE
N6Fk62iJSnO4uHV0BGkjsRPja5cCDh5JMw2iYyfRiI3l6o2HwnUuyaXTMa7fgV8FAmkMlJ4jbv8D
ZRqkFaCpOZINH/uRYRkHms8EOJRTe7hPx/YAcuxuKQ+0l4weHxouaIrP1qrAszWcnadErc1e4uh+
7VvC+2Hi9xsYY1dfIo1ZTIGLpZsystN23UDMU5xT1jwI43rbUq8y9NLNBma+zw0VopHl6TwDvSau
s46WiSGy2kS7vx6pWgc7oVU5JucgM9CjoBRFMUat+psdfInYJjapdHzUtxWCad5M7Hg2jO8Hlh2o
6K6OfBZJu6w1S0Pp448tVHZL/lf47qhWXv449Eczk1O4ZmS+OKWsxmQnyTcjto3DkGLSOp/kZi5l
aAeLdLVPrBs6O2ftFODzPxhi4/hfOg89/aPqlP0x52PnOE7r70+DrenMgbmf/OWKNy8ZMLDWzNkV
sMu8FNi8t8hCUhIxFiLo78+kz8qEMcRhAHyLR15VxiAyA1AGOclifjYfKkFfcsLcoWHjjD+3/bWy
WluBVjUWTudPnK9kwIjO606ZLOkqWv2gCTl8cQkp6aFa98A2kf2oj6i3tDTb4yM4AnzSKC4FzMZm
U94iQa2D6zOevUdvkVZofS6gKYjgWVJ77pMHg2uVw6QRrBGkgFBFXhcYg2bJJlycxJsTItRTx+cY
vDL6g6Bov3qRb+rgl9vycnx8B4gtYBpt1tHx3XslLPkvIgVNg2APDyp/yjnG+q4SSdO0uP/Oh4CV
1vKJCwHbZ8ofwqAFDRtYXjYa4mvKzg7e3TNjz9m2GRYEySFck217Bytt7RDGhC2eCLIdhphELTqr
TZHVqFVqwMtCHpDcTZuyxl5iebm14UVvk+KtyAtU3Eh1s/EHxSFBAlZfEiHj43MLFM0W0Hzh8iUG
94n6JolHOV+eN850IU6b9Ax1ldrw5o7PdBWSOuNbH2MrCHYuMyRl/TgKIsINVe+KMllBvQaBjuHo
k/R7UZ8Als6yrLydiuRUOAT20GpxOvj6P8/ekgx8QTQs8kLii8nOI81rp39o1cNHgypgC7zFPeSK
tiGnkhSrerK8LwTF4jpaJYb8EQhX5pEZKS64zqNm/3WAuMu3NdEXAqHtBzdXsCgm/ltrPI+0nOu2
mNpB2vc17Y8/5XKIKqu1+7TfHFzYjykMgSq74KN04bhSNID+AR1h+TCmIHUIorWRWt8E0Ui3WrXD
lz9lr6YKTppAkK1SqwcbwolLhXcuCsxpejKlZW1uaUsDZIu5g4XaczkhwTvju3Js9lWvH1nmz/nF
waSnTqasC1NyuL+c8QJr5p96OYRKOVvTaNoADpbuDwGo96xHPdwYZHP0UiHfy0p18EFIKNIbel6c
1bwrHPArUq+z0FFPA6eyuizvFJZJRVcFBM9D45+N/6yK0qvjT9jq4lTxbgLtqjDLA38Q9+KJUKhs
WL8pvYrJa2yr8yMAqf8dhoSSs8djpSu0WYIvjRDIjBt7RTFJXj40aUlPohSyxhqNKH52EDf4tzCj
HIY0UjhXcOQQMk5gOHHX8i52ThpeVkWHTTTCH7dA8g0HE1xIrsKIKN5u+Q/Ic3mS/bfnvikrF3Gx
RYQy5FPIRPGYxkx6JT4CtezCslCWVEj+JDEdyhdhnciM7PQ21NWfK2yoOICHkSkk8/Zn8jYtI9Ql
5KqyvtBaHKcc23InzwgCc3nfkz6LxiUWkZB3i/XPH/os/2kJR6gVwmPkqPdgpeTWOEwFZ7d4tNhI
qOcyxSvliwZOfSQLDsiwrWNWy53nohfKZuwmEIKutcBD6uhOmppipIj44Qx2EVNpijSuuDO6+GUE
AN3FH8fG1crNh1mL+C5v+F762dfeJPyaWFD1E9969wja8CgipYSRKasr8qvMw1lpS7Op4huwVA+v
RsegNHaiWpbDYbbeg4l5YfPPhsXqO66ka76a7GNq2rI+hRl230BMW6GwvYSmyEsCb2zkX7yPBTMU
wBdkWOjbvdkXRL1mnGkFXULR4URTEjiU+q37CRgxFcBKhhs5V5Yvj19mcBfTZNMPCJWXVPFH9b4P
PYAq8uIKs/mgsJ3gSqyTP8IF/vEs8fpEY4QKR9TekHEtr7XfOdxPaH2ynbazN/b++YbiSkqmBIkj
urD+7eGVvvOuiyu73NlnhO2xjLhw7cJ6yz9bFHhry2D5eWbNrC5bUohEpXssRoeoFQ4JzmX+JdC2
zBihyh32U2hDG9wpQ9WzmNCfZCdUARUqHKmzYQtIscTk8objyW1x3wj+r0XGCFkoNwWL8jQwmLUZ
fqUG6iNOooQeeXyn/5jxSqyLD//Y5SjBI4dxRmI0wlBxFDoORpuzgStZRys3fEHr48b/DLw6uV0i
ZK5ofKhVrpURfLqunBP+jbHnd+s/pQya3SlIOcRzhjZgJC0Ib9/XF/2aVQZaAvZNWW/VJ++lq/H2
vE2kUoprsqPF1OBIME+vd8GFlYNIF7XRemslwI68vxBNj8uNCrAXrzRLlBFHs9W9QvBeoaxg1OfQ
3VtvCRFS2jgjLOAlsg0mHgvvbmR6l+ZrlpzJyQ/uK3ydwZ7kRDwMwoWHyzcQ4Ps6iiV4ctzUHoiY
e0eLkyAeogiST6FO1S+3cbfXzo7m3VePoGZe+geLvkZ5ojx1/wl8JDMPdi0wjcNWDthfM7Q174EV
av4EoAammy8lJ8yW5wI6SYIvOmeduN/5/sTyw5Iq3wN+g3UsZ6XhjE18dUyyy1OMB7oRJWvmKLpN
pzZESG+85YdmsvBJrGZLAJZBB+kr6yYEKbf/kqCWWYHA63En+cfZrcbEmVJ5+nBm2V6VRWFg685R
V11aZr5YHGPkdFSzH1ZI2thffMFSksnYGRgB1WDLmUcdaAHhPRSbsal9kHFEi+vyQitPOK+/MIhn
yzodsa+Bi+gDIjkZ2+Suh5AYze7p8friqoZd+FlYdEqQdSs3k/7ZzH82+zHodf21OA75rSOJVuyZ
62L45arDar+QhA9D8iHUW4qWkai4zIaaS2e2iUlFfS6BmBvZK3UVVjdiccNhjY8deArxJYFQJ2MR
2DQLFSMiUkj28enDkEGGk2yJVpsSw6O+FX6wjufCUfUh0bgNEP5Q10suLMCfA5m/Sq4YNOUJLoC+
jPg055caDb2izi1ujlR4if/moEP8mAtZZrRFAfaMtCGZ9RZ3aR0oDGL/R95lbL/OXyzdMipJpbdG
isb/icRKk0PVKKvoaSHGnjzq5NbSA3QeGEEIXEr1ATSRJYiKGFCpATLaCAMl7A2RWk6LhCX1GEuk
1rpcDAvCjxShdnr9QZAwnnDG4AfscFBEr+YUK8iY/OMbpRhv+C3lAX7RicMGHcZBw6FG56sBRAf+
XLRXRRQQyJHBE5k5Tic4ih/S0DBEZI/4XHQxSp5dpepa+rAM3/8iqjKYkN94KZbo/acqIB7Ytafx
haxQ9seQ8bIQIqBpk5tvSjIrEj/m2VT5K93mSQxe4RrBaBEJojLkj5LQXLQfiy52XKLBLagzRY59
Z2OkrbIO96r5TEpGAdCrWwXytTy6Y1sEbCokXcLnv7K9FcMxNmeFl3Ry7a4OUsSuS9Lf2sCnvCMf
f2+DTJjkC0uNwGa/mOObj0UBtqbYk2r/4S0At9iaM22eNzTqvuBxU9eVf/b98bnYZoyHoGuyixWx
KGPyhgJIkVj4bOq3YXIBhna/rhgfNqaAHclCFIPFcam7WDsvuBN9DlmEk9AOUcNtQH+SI4uqha29
qQ0tV0Jm0OxDVKbRPL/IczOpjMkPW2FJpTp5Ek1zYsya+/v5+dsWjKOEG8VhqoLTGehDErX8ll2q
7qcuXP8l9SF7ELPLdExkfFRfgv5L9ocrthEJZ2TrDLdkfXTTXm6epNtYkIYFz/AA0jlhP0WzPloA
GfrqmqUaXEXpjc+8LIeTPjBkk+QguQYH3TeiZwbdoGtO4oBsuaW4KtSnOeRokk2PQJnVS18guXwJ
UrUDlYNfgmq2HXEbp3IIKogug9zNjyev0NT6tnXf2bRBaOFXX5tsEnmDDuCMEaiGkGKkA2lfHrpO
wKLlFYp9tMO1gfiq176SAfJw9mEhUFuaArZhFDDfKtMp8UotmHZjTGkUW50aLnjX+E1cl39Kn7fn
7VIa/oo23JM4ybKEB/CLQaZze8Lf6/S7dsWk8kv2hiJqbr4wKTkHIWvSjlrPSTdSG2nz/lbD4OH4
iYC/WmbS+TIIoUVgdoa/tbZyhHfBzPEWWHZo92iwy16jDwHiW7scuBWIKMr+3+vsftwGkD0GgS+e
FT4dp+UhdBxwnIMj//LHPnpONr6fjpMXq2+Z5qLAEdm9YV2DCxMsmVov/nW5WKMoPh/AfId7aVCl
lnmAVu9sYBxnTsbRZgLH4IvJYa/ppaXyyJjCJ4mecevlZaeY5oE6uGMkzCtnu1eGpvplqPdwcC5l
wS+6Vv/+ZYdQSV6YGb4SS2j5qbuJtTkWt0iIpSPVO7oUpw6ovBLYhNwQX+JNIxQbGQcIH5wQ1Xnx
ej2/2oHSaVNvTFpdYGN0dqBh9hnM745R0BFj4CmZmZxmhLNmbPt+QLOtc3npg5XOym91oglDfCxe
og67fuFMwrEldSymwR6M+zWxnp04Evc3r+xTrNrjCgrULRbi9AzCCxaL0GrJLtjLuPyX10Il/kfU
gSiQ8YJZBdux6o9Qe7ek8+hcwgptjtIfpz2y4lCAZVWZnpKSt6JjoDaFSMt8hu1Epczzsi8fl6mu
rmcZvBwRfRygneQFsYl+i+erMFAQ2fkNyainV2kq+MTb2529d1r1L8I03Rmh8zRqCMRSn0OVLx69
02uwHk2XrKAcAPMHtUoVNm9z1RMG2nkvo1dOkuRqD9CN/YeIBIsZWeqvZa1tE7FzvK6MKg7l00WN
Dh+znrOB95sygJonNsDe/KxDmNF4ghXyjhv9lTOno7vCtVVy2dhDfj8HzU0lvrnIGSkv4sw1nw+A
a00HXMfiCu0zDMK5fWIuCpyqjuBK+ibQvGgp7iA1ZySUYYBTHqMNlrLeZp0eeGCehJMQYSa/TCcK
r+64eP4B8dri6WiQnzQdXCtLYOWPFJPUWO/xBxVy1mVYarUxmLs+H/A55zB5NaETyIcalvafK63o
zqFbV+baB7Jt9bAtqVnA1eyDSy49hHjaN4QsBRLCN2Og3u61X5WmT8KuqEpEPl9dQMfJBx+upkxU
FqzSisETb1dmkelP4o0WnvJkUprzkv1W+aOLEy3r7ZuruEI0EfQfAFEXQdbDcGU9SUOgIQ89ThNG
Gfb9tdxskjzYGTF4ecejNOfDGot18BVdFY1TfrficHBVgVbHQfXlqdPCRKam9lbhUUzdu8XFsxos
UMkR+lh11hEiSlDSBrcpigaGnYPUBJyWHq7TVfoDsd6ctX2ypK1p66kSXVkvWynTRpW3T9ZizzKS
Fw1fGKBk+lrECKceWAWfE4WICpr8lDBFBrqKXhbFRkrazL7BjEkE7c7WmxKDHxBngLY3e4EuVOuX
ijonRUgXDb5QxKa/pF69QoIqE0qiMENH5tCRzkt2sF8IbuJEQVhzsgYJh6DqmVlYVZhwzI0jWKW0
bj43Ai1Sv+fdLpZigmSoXr1Uu8V5JO6fBHJFELM8TZPc07uGXba5Kj2vAnH/CvUfixrZYYm1FmE6
WAooYuyePChP/B17e2pCyqkUnTHi0ACvra6g8GT/k1eB0gR5U1xjmUeAmw2YM1gqZwnB3KTK2R/K
OnMjrUbXLu0jtRS6UqZdZC78oMDf/gkR6zPC/O/wBVlUiGmG8F266//PP+j4cPhtC0iaKbB5jioG
UZGVE2pslsVWKLqpWwJsXI7W5tciinu9z3Q3TCdUPxxoOfRVorfT5iMTUwR8Ird6uB3ZR7dxzaZU
PBnJxZKeK6Q5+8TIN01mO526KnWfhdsRdZpbNhsuTFWlmANzhAQu+ERi1aFSrAuIjJ++dDuUoiiB
m8wSQxlVgoKY9sWuSB3QyJMWv92Y0FtpF58PtQ7E4DSbkSLT/TrfhEt6cpzNGr0nuCHgJ0uNmiXH
qbw0wa3Entbfm/CouOe2blEc1CIYf//mH3l6lQVEHczRvMUscmDKIli8qxr7sVqxiv7lxeelG51g
mewMuoCmQ4LS7RactgllyhYzjqBycfWMn68DOPplcc1HJHHfScYx0Hx6aKUg6OJhcBQMyb7Ls34s
hAfB6DvRYNLH+S4wHlxoDtAfHJ/ePFcqfuxwAwilaSQDBHinmkMRn20peOuQZEv2hNvoWM9beTNc
lyz07BPJazjBWy3nKv1Tu6Zbp5bg/tEiATgiQWv8JpN25xv2m898c+5aZZr0/LBYEapwlM899yhh
iRms1Pfj2HU6xU2D4rhRb+M0RBF+HDaHnyij+D1unf8bPF04gb/WLB8R2xm+dJEtbVpFu3U7wPaE
EGxRWPi12G9pkui4rKOfqA+Q5fnmai+5DcBY7avNEl9i6bm1i20baSzoj6xc7CKWW5UzaOKcAWaj
ysgMIbQ+mUcecc8a6eMlygYz8c2ZenAATn7hwZBusQEwzKz+8AXnu8LsqKvMpJSQuLJl6+KMCyo0
GySYNpgyG4rNK2JwL/1EuqLoC1qelyWFN/mZGKZXJMGaTNJUyCVXJHi2Onaws1Qy0GnPJqrhtmxy
OOKQuin3LadECYf/ojYOKIww3ddx0IXbw5uEgWjIVm+oUCGfKeHSaVu0Z1ZJBYzov8EkXQ3AURu9
F6uo9N7ptwTOuWKUy5z3DFfEN67f6FVs5qLouzU7cu8ZT1HhivhfBfKpzOVnvPV9diqvInO/wDgR
lXLZ70Osh/U8PdlWgHtVgWR3hvERahblVXj7mVw7ZgrRabb5T/NNuFzoSq/OB+nC6XiOWyGhZyft
QQBmCLwKpR+th8PSjnkzzk9NE+HyH9tWKnv2uJOfB9h8y/DQFYmRUS64kObNqm/9m3cKnU+4SaQE
pjd0+xy8CyH3JD/4fvFxKYthNWRr5Mn7i1e4uDb32NN892IaDQCYUZu75jgzoYLtWW5aS5A6dLGD
q6VVoHchtxdA23rqgQ06tFLZtF1SXUHeNaQ7w0Lyh6IYwGFk0Y3i7olFf2U6JQVOG0KkHZmiyFxd
tSQ0UW0Qxsn5K2kCEAzmAEB1SIgQziqnH8Ow77kBVgaPY2Y8+sk1jCp87kga2fvG+Xzl/VT96xgl
O9dc1OLYZMbEKS6PO2Ci9Q3GhW/nUFEX52nWbU9WN7TQ4t/kq8vThNJJHW5tgTcxUBbBvtF3a7xL
KLU6WxMQl5IFvSNXFOoryGkXkiSCCkB/pnr550ixtfWIRbxq8RaZsKfBI42rbGTbM30aDDPfx1X8
stkDiKxHKaMKreTFGY+2xh7hHNfrJoeWo2y5bvPhBwx/J3TKfofaK4lRntgria4e5KaJzbC6gtRG
8DgjN0jvDGNK/pARr7vIgmGsEbcAC6DuYXovEKDcDXxZssbk9vKKvYOuSWddE170v4WimqFcxXYS
DGm18YBdDTETCLGcQb/PgligjyCuJ7cx2bWIl7xLo3s5/PNBTtZgF1kCOC1BzdhTLPa8Qr8KY0RZ
lNq68tlZRuJzeHxu2DwGvzgxPn0Xpg9XK79ct+XSarKkB8gbnTlnHzL6tJst/eJlIYcx3GgNUL+n
euJNCAahHUBcf75QGYBtynGz0dNpATBsZutw42cSgjEp7qtloeBqmMGbAy7ZbS5GhElMyX6H3Nc5
NYlKYVGXx2ZD1LoJOgUWKa9+Lcfv6dni6tDqL6Dc6jhZgUEgBWHhw1b6cadhGXKRwFefy2Ob+R0B
D8j/3byIwDxfa1hzTbHwgR2yHwELKcobx5LCtgVleuniKD3c7d0KkRwUefST8k3vQdqfsKI5L8lP
Magy64ia7Ockl1mkOsJWnMG9U+vumiN1fQ0WxDbxPhf6E4sY3mvuuSZoh7DsLehv7DTBxL3vkmwE
CY+3MpycMgc5c8FGTp8hI6Ek/k+l8J9X2pagkswjTfEVLQbZudqtlFWA6koHHO3M7VIhITvq+BUi
+Qx7tDmxBxjoi8QKmjF/itukyyuuSPZORZujGiDXJMiXKblFIuxDdIrlEBUF9HAPqmIWt6BZSxmb
mZgvv44X+nAUrpOJkAS7ceOo/iKSKuaZuwU0pCXy10yK8rYrX60dbNttoH4oIbxrQaAcGxCuAP7s
0RyhfW1jYInEmxzidjKwL3l9pM9XhhBuzCRazxBP7w8bVBJGtGbNf2ULrsIZx8TfLiAq6VhRWnlr
T5mzQ/iGFwvF/8DwVKXCnannRB6Y8z15ZrycCcUTbTrzupX5pOx+gNsbR+L5R3zwr44fVoAq9Vvr
fS8JmhG7osN+XYUYNyUJe28dXYL72BE3w0PC/aG57ApWsYERoNT2UL6s4h43B0xmCVlTC/vBBD3k
DldR5kOemroE7VcNtu8EYz0SZPABy/q9KHjM+2ViYt73cBOpH3/v4yDRWTD7sARagRsCUhxWmQNK
Pr0cKDfN9DPqDqwjC34LMCuX4YGaMPaWVAFZgXSBFupznZOe1jRceCBlnHT3H7Xcfe4Nu22bTuIK
U1duJEK82Q25QZZVp5CoNNE8tXb6MeYOk+XQ6kove4rNoZklGc2mCeuw7B3U5n+wTLpB9Ll2r8RT
oRPaP9rZQ2rHDQmd2UhmvjcoMrMV6TF+yRVph4G02G2IQGcpxig+GLsz0g+8upbX03B8rhBFl1DM
bet7yCKhgqwDHHnSJlKI3ZPZAF0MZ5ZD/LSGyAZnOi8KMoQLfJbB62/JMP2QtadppeCuX5SU7f4N
AGVSh52NAEJjO1bgJpZXaWXYkAEQvtyvJcwN4aU4u7clQWfdMRfzaFEW5c6AyeN+9AipDL0RekeP
C3IxLGvt2Ov/71taKJNkFJWxGfJI/3xRLdalisZdq7SqhIYv4Nf8+I7uiKHB8GsUMFvonISsv2aO
Uy7D2S+jqxCCKEWC9N3aorHfgzDZAXh7LGnRVB/ZtE1gLUFLn6uP1RrTV9+5qLY5btQJ0a9O4gBD
/Jy1vdwJHhbDczvArR6Zncn609RVpmKtTILt9GlYz9oD2xFaFviVXMgcPU6+hOTbPYHTwgLxf0ny
NhfLswsf4998so/etfS+OhwmRZsODGXNbQxbRIC/ZLqrJcNy8ZYsrZAVn5aVecjmDTUeLcRfJmOF
oykL9sF4y4g6zylcVCemQ7G4MDy7iYd3nwK2mda7il89ss+bcAFTON9v6PYqOBGSgDYqc5s73p8/
ULuuvkovE9X5H0792bTaGhMyByP/7zeJgrIKmzn/hUOARJoCWpgYPiC4e+jb9QvfzAL40JOPXb7Q
LyMAQQgBy8OazOojQPpyCGlLdLhp/iIMM4LjZFNJe/kXPODFDopFWiVIUzgNZhkiBB2hnAt66/b4
yAeYgW8Ehy9wRqnrD/bqaDd7siObjsSA+8d4+ZZMDUw7WyIPXXKHy7LkB3whNGqYYXTvRRLmtdB/
I9O/z17LxV9ix6GbyDSxHwfNoI0iOE/UMOsGvPsr16iqPUODhKj5o95AIrQO6Wpy+yZCM8WzBNPg
wpB1zG6TzOvOxQZFfpY+qYH+C18Ienj99GTWeZKDaTRL3zTlP39yojHRT1tYvj4Ad1baBrBug88q
nyw4WNK8YgxLHgbXd+Qa9bt4ZOQnPjG8VjcIq5SR2i7G0wJi1ExUb0VtdIgsEnM45XrM6l9bEl13
JKsCh7zq5hdUCvtrWN34G0ezHBiCb+ZIjECWwmNfvkxwhXhoE7FZjOYPTECONWWFgxf6JbmJQ/pC
dnilzFZQkmW+rVgK7UzW3deagF75I7tTSjEt0FQmq5hCgkHLXN5gqzXmuqn0EeVHBXQytLioLBfC
/upEjptRV+V49mVecr3+Cj7n6DnYVrywNVXLp0t2lqXF3loyj7SbtLcr/1UJCHd0+6qGKC57I61P
Td+y4eDxIwO2YmlO/N3xBwxHJt5emsJtLcouBnErppGvoJ1WBKDBPLxl99BCE3997FKaef2OXpMw
h1UxWD5CAGYZAuC2XSFJyo44JN9JCoVhLiJYvfFBBDtfepWn2djv0bgFIZnuz4byhROeJxChL1ch
8NEuM3p42ujs+znrM4PDFSdzsLHz9QMc5xGWZ0RNAynBpF31B0N5iQ+4JLkcvXdg067pIVZ8byqB
lzL56T4BY4a2hsFe/BtQi1P3KNwG/cqxVdmtnFthH/Uph8bgzQon0X2k69IeKhhHbTgPmGv6phJI
pXE61+CXAtT+pqR/1HgU8DKue2r1FY75Xadu6PsoYrPjVWKLqQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
p4R1JWHBywIR2Fi307tEhr9AcCfH9rS9QQ9Gn4BYGXVnDi5tc0U4TddOAMr9gE8yykBWg4pRrgQY
K0OXjCbgDQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XpdYEeRKQw9nhEXq47MIVZAJ///qNkxaVka8Z0bcj1dT2+H0QTInHjneUzYzLu8YPqeDmQr24kbO
wkgGTZa8j+jdXk0pz4vE9NbRsDC50znZIbuStqJlXvLDnJ/XF6ziNA6WoWAO3cWAa4bsqPLtwXfn
po/UeNJy8O7+GL1p4GY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QlEoufHvgQ/PWb44YQWe5IepwmsJFwFNPYfLZcpYZHOlMPEIgEZevKk2sHVQVk+Cudv3UZoX79WL
wphYFfx/NXYY76bxEILY6xi8UJgE5OZB/8xho3WMAbxPOxsGqXVFSa4F6+5HKvUeUdbcUl/95i1i
taCNTGNc9QouczHLD2HfIK5Avb74SvnSU15xzo8LOLl2seWI7VZKF5Ns4Og8iM6hNW1crWWMg3X6
iXioKAGf757tyFMG9fXDyUmSXOeAXtvTLHdmvz8fM/AcTFTOL99uhrFOflDpodQp53l/B/4nQCYf
5hMPF0Fd+SSegnxrtOt2hyfAAMU8cw0vLo/b7Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jSuNs9ls5g8Squqzlzvp73BJDN7bzKFFmA49HhgojPxPxzYaKRChIZoBvExaRvIm8fkw+Xsaxf4V
pXJXDCmRgAtVE+DzE0vtomDejkX5UAtceGhLib8ui1WEt4tsGidgqZVFsHjKpZ2HK+KBVheABTVA
uqA0XgTtawsQjOjHr1Y=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
i2CJx9GA/gbChKzzIYauuGaOiMmMW9pUNzmVsTa9q9W4VNxlDN38p60KHDBj7s9mGZAB67hrCMjS
wmx4bZXeq6ZMuSJWvmZCCo5IWr8FtWcxCRYtXS2OIJ6O14JglpvAlqlv9DIg+a15jNL/XPABEZW5
8BNJFijY8MLQerMAP36AzPUNo10qiEUdUDDj399zz35Rntdf91olkJWfdhPGs9hn8YxNvESSyc2C
T+NTw1o34iOEmEIJenb7Ng5CV4ypuQ+0wZDmV27pYMlwM8aRSWT3CfYedgGBODzTVIO5Xpu79FHl
1dRNS0OeB7uK/ybKhyxOOEKlYeN+BvnecD4p0w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 68608)
`protect data_block
Ja4qVGj2zyIazsmhoa/FFqvgWGfYJSg/erEY3yo9UlzOc8YrW6XYEZ5J99cgNFa17BoagkgTfnsj
FTBfMJ/wM7HthToolP7vgG8wIlzl+1J2yKgLJC3PJXWWomjyo/LqMlxa/3TFKlBVam5eWTqpCVvA
Ox+IuZef9C4XMC3hXt0UTwiywmLw0cEaV9YMAOsvgrJJU0A5ruKhHHWtT2yiuZ35kJPfU9Vlt/BI
ZMsZ7YwdmBEPSrKAAJaqSSVYB18TpO0p1WXhCHcjMA48a9KDOa3Ppot5MKrytb2EgslP5kKtmhdM
ka3agHj9Xw+b8/pfjNqrjR+QexvPTdPh7+FlYVEq5yecHe2D8q5lW49j4XbJqItYHI0zBQtF6MFM
iAzNAbVYJw9WDcXhoQSkcWj7iEw/eEWof8ZlCfwBnAqxq0zLSWx9D/Pd0O/VgBX1q2aVZsE/2FFK
ftwkcTKipW6UBHX/Ln+Huhmoy6xOZjGfMdcflc+31UQHk/PQ4kzHJvdBOcoaHWPtXReBNHxAJyhG
pxAc98K5cG7iVemLCVNonSKLxhiNarbHoh7rWt1jxu9xU5teA1xn2s+Vk/Wy3dItsTafm9CVKOGj
H44+EkMGodJleLtc2MMRRyqWQDj3kam8tTyh58F9q76bnIgnGgxMHevipr2RZUF9PG+J/yzkazgK
qLdM6OhwTzVsWVByE40wLW0Qc8h6e+qOcEpw8N04PyvsWSgg3KVPOCQRmgc/uPWxqIXrWObEHs4L
LWHQJZekKybomkwAs2OQX7E3JLSeG1AaOWRxN7G5u0zi13HyD99oxrCGzgi9x6OJWsWq/bPg1rFI
P1f+i1trK3oOV5o2oIEC1okD94lIjLBtmxHLU6U8fgj4V49/IRoleMMcUk4tUJgpGlwL+tgQzJtE
S5lji3iSK2+mXB5hdWCvyRqDqSudS1fAl+b5cqpPgBDpu8RK92PTXuJSBNGFy8O0BMQOMQLyIeSI
c1oZTEZekxkpxaxk4VU1qX+U6iPWFRXN1wAnQvRGwQqTVDqOL7Jvz6OaX2vZpD7CuxKbM8SnCIDY
wdIbT7HXtvjdmvtqrKoKYRqgBKO3VuJPF3aF/GNnI2Iv4BeAw0C5L66ewgdJZ+Q5iwBVISdIE7S0
qU7ocG4XBQJHp+a57vxszU1EKhotw2ifgM3kByG6Mf6GpKV5uaPOa7rDD/8lhUpzYSnxQhFQq856
5kWrl24Gc1RJT+ZRdeAlngMpHSTzT7Uch9Z//r0nQbOBSrXFPQvF7GfqFCcenrID1VSvRyPp3pwP
M85fhzf3jA3gr4JKy3PCB8yzY5Z6Iz9LE7ElxwjRxgc6f6QH2nGaMYkinsDPGFeQs10si0MployT
zBK8Y57nxlz6Adhy9TFIUdTevAWTAnuB+AenHIG6Yz3YXW81jPEz5iD57dHvbIDOV536Q5ZyrJpZ
IJu+73cCMSoqEdtjbEIIGrV1ZrUAoj/wEtBNjKXTBa7WxAPpbp3nPj474YvTkJcBY3vkRMi1ucmC
3QeFsqPX7skJqsxB8oJnm2Q9QwpzqZ3OaMKlnU6zHxo7s0QgRKkGelsHeK7uQ0BYS8i6Ttiry7od
iGbB702Tr+E6pob5f713mZZ7fqno5xEl1vxC8sZ6SqrU+VdP3+h5CtatP1+mWYPYzDEc9YIsJk76
wUjhhgKAnhguImRGAW/gb4OAHUM3b+GvSMWZIj29olCn0CcT2ZPGe3x8Blxs3bAWLI5d6kqEBaDW
+bCwZVpoC4LNvlh59N9QgsTHBGtC8ynZ2U2O9Kah4dWRXuMyToolT5k1bFKL+bWN0drdeI+o+XEg
lmnHMsC7eK6nCOdV+TGXrh2uVTkUOseBHAwn28ae4vg9ED9bBCCfLOuWJ5N67wW2Uq4U6M3OC8QQ
vJUkPY3BMTZMVxnwHyPvdSbkbUscaEn29MOhbB012x59FDs5VcwWxL0iLHC4aFF5yRLY+QFiu5fg
GBxQp5A6il8L6/hM9+5eP4FOD400Yb7bHbPsLsLik8aHFi4zQ/i8g+Rs285ZdLU0iQCUhGM74yvJ
QgEna6XKaBUvuzKvCcdztLuQnO1KuIJforiBkErE2JTGeYQIwK/QqeZSLHmQ3s2LDTfWum/6QGKZ
zbWUa/SHnHn+dj0QS0iNs1GFRLumbqSZX4Uz6wgqWIL2YhgVRLJlqlDZVSa1x5H+XCjwetUgouJC
g32awYWGxVmyp6quGaFOL1onYGDKYjZo8stdVWHlkQijw2zWgEBixLGvKYLMv7F2897hiw/BcppJ
x9S8nk/7Mi8RmGBDeHJ1I/f+cj+L8upfGwlMJphaLCjqzOqWt5vMlKTn4r25atgN49l60MfxTM4h
09waQymCNjjv3oUhvsK29bFbBz8n0JjiQF0+ThNH2opE9nQRGqTIXcGfVgclpXgqWElREn6eXKAq
6Eq3DhbQHDn9ExoISmfom9IMwxEA0WIR2OafZxwVqCYLLeusARnp+k4hqmhTq+YYMcGeMk5boHuN
vPKoqy56WNc0TQxEX+2YI3uT6/FQguEiEsCzaBX8OLFOHwt8LOVceYuGPfghviSwPECBRlh9Pt7b
Tr8apapHGw6Ne9NxV29AG3wyasc9veHeqALGKqlekeHchhrs+hxPtquaq7cQjtrYTxdpPpGf3fZp
PG/mBCF9S9cWHv3+UXM5i3zqYB2yuDQVgq7hIkbjeAxIm4V7vIdmKZH9H2lc9YmYjWFfJc2y8bau
mp/IaDcwFFxDVpjGpeFq5GtYbtNXF0Yjt0FFXHQqYp6NK2y0cAs3Mcuz5ADRrPIdz9rYp2jVse27
OuwM9t0YWgJKSiZCTeWRYZyJAZOZF/fQFeXklCdcAnoOzv1PqZcCCxbK6IWuZNn/Rw/HzSZ2/iA/
lvCzZP7STGbllL41fLH1cpwNlWuWDQaobGfZQKc+x4NAwBxChbKKCbXALZA0/F+txAod4V8RmgRK
lb91Z64BuB8E4albz5/G8Wtba9FqxiipNFiTJI2OeALN3WDkVkiu/vr2PsjU6sKro7s3x/sZ+rQ9
4B12lV8HaSf5KAwtrTqV2c6oeFah5YGn46Bm6KmCs+tZ7OFLbDkYFAxWDkqKGXmmCHLOqlAy26tW
fpULE3xC6wb43BVei5PKI5lHOgyZ7pPCAmtgmuTDA6sgsDaRcOwA3wFxrNWq7ykqp/+xwPPmXJP+
UYDh1liJkiNE6P+Aw9izXR3wqDO1U4OBnIXF8mmpPyajynZlC1R0oAWG/NigU4ncPzLhdLXmYXAz
L5PhltlvWEbIEp+LEnxIJ1Ve3yJsJaJK42D+0fE/bilAk7WLC9QVKGBVR3B+Q8BLhrIeOgfjah8f
3hCgjIxQ9F5atms4ZqG4o29B9sbsvtN/ZG69PBsCB0dYHnTTgmPLEu4OHlqm3dfJjqteLsiSzCXw
NkR8ShcQMDeNaczM1Orvuxiljw5XC2UPeg/vn+inuUvjJoQzjDZR2CPUxS2rKbe3lRhluz39NJBe
n6XEq9inUWA2+Yt2TGjMgnpjr78SJ5WqWSelz0eQAZSGZcaLe/cthe/LwspzqYjeX8VZ3hX3V6e1
u6TAPPZDYD01u24jIojb/SBECtUPEJWCYrtQZx/a0dTSdK/KpjIKDXD0Sd5UFUyIRfIyCeMSO9px
KFs8j35smFkWa1Rw9HhmBiANPvnUPu7VaWqVEcbQEMKlmX32NVF4MEij7zpcmuZm6sfxtqRAFRDh
WDgg/T5qHIspbdN4rEusLtggHEKt1eIil1BPx/qPu4KGX24e3ZXEi1S/0A8W214u8roG4Y9H5bcV
Idrl+tBU1uT02qVblha4eUyqlNBMsljoCjH8aiU/l1dhd0pjDSTQUh49tshOheYN8azwnVaZeDn0
puVAP4ufZM8jUSrkm3Dilrdl8DudJYUVwRp5/wya63/v92IHQ7jMk1lvcy6OOS96H7EHJMCuqxT/
6oXtAolFh4kKxKMLpWIxZ6Mq6WVfA8lwZq/qjAs+lDF+y1fnRk2ykXwntUonHD2jDO6lgs11K/E7
lnBNAxm1MAQut2KQvcMg1swJSK31pQLgY0N6VUix6LNF1s1ixEuyOPNeQwNcc9nb1yfqYfAhE0bS
WSZK8H49mIwJms8e3Nxp7zvEmqTPrRpivck873wu+GA3rr/T6t5BaHNOS5zF0RAjwdr0mYYF9PV6
YQ9fovFVw3QVVsctZ0ewjYJ/7D8gk271Q2ox+uJnkdZqBSDPEGGEve4TgdPSO/0pSnU6RG2dzarC
55QD/B2jUFNPzpvLq9HDt7+UDXa39Cp9xcEe47h8L8Na9by6Mq5fK5OIv2oMvHgDbAvSLRgQq74a
zE2pbJHcNRiXBP0JWdSrEQUND9wMc+jM8Oj9LaWMEfwJQPLzAnxDDQbBlwEgTny/yrDoj/NAd8lR
fayRZ5lc1Od6A6EJlRpFBw+AaurKgZua3t9TMJ0+yf5x+cSAX6wmbElFqtkaS4LpnKkdRHHhUx6z
q0JeNNDjoTwBLI8ffgvf2YaMlnTXEUlru5ZboStpCcevuWHFOIVD4iBt7oEoYuREKVxrnbTQt5yS
lz2Nik6vQEEexJnRYF2Y217hlbZ80Ljk2beJKC2IvGxOtBrwf3Y8vix2g8PdcscOfvDCCe19ylk9
BPdNhnOp37er7KWrmIJwJstNAwlGbQquDrg/BhCIzSlwbJ8bRY4jVEVrIP7RndsGS6CVGE4FT7dg
33CIh2KeWgQhrX8hWbU2x+pD1DNOtj6zHzT2TqrHMgsRzYPDEyWo/QDUN5DlafyH09lniG5DvIAG
d6D4hJayGM3HnhrbozXo6h3J1fVK9R50uYI3PY0yxVsHSKAA9e51wmMvcxr+zTYHfDstlfhcL5Rl
VGinKv/jqY276N8m5V9nKYyCp9bWLN8UzO9KvuLlplyQQegRFNHsFncJbLeubUXfE2nmrgaRld34
13XnW6xBqiTHtTwQn4w+Twc0HKqQlHbt3o/r8UnpAQhKiUa1m/2kieG7DeI2JBk7oIdYzseCLyt7
6Db4Da00IlMjARbXO0XN6Vjgh2SN0PL2e+z4Hv9lBxwcB3XJXUbvMCI4WF0CPZ3vP1OQ35ZL3jyK
h/3rqf9W6cT9zuRSlVtTuDcaO4lJ8Xcw7BpW8pVFDrW+gQIWVuZbO+lphDNOuinHw+UybD0EO/AS
ich9e+O77iCXkmZo4v1JjHHvqdd999LPy0Mtv+2F8aEWXHzVh7O8TF7mZhjAB9TD9dHIXAnlxFkw
1DgXWeMjkfMt54aol+uVn5gcb4gtn2jrtOshV65WbWHGCqAa4j6fwQr7aHMQTculWTLlDHpWpbDs
2Hk+MQcsHbQ/Ug84Kr7C338VsuQ4m7I5DmfJj65KjwxCS8CrJk1kz833DT6SVnkt9VBOIAEpefBy
KASzNQ+Y7DRWxItdaSfB2S7B24x6GzYDJL4G7BuXC3jXplyQASYtIp4d+12QsRkmU5N3StcaO4A7
ZXkCaPdQq5zT2VaRCHBfeqxKIGLbcCNcLH1TqcBSL2CeCy8sFSLe+Exx9he4NOeO8hg6EvxuRnEN
aCVPhGzy1QdqIw7oiIu284s2wmvYIurlUVzvcn1nimWynRVOd7yZ1Vgrq2gpJsYzNFWC7yWanatO
JworXAoRxVddy1QZ1WSvpkC29pvRFg1HhP7Yvdk5uCTFjzr/2DCgLDOo//6DX+71ILzGFvQ4jCmV
qpP2y31nB0Ckc2raMuYVUUiv2RwaoY+XDLmSCs0yAzqo7/aGsY4gByEAspEiWqteK9vrZ/kkGBpU
ZN+EzS/M3J71ACZeapVM2X5ot4x2bgHHAGRRhJkVLhu19o4HcisN+fJkzeuCeOoOvjrAhvkiUQsx
TtWyOuwhpc9flziRk22+vSvq4RLqpF+RhRwrzFNz+WCmCJAhp6JMzoRO8gTP9avn7g0qg1QSWPT0
udmW7OB3NlpNTIcTt06xo5sxzkxZh80H9RkpUk2v0u8jhCOGCfUvFggb7DOblPPSSnlEpxwofJrL
ikw1BxN7TWMs8UbbvzdGg2aEKd1QSSxNwzTitvK0XDNgK5p5icY5/lf4M4ueA0cux+JYZSKg+JGx
kQJtSJtif3rEuT6FK3nWNywI4ZyicpH9jJrKYmx+fXNzZrpS7O6r5bfsIpvHcx3Envi8372I7YRw
t2IoEhd6gC+35OM4p3ggQNuJfxR5SEhzQghrcoNtAth3qD3XeqPaEMQf8Quk9wG7OtAVi/1TlBtr
R2IBSFwJkjqI272Zj7Z6CsqpwOKoBVBECAQZ90ZWp5VqzvisZAlVJsO1qKUudGbZuOwsyZgxz7xt
H4Sh5KYrx0hHpEzaVSvxa/3+ZY2kymJlFum0savSMVqLLtr7b6kivaXRR/Z84SkkK/yA3ZP455JS
GW/ODEtWtjLceZ3K7XKi1VtjLmsiacIEjCPwqA+jcYCAwzAuDr6S0/MBCHb5DB/nKXK261WPoZka
aCjmiknjUpijGTRUbum8bXMNYMfTy8vqP/OnVpokUCMLSIQqlB2Z8vFeWCI3VXGF4+TVY+YsiLtW
DYwT7irHiWQFETJAoBlex1fDkjEtbIX3FpAU8yg0OQscUs9zpDXAhKVmLD94L3BRYt98jlU4Z8Fr
DMVmSRLzm5PRhcWPzXJpub5XJ2q5l/52God/9HR3li2UYfcNBtZmBeIUpzMtGCkD7/L8e7Hgg0lS
bfaOaHaWyhGhKs7g/a0BgMeIkNkYdc0sYpBgMl2+Z9rwUOaXdREloenPQqrmsIL9Y2dy5Mah4zB2
8JenTrc8KCSH8s/bqt4YZJLbXYc2M1te7uzxYYhOMKOklMk4eju4GRZUJUzYiFxeXFpA/jbsYOdd
tlLR/es6H6IXfajeaURruz55eaxSvfW1qg1FqIYZp3Ws69sXOU2VNnMrRep9SVIp8fmHacOkL6Fh
CS6NU5AH4soqUBSl+vErtvKN9Pm7puE00HC7+geKF9+kvtsUrL+2aDR+r4EWk0RzxyxM8Gm4LX40
FQeFHgPIOiq267UyXKXfzF2AMtjCSYWqGEOxuzdKDV10IoVlBQMcr1lqUAAGB1tTGV3bbiI0zbrX
URdmYtRtQAwQC2vxivWtK4ygoMZRLEWPP1YBffQPSYoA4Yv3Dr4IlgqOfXohO/55PvJyg0no5b3s
g+w9YB7OfuJsk9LunzT+S1cOfqIB4r6WBRF9akdq+S/dM4Cb0xTW5flTfwNjwkUhvT80s18u+0oo
VwMHKDaRBPM61ZdgUQislJXa+8/43PKiRAtc6scFcyk8c4iihO53tANAdhlZVQ4u0nY0TavTNKz0
LMliLqt2LOPbpUcjISwvzwru2Yndmja7kB/eh8G3VOXPgn5W3c3ZvSBBrEGD/iMAxCXGTqJP58si
UsCQ065RTPgLbEvFpwqV97URTdAKKpvqu46ia8a6Er3TamCoZFVgwYd0TOkVN6MoU6yeeOe0+B3s
MoJCeeaN1HS/5SL55XfcWjXVyCmzgxaOf0k+XHHXTifzotzkb4tS4rJwIUeaLSuV1K+YbjVVsFuE
jQcyi+/W5a8p9vFez00/RULClbf4mD80pAf6Hwkop9JGvybaSIVL/TRftPjtsneyoA/LsDVeQyBx
177bctUYoYtNh4RoNFwwf+mwuPJuKWCfKDEbDwU8NrMbaxRBOT9Ag3CqMLH9mCtCqN8ERe+x0Hci
+2N970ETmpK5WZN3AmxVgFaNIvY/uhYNPIuGdnrDtZlMrP6zL++gsqZ0riIulX8P8fg6s/Q9qWsO
RW3ixsPqMmalIMTHwjfCm8ZLp83BHAaA41gArnFsgwI9xfE/SuK+42rc5cxiTI+OTNB/fFQpt2b3
oCrUDtu9KIJHW+yiM+9Av9bMNuG7q3c4hzHwXb5xHAhB5SterSjFO5C7KcteXtNQpwaXxFvaIqix
ouqwrFCFiGlqO8larTGt4F4dL14NeBgBick+lLraAt1kqrAX/1RIeKW3Yj5JA98qds/ih5o9BCNF
HAwxccErXxrF2ozmXLYSlgO1f3mH3TIyOiXAKOUtPJ8QI+Ka21zZIgH4BD57CoEwgUFwk81GRvPi
7hSvreP4KhstWhRSbt1eZcK9nCGZx4hcJHLX0320+emtYnatAcg6WbwVXNzf3lCNsqZHTWhfzhSS
nAejCXLmOBJ3RkjI0zf4uUxbCQlTZGz5dKRpPdklrY+ePItIg7pMs4ypLY3soBMCvbVBhTM0ABOf
i0THRB7hjKW924yzVw+lPP7ZEfJaEFwJDjwQyAC9Byo+wHm7iF3FlDOoG1MjApMURVDDwPpjQsdM
rgYvEx7ECe+4pSEEWpvn0cgZIWlbhg3S6Z+zjAnAz9SJ/VZRNF2+o9l2CXZbN1xKHnBc5r82Z1hF
O3nifR3aptVmOsVn/aY2LBo4I6sAV+M1v4gHI7q9bfwTgnnGjOZFGsWlOG5+1YM3vEbX1dAkZeMk
+Z1bTOMy3kcRv3+7gj9bXw5WMrvMdSfC51XGHS90N61Eg0NMGG1aHD6cNVCnj1xOUWpWV61Wwipr
WF5gTeJgMbRRtyTnlqs1rzeakiYIe0Uxts9ERkZtLSmsekMMpL1id3tj2PtPpVmNjHazEqcfhH57
gAzhCPv8bCNVPBsrHQ7B8VXYs9tlR6kn3W+ivepGHobtICgqMRitelflJ8z1U3c7QXwpt7ESWNpv
6r/yIB406tr45m/9uEmISoIqGEBOr/IiyczKs/t515AidfXogf/AK7mv5NhGKh9+DsBZiy41d8r6
0GX6v71fgUrV5bpfPzV9yBrfSNa9l7bsHOLAk8l3jT1sqdYzjzswMjYTaGNHwd3KpHhhAqulU/CT
sJ30qivLAObH0PiKupQm/Pr6mZ4rsrcPWivEuS99qK7wUJRCFe7unM+Oq1ohd3Zx81w9S2m8Skyp
Jpp0gf1eOIJr20aXxCENTaC4UBbC34+th1VC9dtRS9Slb1VQwbBiOb7/dGyOdgtNj2X1eR2YNfvC
dHAgfZ2FmZcXgp7NlHVueB/SkRfAD9Q6479vWqXI9ZXsJXjMmiy3/BxmwcVYOwdYpdyFptHNSa/4
Ax5Cm8MiYYwFdzK+RZE3qDSnPilcjdlDjtQwtMKJZhVyNeOX+wX4zes7M9Uo3FETfdpDFLitLAhe
9QaTZH+TKFtSNWUVAU/vFxlSqBFt8NyRAnYK2FdKV9IHzsCDjLDuQzxzdrkElUJjT9NDBjuypB56
m9Ag7Jn5O/GgzBQiso9VjiMLDdCjqculrSPqFWiAFVSQQHrac9WK+GDCdvz0DVRPW7Ug6DVVJ39O
r1cUaAPuFXNNVoHREdCl5VRQ0lCsuaLCVrk2osMJYlAi6jp+iHRoI29Epmqqy6iNtgwE+5hC0BjT
YF7uodwRqRze+Bc7H1uIVC2UFZJNuesScEKApdgG5fQwJAwn1NrS+D2x46cumNlbuwnWYdp16nVx
C18sWxoBthlot5W3uJea7ujgdTgSugT7ybTbS2oBixcEUjorXKrvtyzBgkPB1uFLFNK64gp5MZQ/
eVGXVkrlePSGsuP1FWVR6W39V9O98jxpkU4F0G0bxh0kfP/ycAq4fKratltlFmOkNVsTQl0bgOR3
bYJMQZLMrAE/cwgHm7FBRm82EHCaIBiQTeYARqWGHmXRT0VjW0lJkJrcnrvUOnp0foJFeizIMcVS
ooIK4lTH/hLbkfkd1p2Lm7dZ2PHffHaITdxbPIuwgO8yANdgTKvAqLlXsRrGOW6sQFBGdDLWzGDG
Hrcae5+xIRJx54cz8aYU9sJKJEfYoSg3swIBvF3Hj7af0viNPWjv0vyyIR/Mq7gvYYrtajTJ+vWS
yEfimEZlC7fJWNI7jSqIdaV7EdTbBmgPI6q9Ejy8rpwAtvFT12r3qEieyd3T9rLV86I7q5O6NH5K
UqdamYxpM6+8bQKzbVVJ3Qh6ITV5cj+ILtVswdv9mbuUmtEOGaFeDI8I5aWu6mL+smkpJ4iIUwhD
WE8a4V8c20I5ADMgrYRTdLVHq4OiEOYzm+EA9jcKS08ZO4WIBoAEd8zqGVgYmwi6CCEvHll9L813
5Zfu3ZUKQEyztfrKVjDO/VKgHOj+X53pexPOdb768CUk1Wl5+YelBdtirhISU8eCopUFMrlFpxO8
+pt6D47ubvTHPt3S+Uww86B0O2G1lrioAlzWav7tMZ+rAfdge/LmWBOVlb6SdNsH4aeyOFPX5GF2
Z8BmNoZt8OXCChoF2PavWhBrVniLYY2uz5tk+dqPohG2eRfnyJrzVzhqZd6+BazOzYUj23eK0VH7
630LiVYXR2YyaeoSMR798jxlXpmq61XkplXBqUU0EbHEcRHDXac2+akTvyaNAb1RK2AzD7YeOkNg
238qkbP9d8qORTsM3jWKBgs+ruV/vPEUq/eaQa563tgGwTM2Ktd5nVxd3SY8l9VfFivttsbIHOFE
pOhAYy0ddxIjVsx3DFgGdAuCwWh5yhp/9W5Wpzm6CfzotkR+fRNEGjnAWIHb6Sav/U41Is0DwYLX
LeuJjT6jKUBgkfDuebRw9Pru65Lye32jYzPGltJna9X3dGZQmItyP5QQLBLIknDvHLOF8FdqStoq
/P7cgACYdQBVNc9pPZJvSPXFCfsNJKopqV0TZ9b3hRhSiUv7AAEWvQbHL41FVPYtkfYJjle28XAw
nkKmQDvZ39/2763KIGgI9tDQgFjf1Bo2dkEX+xU8fx68GzQjy6q+KlKFiVf+50RPxEZLWWv9q5dS
SDsEG9/1VZPn8Pc8XJlLBg0cAKPj6khWdH8aGy4CBLCxT75m/FavTklkUkzCp8ESeHp2khYXIN8U
khMnnBTApHUNMGOlJ5Nv0YGYaR8h53hlo3a4OAWZKomP4bXlALeNOOh73qZd1MP05zGMcnbx/9bK
5IbusgJF4rs9qY7KritmYf0WVgxqbKxjMrqqUKM5TjkFN5fnl9adFQ3mZBrfuohLIFX6aNQvDNue
s0S01tF80o5/zvYTaZVsER/LypgYeod8+Me845/AsbQ+xmIPpeiD8hzA2I4uz9lhSg4V0PdvEPe3
4ml4sf9kL1GbumgG2y8WnGEspQzVdTtPWoo9xKC4d6V9HX2GoNKoH/ftRvfkR23zwYh+ui3M+Q0S
xpj8iydIbrzxrh2ClHn1TidzpvJ/NmzPGIYS89Rr31+rqbEbVpyjFm1IsZq0xckzi5DJk2o4WqjY
RIXFVpuZS0lXFJ/azLfj0t68RFkgnAmfyZ/Ab9T0SH+TXXjLuO3VLjdP6W9g9GP6cr0L/wVR3V2X
F9EU8bZDkRCBFzBVn5JdNm0A77SVHf3yAOv03DOZWVj3dmc4jaD0FZ92mU4bRlQ29GKZtGeVteV7
N9KOWEkAspJoN4dOKqVCUjEHRXHaWl1gr02H2UciLUeGxPLHo3QPOQ2hXE8P99L2z/dG1vb1+MOV
HdlV5wamh+D7LGDXet2cA3KCA6fGq8qL8A8T1+l4RFIz3hlxxFqMFzDz4bpD6adsAyVv3728x3Vr
KvcvyvPvjL1ygrO6y8NMpMOX6WbdeK/Funh42v2EERY4FpdYyrIHJI4bw7BHpwvEIEdU9Gs8ZwIi
+ekxbO/nKdRbs68aBwrJ4SkAfrQwyWyP5TTEcGQuG/OU7d4fOkkNO+jNRlLbuN7lNhGUNkreA5Od
gxO+3l3mETNB/DAhVFbxCa1N1/bwg3/pnoGRJYP52LYN3wNReg74yt46KHmHYoCtZiHA2ApMhhGI
CdQNfCptz7sE9ygshHKiO5J3pIYJpXDWSN5yfekt90RxAeIey4ggzfiw3hZq8we8m1+4+yYiGIMm
+18A0ORXWWTPmFrp0ILgmsoxzilRyKirnifwwhi/9J5Ur5Y7IqSJk2XUfRrcWbtTUvMjUZSP0T6d
gcfDRRQMFEB/9+bKAM9EXduNq98XIFuIw9Js6C8KsX//0jnQUCqSWVauh+UmzaV1ONzlZOC7aX7W
rwXnipiNOkUJ1udnTLwqMRjrNln5QGz4enNg5g1zD41PGVzNWHe95DpSbU/NKuEL3DKlGjsi8YRG
CJDQGu2lFQU/e3NARQWPLXFg5b4aI76SHRfafzhTLej4Bj2Z1cRWWQSXPDiYu7CZ0JSIcglGctpS
LGHKQPKRph+5oznURYLKqWtCwi55nfWtOCX2hMjhmPmVSBbUD25C4MpOWjDV9a98u39XPebh2uAz
HXLIhEh73dlm4l7GOdZXWyEkCrUxoCUigFfrwOnkjLl0bEHtGFNebvrgy5HZR93xa7ca/1gpYJY4
LmMPhyG2EODKTC/XEBLjKbCJnIwZ/p7HP2uoDs2rhMb4ipR8/NhOamvDTjqSsXnOIoaz5FJXPhje
ctxPGpSNpo76hftjcoM4jwp8UDZlUQqcqpedE9whmI97y5YTIODae9hCibm/96qLskFqRxw0gDYV
PVAOcIBQLs/3MHu2w16UdeCw2acHyy/h0KnDmrOF7RUiz7Qu7ixWl4eWdjN16DR8hG0wpG5pUX3H
C6VUGcKmlYpSgB6o00ezqQI07B8ONlVGcRqf/zioE0ZUUPoFeqq0P6vcxDTOWsRw2IkHVIxVMbm0
oBgHST4iyzSpbyfsHWiYNkbDpVbgh15Z2fbRATtdDVR8o3HQgc/Mky4zU7zMoBd7NcJTyoJ6zeij
fjAlXw06Fw7ESBUTudrl8N94L1iVfc2Aarr4vA22lEwyyDFwdf7Nuzs1BNXPjqkrfC3A28/RdKNa
vW7vGfBbZLaM8yyEsQVPzwKDNIFJJcZIxDZy4wS5waMLclzp51kCqLtYJJTdM5UOf3Gmy4JuVq70
qXaQHF+Xb358lTovtt71H4zlRtEYP9/6kcmCm61jpeIOlpMDXG9H6hFuf8bLKg5m360i/xhM99Hd
Fhx8dkTpy6J1Tq1ZgIAwgs4HEyOG7lgLTmVfFW5X8im3YpsJu0ck8/NuMD3sRcSrXgPAoeRMp0P0
KeiyjdOWbwXh0lKtfivI5/XhthJhVIfeXQzeodHwRaeUWjO2czrSvR5Tj0SgkYT4RN8jUIwOgrsC
hSrpwwAp4a0GQHhuVtVg+DyIcLvOVQ47ZuSfgIYKa14I3y5KtmcWkPPud121dez3L66Gsq9HtBQ+
FFW/uirxoP3V+nDgl1YX5csAArNcJKGMkf5E/+6i9QKPQJjSmhD3sgKaUhJNVf2fDxu/KLWAjYmo
0/chgvDdRHQAiY5xqsuNVBEIT80eZ2+ixpdNiO4dNph3tUoihhrQ2fuZvsfRNxy84OZH7oPoV5Lj
USx5ukdYTI03n5vlCnp+m9F3lk1DimvSsKIB4Rz0qBaSqJi0jSsKIZ6DQlgZ+L0wSjFW3EjQ+UJP
EWbURKVRMZ+/W+627Rf9N0n9RDReodaNfXYHinV7H0FyaVxXpfqu39UnB7HVf3JzdJ7UltN+B+y7
WElVDhbmih1KQ4ERykeG/Yb1nn8PwrJUTAVNmhW+nbqMILWeT3Zeue8Iw1m7Cjf4piqhxZ+qrPf6
OZ/s1aN6fsh7heN4OIa9X0MGiXRIvz86Gyv2dytU7WhIVj2Y4TfVeUReWTcBJswNtgkfOpYbaka9
HWgVx3ta6iui8M1i/xwxEBWHA7jinnrG7w+D74hwrgunh56cGrUrd/9kOc5DiUMFoXPvNQO3SGcW
W+hyzTfFdN6f872Gksye8KP9pfZmlslV3/8G4uFfn58uewkj+5nKMgG0MXbTnlk9+dRTKR/6M0MD
BiEKURGpMZpjw45sx3yLbBgkoM4QJOZxveKiO85lE7W12NEx73E6EfYSIkOC6Qa1ZeKSVazrppPn
ig3xf8Es4heb5fJdfBYXdPSHnI+jD4cJiPrVkwWlDawTemQukykwlLDe23j97ABtnLg3n58ENsgg
VHyRcyH7IhUD+fjL1/oL8FeXg9lkL6D3005zkSOWZPrlN8eqT6mF2J6ioLJyODhqHnIElmzcNwb7
s84rgKxdzhXX79l7gabzrfZgOYY3UcMNS/smSAXxKgbbbl6zU8x8V/hRqLPj+NJbLydlc8qYf6kA
lHixe0OyUZAlk7ud3RZd2DXUtS55AafYcAuUrWSJ1QZZjdAMd45AuctBoPsR4cbXgRgIxDS7cd4n
+W+Ybpuh7csTjMZwskQmInfa5upbBFTed6uXfIL4DBXW2BovJJkhUegNRaljyEHv7I5LY9LLDXj2
pCT+orJuP5NCksrfltDlfvJuqjFCNjcH6urxtgWOxShIAfooczQ3T6mwG+wOeyMdZglYD8PZTk2k
CV39HYeHysUyHrSh7on8SbnVf0NHt2ssLENBNLaGkSxiqDXgkDCaT2+FLFG45dbHcVrPMAQ0FHjJ
FtcBKzmIeR60yCNG5VAzHJqNZoTs0szSsQUo6wp1I7Xj3+gc8zCGHJCTIRChwk763KXeugKdUOhB
JKqDRzonWS/JrZPg48LaVYyZMZ28Bgbm+Nb0Eh7rWONbHgywH6Oy4o6EHwa9KBQ2Z4l5tzH+dgIA
MdaHNIfV7UA372/822SqMI2yZqQoQFjPf1l7jG8cLmIMJZ4hkwypTcVgmxKREiG1K/FMORKtAqiv
QZvucYCLtY6I6E/qmSJmhHgt9Gk/4mNUtKff9twwBdnV/vO6JNdx7fWxpb2vYflR77a3ui3rBniS
0Zl+5BqLtnYZYNi7qvkQjIEpcXMW6GN2XFPQuaB61OJm1DbRUE3pTQTKc5RNRRgF8d0EFrPdNWLY
pyZAj67xO7RQi4HJcKdrnDHGEqfB9UbA3YURkqSN7kagSWqjFbDsOchS4/CsYmu7UKDf+CS024rZ
gE7BAC67ZhOA2rURjUnX/rDzzjg5Ilr0msuifnQ11Q/0T8KPBkhsE3jtJZMLJzclxn5kOaZnqfEN
1UsB4vOWmnP8vUkYZOpO7LnFFQIpxzeuJ4V3kUYB/ZieJlEt0cywlOkDWzxCubQjq9zu6g40YFio
TTmywtarH2B6YX5Om33Ia2P7QCuYLoJ9RDvCW6ZLk3YWk7FB4RCBU27evRjWhZXhT4LBNuO1nEoh
UgObToSEiVrSTc3tfsUoXUzRifMgg1kRbVL2fKcndxgHyLWK3IqdwYxMwW2/vDZsXP3LwMZ74Xb9
l7ULaxmN4uUgZ7eYgU57vvhe2Tt9uzsFwI4ypAjjukaM12PWfAdHyBA8m/aCYBCxyiUisBtEXYK/
wDYOHMaiZlSh1l/5bLbUshBn3oD/oQbYYhb6byVz+PDHDxl3sGi81GbhfhgApIywMqMJEcNP/i5y
jm7t+4W7sBYq0xLE6v5Tf4lC0NUB7m02D9VgYshEoJM90XWockjWoN/5D02G8fRa3QkYS4gaiMtm
TqfCrhZdW3H+RX+6hfURmw4ZiI62+bkLkLEN5ZCE8/3Yz/iIsVqqd9o0uFLGQuPcxqs/o32z6uQ2
skNqfJaasBDfCC5BlT2hN7K0RswhJWpESyHLv6ECm3CrqR3maAgh/Myd4JpFScgBM1uItQRt1YEO
GH6WL3OGGxPj7z9+rsA35K0+hjLaDVp2ykRO16Ydt9rTYCZI81YkegnHqpsc6hznuq9l0cawIBc+
+kpDTry5v3eaPx6j0PxTJxQytgtsFFHnoC51yGpH6Gx3YrinfqWYC5vsE+FxrXCk5eYI+X+Fy59g
GGeIm5fZXo9Ed8dZDhnqujbDfFNtKIizZsZY2F2XXeRt1e8fNJAcmH3uPRCnLvZXgoW6+CsEM5yz
jK/DFdPIkNb/8rzN8m043yp9Btk4Iic75agA5LMdRjn8CzDo3iPxu36T11abiGiqTp5iU+/OQUUX
WStBw6PouNV6VDvFsDolCcfn4gumqhC/pbfQqOoY4p188M/KSptgpQ664TvjFrXB6FYLCDJc+TzI
CoC2r5Jaxcejrq/avIUlfOz7e9k0Vw1vXOZnLvJ54mHsqlJbHw/PN1KM6XxqOgAMAi8Xs0aIE4DE
25PLz6tBczoj8z/go+p9TgDAPZMng4hiTwHQ24M6m3p1arYbzo/QCQpk+r5NzCQctZyEEq0DOcU6
p0NMRBMve68n5sxDggXsfYH/WP8mPOLQoptoR73VKK6lTSGQM/xI6+I8s8yQkLeN8SrIARNXveO+
aPiFjGFe5FpNJhi8IC70sK++6ExPxbIu2HNiKro+dMT5329ziz5SDf196ra3DnygIHxHfTdNdjzq
FcHWM0nyTQk3Dld5euD3C30Z3SfbmmQ1nyUswQ4uB/aUM8SItdxXRKpAFKdjh8kXIwnzkePnbqtu
QufIEzBdrLpVlItdhm8LhHCLyduRSH0qGOesjFilaipx6KhEHGUqFyMqEr0bZY4hVrQJ8m9t777J
qmyu8zRCmSGy7aWE00PV61lWEws3UnDSJMFLCOMY807YhmEZvc4nQsaUGtWDtDgrYdyOO5ub6qKV
3wuGE92CQW/Gkg6+I2oOVDhJS6qiaLOnmPo3rirAm/0CPKMHFmYSf5TDH8TgoWv74OvL3CkP3Gsb
bI/0+adEnoqOTRx/+z7dii3qUtf3kcsau/XOu3gz2XBkarPOTwgHGkqtzUZCQ/58qKIqvvnalY40
RFPpeiRpzs3Y/KECLrNXHZxMhE9SHXaoSWpe4PiczSPK6k6r0WCKCSOrwSTBb+u/wAXTvUjQY16b
4xFK4lSnlutR7WVYfoVsREKZIqVO4u0PFWl06B68whITcA7PwTuubt+ZBocdfqIEwE9yxbnd0s1k
miO6UB90jN57wVTgeRSIB2fLbTv/S7FxZaRmfAbZy1Irg5dPc8ZVMQhVnSohlmGTCkUzbIEg9jD2
EW7W3YVk9h0sWdD+oBm/la/4mFFlAELzLpGPeGxwpcLAu5RLFCOCgGk7VpRIWUZ0B8dA+Ue/zsz0
Nfn6xkpwXv4UeSX73GVJcinMK58k/RlTyR97bSTk8aqK1DE9Sbpd6iik0Ll+02C9GPPS0v84XL6Z
3YGlWxDLv6k0Mbsd1+gOAcULjwd1PAi4CzxDM2jxsoxyPWKFn7DcnYWxW+0IX1I2Sq0dO2l7LaT8
jyxoWRMG1rQvQMoOin220Pdh00QR2BokcKNC0C1Uu2Y8HqZTdJmQ/aNPVb0PJaLaGioPWMIyqpMz
K2TJzAfU0AkC6LDKstc9wU4IxZYFVLU319XT3fgHDTOfOv4pQYb7Z3ZOlv+xBWASHVGG48Kxk8rJ
RRQ2lc2mXq7S2dw7IzGbVi/HjftUAzMmaMzrieG3+y7R/mYqy0tFwgEHTdgC3cZ8nPjvcBTNWnw/
rJyXEPY5tzvhGDg/NYpt23SXuMvdfqhVNb39OwOl2ZjjHEcBRVn2B2kEjX/MqLu2VWL3IbJGyymA
8Xu+WL6NrC5eB7Uh9qu3wOE3x2pR+JNgWI8GwuWH8N4ikzi+/mqYnvXQ9Z+rPry4PrQMJsHnA94F
usP7JSeM2uOH5kbZnvuNc+tNtSvv9lHTK7oafejfyIq7dwQKQbn+TH44sVD5U+fsGEDR/oO3i0kF
ulNNNuGGlDgdmrzmcEsf/QOcRrh56eoNGFCn5v4G3esmptQbSK8VSJVKifa8zE13fEM/KAQ06RAM
qs1xcCpQ6rPvvKowxEJDQdduPBJF5eJDseE+xvSFy6I6aEWhvZbY8aVnne3uYs5e6pw8Urop7nEJ
rb/tEhgLPwG3OlNnUFQXSLq+yRla3px35ZpDDgTTOOQodErhI4xnHEyDwUlwrAfC3tts8QwynCnX
hdpl/Qky5V1N7Gx2a+tpqIn9TqmyqZ3zrNFtu0GTlVZiQNm0etmeBjLR6Si1DcVyxjPBZDr8WlWw
BWiFUlAnYhP7zE9xiHgyB2CQOU43OLGhRG5PMARh44B+FM/vBsoVqKMtIBjfL3UKfhFRVesanWwC
9RKzHtiltaDuGKvH0EOcoBGzo7SELSDeXD8PQvbQt/vLOkbcJC3TDqAZ7maH4+A1m0dfTgPKw2Rv
IgNmOCavJNPLO58w9oToq8v1Q6zN07vqb0Bh74m5Zj3Maal2wCSyKqJpB+JTi/V2MteFA23p+8iR
Sls3DkjkPNWBkIeM0QKPsF9PHeEPm7XInNRvd6ixK52sQQ9d+771SYPVrDQLCAbwUFEChPyCGw9X
+f2AVRv0GbKG4shleAgt6DvF7k0R4bVhfF/+LV6+L0uqVdtUMcPDZPssZ/1ltxkmWnSYYTB+jTjl
1tBgF0RB8QQlYyqXMiDVAj1GL0fwAJYsgvrCXEO04NIPUEHEILE8NjQ9Thx3jVWXeV4kfXzFNXsV
fqm7px2x5Y5Mtv9Lqty41X0l+HE41jABrgax/x9WaxF/PcsPEHvcSXP1Xm5m4g30F+rfiolY26bx
5gXPQnJM9SHGBVBD1gE4f2t+R5OBEYlNMLwj2l5CB/8AqVmJbd2bj/glPYiT7MQ0q8hFNh8uTMBD
H62fNwtS4UZgwKbIhNDyAmJVlJ9gpjMwY8uhD7TMV3LE8c+s6dQgqMdh7r5JzRsFNkML3PN7sEjk
X7LkBo8UG4bmLNINil3KXChiax2lfyljAVULIG4+FvDa4DpdVg1y5JukHHIQP52tGjt1bjcX1bKR
hrdoO8Z/g+Hj0w28nzE3xO1FUgYGF1PdM5Tq7we8gsoZsH+/ybqnLvP5MPjtSb4afj42TiRIA0O9
YsxIEV4N5oyTPLlQjoPtLQAcT0rc+pWAgvu14ckwwmCIGYz6qfbVDbGeRNFPkU6j/UDbK09GSVEp
awGlo7n5IWnLKFY0qzXjx7G45tbE+yW0i2olz+KKFbwYpUPr/7oXOOsqW2Fl8vPnKwL9AMKFED9I
X/vBOtC0WpDBT2ysdQPgL1IWpzDLUAgTvaYpDiYfgoc03dLEroOOErva5qNK4jMb3LkHIP4gzoxD
fPanKWJ0s/fklzVmf5bft9hWdoYs7747+KEmO/ldQhLLAzkXjt6PcBjPOMZsrDOfPP4DJSbQ7PLA
lOvJkuP/FUqGvZru3+/YspKu6RNBDQWGPQtvG5ABzNVQ7Ql9D+5AU/WvsxtKW9bpc7tb308mecVh
4xmuQUYd7zF4ZFDk+NDRbrkv+voeWZEexOnzObkWyTnknvMs+k3liOkNLQVBLmHLFbPsRit5sTpM
DTTaG9bg6q/E/LlYXVRk0NsD57W43uFqX8L6AYOOcjRfI6+TaMq721b3S8uZzPHoK7D+pTc0I0Y4
V1DNJcLIn7t3O28gAQo8cASY7b3Bfs3oJhIQVwgb8FT1ninO4Ivpgx7jmREDKPwll3kLfbiCgtqJ
EduUgDW6ro+YonDMzX2r7W0ohFHSBrIAYWsU6LYpTsJ6D/hldNzTUBa7UTpT4Xazf3KsHkqeHMnm
Yyd2u5tp44K2H76ushZ5flGj2j6v4UOhWDmMEi30MmSeIs1Npf4JTlcXoQuHph3xQL3VHiF2G5D9
7fITQzdgqMjz9v02IRQmHMymVim99xghPm4qjkJHj8+Rby+LW/BopY7NiORuQBLgDJKnIiBHYSow
C4X4ZbCekNBs36pwwDRI4t9PVscC+E72KWVe7GE921LYQgjCGsGQaiRb2iUgEI875A4FbmCxIlIp
MHOupuzeoyW7wq3pfFtbOqWF0SV1ZbJxNKZZmwHpfeFMQwnC1C2h2EGtB5wmHNQpXuS8Hdn+WrKR
YzUpR5JHtfdmWIqsVe4ZKVnDOcTPuM3y26DePIPZfDTogxbU3acYBmGqqdKenvTcJx96NlaZyzFK
PIYGU3DVU6NwH7K2/4saQTNqn56RBo2jBL2HCO9YVa9I5wwnSVYNXsaps3So5FuDHz5qqk++N/T2
KclA5Y9tY92LxOj6ScktV6gplX5ybE33UKYDA9kBK10hr2Z8o4Uqg/C0bWgjDvod4Nn9Tiw4c2Nd
9e9GV/XUxv1KDLT9bgfPXUUMnZWc/N/BO3rTDi6gxKoEDkraSrGFbF7iaUV5yjr+tNnL75AF5vuY
fPDlkJ4342ZEdcRwrymjf1KDzxcqD1+lxU1yyoMaHvKy4mkMsG5dZF9e3sIgccOHkjOcm54ZKGMX
JS1m9Ak0NTt4Cr63f5WJqvyL+neJcE9F+vZNBgYi1lyBYP5k7J0vW9J7GCqjyAplM3vxqrnvQkiW
/L4f/AEXLAOIjrl30Bb5ocJ6AIdF9kGVUcOGoJvTugO9rVOyJhww7Hyn6zeQHH5nhR+v0h7vAtxM
oxnW1uXS7O1PpVWu+jf8ptBPmowUgi77Fw+EKCeunUttG/BK8UyZwNKWJ878w1E0FA669AgVkAl0
1psEwS/7vQAdJGOzEH1ygideY/Ah+nGeGQpePjDDC38OE6eQSlB7yX4RuHxLEeVukSlp7K+ZCKYB
FVSFH5kil5X8HarO923F+50WsSfSEYvmc/or0zRmdPviYSez7zPHi5kPb5m8wizxA/rhxH0fUMEF
3zQ3jYRB37Q5kMr6DSy5IjWCM7W9racTclAFDCDxqfKx/mTDxSKhu20PC2ZhuOiEca1o3W4wKxix
Bwqt/Gk7a7hGrcqT5pJ3fQ1NoX2E5MBHDumu5Xx0JuXulvpqSFKVBukqL1LLppxmPNdg5v6IjsP0
u4nprDZxV0pEDHJ2cNuLjAVdpWEgdWfNM7i2ngwAxMYnvA6q206FBpyv4HOlbKhHtMeh6ocZkUw/
EvWbhPNOJTuVGI6sslEXKxaPF7D3jppIOgu3Db5nSxEdN0leQNsH5/SGO6XVdncXIw2KjvADoIqI
/Q5Uked/IU+aBIhNyLAnRRlFxYO756+gu7YoRbTuC+rumKfBu4iDw8bB0ojmTjQU5hI1RH7ei6tI
frgIwopRvNugRLx1k+cLsvzN41xN12N7hphwt894lczvWt0VTfu6+fDrGT8Y+ENdrqn0z45S1eV4
+H3ihwkbkMjKJkQCLb290o7fvEJ3QCtcqyJiLrzRs6reaCw9kgjct+0zxOtzbrL9VzyO59pcp/2S
waTPfTehNyBC/YDxygmAYTwnotALfL6RuAYQ0dgSqzurRiar0pEwAlrx9sy6XdDiP1FjDzxQZydN
xQadbsj0y2bwf4GOKoeysCMkxyoCeZ/OADt1jQAMTNA28bWh3lJcPH5DU4daETxgFQILE7RXoiob
AjjVuN4w3tMjpG1UMXwBGdDA6PGWcOGLFqWzp8tXZvia9Ekhn5VDWSmimxT7KeNRH6hbgbk+8bs5
yOkTRDW7LOwvVzltOm71w+SJjPRdAyRBGHWcbj0LmJGtXdLrjVSN+XS/0jxh03YKabnoqciHSrHs
x3US77p4Au5M0n1cgS0hodPHmJYONmmYfDObkwh/hxA4Xdk8kfE6JS4kl7mqUF+tKPtiR6gY6KpD
oolTtnlU6YzI+uIU4ow2MkZT42iDOS/25WQZ/8kfe/AUzUuD9lKiJMQu0p+r+cwhpuW+M4Rt36cA
3pYhq1WS6OS/kRcAfGg7CklWS+A+5/KaCw8f0RV/kmtoaxGd958JGBTzDnK1moQ327+ShebS1EqL
Q5at+6A4cP3iBmJptIgGt9/pPtdSOi2z51iM686KacSMdHU+7TvqlIl3q552gdCcMdRsR/9HBxoA
Bj4aq4kFdW5fQ4DUWctwaas70dfoM3NPD+CP50VphrbwHqVDSVURBW5+sRFFvJIA1BZK3F+JVj+e
JL+nd+FFSKA8W2Co4OET5dcdRgsSXkp1+/GmskpAw7jdeYuBLpCjYtS/dMMhrX6Z+ARaz2kqbGnh
0W8xq1Kk/KQGfbuQ8yX+DbeKLIjGIe2sGZweIbpYzu68/ize5mAwFrXUG6M707U4qPqnHTYrv+vJ
blBG+T0xXRjfRsV1Qvc974isGh3ttkfZKvwAU/lms/Xk3av86y03Go0Y7/84QdVdbAvXU9Fm/O1T
+rJAA/2Q0XQotPo5Jn/7/pn0Hej3UWGOU/teUHSE+5SmVc0zqv53sEYq7sKbwlpb8LzDR6yatMEb
BuEHRJHJDRvDKZHVboB1Jl3TP6M6c3CvlO5xEUkqdq7qsUzhrgN9Neyd3vxbE5CH6tzlNMr8kIs7
a+q+Uuu6p239fpQ3S0dl1cZddd8SfK6qjemuiTNeIOfKAsjEfL9OMB0UZw7KfmbduN6IxlgCCTQt
H+NxxtVOYwl2QOIzVP1CT3xAI8J+94gfFcqrNqK+GF6VU1M68wIZn2VK2ggBmVOZSrvnjKD5c7R5
tsajqZACTrvoKH6PrsjE6/Y3OizBiDVZrxinCv02a+qz6cSWHWJpoyKDPQ79yGBlpQ/w+q4tvfV/
DpA3+RitNDzyDxisFeH+EGkTQaFn8S9EHG/dmabumiYddHiLzPAugcJo+VJkQgojUhBwXPeOf4ng
fkHnL9D2/ymqNy8FB+w1AMaxk8BHtsZYn68hy3gqm0dRf/EZQzXUJNNweO4Z7zEiPbxfXpnAolDh
2AtlEYLfGSrl/Y2/SPlYAdsvvDGSF/r3G9KLc+dOCFsnig7+qEsLFxPKJk0xQiKsmFyo7VLHOXmp
G7QWrVWs7c5CbZU25rS56bpVBEqD3L4epz1SYxCv/ZSrrOc6s17hVkUEXgLzy46FcKCzUIhTahdj
efgXIzSJMoKc4zCze6TpAytrXwxXASmOvdE8DSl7WSUJXLdGJ9gv0DLzMwvEN8mcz0C3B970Q1Oo
p9oqTRdtvWd6Z3gURT0OxNf9qw1W86Hc4K0/0FYj9QSHTaepRVyUCQCO5iPbesoEAEiwuxG5stso
SjexgG/ebitn/lXeYlCBpHQo/cXq2GqzW5skc+ZWwoeq2JhHFT07ghIan6JeHspGiZz/hX4layu1
CCZTomIyBPP3nM/8AOJGSBugjiNUNy90Sa8HQgjFO7p568fYlJIOTMhHRndEMLBcPWa3Rg0wQnPg
+wyWgQwFRXjUnOTSZiolt1sbmcPt5lHbaneow5m2ed7YDuTKOPJvIsFDMWXc1bK3imWwDTZEGZ2j
C1F5F5AdPraiHO/dFg5NNE70KxONhpY+BzohQC0WM488TPcOGKoBIXDQvlPpqWwpbZJZnoLyjuPD
jEkkF+QriELna2ojstC9h65Jf3uwWAPVzXruiJIlJ0F7hPvV9aG7uAlLhdQh3aaO46H5U7tllK12
r2hqabs0gFyG+Vr0EE4R8O9xZXcl+0ekjFpg7oaC24IkP5zkVoXL6G4nech4+pyDuO2D8o08G0jO
ksbjIFIIggnf28RHD4s6SMgLdqvJY9ebNzhQ0uW9L9LHLBBj0Exh2B7DOFg6Y3KTHkK2+XbsTq0M
n37nhByiV/P1zRKT70AqpyBIlibPaeYLZdLM45PlMMR/6AgKtnLhEWCt/cIQc72QYEadbQMsZFeK
PM0ZjLShiepzZ19z2GcOHEo+BM5z6RZjXHl1DwIzjNgkGxjnxFIJ/bVdswQl75fXzenGou5/YG/R
t0YwRnkrls32zzuHTwwO1GdiHxuGvXtnqyXJdk72biYf76twi2KzL7cbbuWFuRqlFGoMmB4gnoO3
Tot+6rmC3c/7us5NyBvXjSwAIg7jN6o463qgPf5HU6tr704WCckKw7NfZMOrEbr+DY7pCtUERIO4
kZAhDB6hP0mukfIlr0+d4nBs4glzUSrlDw8MnTBtsIdwCGSZfA55M81ZSab6HzN40cnN3tNrYVOy
5CZK9JSTOoHUnDsMn+nHrCiJC/jgFzb8Lb1YZB2ANYC1ba0RLnQ5YjLaflniQPKq0advSJi4NgqG
Vrlevyh0ByRtVp6kcwXvEwNekdgsrPZEHoST2ltji82DD/loLAspokY0pAhqBPbmVFcWHm6fzmW1
nO5YCV+18Rob1K2yRfigxnhmefqti1sgpksPnnBuRitfMJ6BFl6bMM74rPwG4hyWicrsXthRLXnz
z3muQwzPm+gCGCnwhvsKL1Yo2bWUBXOYEA7vaWazE2Q87rzkl5rcW7+OriLqWFJwSWQXaFdLuwwq
FF50lJqHfaZF9oNjgi4GL+elwrDUOt8jLn4rAX5ksE5d98WIlruC7v09BeL1xiu5v8lkP8t7h8fa
d2K5sdu8hU9x3mwAet2ZfNJIcAjZpxHwK4JwO1N/KcliSJW6Akge6A+DcGlrlyWUsHbCOqik2xoW
7xiztu2X31SZHLovWy3Hg1PnEYOAI5l1BoDI+LEreiOSb5m7WzMtae60IgRvyCxu/WT5DYe8w62n
reD3DlbtmbRz4jZnSwEttHq193wez+cQx2Oy38vzOpKWe+i9YXP+lobD8S+eCHLDRpMH7dXdMmcK
AGtuTvByTeNureCGg+1cOw5CVkjVHkNeKR2bpNJ+xy6tzmZW+6HDSlHqnBI+WTWEwt4d35BmZWww
M7eT14kSriVPxK2/2DTt/lNP0fqj7oJCkzb0DZzjyiRk2x7xXtxavGGwQkz5ZyP28Qe95JbEXAtb
EQFskOzk1/znQxb1KoVdLzZ1z7wgeddzTsYEHfqz6Z5V7BWDiSNf7c7RTwPzOMV9YSZw8UqBFQj1
3QkQCTlQ5hmij4VjcitXp1z4tTboC25PD3Ss0mWYptz5ayH02aNnx8Ru4sOejqBuzhX61ZzxPuWn
JucWGkqru6fVsjuTaMZbw6Mc6pt1lr1qtHHoTD0+EqHekDWWH1PbJIpkvW/LxAC+REFAXGO6Nq4V
O+/v0N0Dq6sEDSyLWWeS3RPS2BNEzRF4QVV+a1qruP12d6CedD5p2FMh1QwNRdyd7bU1wcexB7Sw
i6eZy3lJ42bnj5HuBIaan9vgHpa3Fi4Q9mMgykM/wCd26XAKbODOiEoJpRxwRo2+qgzaWHXHq++u
TfzVX/RjFUAkFA1t/k1NFnYjhPctUcJnde6C5m4g7nGnQ005ZwTHkQaxTt0/XDhIbaiEsRRlrTfu
reTcow5g5hEf52w9cywP0LrO5VJIlV+mzp+Cz1C9dbDqIGnvW/6pqLe19aTkR8cjih1fMIc/QVEZ
cFPI8H1WjBHLAeyWY4EOHRTdhhxTk0/49yE9MtH4nb7jCB5Mg5Go9zhoLDi0fq3D02EZpOCUJVIh
VdGmQHEdHaBOEa/U7Bz0BmfbjsVwnockiSiCtEdyFwmktLY2RTP9JCmtfmttq3DqwfFnQcuuTZpE
SqzogRO9TCTIw+7Hq7VANkTxbnNdZj2Qga8ambQWAujBYr9AsWNI7VTjElVTL7dxazYQr0x5P6ii
MpTgX40qY1oeDOnqBxyZnN9wM6NLMQCFLmJJh4MS5Z53lbs0NbduBi48vP7ZTPDm+MSq4iFrBzWC
HSJHGx0BRrh281U3r44jdT+bsXd4O2vaTw1amfx8KtwlQH+nDFG6XBy668TGBXsntcDoH1ABT2Ud
FbKtuHUyrsT+j/62I0iDTIygYbv6bnrYPbWD+Rb6ed0ldNfkWK5Jn5YRmeHy/F93t1YcZoUHwa4V
VDnM+Di9Dk50sImfT0UI0lXKBP5ZT/j2ENxXROxdQ60gLv7vS+2PnFBA3q5V5ZtrUWtsDbHnTE1I
Sex5EVCUbS9o9/gCN3lmiBt6OWEKCoj5km/nByUpQVWP+p3EFcAWiJZl9dZKxU06S4tG7vSdIDxa
qzy/DvPdN73P4x8jrwWeOzsgUwYFIc5UgneTSOqQr1BtaAQZgcEe089TGGL9OCLcB/cuvGTqiqcs
fCAa9RwFky5LcuSGIpVtw9nCPnp2cQfE33oYmSpGmj+9lDxq+Z3vsML5IcgjAhVGiRw+jhrCnvhu
EyK58o9l7UAQ+QRrlXBEX0rs93c9FbLylDW9h/GKVi2maRuHkmgYwgMojmL9gDjvR0TXrO7Nm+v7
M/zdWW9v3buhi2//6oYWNa0/I9MzCKbgdJiLrJ3GBkYnmohdaPBurAP/qBoR2OkIbxTSsSicwA09
6vn7Z0z3GJIyOkRc3yAHy20V6VZO4794HiclLZNCEdrnAtDCriPZSeyW7fqzmHScU8SlAlAk1Ey8
2CgU9rPFWZQ/V1UYqFgpMkZPWMHKGRJkaAP8MudqDl44DLwzCWrSTm50/R88skUsDuXYvZ2HmQPy
CbdmATq68GJAEICBTPq4Q2UWWJ0AIsZszp5jP9rG9xlImv/RCwkf5qlybRPC2t16HYb51cMyDHOh
rJw0ckYU+fTitQDaoKnkcXzUMuZ12ksk7pwHgLYSRmmWpEzpPAQuO5M81hsa3fG3iftvi1jlCXp9
fzmPOOBm8dElubphjutCv5WLWbD5eG31Qo6oGnqvs94n2cbtZMrDbi1EbW+om+ieQWKVXKHWqR1z
AWPUL4nFG7oL3neli7Lj+UNfjZ5r3l5Rk0bFHt2FANT8NNpBvpWmEjv7HMo/b3hfFrffJpehh5WP
SJbqS10K3WKxpCOtqq5VvH5tv+UGFRyN4oNcDkJZhQjYRyRq4WpcemYron8bNkNp94jRqHlMdpmn
GvBsMsbBG7W6nyLRk0+YbUMW9Kqks0JVn0jbkvTwpl/so1FTcc42HFuqXk6q04fjr/dF6gZvKLwd
QnGtZ9+Cs9Ts8zvyBZCXBvLYvh7D1JbjM/jy1rIVP24qRiIG1jTyzUyBgPTEa8XGMoHEmlz/95Nd
CWUPvixDC2YX6M8PIaicn4FjGNISATulyXRYg6frlSnH+j3o0yZxX/4PwNaOkT8S2NmpeaOg1DA/
j0P0+41LVftFUg/fZfy5Z6s9JAkEJOOwiNh/PPvInZ5oiUMcp/O38zyfkVMBZNwhnnTS47869tnZ
O3s4EPM6R1twQO65ucpxoGJJas35JgzYCXJrNtKaCbHRxLzlAUWlEUJc0EXCZRnjQNYZE3P2W8ur
8M3NuUxG9mziIH/k9Jbq0niXseWscmtXMXOh3gFI77B+mDiD+ukL0q0lWUNK+dr/mZ/hyxZxzjAb
mJqkBzIv5HnQ6he7jKVV/4CEU4lc0xh0qc/54ENDaz4jf3xzzUenKTTcAmTG5tF90CBnTuZt59nU
zCEDe/Dep24yjPvtvwjsukYSjjR8M9NIKH7vu+kc7tfqBXjBXInHlQaWQ4czd0cle+FpPQyZjdKE
0zJH1P12ENg4BvJBLnJ7sjSEtEQJPmtErEJok0trBNQZJfDR7SXIQstqoh6m7fbns55PrZb6xDWi
HbKDSEiJD62u5CL5MbPcIBfpVGUSELGBi+Gw3jb9zoQ82z+mubFZ2tD/FhmQRruVr4qHXfgYoiM7
+cHTiVpBBOdRB/ajD+c7aCSlbQ4F3hBqbNw+vuNXyxdB5VhNeTrPkYFlMkbuIZ6O61B+Srq4Sk3z
oiIRJTfK8tqiIwKclP0lcWJ2JT8uUBOvcA4hOKne9YYC0GxXvZklif0fxuqZKQdWdh3jjsivyCk/
jnk9HTPKCQ+UfrGzy1L3SJFTqCwcVbd+0sZkdGFQN5fs12ndfrUgG8zQW9v+G1IhzW5EzwwaFhH8
Iinwjp5Q1w1C8SMCoqHda9xtle0wOMStyAFv2lND4QnnhBIhomc0t3tKEd6XoUn8yXfaGZGUbDtK
mMNzGMGenxLQcwvAQeSbkZIH6CLpYaJoPutxDXI+biM7YGNFjCEQ0vdl5tvzWnRBkTx8VatBrWBS
0ekYz/Al6dwpLIy7pwTn/Dsiy5qEBG17SfM6IcuCLagt1IJXKsBY5ZQ2vzNC2maFzivihA/BxOVl
qntoQJW+VrW0uHsC4MgjaZZBqrSiWVXfRrI6KoulHKwsWp4FlhJio48nbFFWjvqPeyqprOyF1XHH
i/d82K60o4JUA7Syw5TMGZTlZ/ir3gLWPOGIZ4X2mUAMXDePmyAHQUSdWb8zejEUVVllaNEIoQeD
+C9mO25FF6WfzuFkbbzhkmAvjMy84uNOVJNfC6n3oA0rTWoliPt/ke8Ouv3YehtEhx4bwuFt6dEe
JXvFvlbJL9koMUJ14htlz39yrPfw8dyxRl+lgJIVQh53kXsXgzj1mYqCFrx2BZRfpXvEbvETCVWf
BDWwpMekxjADxvNOnLN3cQHNwwH0GTZDKwn0ZE1ms0xCII1y7hEi+6rbxevLFL0dOfZyPCvc4l5U
JNwCdwWuru/XlwGrFva/loDsXeqUb9h8Kd5X1LIzXw5UkidYbBmUDI3Ne4C3kDMD6LCPzZ9T2bTI
c6GxvQtUg4eCk5XrnHL7WEXCnXXMcyCyba6bHn8NRkYWevtn8DzoTSRW6xdKFWer8Z+30G7jIAaC
b0jrqRlsY55KO2LAehOiSWOynCNwcwlZhBHIW3x3i4Z9DsGzWbDvt5DKO2g3xitXHplbWLPQrgDa
e/1iJwfp4UhmOTDiYHhwIff39Cbgi3qcpllg3+Z/qVcbfsQfcSIelwab+SCNou7A3ujtQcmFYO7q
RT2Qq40MseKQXfeCp8FAZSLWeluWwyKOUyLUS87T/YLkHmSuSRWRjjYPONhTrQ3J0OO0Zi5HtgeK
9HwBax33ngpQq2fHnP3a4rJolxYNsCDxYo4rFge32SHmfnpPOkCy2Cy3CcLFIRwqMUMBHiHeTzvI
v+G9acXWiGoemvJU1Nq0S8/nsbeAr19osNjZ2GCqxZjh9A2iV1YadQ3anfh/sP0kjrxXSY6telT/
puw0pYndneBFDk79OtQafI7rOVLexyRj2N9rrghaU45kaUTptzPVmpyuZdfmRwXrxL0XqiXr3L8R
w1D499owLDTdVCLNKKq06WmtyAvirWdcRELJupQkVLbZc3oTAF+yEPVN30ZnEvPyRcdVUYY2oUns
kWsriyYdmGtVU1GDiTetN7X4dgD9nCFQl1CoHOXlQlT0D6o2Fnuvn3YQTHhPnQm1W3X0BNsxlb3g
DNWSZ52hli66py6mmTb+ChS7XS8alf0JFeK1DARo39BK7IttbZTv7yiDJkzPQ7EZWdVaHGAlLwZr
fq4i2XEZhWswBIXGdr8MNDq1tCbanIW1N2XTaYOD3XmX2vk8yxB/N1/uOcDqtbp7694N/IiapLaT
BwOC/1XYmGPEfQ5awLl68lVqdGl2WBwKUDKuPhUBZa46H+xqo4y6wBlQQvRKn0/uWshlCMwS/2in
fk+FypnF7wvug5lYvylNFDNCaw6A5tAbTI3Y9oJbfHC6stfCUYudhcYHGd6LFjgOQOm6DyQIX7mV
LeqUcqqGXYrGeeG7ORyKgIdJV4Oi3b6JsQl2HBIZy60Y1IwvS1Td8HBneMkL76LEZBgUp+yEaZfu
EEHv5Rm10g2GQTdnI1/pAzseC8/wDZTgcVS5NjK4ceeuT+wGROnscQULUlik+1VXWzeYM7CQJIaH
4eQr8mktvr9TcdEq3ywMcX0zQ2w6hdEjPfSnhqQPOcE5FGkvUUb80TarGVvVU0IpLvOS3kCEAu3N
oZzIidTjgshj6DAbOvmfJAUFcYn5P9VbvlDgnPBS1RanOHc9/2KLF5kQzFax1XeefAI0kIqUenGR
ZUEXdWsYt8hOCsQdORNf5pLCG2DakSEoAcXVLXoWWIq0//eTpglGvOr/+urQcP7qQy2HpCjYhr63
TaC4+Okec3c2Gn8Nbqb97WYz2lZiGnswCJkvq5i1tjxu/rjaW87jLBPqmAH8tTvr8JhqbAnDAlNF
3/kYRnF09CjBZHg27WRDixopCywpNPuSrY6QzSXrN1mimGe9qyd3UGhaohvaQRMJoIECnULkKmtQ
MtqlhKshLm5CnXR9l8MULIpZX27VF67WaSXNTEXqVVYUJBCE9O9jm9DuoETllEDNnmXpvf4eicOG
GHisUst2poUFLXCCh4/gm8lCE7qA1q6g/6dnnh0MwkC1d/mdEzyceQmUJ96KOzlJMvLQU81NklP7
zg4w9/u0lbH0hdhJms4FvrHfu0YIF8EsC23wZyHB5RhUfWV1ZzVrcnk4KILRy9ypRSfPyFyIj9MF
NPNpZ+Av2xnAyRVw9+GmQ+jygGmFw8lr+Zi1KqB+jrR5kifX5lD/2oYofhXCrHh3N87yPobPnUEV
b3hGJa5Oko/tI1v4bCvnhN0im0xhZ5HgfWk/sFBRhTphShCWm4gMLGKJZ6qBqBrjarbEFzU/l61Y
oqRk0qxcBbolH3RGxWXYgcvDjGu9pSHDt4zNJPItepg8li3zlKc3st9iglh18fuMJlLPiYIf5/gn
Ru6f1VjwgSCfdxToE4D8UMA1y/f3/BYaznxhOi3EiTyebThl+JqXal1jho0gLSH4TdEctqKqdjC4
NKeDyBWLtNvu+lzRf567ciMyT6AXLwApdFgKJeHTT3bgRkAE/3p++Y9MqbDOL1FkZYE8TF/VjYWA
kgSTY3tyxEnvt7Jj3l9eYgZm7SJwfQCLJuv/BjYPefTPnm3eSnfd7rgXuckZMxNphPQKaRO6pk96
PJn0M4nKcyI5/mADFMqw3L9VUJ7lizatLhF7ouB0D2Bb9qWP4Rz3aGYOjMrK+6dPCSxPDJexYjGP
eismrkqwElJkxU0RtG5eSqKHleFEJ7jf/g6b9mDBCG2r68d4kyhLw2gPrstwwAa2Eq4fDpLxzsgS
Xv8eLH21L39gvcIRjtlCNJj6iJzXu4LiBY7BmCTpYtX87qfL/ORHU6yP1J+OCj9+z8sOXbfrVMoA
5odRIZw+Y/9IeQ23WpJFf2w8E32Di4+I4Ln0Aj8LEVMEhJ6LBQTNvfNr8//1zF799HmqClbw2Rx/
iIABB3C7YJQPGEcj/k/VfFkhw/N8rvJgQuovrwrHia2cneB1WlXbyRPQYfujLKVzKQkvfPTaRHXY
zh+1F4LJAfZj303k4sZGqvD7MLYKRYV7mXUmr7Uwihjg1wtZtKwdgqehnGhl4nZuV2FRrL66peyf
rBPBCoJ0JyU+ZgU5PctkjtGAI+YCffXbOYanxm35TPNs1BL0eHMYWxY2IJihj83PjOa7TCVP+MOl
jA1+RkBjf9xnIuagQEQKmAU2pclEEFOPcfhHarpqxaf6aL8dT7FfWImCk5F6BYFV8KFLkcYE3WTT
qAha/KLXeZ76iKG7bLuHphLAHPWbVPWTLxHlvALX5PoMr5XKG2jsUTkRZF/t9RaYzIMyualiZwIv
8nS+V161CPdFixCmY7TV7vscg3iePXSJf07V6QjINUiRUvOMaORuNtSwbKXFPuTcE6Ac2iyJCrz0
/TGGcL1G45+E/RtzXhOze3wHxj+e3dnS5SDTFTpTAXZ1OQhrAnL832toIV04sLRh4rEnetrDwaIH
IHrMfam3pcDAe9j5Pl1uWyWtk0ufFBmwpCxpw7QF3wLFc66gKvMrd3el3IDKYsWrJU44pPCOfAlm
8TPqF3BcF37bIzmB1+N52WFXMzr4THD7VW9vU3yGv5meCyXVuDBj5cKpIMBDO/f8niytmafNCSnt
FUN8Yaa3nhzFBQzeCOiZ/6vkbqyZpYGUrMfSVoVceOnA87atp1e4YQOBXRH9tO753DB4lofQGM2p
BR6HlWcDZfSPmqFLbU8+aOAplkimYSbIQ1Ty4XSIU24V/swSrkw6e31PYHu2dGeM5CzL1z0qQMRl
C5UNgvAgeISYRXmsz6kIz9yuyaA33Dxvpv0Uz4n8WUmuDFkxZEycwPA4kaQL3OfIZcqot+9W2Pdo
6PGdeHDZOlcTC7arCi0FbtuUekCYgU5G44ZlHZEG+oBhX5NcAzUsj5fbUY0OG0cHsVgHlrDehE+U
CfC+hcYKTGhCRgjwivFaOiY/JyjlSeEYRTv2GbAEEVvPNQwepCJV5xvNqMqvarcj/bqtrXoXjIhl
N2mdd5Nz09Bv4rRSEwh6WcgzK/z39O/HBtGqR/exy0PovuGXLRkQlrc0GVnPVCQB0o1CFAL3C4EM
kfoWuKvX5zeFIHmZTonyutbIyS1xIvspEhKm4n2IHhJ8USTqpkI67FK8RHRcGnTbt51m+ycV4ImM
8csU/Q+YVa/fdIbREWGHWcTq9FLUDemh+yW1sbeYrClkwK4owecqmVYSn4alb+sFilk/E6DoJWlR
71Nb1IePI3+xFXLXnTiHWvhEDsIR7zKLCsJaajtGdw4zy6ZAIy78kQs5sbW146AWVUqMf8BfLhLq
aAksbA6lipz67B1JkcW+yULzUhOiDxDpRO61J9HejJ3HPjBTGHD6GuqSma8cP8dD0J1TFXGkd9II
djtydF+lvqfOfpNP9kxs1PXys0cE2iIgstPGprG8Px5RzekVo+hb/fNqB4q3hkyBRnUudNoIHxRC
9Q5Y4T7lKKkWh1asCYoJiPuno5PLHtPFtOxh+mEp5MybO/phXDc13Z9U4vL1X2/sjidEtXd1DKjj
sXd/vyvibYdhbW9+2DunFsVFDajZyfIg2qdAJXzclHNckQ5Wy1znbf5BVosiq4zODJh76Mrzf6UP
4rg1wHsKfLo8ZjgNN31grb/HvRkVynbKvHpH89mIaDNiyINTAFeNu9o32z4AfQvY5C49nrXFk/Og
T1ad4yUgdq7wn+YHybHBdBkk1gCQT0ie0jXGW/U01QaCQ4O8ffN0XyYNED9IVYSJ+v3he/XeyNhN
eQXOAnoa6Le8yTq1Q1MJfq8/p/4jwUovpXvEdRjOIiPzY9nxDmN6R3s5rmofFEZEC7bWzQE7YuN8
xG7fuEbEa2fCRYSD5STi6TWLQImgenyOspVxyAufsDEzikY9tpztliGI2Yuly/kbfY7kNrR/7uIE
C6miMs0tC3yRJNYN3n15vj2csdpWqpZUmFgD3PGOSJsnf3UJILuI7+tm22CI7kK3tE2oJVD1cI5l
Wtj+QTHFJwP0az1hDw4X2+upDWOAGyRDdkmjUxKosTIyjFutgklXiYxB+h/UOBWr79qcTbDHqeMa
0S2GcvTn0jjPV6U3sOtlP//1mqPUYOM9vcX6wgyzX50yZHdYV5HSDsRVDzlOw2HdI1Y6nmOPRt9b
dDDDoFWW8jD/pSawLX/9yYtY6nRV5Mj4Jg24ColR4O7jgQPgDfX7gYfR6vsa8QmmigFB1b8OSboc
OuSQWtNR4UexTKQVEd6khSu2cPoFj5Oz3vEmECFogyLechsIQLRl41isaSAiL6yTY0D3/tnaDRf2
8dtDUTczGm3AskBEAhWeiU+yudIdwo88gQDbRp9XLURBEB2PKos893kVWzx0rM+Ht/5O0Z8OX9zK
a/TG3qh3sE7zTSSZVXG8qd/Y91owgM0f7DqZ38B0f7khvl2SYoUDcGuVCQU7Pf3W0skai18zsG/V
XOgr+Ri6HQaPQfGtcAAoeK8oi6fGElwQigQOfKegAfdxxVV8PJJ/6wdAQVYcJvOr0H4K71RyJ5NC
4tosVeZtmuJX/jbBCP1Idxp4FPiS/Vfk1X4diSekl46/+TTKAp6QUp9dCyNaxibu2uG4l1WwT37f
G+aVgdSzOdcHgAKzZKAlpZN6rsmYPOcI7TYbpThC2aXaatnIi10F5S1r9lczD3tLb8OJFQvJ7GaG
lkOoMAkicyA/jcVwVd9J0MFj38GYkSLOEhNuRKVy37dihNuHhge8XIS5ndcN7Jz33VvB/X1VzYLm
FMnGD417fQcs02EjqM3M7OsskYNVKue2dH06G5k3Db1KP2HOwCd3cQGZecMs0APWPT3xYO9oxPmX
rLQrOj7ZAMgXHSFAuyAoh8QyPYjVJfcUfHPESfhVdrcZt89n0AP4hSGKtqnbvgvs/ApH6xk89jYk
+rzNawSnHILaiy2s4d0i6RwLEzK9X2WS3HHrWwfn6g/fwWtHooulIRB157fg24oqcD5GOqi0U3DF
gtvnsQ8YtBuwF9RZvskTC7+rTq9OnIwSx2qwYXJAboN+balJFLuMOi836vs7AT7+Rzcu/LRXqx5N
2F9re3CltIiJYUCoj4tT+Zzuznry2ufsDoFTgevKaBHlDwiszIVHQ+DuxGLejUXsZxH7aEsoeGUV
KPz+vkltuGtq28vzFBw6oRMfD+zZ8/1FUBxlHzBUf6n7jRLNCIxjdpL+FGRu9ob/x/U/VrHA49gg
DW5iowin7nQxuN/wzyOHPCt16GcLmegqzJ1E0vKg1zhzBXuTLHn2y3dBVtayp06ie9dd13TkeIVC
Htxh+pihUFFwhSU+lOBPSidZRLafi5k0i/ZqdnBGXq/I3TMnpoeZncIwKXAVqtWGyMG+eI9X+Oqu
qgOdW09c//8ejkg8cP7hMFLtgzMscV0WoofXDU7Jyv/9iUh4rPQAbIangb0tIb0Pe4UIJRWfWC9W
QT9VOO1KyFF19tBiZG6WKELQX6aBlQ98rmmv9YD6fNDxrkyDefnV+HUY8Zc732OY73zOXzQFSDAw
J4CMB/vfr8c0x2UFonbWiQlCSSv3IG3o/3R2IvTK87ZN+//U9+Y5vF315Wud7dFmbVuTAtDI1hSg
1lZo24iDHoCN5YX7EPdpE4MXKXn48R9a3i2CoFOlPOQ2wpi5JyoiOfa994j4RS4dxSxTdqoiCl9j
2+mwav3PsGRAGiaJ1qbQ5qy7zs1vQILrTkLEvrJA7cGWVRQQJ6o9zh9Z+K1wE/dMG9c46W1m7Rvz
Vf/dT7Z9Dtmd+jcm9rRVZw43Wmkl79QAygaaa9KzMe/O0Dg38i+ze2hu7hV2LBF6viwTqAi1+tjB
Knx/oy1c+JAjoJczkMMdZYZZ0xmOV5HBrT0sN1XO/XsJugyUbDlbfHn7PpjkpbP1bsedNpYspJYW
e3WQjauoJDm5qH+eJKWpMccWSmYxHZbxRslh87xbTjEy8wxn8H1G6Md9fndYnhMM/RnKJwY385CE
d4hEIUx7kXrdOgkxiREqrF/U5SjroXF1Ijynxv7s8C8RIJpba/dP3FL2Z40herQG/0sCLz0Iw4Jt
LaQtZGtmZD8w+ikI4Q3THqWGQ/VmxXnQUURFY7DWH/MYUWuNl8LkGG5Fm2QmpjW7seZdRUi3oMer
MBlaPcZWd394K4TX68WVHIt7IpK1YtMKrdY4uHp4R2OzIdTZ8HqhzocI/V3oH7TrE3rf724f5CE6
mALi0OMjSqDkI6USfhuklu1x7hqHtLaa306T7wg/QTWmfC3N9cQ4JETJ+yP0jxPMMkFD5cV5mDet
ZYlR7/Q9mqR8AtKbSW0zG2jr5oDXzSNKFKtLjrF48Am6GpB5quxpVkXIjSTr73jTpInrKSCXFvC2
ZvOvOpktmHj2siuFaigEpTOzckhZBzk7SaYLBch3XUqnFk7/tXvRmNehdFymqIBsKnK1U9c3tRE9
JoHZ6I2VdgjOhYcLddbQLSv/1iLRfkuJf/hlK2xoLsmtVeu5ElzPjtsNM/eUEDh6MbFF7QkPHkFI
m5q5mEnhS8qi2AavNksZPH6+nXyhw4jCuWpCIz1oXhc+257t2xm/5Jd2Yk4w+5U4kp/Dd81F5fMH
wQFSeV8eQQt/GkO4UF+wn1Gisr7GjcgGDWjiMIWcMR9Jwuwq+gtKZdSSplsVvcZUm0BzVArM9VhM
V9B04fGyq1KOJp04/IKwc1e4Gc6obnr5WEdImbtlgsjw+cSM8IW8nEEJaW1xZDXhIkL4Leoa3JBM
O+QF2GFATuOcyYqxWqH9oXdB/29HZitTMpXmq+FqI9fqnUzn+VVC3IJ8U2y7bDTlXC8maHn0/PHo
YbpEX5nH7+3p2WW6dftphSezjqoGwPIQtl+LOyY0E14m/qr8pTkGmPIGUqehhSORkwS7cds9tcxl
bhuA9q6Z8KzPvCoKbn7A1zf5bP9S17ESw9HltQJ77/rKN4MpycPivRokzjwLBpajAE2QpDAKLXA/
nsf/Pzm/xKKbjVyUZ/SQvHPrabtLk1fEzM15AvyTuZfqUCR/5PKxEMPnmYtYfVD5ObPirvVPi5Rx
oTVG4fpUf4VYn2N/llFJLEQv3o1VpCo/daHCmj0picfoZYvxBHYTxjYjR9AKQ2xG7RtLfTe7Bpbx
XabmaspVu7EL91RjWnngzAoZxfHvZcDvSb087cPp0BDuXZ3XtXSO9O09fYvSsITKfZa+YGOLNVSj
wDkG3TVha851xoOqrGE9GjTKFLWQBQZgSTFYnFxMcOcXnwG2LtwLXIEdGjsYEjMrE2RjnFjokrN9
adZFMZmhaehKbo17yCCzUxW+mlCFLfU2pX52baM2sKIycSBe6OAxldgzx9UuvwmMZAUCeJQwG3uy
T1rsSmU00Te/pFKBO2XYLaZkncYlw98dgAv4uDBi7saCI+2ES3kd7ZtIgfwni8GvdvxsBJ7p72f1
Pji4vq2Oc1DOsoNJZuRxCrhTrsXBkWkyhd/7RiUvQFvkd3BEzNJmQqvqWKIUjzxX40J0IX3N/dji
AiuLZavtJaCILaS9fYDe4GSqmh4Nn3EbtKr9/bmV0b1jkUUxMkAGGG1x0YGO2CpSIpKHlELpjNap
IAO4Fwd58Di9oUrYXcwkvtVksjpiKpyM1HZMIhKAnmYZ18WQYoVKquKP6zZ7cyBvoBu1cnlekwKN
ZLwrqkEnJNWhl/8Su9hBn4u+2Nk1oNUr6ZHBwu/Qu3EF32hLpeXUmQUytBtB0WmEUE4TdIUTDoFj
CMkD6aFVMoYYd4oBW6p868PEAdHleTIaGmI6nnoq/s8qIx5k3C7MCPQNx/qevTfheePVeCQdMMcJ
A8/ys1+UOpDEpIAUO4aChBEomcUwKYbPMX5e3wxNzA0eZhJ2ummiH5T+yfHbaMAgfhOPD+Ik3b2E
QuRHP35rlEJGbZlJR+qehscH7lPGBArC3d84DDLwzOzMnexzcfY5z4ZMwZi56oPYCPm71IX10fx3
dbfc7yGlkl3ypjA8+xVbmkP8Pe2uvnzHb7ZQPw4xDAI8kuA9y1iJAdZyfFlGoDSj7ziD/isr3c9I
MiwrzjSnSP/oI2e2UY2XUtDyUhTVzKSF91A7aR3OwqvQPvVNg0xxcjtIABuhX3b48LkAH7LuL6Lq
xqM9vLKuKCdr1Ql+2v8CUVShn4xO872khTC5hfqusLJKMoyOozJQ05S39gs9ZNAHpHfSvyiyERK3
Ffjn5Dz19xdAAdypNipkqQTQEKI7JB/uTCSOpwSzQAVdTI/Mzvfx6YWyWjF8NZ4s8Tx1MLSkwp+X
UHxhVlIkAsZeesYgugwfqovg4ilSLpfPz4dDmwAgxXqfAm4yRWDCFKE8o6gbP+vj6/vvs8tzc0dE
cFVnjC2L61bnRday7RICdpgKC8gZtpYqatQP7LYJLO20Lg1XW7pBJyxRdQizOesSXQL4ayBfkyKF
ysjUCA3mnXcGV5aLcAczbO3BrsUYve/tEafxBqp0CTEq5Q8Bcbh9C4nQ/6l2dPTF4szjECuauxtl
WpXkdxh52jZwfr+KMu7LsLQEbvi5pc5/ubNmpuqH5W+qMJcrXNbhMy9rDvMQhSTAqHNI6bxBXiTe
YRWPGj5HxOeQezsWSRUme+9yc3dfYkpUeikA0mkvh5Fbqeeuc1zC628GQezbW+BcIWVWxa1xtwVI
dF76XFbKvnK5pGloESlgrdM7mRZM4pyVlQD6D2rMPwGSnbXz8H2mL6Ycwrc4ONR+0Qfli2rFkftm
2Ga1vkEkxfKkUpFGxockHL7+cxLdexhWLc3hesSatcM1/BfJE1a0gLiN5atxeMQcFio635YvbMV3
yGFAxTDtBfEZOoLIcdtLcfGF5pomgRnTX45JhJMJZuYQ0o6dWnFls9wnAyFR0VzBziIEoHGljetx
n0cbCnNT9V8WE98rPa2CKYp8fopzHhxdRI6tSrNRWW77j51wPN6IdJP+2uG1uVqIKgMRWAXps1k9
iL2Ll+nFsIabV72vPVHLJ+Nc08oSZv1OjJ+5e7HCAU2KWfvrpLL2jmWO/GItS6/vueL5t+WyGytm
LesR44mwpggjibJBMC5L/H3t+4BEgEJ1eK+0q7bX8GVnbpT5gf2aPHEGJUA20VTUpaFu3H6Gfd+5
BpDB2xjKmg+ojqTtl3UKy+XekPbePOvK7ksUFR790TmLL3wJ5XY4UxyygxlY5aeBXZu/gfISxanK
3AQ5wJ3pyiiZkekUKGSHfdQVr6qHP5vtJXaGERlZFAmX3RoeQ0gb8Olpbl978JLnHezSuD9L0WOp
hiLCctM36tvL8FImWesF9T68i3o+hS7r6sRYfJCEdzRgVq6KZrtKfs7UXvCw+q5ZX6GJiAUw4jpo
0T9UWQn5YoMdZAIpeDbAl7hPmGoQVIA0H5SpjPH4YATHF7GvpHBlFJSJeBv+2AgS30zvTKCTZUIr
gdX8fH7h36n542F6VMiOeAxZg9X8JapBNRFQNSNiboryphVfeX8iUk8UiS3TNqJay1GZTypIS5cX
+bZ4CWTbSeNnZ05YoMqyLe3ydQrGpo+f4xx5A6CFbWG4po1qaCvlcp6s8oaPl+LHpqPnzKXEmqJr
b/oGPHzrGrw4xl9YVJj8LAmdKiSh7b7mPrZJO+Bsr3lWZ5pk3UHn4YkDf9+2Q1CpQa6VUl8ooMxd
tbfPDpxXIS/bw2kFIMSmq16Ac/ilgEsM7LY9Yd6M0AI8Jx9EStSCjaGFHGyUqjLM+zz6x8sl0GAY
1/DffeDf1Zw3A7qhBtW50K9AbT6gIN8GUJJh6hCjidmxnYCPh56Yc790Z7DBopxWn6joZkwKhQVe
09LxcfcWIRZd9RG50UFYK+w+amEkh1C5XOlko5hX9BEJaqalbNxhKmhS8N09WWjut2PuuQjICLDT
xbNC20NSQIuRDAc6aOLSjf2SNjZ5ej37VmPltNYHpKZTmvr8yDLqTsYyFbLgCM4BOamDWOF/ftRe
U6BM6u0nsAL+lVMe7k/zs+bMfU9ngP1evlSYkgsZp8uwRD56CMskfYhvn1uMvc1rwx1W5MaqQT/v
1pfoGq0DtcAKlW6PWryPScz7kHFVatZDxDGeIPXvnsGuVDmeCVrZVNF3hFRxxC8v/uofCP3BA5zj
cIGnKS3c1ncxpFA9HPgdN9xlZKk/iEupt+2qRTE8BsjV77EykzW9jeRoUWU1g4NsFAmGrouXQINV
Vyqv6li8gTGPU2X+B5KikIkSlaWm+QKZHbmIROpteGXr177WKi1Z2fLepJxMcBTtlXqJ5UGPTUOp
gnHf0qSWOvIg27CGGvPcFj6oTNZaKcMFxPxW7GJc+o0Jk+e5W0r1mzkSKBbnHz9JwXklTddKR8Zk
SHbLt9GCDL3Q+LpFh03/52vI75VGnx5cjzJp26ur3P7XZae6zrWhInEnC1sTSbiE45Ys5yfzqOkg
oBGpsScqmGBSEWDwrUrsW+5bI6DrMKZAy9WI02z+nYVsL7/nwesChlF5L6XoOLizRnzFysOCIqvS
bTWP6OjN1TGH6c+UKKC9UZAFjZAu/boYYRCWUNK8bz8XVDL+ODN8IG7CQ6n6PavSLo3grGGMiR5z
8XaPBIVJkcQ6o039yrS0T0MaiSO/ZdF+u9QSyeDqrssMC9OTZfQBATBsRz2FN4jgW4TmY0SV5gVa
B6/CzJbJ+Xg4yFi98Vo7QvJFybU/SV7YIhX991RyT7ZAu5Ln4/wosquTkbcM/AOn6j9iS3R/yfl+
kPeJlmHiS+uN44lW5yHMbETlh6sCK702CS3EsmwCgudoTOQInA3J79YvbxfLRZZnjQLFf46qBGNX
E2PmA2vvfQdNGjsTIbe5PulbP4Uv44iDsGzATX56sz+m96oYmjaDlCvEajPMezwlo1lEc7r/Y/Vy
4DIqb9YYi0DvToqONAn6ztanIgT2enXccmz9rvDWhWBrjuoEIIXt8K29DultjEHCo2NQSonZJXTy
oOIXYQ/Ov0jHNOPAxltRF2ouCbw6uKcr/bJNEw/Hn9xGCoXK0oaQHZV2k9poDPykU8ugkXJZcd/M
0GV3SGNSBNfQEavqwu15lp97iux5lil09zTsWgrRRcmJzmlSS6ZwkpaoKgZ9DfNBSIbcmHTagXfv
Z8UE1KM0+PH5EUXxQaVeSh7CfTFz6qarx+doJKTRgMvlO9ckhpBexSsu23rfAa9xSgd1DQLUEnai
t9OZnMDOtTch9HTAaKhAupZ61Jdcy6gYrypyffW9YVvQl0P2vh+zo9NJIqK7OJ1pc7ruaCPalWSh
TrTlVxw/5BeBpj5Apjj7EAPR7/CmvHRIzzG8rlJPCPG4v47YrOTY0b3uKmW8hJ9IjAvpDdaagIIp
uN0ZunJquctWJXrV+gTE78zMmPSLhHPdpfCjz8CEmg/oKMMCXHsel2EduyC3OLkjUBmXNOEs5YYm
DtWplsaVE7GqwjqapuAhSZuUhoBY2y3YoEDomVQX7jYGjLGKAvhwqU9xjK+uAYdQk9V47JRS0/Vt
xjSXrRMeKrS+j4UktTBgmYUqfxaf4kRagk00UM8YxNDdkq4VeIls3diPHw72x59C27Nz7aRblgmf
+LM+z9nRjCGfRMjDgucZ9ZJTynB7FiRlrD87u98HS+HjveoT9f6DYokhnGtUzIMt6tvZNczvgDIY
hbu+bQw5yNvWQN3BKk1AZBx94LG6kirjXNuHzrM6UcgYRPCWUQ5Cvm6LimMap+43ebmsS2s7bq1Y
7Om9Ttwo/pSAAucfUIYZiHx4rbf4fMtFm72qdfReQrvhu/dnCokKVAEzHfBFILPpn08LNatxcD6G
jpfEWXGb+K+8cio040m5CpeBsJ0+7xBe+9ReL4oJEsfRyyFWOHD1ik4QKg1FSPzTfcvGyRqFpcP1
8O+sG3GevyDwj3INvltr7PX6p9BodEye52WK8yXVOKRnxnseh6LXgc4ZGWSxYLHZViALkqxh4Xng
3U7127OQqR2tdFlkrVjT4MfE5G9olYzjwZdpkJQ+XgWUhD+WOkZSBFQQxtlOtq+v8Oc3WigSmK8G
8phHgd09OT2nh+QnMh5HH90cG3WmDCexVv8M/gsb7qEaHi9cPAE0e1KSCtXBqpKZgMYGvBYSkWT4
A0w1bqzW8LV8qpTJxgYCoWA61kMgOvH+9QxxSqA48qQHLFQpGv2MjecHeq91qwLpi6Ho7lSSHidV
hyGHT8Jbi7u/IxIjSdaK0WZb7cbeTvFm5FlH1w76OsIaHYxyqpso64MLRR6Xt9PglcH/1yH2ZRwB
irPekZ6QRJr2A0W2IaTpKLFMmDjVuu+m9WLqbyvMGdgNtVav/+IOwTXx2tdAeCnLmaXFiv5K2wYb
k7JgGK59IvCTvK482zTQk8MDDkrA+XKakgxHIY1Snpy4t2+2veZ2+n9mk+wX5R7KqN3hWTqd5tTa
IH+h/l1TNhtqQQilxGdQOP1ioRmUGLXWKvNLl3HCdIMErBsBw9WWAHG4wHAIcJwVsUFWlnzsY1b0
oJ5VSwMqrfq5pfCOXVbzRPIN4OuZW8uKq8nP/48x1A9dx2DMsJYnBKrYylyv0mhnXigoq5+EDGJw
+HpTQJ8Ej+HQjSbTIEJ6UOmPOembT/RcNP1qOR65bBnAT8xuC1y1Nnk6pRlydtAztUWaIQyob8cV
2lyLcscZAv6IZxm9m4v/XI1JtIlOSWI756lkViFk+ghhxkc05+fnslJD+6iXsrZL42zMAEmdbwwn
M2Y7qNxLDmWvDKCFq4Ttp6PCxw7Onumw1qDQgAz1NKQScxLaftwbrQxeborOn3GGabJOv1VARlpn
jnzi/FnmR/gNOC8EkJ+JunqV5D6pcdJa4OM6JLHwmBtmsM6+9Cuzj3FrdHB8uhmNopaOWfP8W2iX
Jv48PfnkqI7rJy+ksI5vCyYTekQqzjJ484CnIBbJrwf92Z6D/x6MQbakNjorFQ1iNMaPAdiQmLkx
3n9D3M1nQZ4rjQyCKMG5nF9bxU3hLOieQuSX4cCoZkaKLq+PeImRLEJJQUCxwY4tqmjYroyXjF2m
dCdUqSZPWwhE86FKOkmMgb+P1HJzL2dvStULh/WNKvqKqjBnzpUhwWrTaE0NuW/hLHhtyaOZ3poN
IcdSUzWM1pZT++otLsQiQdSUqh8b1pwIJN5kFLAAXOu4kjyKkszRxTkgxqAPOOn6bvrg27U6sEvV
6D4eU8UZqRjJQpGZSxg/AmKU7GxR+UAq8fENPaLupaQqKgBHAHOo/+wrkwAtZsubhfTePEUPfKdV
58wl/S5olcib3VtSMjde7+ovYFD+W6yvXAedXmZ9JnJk2JcvHr3vq07YgOE/VoiyJ8OzOKuW+fBx
+/UUa73tE9uyoJPs+HAP8i/NV928/Zm4mf0D/+WFdBfEzHhz6RlW/XZ5xF443jW2ubAcjvHPFtmM
7kROD8aCW0sA+/KQScARYONQ8V9iuhrF/jxPYd3oEu5IFuXA1RHVMoawrU6uRnVXmmpFbsyYjXbk
5MBkZ5vc+cR7+uxaBg+pUsAezXiLbU/t/EjYDeY0FRk1msKsHORGDlGdbXgUht7Vnu3WLijLRBGt
f4SQOAUvrtyC24KTvxP3DPo+6kSUIK/XNJ3n2DUE7qfr1+mZbMXPRORn8y2bc+f3QtoTypPvZjYA
Nz8ouQX5ElZ8laXVS56iv0jKSmM5krNSaB7x8WGabvBhW+s3sdJ0OcuJfuooj1UP59TFtiP3HS0v
ztUphovt+MpO7melSQWoKaU3kyPzWVf+FnSf2a94w/yoisxsKyTWaA7jpQutoa+tRVowEMygZere
OKL62WZgHNSmGiD2ugzjFODJ/mjC/fT5A4W2NiH7adAYLzVblGK4qL07+76DCL/d29l5eq9J6rd+
QokdQ+rkFL8OcgDH1EaVOZ7RMW1hasmBnXog7K/1JeUDCcb5hfY/sH72VmA1Cn3Tblc2+S8z9kUd
rv/HMTAN/n5YFah36p4g8U5JL795NSLTx43S9Llh7sTVB/e20fZWI9uQ4pfBB36UjFh+itBGyV3p
CWsPIGd46zVBr3K/7uN4EvjbA58eJOa4HUsKG1akvlLUjgSuSVZyBNnYaNZ45Bn49Bj05/aP8HDl
4WoqTXZ0b52vhlAOsJYcDMuLk/hmSwpSzuGmUwymMkPJDXbEEXzz4oVuchDs2HYbc0kRTn7IVnke
Wz211dZIhCNG2MF1ZJUrP5CvQV4n+MZ2T6QATk/SWNKeEzTtVr0SI+JIvLCAuhvkO2shJ43uAsux
SApIPcRH829iwMAMcpRT16NPF4E6DUIrrBbbR39OhVcndE6IZYAF+wWHqrdKQDCS9m03crkANpp0
YJNOj9k/D27AvgYGdGaE5C+Fbv4rMQPg+LnO7uhZq/b+GgvJofvyxqCY8XFmH3F6fBAtpmWqLglG
xsjZMqrc+rPgZCux+axkWf2EPJKkvyz72po7kwWEmADCVLlk77pAJapE/3GYJke/+JQHkdK7ElOs
wBpEJp55aQcqceLjIIaY/F/mNMP3otfKu5jhp8QAb1Y4X+bYWSGm27oldNOwH1tVA5iCdFiDYm2e
pnXXS66UjI+uRKCIVhBW781IqpuC675J2+cuFHGSNArFPZk8IAdUrRW8cubm5nzzk+NIRGny+25f
gyhuDP9zZFuypZ2aKOKwpOFRKxs10JElpP8C3FAOWuNPcOnZ3xopOM7Dz0X7BaPdYkDBr17Zxi69
Wri3pX3I5i6XJgqQLU7HSoEJeZ0UvpEocBM8lkqYYwji55YDr6ZAAN+Cup4D9mKH0PCTTvBVBN73
VxSH5wMXheJ4nCqLSaW8QyWSPWNA5vTYZEXpj3h71wDccvTwBmZj/0MVtXdOxgsmK5IL+RSYywYS
0oo/GhDr2QUY5hCjmxCA4z37XlOQLeZTyeQfYsoTndSg3yFHJQ/v2Y657NktNrddljEI50u7m0b4
UJHKItEKsqXq0nBYUtgVsXjhBy8VpRNfj9HOsjwdUyS/h5JUPZwX2popYCAFIAKrg0P09DtPFtvq
iq4VFktoIcFCpP948TnZd1lHNBEz4g/bVsWqI/h99iTQubFmgdiC894B+1hM1TswH1MBCpmZwX2O
bEqaVeC2GX2gtecVJGXSieykeU3G+vJZQVTqw3WOw/VVQcIACYGg17HQE4eeGCxASMP3Q3ApW0ln
c3b8KJ0CIMV8O4nDE4W6qF/SUwsFm9wDhsIPgF3Ra8xIDQvR08U1vH0rBTKAb0wcmKLBb5NoFVVr
mYG0RuY4XVf9kxZiGsZbdwfeSwClj2yaj7UOKcVU+nHQkLkDHRiYGHHb/+jnlLVH4YpClE83Cpu0
IpCW1UqicFinxY7E38DX3C2Zzq8fC41L4M8GAMKeliw7EaKbMDD9aTR3BBVORUXyGrbQGjjANBiB
jHJ1XGPOOmY/pyezjB88pexWMi3GKBSFbus9yo8szT6feZ55w1ne/MQy1GohXYwY4cyj/tmEJ1JY
7YAP0Bn+RydIgzrxc0+CKGBJcU+aCw7PwDMXANzDZLhmNUBnxagk5JrzUKET5n7Myuh0GEKSjHd8
NMdc5ZyvyaP0z3T0Zh7AxsoHTO1eHIXV1mRVA4DCAaQVj6UKb51NnWzJBr+zqlbZhBbUmkCT+G8W
prRc4WPFTpkTRkfzqvZP+yJ30c33zZYr1c8OxwmHoQt1GMrgG4H71Q1pua7Mce/LYJhqm23TAix8
GnVCiwoOVhvtBE7lwqKvzsi3sgy0xdO50fckQyDtRE+bJ1Ihw5XnL1KJe3u4AqwW+87lvbVpi2S5
3ysemJ0L5nKrZagkpuc9TKx8YG/dQJlOePl4CHLTvgPDINIcgSquqGpMHuO+DS4otn3oYwL5Rnvh
f7S9Z0STS63s0cfccXQqGnFH214lUr3Rx/xnJ+Y2cewNl5XWYBILk3yGONMk45/r2eK9XzCHq5Ex
Rvst5CZHWQhLPM8/G9grrqsRfNkjan/fzRGMtZ7PZSxx+lkhJ16GiQVRhaHqFJEffK4DaKutfM9q
LuJrJW8IaRkr17STNx4lE3YyKXziZotkJRUxpMZMRDmh0EZfJkiN+HXiyLMh5qoysY9C5fSZPg+S
AcDBIxT0VqYvnqovgfdaCDTkLZ8OelhwioEF46gpWmBaCI9iSqroVpCbhSZTWYVDTY44hnxRn7KD
HaBT4rStZ2fl5hXqqjO//aaaGAdA6NYNOCBAm9RHpmw3InNhCR8+WNtKJnf4/uvRmaeq8Oe7w57W
mSbf5vdg6P7XCLdGU3OYSb4V6tEUE59GzPdT0VbzV3O/j2072QayOBQB7AocD0b1pjcM7qlvOfw8
4IRzJQiAbWO+zSbu8HTXdpzb/fEEjG+QmZunsAbFbLwmNuE5d0spheUbNJ6R+piY8JCtRIxiLP0H
uyyTTHCJWwxAQongcj++0FHCfPTv4nEW2YZdLzM3hF/Bh3NTOMKeHHo3B1w6oEPk0sIWw+TUfzG9
qGemifM0yKaeDKCF/rtwnVHZWAiYWEtZCSdUKjWh+jMkrNrLhkoK57fMfa3yOp1uTis83r/8RlAQ
itg5xb4KW7UCdbxN5ABlufwu6FvK6E4qULb2fGkjJCE1AtTAe1nc0UQFGK21vN3mDTByfFPh3awZ
rcILnNrw2yQh2TBc4Z7JE/8mLIN4EiWpCSzkj6ttV455oqK6u0wY/8Z9IW35E05eIqXlOrZEWcBU
6lQqUcpInsO/1FhXkoUEKNr6OR4oTjeJ3x/iUBmTU6Nl7/Ztd/0W34lTsY9Bay7WJVLVH0EDoEf/
uVW448grJq19rHSy9DLLI/Phcbtxr6SDZdkt8KRLeC5ylMIuC8HFUU+eDIR9wPbltVzE6cJ0Szkm
ISUzMc430qc/nOAdNq4+A1lt4ejGei2jhgn5AKYLN5GFd6pU+AtpW8oBwb2UZhJ4ds5f7pLqPw50
bjr3kRM8B/C/+tfSvdFOoR7ho+71nuBKeHYQ0pf+QDbsy0/TNknuRkiZI1O3STXP5uGt5CEaEUAm
X48rmhgZgSAwSwCxE2ZpJkjkQBtOFI55aq6vrD2dAJ3i16j6WQnyMCx73W0yAMSWxOHo8n4ANe/Q
LNdppYORlIwugF6Jiy2p7/ZDaMQ+JpeTRsB1AL1KAX1r0rDpYeymCbhBTS8MmGKopII+bKsSNusP
63YBCKA/aHOk87mkIbaSw1nYLpX/VU3MxTrhykQnjkApkBrv/560ko/LKK5IsUletBPYyaBet1Qs
vkVa8519E2yRhJqB/o8lqYBqocX6sQVdBgHDeBuaZc42iBbbqUSR3uC0rPiSeXJXdCpmGl0ZYgjk
Y1T9mUcB1Zbdp/Glber35yveS9vw85YNjZMsFdYvclRi3chnGK/EMoYwEd55UlbSjYHu/EjFTfWJ
B+uv3mVriDqqb8vUZmIXU3UyQdwnzPRH6mjSM9lOtjWlO/0XFAetPbo9FrvlJH9t226nenoxxQSY
E/8MULupiylPZxKf680OEvV4vXQXIoY4IlIOP+sIBprN2zjs+bIlwCBKXpWPnaW33Y0hqC/W3c34
6/MODIDXstQOJdcFb9eAhLz6oxl7Br4KoPJzgdEC8sV5P703uphC8XohCVbmWG92zfjmdueU6/IT
hRy+tt6VVBNqrZe7sXdoMLQtrXzsgwvuNy2UrQRyjXfoXzqHhS547TU5ASd2GB46NGTKJBQLC0G6
2sNZx0JZg3WqQGAzS7g16ivo63RJIhuGKYSQhIAUYtGB5+WPktoLm48q3KAoUCwgjOf570iA4uwn
iGwKbVw4DEmlC/lm3Hk47mjFsTIqKh9ek6RKT2uFc5wIPsQhx/bpUvGBf3Yw5FugSl3JyjONVncT
vkJwM3Rn+8QXb1LkMuIvgAThRtBpHFhyYRHBAc57fn20l1EQq8DMlyUXgsY0LN07OgffgwxfeLMA
Nvk1iSESgrEm0kZLRPvQBkJ3x/OkEzIe3tqa9px26Bm+2mQ/ebvDuajNLgs29oJn13BuI3V0PbBM
NTcA+3ZyBVufKJC6zwhcI12h2MWcKIBtXNb0jSs9efoeMHnT2yOUQFsjItgiKFb8OD5V4D3da975
1yBEvBHzodrUexZN35z2u054FWjjEWq0taCNCMnuOAPrNaaE3kl3YMz2aBCSo8JnucX/jUcWpb5i
py7nSBKi1xz/Gap/Kw2K5b78gAjnOi9yvX5oZDGv7fMt3AJzxrDVsukztdtY3t3zR7RwRgZHP1hT
OlFchn9oP4mfCH2NccUxTe3wtdrLrekZTcYX0oSIrs3XtlbkaDkhp6LoHDtCP15LK4uEHUepYdYB
UoLru0fxCKZkIUn6aJVXgkDrDBpPJBM99EMSaZctRNdxyipRGMUZDvu7LE4Skhxhkym2Mfr5XUOk
J/BjrVINNfokxbgtaKcJyIBFqozdS5T1NNu464VGp/CGWdUQshGcjmFVcBtJp5tbPBi0VnYI2qJK
RC2G4nCBLPO4Az43EtDEc4Zxr+EzQpyHElUQ9alBe5HRQ9Lpud1c3T/3xccreCmy+IKlGsrNcbJo
YZwQnvioW7yLuGLBd/hxzpeLLoVd5igS5PO5mE2sULD1wFXojDBVNcNKFsGGX1j3fZe2C7xXGbcH
yEleToB6QWhyLTFfcj9lpUoL2Jner0nL7nrnwIEXo1EsiDQCl1nP6MB1IUr8ZMjGurmDgZsjPvYF
aT8PHBwODWuQExpfN6fIwF6+xJ5AZHB3eC+fdevfv/Ci+hXApjwtDiKttlwBtFcPBlXSbdZjcq9n
JbRW8gUE8wOF0Rjf9n+6ZoTRj/OkAktwn82hbKnhddSfBZYXqNNemYfcrNLKsT20z+2isLeoauis
9ZcsuzgXGC3pBXOLVND4kyHHGU1AlurC3AlDfTYA4/PNUTOHreAj1f8GSWLrcvw1gKDs0sX2+rf7
J0b4KP04nB7fhYCjssc8HM1EVvVG3uPa94YyQwS/pRwCsaOlDO0F0XgTCjg4waLuXFvRWXqLq19z
wqu7v83hfRkLXvr4saYdHkf8XfUM5wFU3yQRZQWOL2kbXRR7eyEGBOVYdsOMaClDAMZN04ky2uvN
96qEAAVbZAPYcLf5pmll8SkFnz1+gbNJiRWjNTPlhc/7no2KTCBi+mPZrxt/3WggG6PtIvpRr7Jl
DipkzqbJWEr/LyBmqkAz7EBM5oiFFyxQEdompluSmF0bRakeL06xbRH+ZOt5xyStmVg1InlcMYVD
jKsxCMM0YUN9GdVSwMvH0HLwufIQOpFd1dVNvEnRVeNnR+5JH7qQdr/weWi8SGeRkRzxvtfgiK8p
ymMNWB1mV5+voGpFVxivsZw1CiWOznUrX8k2Nr/W0U9JKN4rgX6UnhSIrscepFqUD8dc5wtUM3k2
0Hm/ulLqa6hBmpbcksg96Gm5sDJd7khU8uiT8yKOHh+Ua9b/j/jHHMSn6nKYVKnAjuKgQwZYn9DF
aB2Epk17jbokDpAAcu72HCoGGHzgWc/A45ed3Q0p4Zs3QVEySg/KySNe24qLvlEMbWfM4mH2PoQ1
Sdv9ljVxsW6YEyKYbki/jjpJjFSqkB0j5M5g2+/niC+9VRd5Q3SkbhUOugLpEtCFkoBVlYtvDYIm
m3HGAdWQbV9mz6VeT9XOxMbFZHnYO+6IF3Kwt66dEvNN4Q6qjTIY9nAtMMd3XEFjfsbPmmK89XKk
sNXV+LkVs7tEkTZcog5gn2cGSin+V4s10OYBOpizDmI+qPOxYMESkNXwtBHUjHBFaCzZZo/TTz+T
hZUXAbx917I6W9L4MBGOoABHe8Qp8tScqhsxfBQp544ThPytmd/NhrPV8wcUP63X8PhkWveSIzEo
2LNypFdVTwTLggOthcMzC6MkYmxlPBEHqfPVf2HrBYMLf/lxQHGgUkAVdQRYm99aiu+iYFsgX/2/
p5xQogEAG15rWqNLUapsSTc/wEsqexPQQce4hB0RORH5AHkURnrkicIrR58T4ZhwTBw45i0qYZlm
fmkPr5haHji/yC+AO0+2epb3B/fQ84uDemGNUvMZOwz2blXsKZpgZ/gFeIub83ZtdCk5sSjRhKN8
nK8QGqrr6k85T0/T7hXhjfht53SMCuwzbnXxC/KbbedhXEns730J7obk9JHyq2Ds8qv89x9dcOYW
ty/xM29+RBQMwc5m0LKkxXVz8mfEGG3g7lvCu6c+ZoaSSs16U4XCNwTfYGD6yorvTOKkzhD2AqM2
a3aWE3v9j1kHFQLuWnk4ZdfwI+ala6ZTzGSgbMT8Xu6D9v7wgr6UL2zM390dmX6v9go7XeM7KySi
o5CScz4bBPYwo/SSblK7kYkhz5Tq/j4vR4KGafkLgOIB2XlTUMbYbkH7FpshlXDe2JyVY3ai2kzQ
lE9U+U7SLAI8UpVzxtxr5pnvnFx/PKXInbGyvCQXMDfpI2D+Hj/EmwmwNicmCe6AXZBgbdK9O4Bs
FiPef7uHBelK9o2IxtwCLKlb397/H46GBQYU3bsNNBVh1iiExeAiYoltv+C8Cj+MEBxDg1dyD3Ny
1J59rCS4Jb+A2dRhTsiawB6iu3imEA/ucF75Fq1St9E7jy/7/b8EdxaFd4uzMIfCPsrOJlbaj+d0
r9Ri1D+SAY4QPZR6jGQYgL85roPC1LYQrYG3FD2Lw8ZnRImliXz9MaRMMVs2QmKvU5OM8bNEQ8ga
DQMo0zAsRA0rU0yHVU6synFIF+3Zc92AFN44skm2esIUayhO6KWuFMejOBn6JNT3zecrLizrepv6
D795FkqZp15naXphyb4M0RysQXW16uwefU6lcFD5+yu6Fob4TbJ8jyQSrzdT2eQbSe1qoQQA3EO4
Qtf04dS3FDjL7jYeNq/9/v7ExQphFZaLoGac66OLE+FLT41cR/itWJNO3WSw1029VjwCe1yIj4CO
uDQRd8xSCT4bVTiOxbur3i3aZocUKlssIk8PUHO0q4VwYf33Bvscbwvq9WcFzYGVeERwCxGvIZA1
hbqf+WIlX3X/mVmGp1GZHWIAkwsD6zb7H/RNLO1MJ16w/1yeXsBEjazcAytyngRgErq65MoYP5ez
y7zfB7pGNIa/DdsZOygLfRDZ3dMpH+bpLnKjHe0pO3MM49LNjEg7SkpY1xSZdX/zslGUJxmH1/eO
wYRzo/JF1yIll+q9M8rkwOXQ0yRX9cRHFL931x7pBNyvWCOVIPlwpISLFapqQf7pn+W7SurVFEYr
QzoTD0AL5Y57lnKVl0RECrU9auf2NApWL9xANK2DrVCeoWePpB0vyuKYnzpd2dReDsoyO/NEk2Ga
mA2U/luE6jDr3HmTDqY9l2eMIGQrJ5pxAEztjWihrhsKCtI70pIP4Iakt/RApYt65QZ8nEtuUwHs
YwYgUgS+DtXmw0elM63XdoKMJOm3t3aiIO5w+i6OTrbQKMyIHHNSLbIPBe+uXo2yEmx+eH5VBxJu
IBLzn3QMhq7T3hIDEVuAMOcZOiQ8sJHGw70O8B1nOXtnCnTXeSvCvP7qDL5aCvCCLB0UVr3lHVPZ
8fpMEJikDCdnaWmepWrgAleF7+iZE2Vyx5XShcCSzORE+ZT3+WuhUXlbLNnUSoE71qhWB3wTLZqV
f8le0YfUX05J93w+PABcDXqGoT6uZ1/O3wLnsm3kKtiBUIYB+GiXYaacEHU90ADgnq2V0+2XuDCk
A94oOtoBKBeTCi20Hm8LhUO8smC1FZrOZRPIRYW5ExG2HkU7XirssrE0kTr+Z7KMbiQ30m0j2EHH
EMQb/xqbwCoUSa6HuPMFBL3P8DscwvxLKoBwwIbP3R1lk/GtSYAUw+utc4dHNQYkkDTAT19zhNGb
+IrUFQxP5Kfuf6OowGfq1N7eWFlFQu8FKefqbiDib/2c52SZ5/FzdBNHgkIlTlMWfkFAHzN7GFvD
VC8gcL8MtmrdhKqAgQdm8YxXBv+vhdqArkjHf3Ir/VcQTqqFZoKxy42LNuovCXTqpWNGpm09Jqqh
wuVhp6fyWC+gdkimq8mcS/CwDf7LS/578eiYTi/LmO7D6YKr5lQMxPbFNxBRAG6Emqg10bIh8yxr
U/TylPaUDAe/KlrPC3CLkU1MuoXSLP0/hiVKRpPEhzFlyWykTWsnLGvLEnzZf21Tm+zJfnWTde6P
OiMs+eA8VyMN1flyX/+mvfF7DoQNT82474/65gMcJlcgDyc5kQhixxW5Kr2wOKNsGR1gzhLcaBZd
ia+Lqxjm5ZEMNZXECpy/g4KfucoGfMOiL1+zt+HHBhPNNKHLOf9aVuBaTCvkSdRJ9voV7Gx8YM1e
R6xhowKUB8zOqRce6eSa6tW9ofkIj+owfCli/bYzb0cnhKMy/SCoawfxNfK1mW16aGRVePXwhXcD
vWCcQtLhFTbehgJzWvcxx+L9qD1+fEwnmglXLg9+zOX1Q3Qj1u9al0EvZV1JYBbAyCrvsS03GTvz
t6k8uoVXQZwH7cHMbXGZBKIMP7cBQj9/8PUQLKze5V+RZIO6Aim4yGjJhD/ZaAChiTmISgvX2kS4
2ULyhLZcq+ZgfHHs+TXFdxDbpxPFikbqe8zsZck5hLz3BCtHAi0D3yEh+EXO8gyWaGHdJ+1Co3dW
Yp/354OfXzjdXTUrm2NtpIL+Lkk47ExgFXTGgWDHIzZ6jgdjmZZHSa8UKiClX1csZG0bRM4Stbah
ZhR+J8GXEJa1dX4+bVuQ9/jumebv+YbmgJNHxxLpd51Mea5kwSA7VObfagzGN494sIN3g0kcuh3q
MEc2vdrxIU6dm0dW8af/5b7GdDYPg0mX5YcgN6JZAgbxyMzQElv3TDhxWPypOBsVCGeinlbeHS/g
mnQbg1l4zCZ9erK6+JZyHcQ5plMmxYdEQ9SOZ2r8cG9MpSF5wbzRcuSTZajf4wxjxsxupkwWYkwS
mLqZsVWgqk71ko6hNHE/+iNKc4nX9WxB7++4x3sGz3pOB7euj2ppse/OLrjiLBIvoHK3QR91JHfv
KEgS5nARLQyvv3ciH1hcu+lF5mr3rlBaQdcbVhymWog9h/J93iAkIyqSOfXT73ZiQZWX+NEJdvS7
NuA58j9dLleFHrkJ7vP95tzYw++KV8cs+8EPUKDQc15u1EydJ4YPC0Rk11qrZNw1H7NS0kSOqNrJ
CMgcKxF8/bpcPM2aH8sCFJI0z+CdW/4NfPA7ejyjoBiIttE87yNaxBT2XRJzT5AvSY1tHdm9xNBz
+k0tDMMg86h8RtaDOV1ojFXmHG8lGmQwKGwYr4PKnVnP/YWfab8LGRcE0ZZR1p5XFqQ51TJnQRqz
Mo6U5C+3AHWHfc59vgS2VGVBKmF7IZ/CJmrkaBNhciMTZS7yXpgA7MElkIpaE7O6U8z2wrzxbSdy
KKwdYZill3bWWElKXQyNC7No592zkZWpoDA/7jrGv+DyOXxsg4FQCjXmqW7c2HyQ6UxNloVcnah0
JczSHJo8AlkNevJEOLNzUWLtlGdV1lD/VeA6xNen3wFCHIsCK1EVaQmuutqzy8Vw8mhv0ixl1/Ha
kCKvgg3pRqfNQD1eJzzwjGEGUUcrOsZSqJ30DMFxc/yfC04W/VKG+VCgCV8WW7DT+5fD0ZdX4SiH
u86ZCGkiv6SbBBXnHYM/yfwxTptphs1oC3NdcmxmaRs83Lp+EnWHapmNAPH7e2ZJQJdn/T7euldN
kUlrzHjFH69LwSslxwvGlMHobXhSwFlbmSzu099yHHianFcX2Cy3cCW9d1050RBoprtXClRHbqBZ
D8wtvsfDOrG4ab0JRMrhoy/7JANSLQUQYKRG6v3GnOldjnRXYAkBEYzAXHComjggLyi8y1+LQxgL
UR3PuLCBteonM6yB7Tm/hK9u7QAnLvY5L5exs7GjHw9q4bVeaUZEZyxaeNocD7vzqPP7b6mNPOF4
EP+NhYgJf4fWcYrmTwdx4GYpKZ1LAIiKcGqzT5+Sa4u2fmemvRcFQheQ+Glo8Uvt5e9KWreVsOmd
MuD6zpD4UdzXC+tWz0hYIXZqRBcXKrQcKLyQcj2fxfszPpOCaFpuJtn15/SwXKjEAO5isW3MqUgo
jlVfKBfNkVGvg83K2oJFR1LcQQH+EsNF+54NwtnVJ5ypCkeYvSac1P6ztQCZ1fvf2wabgdSHici6
70tHMCTfG6bxwDaN3gL1a/g40JHIj2YcOsrKJmhenDSfOKZjAVuil94ay57b53SxrI4bfjaU/125
UQTPK+T8x/os8A8AJEa4fg/L099VJCOnERkklWDTioQOyrZB/PuTR8eKkkspoVOujIQk2qpOmKo4
D1Lx/juDbUc3OCjdKya14wr54iiDZCz6ej7OQPUj6Eo+Qw36MjkyngjT6dpcr/rHZP1SLZPx75n2
PTrGM7RQ6HYITpOMepu3FjJe2EjhqgKnr1bOpIqZ+bKPRvG3J/cp5LBzM3V7h0Ni195WBwzSNAaq
beFNU6goRUwwbE6RZAyaw/8jf4MMo4poPEg+NUx/MWTWvZXtYuOBWCxjEmKMATXunBmE8jplUoEF
sN5LXazPSiIlvxk2u4P67XBOl3nfBOxbkUPpGz1ZIfKQSYOLh99VpPC+WkEobQOGbQ8BF2r7FuFS
1BOYATw4WEde3n5pbFTPyAH+aupaywqmibpGIzc+1LNDu5WVBekP0vazg7pjBgeWiz7qk2G7znlG
DTM/U6TzJe0WhZgF5DS4POCdy5eeEO23dUAUHNPNA2yhzhD5vIGvxA5I4S9hIbPr1Uz7Eqp8KbtF
Wx1CN3Jj33l2w2sZG3NUVMwRRi3sBE7krtC3cE/6l8L88A16rpnaObqQFLsdm/uVnVuSdDJNrOSw
ltG0BpRTvGAoIBW/dLo9gdYFEmTbgippxDTFj+Rns1WnvPMNc4sp21OD1+whp8wji/gkZhtgJLYO
hibKZ037NbmhAALO6CgH+SMRKOXB7qRDnjX3h3t0JxDLaVqnKN7GCF6HuLB+8pZGu0BCGZwYFL/x
tEvIZukvHTJP2tIo0NpZuMzBZxt6mNmD/2M1OtjBKeHQlm+CRBrBWQMounVrh2gW6fJXOrL54nSZ
BcSLGQBwVy0jTIbWQfe8MkhwqnuFNCwh91NKD465vfC7NiiDmiNyzlIIf6ZOcStwAoa4KWo91Hrv
1nAs6Cmnrxu0s+O0hpZYSxmN436mPAPENOCAKBcJUIUvgaNMYjVyOKAJXYHtSC2XcD2KU/elhXXQ
TEDZE85bTUKs50OpEV3JGQbUvvM8pke+4HS95AroomVgeI8TKgz8qPX2Bypd/KxhnHIktdQ+SVcJ
Vu/qTtQsulgV0g2vD1VoitL5Fab4yKhwk6yhaT+PoM2s+AUFlpvupobLhjKNA07YaJFLtRQa2RA7
7q4ycoR2RK/N+sP2Mr3QhH/HwHqe4NcTH+uk0cFWO87+jgsXI51F6JWmrxFuH7Wn42ml4aOruPOF
SwMDOYikfsRwZQsbEgTUgV0vhNfzYjVAJ5gIdDZVN8UuHd79Vq93Y4mrvSlgPzIrJ+lObgxuhQNP
JZOQPo7RTXa1T3jgCPjKo/8YX4Mp02d0HjEcAstoQhd+5TIvvn3LtdMJwntrIDlpcJXWoEuNITe6
+z9fFbDFIZ73T7+SMOIlGCajKw4J1J9fAgbVK59k/NoO8B+KXhK0tt3m9Imyl2QFVyLi/sl4Gh+D
dyociXGl73VrGBdd+h3+WE9hSmEgtU0YC1QfULNXAwAVnuUafYsovnlmqRZTedE9H2rbnEM19TPl
ncCboh6w4qajb5ozLHvdiXp7aw8pb0l5VecPIX1SJh+0H06civliyIUPlM3XPhX7/ewS470kioo6
O95BwjMW9hl/aa0iC7p/ti8xczPseg2ESUE2wrGpQ4UPNgklwsBRo1gRYJNsG3LKOUbQM1i5wXeZ
f+zDbdEbc+svilVQTVDc71yLMtVv9QLvcTtsQV6URInwQO4HVSYe7y54cmmR/ioEwoqyeTR0hHCi
8JmljP2Id87TbM+FnDXAd8xG/OpXt6M1WPkRhrP32a3EPBgKyt0ZGlALjQ5Asas7fDAD+kBAWPEG
sejnJo81KIvcr364zRKhnDfgIZko91Xl8BiCt5v3vn6jAru3Ql5ennfjbH+Ai6jPHyZrdeR/Yag2
GIQHaAqs9iE3LlNvQvQ1DDdZuigmLjcbmyBXD+aIk2JSYnKBpRYfJJPcF15gVwp5OlWXbXofpNqt
sjZEBfpe/QHF/X3MsLTj7c/7tzfPlqXy7lyecmLIKUzrdrNpV3p/iCT46+TfvOETGJQl83UOEj7y
wY5QvuxynorGjtBwCQw8LD3cDCzgFueh+4oJgAQXVWpHLRRqnEczXtHAsTHXO8lBsVCDSZeTI56f
LW/UIlvwTHcpmKY2sAvhMMZKjoXU359SNNiwaOhsKIaRzckGXAY5PAP/Vg3+w8aDGWCgiYNugadE
y2UPOU2GCLQkbCZjWU0Ruy8iJj546pEb40QCGde4UK6IyA/oSMgA3XM50Kce1VrhuD0lPHXXVwho
CIHoesq2w6gCUpRqxBytRY8OtF+vLFtf3ytTj41ALCrJ4o5JXEy4PmYbu77j/eCXAKTCHwrmJSZu
fW0nzoXFAmLTp47IjToOELuwkSbB+hYwPH6qNzxjOh0EvYdJ89RjGP0vwCcgeez3t5ar4Wh53VWg
TjNTfmqEE+QQX3A3hIIyAqHPhnCtOOwuaMv+ERe7OuFxCoEgM0UWpOFa/TmZkxTrEJEGgX8JFIib
TYUZDoJPHzRKC7YznHERD+AIu6W3xfR6wRXapcomQ10wTIQXkCB8YEy+l371+0H+Jrdz5iMktAZa
xt8hZ1ZtWX0i7z3Bvm6Utj8Whq/S5qpPlgB6y3OGXIB0AvTgAJlq7K/2GuZ5cRh1VdGZVFGDHmwR
O48kWXd3xMKsW3xszIUvwuuiEit0mfYB8kAZtuBDs5JPJHYFbJKY2g20YIrTj1WoRa/CCUKb0nzf
jMRG/b0ZIE+gQW3kAXZFL0oNnEVyyCkW8rqtfujmGR+8rjulL2YofGNXpcn3iG0VCneYBPR6uSXd
apm4zW232x5DCcX80zHQwHYixfqwparTjzbgBtz/Ai+H+KSNdKSATNwPEqBqF8j5sYUzST8tUpeh
OVQdwhTsuh+11H0xwsRi9SRTkcbg62yMbMZWAZJ6iGQJ2g9INo3Yf9TDsQJMF6KzkYUmlINXu1Hu
t0DwDP8S8JrDY3IC1Fcv4b31EDW5Hd5PxNaIhS4faPcip8brifdMtEuEDvMPBdF5+tI532GO1vO0
ciMgO2fyCqPNuc0i3aYzJJV9emKyBFDwC5xywTOh3Oxy92YF514Wj1q49yFIUnGomeovYNBnhQ9D
Fwr3aABgEF5zsmR1X4WBEUyuGhbIRE5G7286zCUvsHy8Jx8Rl2yyMVZ6/x6oYm6J+L0pzRduczld
rNtVhgF8rX8FbEM3WuT2h2XXZdh3TrLZx4pNDHLnkXRzBpMiQLR6FHavTTn9K+gRNbxzvDKDgDjT
+8xDIv2jztv1FmnMuCqA0OUU+khdyE+IECmwbDYwVftUED9zMloFpzwezk6Eff+cl5Zd6dLpcA5t
Wkbl8HDmZIBAWOF6qYjBvfWb6UZDxkowr1TE6AbbsOgMVcjkmUokaWiJuBLqy5r0r2rl2MYBmxKL
VnFdfp0p14bs29G6rwEUamE0Sr+12qoYrweK5Zu0ZH4O3J4zR50SVK+E8Vp3aGa88ht6y1D0ZMl8
Aqo/4cHUEHW1nFlo/Axak6mnomEMjlfj/rV1iHph2fCz5hs8g+dufrPxBFmdOVCAriOmYqfJiRgX
uJRCduaiA5iywefmQ5j8e4yR6/Jyxz9AJVVp5Vp0ivPBTqNeJG7KuMsDHweFiAl+iaIqHGIe6vPN
78VaDzGFivmt841i6qR1l92H5CfmCA6etZA0alKdexbb02f2OHhF1QbZbrZMK+Y2x9/rsNU7iOon
L+IFB8bzoMx9wodRywWijFFQljaolD/KQ+K1M9w3uCP3VJD8tEuHTOhKxwd2fZsbVPFYtFZNMRRd
n2LGKcwTgEmCY/a7w3MZcT/ddTraOvcPjnodvz8hB3Ttf2o8l2ma1ZFeqrP5DnPW6qgF+pZwZ0V8
Xg2WuCZJc53ujGrGfpYyoe2HgKj6qciIeAa2uSDQV6Q02VrHV0RaLxPCQgiv0Pl+k+bzExifWXd5
H8jIFeDbxrtMyKgQ50QSa7msBpFTYucGicz8FAyCnO9yTSGWX5m4YE8pgowGtvFs08mCzxj68biK
QVkcWlAxSYPQAwcHR1ol1aNeFgkWwW1sS/K87ELDBvDr6Ejhnybp2da4nScZgboVEodhDst7Vdmv
SKKqE+NYh4HuDa/zVrBnwpE8eaHkk/dDSkn/yR5aoVrZEpYow3mkJT9RPYRLec63si5iU024x5WY
ESsgqXr9yLmVkugOJD2ltBPBidmN4sSIsLN6ZVtGx7HXNTTPyqovpLZCsZZC/tAOpjv1MVL2Q9MM
CqB+m7uZn0M/NeLQ2in9St98HNH5J47rkxpf9iY1h8Qvx7GPBpLOYPnJn09sMBToHAK/arpSGRCP
Kunn+W8YfjYUOYhZrTzcWbi/2zdfZKe875aEJ4EBZLNUvxNxzt6NG7yGUxFPY2bAGYcBzvzmgmar
RLn4++d+bgljZfsAFYy7uumvjkMpa8y0u2UFaltvSL8+ECXpZ7NdzEEXw/wUTAKf+2OgA0QNmtir
hDTyITb3uzg6EvoeQh+mQQnEFe4p7VhVvT48slAs1/cHPizqcbT/I+PETFrUeW02nrs1xgEQwiIq
0QACxiEbt2w3xTvApBlwjRiGM9GR82mqd0VYVq4jgLL1c3ybpp1xxt9hifti/utf1yAOt2F9Ao9m
SIw3C6kMOhwQT/AwwwOUunDvEUJxu++r+fSQkuZxr5lRYo8FNPf2Lww0D3Zq3br6IGAYZ5uzVpRv
EzQHU2Zeb8QJndRRGFR9jmQCCWWBReUAWWMaGpbEZtTCJ92bY/X9663z20/MQ3/z+f7V6J2UT1g8
GpwoUrIcyZk8QaorOpeofjsRMbrFX4h/xplf/ro6aaMtaa0y2KK+z4Qz1GV0S8OdWaztQ/njqk3m
EYcxMMaYTd/r32YCVxizGOjxubyZzxBqyVF9QjiWUqHV1VDA7FzxdN7M1yht1vMmtC3C2dgM6gPG
Pg3ShlT7AYy3vD/W3V4l8et9XfQ4EVaMXeF5qd1Ar+ZT+1WuKDTI25lN5NrRWOQ1EOwd7yrduN6u
rGW8nksVD6+nZSHp+01QLe98rZeqjPShTODdGEHhK4Nb4ulbB3IrqgSA27aBOuFurorBdE3MOoy5
n9cR0OyhUFYufmNPXLKKR2uS9SbhNF+1gdJiJP1fE4XMlnjbA/EMWt+FwUUmNxLArj0CEsRGR9ye
Rk0MW2yTpCmhQ0HtsFUEADHPOSEt5t+zVCJsYb4xaipof9v4QvM2tqWC+2jS0n1G89ux86NFqoY5
47xSdflyptg29a0NoFjb4lfA3656G1N4XJdiPygqT+lgq8OGBE8aJ/Fg0lUDne/Krv9kTGzSd8Qg
XJS/6M+YCVPjNacZfKopdryKHfqQbsuub/A3/RLA2octxWn4qf1s+/VKPTKGt+Al7BF/TwSFxJtI
At2w+Lch4jU3pXbvLoQf7HgqsXODGfIZO+BALYPLipOTVBEvQae6OgBPfKJanjhE788i+p2mVDJy
5ZktToC5Y2H8wVliZOfmwERf5TWraKSt3sFyzex9F9I7ymp2aviD1aFrr3uo1Qv6HtBWLXw46Yhs
ERIaZeenfr9jm/aFc/lR7DJuoTxC0eYBDY3jMf4Y+R9wOfXofGKRyrzcTaLMnsdhie9dVOWYkVbR
yeG23PbEJTCHySD5hh0qu21vTndkcPF6lAHNcV1I7f9J7vDRF1kh70HYcti4b1NKac9MNCi6VRXO
EBOfN96f4XZubIrOPW1kZ1papZJ0/6UlXpw6Ax2nRLI4g+8Kg8ssGgl0duyKIVH/cgJevNddPuNi
2TtLZ0usP1vG5ijCHa9jMV36d1uT3boQQRB0UqNbPNCioVxeZjntd0Xb5DDezbgDKvAd7m5LEYC5
w9GDfiKHbXmrdalwsc498+W7csZQe6+OV/6EY1x+wPfmyWj8GvMpoghlh0hKlSGYEjAn97/BTKTU
bJ2n6Bj7oz8AA1XZUvKUuNrIKOJ9ARsg/4NQyRTLN2QYixxcI8RDihh4m+tUzMbOATSfqJq2hjW1
cQnlZu9zNJ+DZoz8RbIN9bjV7QLsft34c+M3hMJgTlsQWLx4HgeHafrXqJaKcCN1p2QRPuipFh1/
tl5UmJLlZ5+BQIi+ubXVs5GdXqUXMhflmEdH6nCWs7BoFwpsBpFsqgZBu1FQYMgLE4Jsf7XcpPHD
xnfC7GUB5/AC0BXCjtnZI6oQyhLGmmk3SbWVGW4kSlyYwtJji0T1hKieckQ8StEISX+f2SVebzbG
S/AtCMpaWrKi5RJjIit4bNHW/ww+28ZeDUy3GHtN8Ia8AeSd2ufmqX1UFuOaxNV5OW8bIy11hPp6
iMkZDxvn0wTK2s9QpjYagrHHLc3hzEmTXUKn6hcqKi3EB+xu61N23s5TSCMd3HTxGasBPV9Y9LK7
/G8tsUdp3XOuBibZtytDHUI90kHm+UqsacPdlhG4IhlHT8QnCbUWAy/BgddWtsmY0G+LQIBoK8yy
1YRtxAfzAvjf2mOjYoEMm7vQz1DoIO6njYCBF35grcFDwd/J7NwM30riKDGkrTpjc+uYngSziNNQ
gI+goWPWTOI6lE0MpPmEBPHU4xX/tvmxq4XtiEPc+S51PlXRJU5AbhfwfnsOtJ5Wq/Vv7EKu7B0y
JtqmRum5uwoqjIotvZizf8yE2v7O4yjhkcgpCqhFy0kRk8Z05+wxgmDDoh5fMlw9wDLjfUzWHa3l
/F+4OJ3kAvWINB+cGXMAW6Qbz2bo8zg+PHd4Ix1EWLqbYWk3vBrAKc2h0qvScNUv6upTDkoRICrI
9gcaXEKh17mJnFIUaPArdiWeYh4N3YAGwFSaIYjgiC0xaZOHfvUl0Zl2H4d5B1cevW4qQm25ZkGt
050qbzL5SOOjFVbV4SAqw7KjZrN7vHNTcvGPLSpsmfTItGPUiuHmSZyvcU1AyUMEdmNvaYxaKmyh
Vvz/gSyYAH1fB4DIjlbUDi2z9ZMvvc43rE0A9KjlMD7oOc3Y1z5exrMqzA0sfYjl1szSF5tvnTDo
+lF0mDjnAYwxAHYNkGEdtRLL2jZM+o3irK7kIo+ePTkCrF7NaDTTYJEYQF2YPQgy1QTOh3/SuVkG
CSP8L8lrfMcdV/YO43/lCyArYyQZjWS64r3mTa6lfHRriC7cjopnBwvmFsxWiarVbHWQw65cvjFO
YN0o6zVSeG0A+I6qnVmu9N/QAXQ9xa70N5EdWqtwePvea0J+/QdevEei8DSVcqDkPBs8WTPHb2pR
BOsU6NeLkCTN0BHzc2C/DdyUDmRtkRAfthOTJIgNHdmHJpaAkEee+nzGxUJX81q74gkTE5KJYAAI
03UkiYKsiUzOJz6RE4KbVmeQEW5ulNzvNJVhIHRjMRmEJRFp+tLrOWsTrVtyWzCYuIWOmup9NCY0
702LRig9/oZyhkxKITFwINVTTs9lbF/LqEGed2Ipg6NETZ/icR5NnSxQVoua5sZYyYEckJjS/V/N
W77mMYvrpvS5IEj+SX6grWN7BbfWGQfnFfxnhfUBi/FaMlWqiIWgrlsjSRGM6mDbjK3OmdS7NitK
jisN5OxkaITm960PCipyP+YmQYvFx4xzCdwr2mUmwI5QtbYiWna9Wt9ZE1NJn9G7SantePq9Pv5O
6oSwngclh/He53pcvUOhox+foSC8EXV0G90BVnrK8quOBhFlOd4EvhkPhF9+OB8Kqd9x6V54ue2n
pMxWJidhXmAgROF/NBHzYAI1uTMcG8hLlgfo7iGiI3zpZfuDMbO1W0AVeYzLOYobtuzU1UlUGiL6
I4fcVn5J1rOUwtC70R7KvGgAlT3JDnusjczNnw/TZVXfqtMeSy8NrSkp6QiafIve2XfX5pCdbzbm
WEc0VP+HfgbhL94tuo42BFfSisEAIyEoiw1uUaZxZNQiEeyiFuzVmULFYxIPjSgbtS18w561/xQk
cN03WdqWm9XPkyUa7n8kKakN4eZpCLJ9Vz47LZEM58w4Zpc7tGWPrE7yinLI0kfH0midcIhWtpBZ
V5j9stnyUxK0S7MYSBgJFJh0+2uErnhHUSxzYAC7hbgsfFmHTDIOy0PqhCIUHwjSxHvnwNlSj+52
8/XybRI9PmcNkBHnnWWx2kWlILX2RChrPOlsJOAUSU3rDx8b+TH/cqurfrAihPsDR3377wBYqaWG
mpalBBnVNh2xxUmqMwZo/qdl8uNv8BglSBALtxxO2UIRDF0Cn2bZ4TOTsPDrqF2EG0pDCCajPU2U
nr3DZEO8j6FQDOzAS1eg2nUrLVF1f3WvczBrlKyiz1vOkhqjNK24DzUFnSgfBCkVClctAMDlJpQK
HiGKTZ60Fn+EyBAwl+JbQ9w1d1ArmyZ2v5+XCHIHugD2vFvQ1SZsp5BtiITRopjzEsJHEoro5xtq
1jRvwp5LaeB5ask6KburZktQhpzomndeJ/lesxKq55LCEAZ9XVsQ3JpWCrygZNlbXUrrXt36lxC6
sOGBk0gsdvZALjCoF2K9cTIt7pY26aXCaEkWvIf8OXf0Nr9Bkbf6rLTQyGM/JuUBVSV/WCEcC1EB
syO+WAVoFJvzu4CCWTWkz+RCBvNKNel2DU6nqmN4jRdMmrt90TEZTHIeXgC+rreNXqD6RKp7iE1W
Vp8gLewLrpBkW1WTT+/OARTlYrOPv5OwsMftLj2TS9l3zWq99b/StmkrDGQJYMW+n3++xtLSBRp/
k9iR4DS+ef2NdnzYpch+STjmuikpP/ICbsSQ7v9+b38cTD49fYl2Vaoc40qE5SAxKhPAexN1GYAu
g6YOEHZBBn0upowN1Awld73oiCzmwcks0g7RufhE0hfFE1ZohANap2FiU9OqL0RiwirK7xBd0nAT
viGqwydcDmLfCT7TWmyyJe2w3L5l5/A/fMDoi3o1AOroIDykxYjtg04Vsj+islljqx17p0tLpyCc
t/r+pXIiykGx6H9l1ZJyY+kPXlG0D7nXiuDJZ4HaUAw+zLuzxFnDHDGwBOqKjo7VwroQcvwBZy3k
Hu0/eo3GrEh2tnakqRsRAc9N8Yn5VAwNHKldY/L1adpZokw1xFLdJp4MQuG4Am3wA1KZ82jhC3bm
T/2AwkLckA9t673wmL+TRgVSnOPGg/d/qdrIFH+viP4cdn/IuYAtzI2FK0P7PHjuSbdvNUDTesOn
VCvWlYZafkYe4W/ciGgXlBSmYDcFt9zPW3nct7xh0KjNT8FB2+L6J4DOcOGmvdriLazAqKxAOk2V
JVjyDv5L693e++rpOm8Nn/fjYFvgZvJY49aUopEEHJT4EkzjnCp+W8/A7rvofmUgQPhCewEvSRQj
QS+FgOKrac+7HNCy4jY9NTl0Gxh6mQhgjIiyKbejNkI3gMlboykZwshFMKiDQfVNqiBXDfjn3obc
knC0izk+Govs+XRUdEwUd28r5zRGph6y8ShkETqZ1xcSIQNPdPbIAKQuyXvslxoobUcpJYbQ0JL2
3BPkWBahqUvEltUceUdpDZszcjU3SNYWd0w3TqKxMFOddQ0Hk9JsUrj6yZzYQotatiZOhl8SN/fm
evosVrL1eT1ggnWO+Xi21lejeWgP5ALdg24DONhfCyUe9ovv63qsRIZCB70zBWHz5Bg0xEvRgLfe
E11Byn3kdDE8livrYIvaNBOLWMUcJzO5ZfuuUotNj9RBA9NNsK2BI6u9RGelN4I4WEaNvel9+nHV
iM4EIQRyUyHbffVd/HzgBE8b4d1YWqjSxEcd5KF8tl2QKVpOM1TPC+WGWo4wxYO3ZN3/iCjdrCb4
kvxLywCWjLCKyYEb9r0edRQKvlQVDYJSGzB0Ul13amtVnyoW/AHWZDkQuEyjCKb+Tt1/L/i2f0FQ
Q6c9ZEKX/8CfuJEw7fXbHMmYyQFX5lWCQbLhuPqsfR3+r3HZBufXC0WVS/drvAoOzgWOnG2JVRQ9
ea+/q71ncUyUZDy0TIoj3osWGY0YqI5jtdWBm0dzyovr+CmOqUF2iKimFvrW+1cR+zNGeAmt4ww2
pXLNeCKG6PxnzUKLxTAnF86Wr6qYlFQUbVKJ1+CFhcHuttgtcqMKS71NP04aSFGY4ejlxqiKa8dK
xpTXEjnp8sMOSfEVRJOVLYTXMii9oOsecseObDQfUw+hWP80ip/PUCP6ybmUmo+e/YDUa3Wof9fA
gHOj96Zt6+UHRMbQHwRxOJ8k4Nn5erZhidniuwdvUVHWdKjYkh5t61mLjhCyXlJJfwS+VuJNvwr8
XDdGXmdpzwx9o25g893DRyhyGNmWHiC9Gg85vATdG+nNi8Qt+Sd6CUCTewURE3+H67ft+wTU2bFM
pxRt4vrMcWIVlIxv4xGfRfWAiEfXt4hVU8FDVsfWNYk3GUDDOnwTQssgxDmWA4PVSyT2vTV9C5y1
hzDQh27I/cDveXre4uMpHHiLxjP7TkYDqqxq1ycPeI5LUDGiYxpJNFuEwo/bkNhKGePyhiDpyI9u
IMxA4EwYrvlLgVzG7clEKvRThHK74WTl3yxSM5EW7fRmcq/g8R7l0e6TL4NY7wyHc21LbW0b6EYc
E9+nWzzLq1Rfd/R1+Qf83cb66AHRPpvRBsvGOaMDZ3CH/XftbZ9cYsUVYrZSVaQHTRmKFyIrjlKR
mS3wEcCtWlp2IrfNawPs7UgEX54LUNglPXeuQ8rivrBfQ8HvmlMThXkzN+NW6aK6XnTEByVWAZbi
YItGMfdD9FGJq1MrdhmpIPdfRtRiFBRIFAmtrKVwTWoE0zf9ijHHtRSnotmAWH2aW/iQiW3PjkgD
qrgyzpSaYiJRWt1RUY0n4NAsXCIirH+B40brJdDnUqpRhzLGxSIjylifEL0adt78GAf34M1RNN7O
Z0rIFmS/iCb5DtOIehDmOgthlTsHPI4MPacx/md7WZQ952NERyq7IDaS2EwIGNRDD47JkRtYvqte
eW5ZgV2qWMGE/6+IcEoKLio32RPzvRvjt5buOskRiDwU3hCKFeaJaqnGbqnOWS5cJSX/GKf5hkVc
06DceM2F6yv45Ny4RTmuVNtHNu6gD6CmFfald7+43DDk/XcUqyJdb94wQI94+vaT8ExCLxi0bDpA
SD1hIIz1GuyTf3QQ9UPoDKX7qDYejsOr+ndGrCcwgDDuHjVeq/7jXm3NgCWWF3VEXynZ5qZ6UGyH
Aad/XsGTaGqsm7k6sk22EJWr3+VdhDEBYLAvR7Z5GUI37SbALh/Ju6HDd3edUKffdJn+Xkw9TDsQ
3jg6s2Ou2C5qHjhqDbuM1xY1UQUHgykdcikplYNfqmgFrXwDn/oW6GzGf9O6bEcIyXgSr8jA+sIk
EIFwn4NgPiPgru35CxiF0JEQxBbx703HrQcStAE1Dz2U9LVzHniSGQvgFEjAq/OPx2M9HUwUq8dK
fjBAWDBRFiZ6YTtE+bbBdIUdBOFyn7yb2W62vk1CAQ2dnmtjJ5+gK8bz15feYAd94iLXAsgvgaRm
r+mPLlO5PESYJ36mYct6RMmL8lFtms/ORwX1ZPbca2fCnPTvymZpNW5WFGQN2zBb0266cEhSg2FK
zYFutf/WzHSGjpJj1xcXqwTW+hu8hcY8WPboIBI810wgQ8es2IPDcknyfmJ/+y2sB8PCH6OMoAYq
/QXiS5iPZMp8VlUphRaIzUFJ9jEYo5k+zClxQ4dWrlmc0Pel+G0mxZQPEKQ9Lm4ZoP1e4sfDzkbl
jqf/es7q1V40VOG2sIyuUPf3igltS7Uu9aXqUj4J78/K3G+QSGbPq1Ltjaj1ygjQce6yVOdl8836
adw/z08qaDBlVXxzTkA4djst1afjUOYlWGTawu+LXlnGVsTnkisgermkT/ujU3fbyX8glsdiGJKI
xx+u9psiLtUgT37nEkNZYy9C53q+TOENpfWrMFpXutePjJKGw6KPPnQ23FSkDAlmb28PuELrzOp8
eDX4u5ruKk7o1YO/5Ty6piws4b380CVNFxWysTfuqPR1EHGmO/QnBv2HBAJ7IB9gVxvypCJ6iBpX
cP56uvSIjZNcM7EU08GdnzY/FS4xDFPIyDs8YgvquKLJFPXNIKcT6OsZ/k+Hbnhalnci2iPjp6wE
bL3UYU3/wxh8Meb+kuYoxTt11jKU/2z7Nfis+F76IsoYNlj5OMCoMv9JkUF5B4WL8xGhPDABoGRX
AwE2g/E0+jY8NH3DGC12PenLmpWSwXwAh5hbz2ju72XEvjBk4EnLldRZyiWkRsDMd7yX7axY5YJV
UW67ASFTG6W5T8f0U16u66iaXbW3pwBfWMPty6HBhcnjDYMCaoJnYPZNh/R9V5L8gl0Q6T2S3DnZ
Hu2AemhEEN/wbKEUYQezRRkO62uchvob6rj3M0sAV4I1scpnID8p+RAZefa2QK9zOvc3Bhhoc/Ki
lfol6FQXPHHIaKrvek9s98BX1pSYcs2ZKtdM9i8NteLW+n1MYzKZSGEZw87GgEGW1x2HKzgjvuDL
cMRb64eKWNcMFDW1t8EzJ3MIIiCW5OGnMMas5kRe5nm0ScLG7Fm8Uoku+w8ofcolX+sIECjyGtz3
EblxkVRiO3oyJu3oM+UvjavvB3wrbG0fnSEWFwVf0Qyv5CKnTXuaWbrNHU3M3U7hM9vuV7uVaaln
oDBpcl2K0cUt23sOfwDdB1fTH4XAChr8vPXqT7D7XHIumdnSjoRStLWElpyWI9BJ/jBMNXOvmvIT
e1uinYF23b6HX2G8MpOhIwqpZhQWqsGhveyH+TCnvWmwljU8+4o/7wCY/Q92b0bRhrmVEI/zi6JC
NNI0zCKI22Xpze1zrZAhp/rlD9bguQmoHtqUUMskQ18/lAyU3GdYwX+vsWO5YWJ3oZyPKO++7kWJ
ZZ+7iDi+Fx1Tdg6uHgDXuWROmp9yJ+slICCZU1WKzFp9M7lVbbtibB2Ni/Vfz3fLD0++niIdIJcw
Jsil7w2P0YKuqMhAM2DvWXkpIWLCR8TPWZ8p6VyS/bphkhf1K59+hmp/0OlWBQ/8d1B/AwOlSVPe
ChLPjBDHBsL/F2Goy8gVNQCSqcHBTzthuoeuZIHdtcBr5MzU1eI0eZgp7JnAPNQLS9aO20G3W+Nw
WgrR2Y/KPlD2AJ2moAMK3LnSgeuNKFu7bw+uPqYPAUAWCT9//0UIqadXrK+dqogsYZuKllwa0SoD
TNBrEHqiJyZYvmgiRdAVLuQxQmQKKeuC9DRMvV5xBb9h41/SQvuVukA8EeN0jVgIREjYeVvdJEbk
UuVa2smBtzdxDbm+WJZoaDVc4D1AW/Ke7sxIJpQlKAxLxngzHiFeRg0ofqvpnW5zZzP+kaoT2j0P
e1kvPhKGhTgvlV0qS0zuBapplzMOHmcmrEmrr8uF0Bn/ZnOXPH/eKBBlA0hqyZ/TaS0Ur1XW2KbR
gJ45boCyoAQQXUJwUQZP1xM8BgvZQO6fQML34t75hSuuZ1w7NTJ7HTLELJyJSeyO2S/iXag3Sjfv
WWvj7Kn227rQJZjeH1GAPsHR2o+/LHq8FUub3Rdhyl1wriql2Zas48w+8UTPd8yLD4JoBQOhyfLd
XIptPGvVIGVEZPfFSxg1eaQWLV7t6Jw33aX5/Du3KLk4zWvgCz6nIlz4SEYvpoylNPUrP1HPXRh0
4vTc8aGy5mQ1Cc+VXfAfopn02QDMMzV9NYhdp37tHyamJsSd7RFKVOYK+RHM5Ei0kF9E7TzF3kB2
ZCKN3U49VHG8n2+xXaKHpdQoq22848o+85DhRHfk9CF0ZwCdmvPWEh3yfecGZ8S7k9ns3c5q5Dws
zFc04nEhAQOWjgjx1gAa1F8czycqyl/kYrJNwmLJ1rcQp8DmWqhWS/EF4nwYHFmthhpbG5z2vKC/
l4RVediK1EHy/EAioQf6O6iz6kf+lDL1fxMPQk5JXvgf9GZdOxupqtIhtiJcR4iWagA4xMfC/SM/
cFa7ZTrYtblJgI52ykrnrIe55Epg7mUCvlxVDm/tDWg0lZI6GhbqxnkhAzvRJ+hhoxyKHtFGW3eZ
QQwA8ZtQuE2NLouJtNo7KZ4tEOk3O4KZWBJAeykufu9jY4GI/E9TP3/XwDLtvzDR02dJf0b5TFY4
UDcVEzHFnyPvPt2RTr1P4kPzkDK+3CtW8tJ4ursLrsOfqrv0m/M0D0D3E433PL6LqobiKdL0akyn
xV1mX5K71hAP7NqHJ+stci++ai7OjQ/PhGaBGB0SK8IRg9/W9uqmONvwi5b1pE4uqZq54u9L1CGe
16tPDjZl4SlOZ9YD8AVWoZ2/1tARxfGu9Aqx8z2lu1CZgtscsaO15MsF1t9KrOOdVOLaa3tFafim
yimjh/MeIYowKtSooZnM/muWsjZ8D//0/0ozyLlwHb0YIyJVIM6O/UgReywm+FCSAE00zfZvPFUM
su93ghsdRtKw5iXVXH9IBih+xuacBgUI2XcerWPzF9k3wLJW4LXxL0FhfYvb1Pb4PnEjx5cDFL2u
Vi2BIjgcBRK2ybmCRxv90yhTNPDqq1Ay72EVs5bLyJ+Xq1HHC87E92EiOAPCDFMZ9o/EH0LIHOKf
DVDCG8M1Im2sJNHBPqW4iT/VT2oAL+GpcszzzhHthv0DMLG9n6GDa3pi29Sr14Jc3IeOTLRegX/F
fWYT2fcpHPiO3pEl66Paga8rz5fYvp/cJ01WWLCpuaRHJ25k9FFDvM03rPjkxYBOcbql8d66R5H6
ZkDadSYIpHC6W4vZKnIT7LvV+75sohGRNsjujAwtLlnzLKk3Tj1RaA1Eosbu//xWW2aJHxD0UZEb
886jL5gWJe9e6hWQGiSZTP+2O30GzauZwroklpptSgW6ieeJVIYRFZkzAtAOuWJKm416l6GCNuVr
sr3tdFf5i1lCDy1+/JtUeTK8WgM3INBprNjfXAbO1w0pfbTiPRjlEZFCEpqwfP6zumQ1XaJ7T5or
Bko9G8iwG5w0hNrgyC8pg9vS4QmDVhpQ2vSKzfaO+MIfIpNVgRicfUR0+BCpdMY9Es4QwXYFx5mK
bCQHmPEAhpVs9wLA2QGU9vT2ocvcRqwTIleC6jyaidy8Y2h6GYHTfteeDcI2WV9uLa034im5nTGf
8fACxvRzX9DbidLjQBGN0gUPUShGBX50XJ8qhBOQu8I4D5UxHbB6o3JT0SxlQ+nNB6gNiJDUiXV7
qJNFY5ntfEC3HgW3PQYP7dzFvKtK970zy6da+BC+ZDvIcibVdsqNbMu10Hoc8IzxbaJfRyGy5yfr
SWbWlwvQh2wXz0LHNJgdi3Cpq77lZmx5ZtFZuyKVOjGBoFK4YvWlTUmLV41XtGObPCrwxNo/z0FE
tMRdODwZPM7NCdH3SBj8RVzOxRLL5m8SszXOjbrO4EAMvsHivpam+QdJXnzmF8htS5QyhfJ87G6+
OccW6S4oIqWVg1P5dY2XVTe6Yvxq2uBakS+F9iMsN4IvKGiFkq8Y7krumlU/KnXAJa8oU2j6F/ea
y31xoLd+dFpEGjK0fhSvqioZG0iJlVYro1Dim+zSAiGfGRZzV9E4P5xE18kDpQBQgtlaIUKKbdUP
/83nUUAEyBnSWk0yNgjquWcAVgucaL3P0+9NocYQnCmY+mipK5qs2UjWFjyGeS6pVOkwM8L//0Se
FgIyrAsZqd/ZeSgM275ud4eEJoCZD+gcFqHqKPrzRAJ5lBkqH8WuB4v87a0XdP4IrD+qjWI/7nCI
zOG3vR0agaHF32zpnqJX43MTvmI7wmTP7M4N5WqOMkR6dD9Xk2I6EBibclXnzbRenO8RyH4AX46L
U3OoqN6kghx4Q7NhawucDcHQWq8lHBT1Djz0UFRRnJUZBC32gKAxDX9HUa5QtIx0F2oNhav0bkdh
fIzEeb5CaRM4RRbgRgMgzj0P2GFHrlVuzxtD5McBon9E0/TbjXfVJtfcsmwGsS4O6OUUDFJJBwvK
0E6NIlTayYWPPbCagThZtxn5udoUZjz4I/9tVqkGJ8eC6vBh+rSQimYpTPoPxRaw55eiRBb0hb7W
qvqr6hcntV6AV/J5gBQtk8E4tnbiaa5dcB2qxsHYce7VhvhmJzAa/N+wuZItTyTmtOHkayVrM4QI
+459kGd6stN97E4a4IWHV5tiMFG1WMLCmKfNGfYC8PDcWrFc2j7oAxqdXAwMOSgNaXYzo3BR2bYl
bVhjOeURuUNhabfuWRY1lExMQJA2I+K5CfllWi04p1eG302SzC8X/M6ur3tZxnSwRdWrfmOpsvCc
hC1r3d3cIrH5xqktt3iJngtMg+0w8i7lPZFzGilX8MI50I+mTsuCjAWKba1lrm6yH0ACENf7rc7o
VX+nf8gvgFJe58DpMt1AnVS2ObFTXrpfuZ9J4hr+xa8EWWYgiVAIRn5Ql2wagD5tmPfOlntLt1ya
d2h4Xb0WHxlKOqmih/N2/n3C9QB6fTHNgEwCttCLyiDMQ1BfnHdZCbYz0NL/xW8aXGqL6W2S7Q6K
UJ9goMeX3geA1Kh3PwMlgPEKRfm/rtf4DUVXP+842OVBTphKHQZ0oCLxzGH98GuG+8daL1l5mcFj
d1MT4xkc5DPF4Tb+ZKrnL1KUK4VL2ar/AEzxkrLFZCcna49pndDAF/wC1d2F2fE+h0WnkQB5NNwz
1uhkzWGIZZz1CJmZAKn9NYLiz0TKj9n7rS2CNVYetdrxO413CuuPV1+nqyMB1/TmjoGQSWQSRsaA
+Q9aUFniLzP7s+evkIl8M84BkTRBtG2SHYi9LA4zDj9s6QCfpMIYjbNovH3ivgMhrRSI+p1jtk4I
CHVQURgekt25M2HXEf9aeK7u1kTbL47IkRjty3mcL+Ol7dJA4pP6yK/Fi1owjvtAeA1et6iD2GzL
v47SU+aZr5tCLKhtbxv+0b80JWqzdFEfEMPsXHZdP6ux9JrpI3Jn6Bi1zynf71gjYD8whf/PAr11
40+WocrzK4b72hqoAnfZ/gkTsiVvEaoOVjCp9DRAVXqrGw3zXNw8cyEfrurUbu+KXL2GJDvGNlJ0
QuEYYPBAK7ZkcTPuBO9/jObUKarTh1gn7pQ759tICIxb9EImHOoqM4IqtBDsHwTHY3G0nTxSdoHm
iqaZY0HogkzXayEkpgyivwlRcEjvnmWs2ikoSXngyAIpJbNwgt5le7NTKLA/C9jR0r9E2FvoQynZ
nhkRJd48FJtQyz0Z0vj4pTO1ixOmXkAp32HvZwJLNQnrvOMEQ6GjKnoUHsiE0Yk7khRl3UlpCwpB
q2oSGfb1ZBpeP7GKjVc+Wir++olCmKf1VLhloqKQDYz7U2UCMJYT8I0KM3z6tL3YZUIPlE62O7Y6
F0TIfRxSJ4capCInyEXj4w15CFhu2UfNj/SowCl24HezD51/4YnjtJuG8VRkrm/4AvBJEB37gjHU
/X7xpH0ZysynAX8ZytPZJT7ewBwyJE01ZGMPbsOCIcbSOGS9Uiz6R/5QjfcEjSfkr8P6UPBoByX2
3b89b+xtgy1iHL1+xQXuQfOAn1h6qenfrg1F3Tv3czd7TGRBHQT196wtaiPzH3sxX0hoOgdubPep
kFfyjzA/ySPlVEjRJVGjKN/gU9m0d980ie65+QV4eSuo/RdVY7SlYEair/zQe8avCOzx75SUDPZ8
rwOs+TnVgeLyN4B38tMaaKRiwIM0AXQlgy69Ho/RdIjKoGBrov2oDB8Cdupd/QGiu5l/WCBoJFXQ
X7r1jskETQ9qV7o1kuCuN0FJ4UnbZdqE8VQRMNJXoVbMpyvgaAc1hKn6WRWTBNAo7guCEXOqRsH7
qvkkEFAHBykKDtaWX9CMCoRMtKyXMqqzPsjDrfe6dRSGpj76n5Cgtr81OL5FcZg8g8tZav+ZVEDZ
wW0Wf8Li7JSeoPInbG1KqhJ6ADPhKvL9WcAECKDPgYKnwJTW1gP368nKbeQDdSOQyqCEHQIMdf4l
Vq48DONgtmR43yGS2YxrK7W6ouXr193pRRYPvdn7cY/IhATRIcLEa4o+A2Uu4yWj7cxsS3BWsVRG
7EbaNs9U2LzLWReFRuOn/eA8M1qUDzj1Fi9BNcqs3BsHWa3be7vgyMZ06higvI4rhPObFDMg2MPt
ILAwicnGtF7cq95i1gogoM2D2sEn6k8tJgZaVfZ0D2BHIAYG0/ulyX4E6BtHABUCNndp0mV6L2hW
zDnGtH4D6Nvg8cGSCPbjBAR090GOQPHkw3fPZpXLg/cRg7IuMoPEH7I4GlSVLzGeSQPJFfqn9hyA
XWelif9JyEAqRoGP7Ijm7ueYh2cVK0QZpGvp4YGUb+ABaepco99rSGnqwL2kJ4PIpr5tV30A7/nz
YzEUg7QlqR+eRUfj55RbfcxPCU3waufTydY19P/ftxNN5AdeZPLx6HvGxV9EyB3qOIV57WgxGhYv
V3ohBGQMy9MUe4vnPMfTSB8UX5wFNFV8RiMvIO7eNJoL3oaPZQhvQDIAkOdiyB9JMn7X+TMJFiL9
v6JvMD6ibX8AXxWwqVIg6z3ZmwsrkzE4e0f75ixoXE4MguNII1kv8qGn5LDcw4vx1+GI+ZRoyvvg
2FhLOgopRIgfgEZR1XTBybIDb8oV4jxGPnMS7aye8599h5JapjNsD247sr4zPVJK0aq2Sr08I8HL
1Ulp2JP5olpwIHNhxKDusQz9xQrA7UEIdo7+iFLPwgCEtBHpsugdbCSWRUBUEHSXJwkijslHLupX
L1fh84KaOilUdTltHXmVFbi5P/yGFVCF+aE6Tf+ut1zDOuuNqU0EobIthZcOkdz46Ifn0iW7e9DE
VwH0Ug1AM579esa89N1QetQYikh/KJRINwL7FwrV8Wzu76wjzqluYv/S61rsglt8JCynZzkTfjO9
cONLjJGAI2Z1+L8stLhMr5HUjUFggflPHotsPanwuPskWwAIiqAwhxYxuGWg2SfziJdrQ4B7zTpZ
zJ/iMo8ke6EgaqQPLXUMESeglaMNeMIELHkKpeFL0b4kexkLylRk+XaxEkNZg5GQX9I73zV/t662
d0CP4358PAw+SsosfvN5yGVhWPRzS1oerfPneyB2qipDSaL9KiTu1/YSuRG7hP5QLPkHtrk6X8iV
E1P01tQTQsqH7vKd6x3mRIdJmuiGoHu9/5oSwy1Goaki7QIxG9vwYXfNhm3JZ3fAwe5KRSuj6gw/
G2f/4TwMaAj3iCXn1zwpStflGiWDH23osSf5Y1hMp8wa7QJWAJlXChzVuStXt/4DfOJbAGYLgsLC
ZgA5Nh5VWnTIu++rUa3hNd5Rf+L/bxKGW8Ic9MMJjuvW5RoonnkanmeCPd8WC9if3uchSovvPqoR
KPfHhSU8Yuqcl3otYAmsjdDxxR+6NudnJe8w2yz+7jms75hU39VZj6A3YgAilPkrxC82lCilGNZY
/LzXJU5BIirz4Tgzw63axQcI5BxgCuMq7+s6z6k7bdGQq+H7GyeKLoOJVrtKLvL7HkTZ41ZldtyL
BgRCaPnl/QcUlnYlhzbrR35eOyqeGdTALmsBWze7ANtBiK3ipcDi9kiax9ovIKSjoynT6wjVrc74
nId1WfHXvxUroeLlAd17z6rHhOjGNLH2JWqcfQAAffFQjaoYsD9LgYyl5ETz/FDWWoclzfiMJP9b
Z82fZ1L8mE5vq9gE6M3jJ8YpVuYkME1BxA4BHkpXqi7oMqTICpUdxOrMgLWCeOs1S8iUWnXvUJa/
mc4nGdSXNUra1ceLFH1HMh6PJZhJw/F1iMTYP6/rUz8MviQSsAxXQ/xoluT2NPgjeeT7lbuQiWaR
vtHJQbpn+JVViLTH4YBdV3FHFHXVHoAHKeh4zy+rGc9wjWHPwGlTSO90iZjUdnKViI+LMDHG0iIC
Cy8C4W3iAs73ZyyoEHoKOBRia9vxR6bq5G7BkOQqGzslhZEwe1WsW+bV4/Ug5WsNi45+jn4pR+bR
57w8Klbs5cpCNd0miYhIDmAXR1/l8RDbJXqNtt5KBgT7+0u3RkxvVhDVwraWQ239E5gGM5v0Vccn
V+nVNM66YE9A90cR5Rtng2A+HdQgKzMNfttk46hpHv3vEwWWyFVLvnR7XbBV3i9q58qUeocLkYOu
vGUVP8X+pB+CpJUeN714Hn92sDQmgq5vCUQPEbb6WFOPqtnIGhJwUYLb/BV7U8CAsXPltYvXbbP8
AL9r6hnUCjVt2NNMGx/LJKCUmEHOeoQFCb5poYNoFku5iVw9g43MnBfaALF6wqfJJiHdK7zUDzjS
buVc/ZjUHs1pwA9PNdldWw2U8o0CvMP2wCgJd+jSHMzWpOFI2wjikRaLsm104ABymjbcMde8x2IQ
T2zFnZSIP7YVFtXEBOSdLY0mRPAS9yd3Hg1KqDL/4q/tS07Qtx8oTlLTaA20tyfA0+KjcusQ3+uX
Ze5ihVMpe5ulxdCYHjH4t3CUwiRYWVIUX7Yx2wLXYngmmbgPWXrfPXiY/jahV6LT2JV9ojcwq+sp
MXfAMrW6T2uL5ZBGNOBrgP6Ry4ZqpnUOc/QSTDPekjTQtzSaWrzxP3FZDTAmBEdQ4roVNWT2t8VX
E8Z7QTR9Mg8ONGbH7vA+9wuzX4B8CHEAMOi7i6mYHpSx7WlYDQz+dXujkAj9rmxKaDLk/qoyXqfE
E8uaYBNZfAUePbtcBOWuG8mfRgBeXUvu/q4Wlat2o+1siwVxmCyY5b/ZwvYYiM6l0jpgD5aAwXvS
b23NHzY9+I3c9L1tMGSS/1jZia1y8EzeOWt0PqZWAsdw3KNXnf9vQKpcTUK0U5oqqRL9FtPDFy2H
TSwhZgbttHenfSNrw5AZHz33Lb+WzsnyHVGqRk7Rmwo8vWTSzbJGu3JuLWP5O9aP8kRo6gt4Wu6Q
QuXK6lDSRJ5JZQhARSfDRUqqDaxylFjbScSgpOLAV1eB4qZRcKd2fH7lMgQNObMUpEXrrdhT6uGA
T1Hk/HHCuSoZrNnTsrirldBXhZj5/tZfWhWC/s8BWFW+98VRwapYjU2I/avrjfsMY1/+I0dP9j9F
r8EktSU3zT6N74F55P0rINOndBXuX+ExcqaZzAQBmDeR8LQRXzqlr8s9ALS02QG5kl1xsgxK8JTs
xlX9z8h6B7UWW/8gLdp2qPfAIDD8HDrfv/3KtXrnlhSgXRhrO4yPKYfkaDTlxBGTkHho5FN5QF08
suDmSbP9LsqyMYLsZExNWgLwR+DVj+W62noo4EOOISBx0WsAaJZEUYEwgLfV6tOq9ndwQRLREhMx
WT9GhdaisBSS+IA/c1WB/Xe3fC2zltO4Ein5Oiev1vfU8DO1RPmp0aJUWOvrRbpqtdUawdE5Q36m
r35r+3ZwjdeySHHWVIBp4DvSUKaqaOE7n4lIRJ1sWZUlBRlZPR/h9iNzZHFW/tvDfEEDJqtzWFMQ
EXlhmoXYl/Umnfs/9QeK115Qt41mIigXwKDe2ZN5bp7VQhzPw8ych4cpAJXvnSGveK7X89aXaGgg
JLGxoaShczNaqFO3ypI08hk5XZkVQ2v1zGi9vOQmLHUgXIuY+KA9+0zCQCB7++xx0V1Wr6fjLKHh
P7yctE0goLDaPZL4SqHpbOekfIWrqzD+tGBMwOLZYMxGL7OMQEo/WW4v6gAmlnS1W2ZFMmRHUkqL
7LNWjt/wmNa2a77Bb1AIfjxRjQTZrWZz/O0DMbZiO0a2dBLnb1ObwaDDANJ9V43HgA0B9zkCsiaR
TcW2RS4TXQrjgopXeXJ8IaEd6Zxo2kaOgAo/xQu7y1amBrOYvyvmTNmN29LkSugnywlR/TOnQhcn
RLytqBHXWvo+NX8HYyLRlENPOqTnYSkjj47ZWIgndxMOYFzwM92adLYk/Z/CB/yymxaw97Qm8/ZX
0eg993ow2QNezP1o6Jm2a0f3behoFDuFFQ8LYA5bPHcM7ZCYOKVr+UWUSDIaRke1kYA1pgVJ0n7A
h0eK1Hc4Ga6JtTC6G9lJGInx9RUrtXBHQKZLbCMg8zLXIbYmMA6ADExp75z0AnHWBdJDaWKUFrgJ
+Sh4euTeAcFOVc1gWoocxWQxySK1NhQE8sd0NZ1aSTj99HagPbGjYQcHxvrdprIxWU31k5uKMipL
o5ihYT8cGuHnLsIo2ZNq6asq1N9UxFm7n4lwXTfaeKlc0zwFXngF0uZgV8GIdw6ZEnKC0AAT5o5p
XFyYKtzlFo33UVgVD5WNETSPiN3+y8/RjPdmUxvCurLMpwlndbR4Lx1QOVH+ml9NkuLij3iQstXI
S18H4tzgi9VoFMWEufssOwaJsRPwvkltapu2maaJDly8DVQcUxzic5u2bTbOT95fFQT1qxh6rMRk
JRgte238t0kJq5cg1yZPaA/3ITdgzHrymCj4Hdz5eQOlNhJvtRg/Zw7QbZOFeeP5bWF1XiQ58Ln4
/fXsWqKV3IlfubZevs4RZMKVhX5fSS7L0KQLic3JwWZ7hPRoMy/u6NPMotGzla2kzs/FiMcVdml1
iTCaxWLerZ33s6IVlz49+AZJ/iAJimIj/wp6b4aLs7cTSCboBNfCNJOc13ehmx0uPDQ/UCJ3u1jS
3tFUILwpeDsCcumIzUHuw6b7/Rfq3jHO9pid0HJ8lYgd2KcjCyo4Ed4nPGM1HAjGG0Ftry4+ryjf
Sm9CW+gAQ4m6dfS8PZycmdlDo5mZjL42Dnw2PauPEUVxSbd4xF8pYqePoMDRD8dQr/LPSdgjXEU0
3LqJgShiGl9m4zPPN1uSi7gNSc7r2YQpCpHGmm/DEZ6s7a8NBzrZm6n90/BKHMpFScFl6BHLsnmc
f8+dEqVX3lvb0pWHCt8+s415mL/7jce3LiWEvBe4gg4s5ryph41DdBOKn2Rhs5X+1zKJXpocU3MQ
dnTHy/TuOEKKoRuqCh6eqiihme5AbP6uMekpB+2q040Fui4DJ9Kbv87/Ziz6yssdWW3GJ4m6Fhd6
xFGfWCW7cXr5oT0e11zKZFQ1gRKHeCPTLXMQafajBqTd0u3oyPy2BzZ+2DKgLYloDw5PEuk7Li7d
WEn6IUQ5EeNz2AMANQ5ySqAxOxuxNNI+QcrH3fL3lvYKwSgXNao/fXgYu8/bqXMKxppHoDdq7+d3
koHUX73gFUmawgroypMSzMsfX0ArRpLedWKjE1SEf/VvmdoaXM8sqEb6PqEAAR72KGdwSeN0/bZs
gA+vH3Wo8Z5AzHQ2elxD0UzavADqyzqblPVc/XfgM9mnEjGDuwwaQOPf4yjFZ3av8olgvzoYHxXA
Rjx6ej/Z669FS9dAsKJKws3sJNawrVOd8dIjjAyZ6rLyvTeABqaMAu2JaxpuY+eRkEJhqPstNfzx
kG7XS1I6J278QlC8AHT7rqXACEP3kLNv5D9lO0FcuZTaD28hJmvWuo3lN47cpAOVYq4e0hDEGezc
Cjdp3CDFjPtq2FhE4BvpLDqM2nwdiUedhRSLW88DxCyLKp5pz6YVNTkVTW9PgjwjMA1bYN1tz7PR
UhvFIvFvccw42PAB3Ck9ymJB+iYV2fTLkP1uJDx/Dh+dMQpu8A+YLxcV62qoiNDIMGJc7OM7WiaZ
pSRRE+dKCP7LsgY4hdqE1Yv0NQGY0XnEi0dUOm8tAoCyzBHtFMqhGqpBOvz7ILj67SNAzR/ClQzi
+fppJk1dGXYOtDpeavDUFDN9LuWtIC8SSG5vmImGJiAfdwsfpdK/5BlJH+GVI3H+uhCULR5IHK+a
H8GuulBJVTngUuTgse+aOFCjp4qi9BOBuBgD0abSmtpVB5zqRlktzB3RGWLumoc6RSnGISo91O7k
M2LrHNy51Dz53hsG2aFvaaHisHr0ZiEoW4uGD0ibLI/fUfw7NHKYY9T2oDG3N/Zapcy0yVoCIMUQ
esrWV18JoN3loDaRa0j0tIkSefsMhuoRxrNslaAtKxk7t7SunQaxTBnDD7gjYvlEuxnUrjSoWUn7
i54uxluyPEBqp5HB0mPyHfOTqoEeEndoZOWm42k9B6l/JHNaoMlEHhEXPNyDAIns+mvZSAs8QW/J
TsO5koeu+l80m+1/4HFQmQLEXIdJ7YmK5dC1L26csnvVY6LKZKU2YDtDMUdVQdqOTvCkJuNWgVGm
K6HruVqXtAPkG+TiKedOnUNE3bEhTiW/II8SdXpPjGKj+Y147fq4mPrGxrMknR2tiKVji+rfQTK/
g8Ljwd07uohdsKgfikOtFJfhmF7t3nqTTQOAArCEnWFHc+cykLmJSYeMZDZ++t4O40OwjXOcamdW
E8RIcijyDa2Qzxrwq50pG9y8MqeHCJ3mTB+btWgiOG5AkAUrzKJdfqMSfZ7JQGoFg3IbptayQ0ba
pAOxjuxFA459yJNFeUfxXm7eZEidXgBrnrm8ocextH2VF6djJRwBxZRdmS/6+m1k8O7cYBNkxL4a
cNQWGiZQtMc0faXU52nJenr2FP8rmuRkGwiK7OBMz4/JQxVoDYAY+qb4iglhStF+TuJoKgHosd88
wXypEEkpJXXAaImkqfvKV0yPMTQj9oK06+3FdRJjPTdVx4VicvF+Hpi16dwdkr1F2KK3p/vjRliY
NVmOkKt8CEuyBw8Y0tJUL34GcHSwMTEzIMVy2qk/bGjAUWO8gV/S7UWov+xVxUPpK6qmx+wAuwAW
FRlXlmAMHbLr8KeQQcJYPi4pCC7B7joTT4t7uIbcfHh873wKOknqfpzJWALcYfIYZk9r2f7oz675
uAuQdt1EFgYUgGkuT5ppFBvT516b9tgB0bmK+ahN8fyU0aB3ScStv4UuG6pyEkFbAdN81mEQEPar
Gmnadc4/Aw9HQ8k8Eot0P0SS36+ffTcb7Udm2uhJDgNftdRLe+ncoyog9K2I60LEveP+Q+H5elHn
ku4uyFawNTZtS2Zh5WWQf3h4+vfBCoThGIdCaxqrZnrQ56PbXX46sKVd4n2/0toSGtbAx3+eSKYP
IdgCZh9fgzn1vHaRKDSkqJ3ciXPjeiDUgTMKwI18LlpH+x1lbrgZiC05H6hR899IrY5C8BgeKF+r
sj0C2fgIycbWVpactLBLU+vxSVe5KeweHaNK5EphynEC5fjDGt6WjZB+WP0zoY9eAposUQ0dryo/
kBUxtAUTanpwI4+qQqGPfeN57ZbnEAqKLIgiWthfY82wmTTpQKtNrbQuW3XzsTynjmRDr9qcrQEM
JSxUenXN6XQ0ycFAFwtLCCL0C/P9I4p5O0nTYg0QOds+OOilFERV4O8caIMY8kHTjzjR33QHkOTm
BsNg7HvMkJTOuflDfgyPmSkHZYy+t7OL7j3vJmilKU0DEVk61xr1m8y2LS8z3NP5LeYNXDH0BHR8
d+yrwW1Op24vqHVsbs7/TQjyeneO1mVVVdIvKSx2k/iF/WLfp2E5U51HQFyqdEMjts7SXpnuN+Nu
F62+9ZMtab6/ZxPeApzbJac6PeEYQWOfruARBvgxv2A7dqC29QTOVRhw/IRE1i6JsGi6N6oNyfEc
gDPJeWd7FimrSz8PkZKCcN0amD8MhAQktL3m9aw39vfShGKWZn+QNwN1AlSvrza38hJ0spPHD0Fb
6iXyM2bDVEm89TTcXTj0PDUy1GPkQ8Hg3hgjgzqtm0jkboh1WSg9VvREUWHh+QiuWho+j3JzeJy1
EGbrarI+eCeSJj7gQ9+4PrC/6DDW4U2gYiGPBQ4i3wN6CR+YRQPzmvVlm5rzis4dUCdc7baZNhxG
fAmqsomMQW2fN3TgsLT9GYXdkApFHVmKZjm4bT3vASGOCcc6qk50YZcXYTw0VPRSyY0bjMCum7J4
KyOYRcfmWJgVmDkxF+dh1iBMH+oYpQgdRZZpQYVB/uiCoJAazZLfR+ATTKmuQdr7ePQunBr1ewWI
suvOo425S0vqpYQ9GNjmrG7TEhXVlbS0EbD3GPDy7E5TokseQJEmafVjfs+eOfQZXGnSo0zDMesl
rM/IatuvhdM4H3m0rpU4FCXJkFeq+LvXiaY/rMXEGKsamSpfeoNvEHjoAnPGgjewPbhAJgsTQHnX
NkuHaudryjeUajDIupWVbMhmuLTN3MpA0HPvvPA2kEzRM6YugPAlFiXg85nrYxX+PaB5hr8iNhqZ
RRm9xw+1Mf21KoDQhTCMQ3rzjunee+CINYz081r1/cKcSQ3Q1d37meBR8AmQgNvJztad2oUvM1p/
zWjfRyUonsHyrfTPbzYOEP712m328TqqO57h0jOQ2G4KCRaka6OTdIUD+S+EzvBMxDr7+loFSPcT
pbj3jt0t8U9Lz/sDcMBaq/MDfEmDBgqgGdtlZ1Hx5CgZPxAbVwintamnLqK1Cro3qn/M46qtFwFx
Z6E8zgiyKQoQd0cJpkmeGpHPPxnpL0J56EOX37aD60faUVOT2AQTf75EasCWvP4Kjt6BhBiefVlq
pQhIjxJibks517i0Z1GHGeoje75dvOSKxf6TBq2Ywq/cegxUH9vIfkUjZCulrgZoHWTCbjYKe8VD
/PZN10eCjh9eaXEjenxlDCLaIDGenaL4QVFrCLgfJ8LxPWu/XJiBB+iZmLzLfiKNCdK6Z/8YahE1
bTbSEtDCzJJd28A1F0t1x4mQp7jJCkyU19+uXW++ZrtRemTnfvAWPDRmRFh6Sl2UwdtugZQYOeMA
AYKRLptc5oNpCd+3/wTzWQodS6f2E0KuJFcgvEQLRcDDfi8aeAu3kIUmdQGM2qO4IqUCQN/Qvj5R
MGk0cbf7WvUrG8hcnzw1fvGmoXG0dTibGSboMbruDUs4XjhtRg75vTGphLPF02/R8+j8WNcvif74
1C2cb1oyGPvnyRp6lkmmk9P0203EOSb6Ql4gMKaw0bd/q6YAONLTILzrKwSP8yse4IBw3qRcrX5n
4J50U5Pnm8GfUFvQb6OYM8dvHA5OtLKQCbmSB9o+gAiiB3rnlx5B9LXeG+hD7P+fOVsA7yMxS5dX
58SytTBCb0syliEpfuG/l+v8lx279Bz4sq/LUYOZaFLTkQJLA9NobsoqeWJFx2tYLAgFHJzxMXMc
faBYzQ3ciN3ktKBstraYz8JhB+YuluxOUVJ5rEOsqQJyI9z0YI21eqto7waVhC6X6gLSDVUXCAct
eljj7rV+ZC6whb1ljw9iaRP2ObW9X93OxiRCVhTKJqRVegiPrAEOZQ8oZPNp7Hc7h/4JoiIoe8Ig
alF137iv/asv3LNKGB+vVXy0ug/CFfL2OGABu44FsDjt3sFQ0EAiaJwMoGr5q6qmvBxUCvuzfyuJ
Qn9TwUxhTYsW5+Vx8nVsYP8xl7PKzO3q2VEzS3X1UolYxm1oQyuRt9tDVNUiJtgZ2OXJ5Cby92B7
nwhH+9fyrE6Bmvp6mMgRiY9wCHNrzbxKwc3nYIS1mY4sKTeW4XSgwjteg2idjOUWSaF6TcDWLj0o
cekeRNt3ZgW88ssJWquyS1mecJGE8jayIXEXbmW2e/X4hcOz5tqvU2zSQOwSuBaZJgsrQxiV+rml
nh43xtxua+LhOMuzk0WLCeZcNTdcak84LgSNIqXpfUkR6p6WHmZMFfms/JWHb8MOo5ByoHK+BUpt
4bbTgjs/iHtRMhagP+IxmebMqGrf2S90YtQW/aA9FveQ+ZZRU6fMWZc0zTLbwoGW17jwncvnIKaJ
DpoZ/jSW8tFqURsYCuaQmCOWF6ftmE5lI5I628ODTqfcwCFRd+rSt2mwaSLv2RRN6CT+prdnNrmO
iu65BmeAeWQ5diRDApjwj2S4wEViFizMJQ8bjrCVpq9jioN5s4RONLwurMpZ333qoqbPhtxc8+FF
mwsA5THx5pVpR1cZbR+zbOBwHfKx6N1pMNPI5MxbPVUd34LWSzk5fGlNALfV4dctQBUnRCWXSpHm
MeL020HddeKUXt33SdKd/3/6C5fe3yJv71KGomaZ/FlAgZShXnNQbwfm0Cwp64BBAftSptSUQclw
+WAf7wBLSKqH/+48EanlzwTThFKGGUS3C26VhlFwjmPNF9N5Ae9tni79hctAf2gI44FcKFEBK8FS
DQhtSFtkB8k6Ns3ZDPnpR1OTLznTL4J42GIZnnxEeF2YKY2xtEN3Hp27OpUJ/tWda7caVOGhgFes
M/X45kbYBvTDdwts6frdMNTjUcVDC/tes7UBQW6K7wYunn2hscjcWtxnAWTG4o/WqFLF74Wk32C4
PrvtyysVlRkhXmbyn3E3tpRx2EqJoIt0ecPQhJB/SVmYnwodnuNC/NfuwOa62ulLt4Zo9T2hqcOl
kFVsh4OFr3LMCTtzYHhRsn5/JcTCjFEje5D6sI7y0Z+j8suFvsuEwp8JdKhRo9qGJObLuUPog/OX
AgwOUmf/jrwPZmkgfEwW+UH2IRxj4DTuI73wEIKlYpFHli/sLZuPse9G5d88WmjSXOgyU5bBEkT/
WceOXu//wHYQD3P/6Zul6y1iSQ7vcnLdR/JGHNBR5EO95QVUbVuqcn2JrSSk5YMkuFfN9hj0GNij
ix9DPF3RUvl4wizDwUZXzq/uccuTt5X2/MKXZtd3IlqDdE7XycgPeJRMKD34vV4aKGiK0IlLrmG9
ZU/De5WsMORJ3gqePSqmlEIF0bgkK086EkZG8kZYTr1vde/yu7k2O0YkttDj3dzDLURKcyIWcDV9
Q73C3DnaEWa/vR0sDutd/EXAfDJW1DNUp2cSq6cDf+RXYRA4kOCS9JdbxAoO+ME9vY00g4QtpKYM
CRztW+Dcejj3BfmJYVlt7U6c78tAIH9+eSm/UHCr1F1LQavzIAra+l19JuZfyyQb9r0nYLW3fTqx
T8Mjbh2cLNZ60CM9W8eVY7jurpZbSd6qv8kQ1Hy9qWV/iiwLs0Bib/rcSFpsiZg5ir/r/11Prrdk
8evrojFJhZtCju0g2nliTi3N2JF0Smltm/1py0d5sW/cZ51yLt05vElA7tbq+GF1qhyUnT9lUK1F
oBMOvrDwEsJ+Go0YSEOQ/V8ldxlCrCNef4bIv9kIJdgCxVyKny2FKXRl4w5O2k///qnB/1MDI/zE
N6Fk62iJSnO4uHV0BGkjsRPja5cCDh5JMw2iYyfRiI3l6o2HwnUuyaXTMa7fgV8FAmkMlJ4jbv8D
ZRqkFaCpOZINH/uRYRkHms8EOJRTe7hPx/YAcuxuKQ+0l4weHxouaIrP1qrAszWcnadErc1e4uh+
7VvC+2Hi9xsYY1dfIo1ZTIGLpZsystN23UDMU5xT1jwI43rbUq8y9NLNBma+zw0VopHl6TwDvSau
s46WiSGy2kS7vx6pWgc7oVU5JucgM9CjoBRFMUat+psdfInYJjapdHzUtxWCad5M7Hg2jO8Hlh2o
6K6OfBZJu6w1S0Pp448tVHZL/lf47qhWXv449Eczk1O4ZmS+OKWsxmQnyTcjto3DkGLSOp/kZi5l
aAeLdLVPrBs6O2ftFODzPxhi4/hfOg89/aPqlP0x52PnOE7r70+DrenMgbmf/OWKNy8ZMLDWzNkV
sMu8FNi8t8hCUhIxFiLo78+kz8qEMcRhAHyLR15VxiAyA1AGOclifjYfKkFfcsLcoWHjjD+3/bWy
WluBVjUWTudPnK9kwIjO606ZLOkqWv2gCTl8cQkp6aFa98A2kf2oj6i3tDTb4yM4AnzSKC4FzMZm
U94iQa2D6zOevUdvkVZofS6gKYjgWVJ77pMHg2uVw6QRrBGkgFBFXhcYg2bJJlycxJsTItRTx+cY
vDL6g6Bov3qRb+rgl9vycnx8B4gtYBpt1tHx3XslLPkvIgVNg2APDyp/yjnG+q4SSdO0uP/Oh4CV
1vKJCwHbZ8ofwqAFDRtYXjYa4mvKzg7e3TNjz9m2GRYEySFck217Bytt7RDGhC2eCLIdhphELTqr
TZHVqFVqwMtCHpDcTZuyxl5iebm14UVvk+KtyAtU3Eh1s/EHxSFBAlZfEiHj43MLFM0W0Hzh8iUG
94n6JolHOV+eN850IU6b9Ax1ldrw5o7PdBWSOuNbH2MrCHYuMyRl/TgKIsINVe+KMllBvQaBjuHo
k/R7UZ8Als6yrLydiuRUOAT20GpxOvj6P8/ekgx8QTQs8kLii8nOI81rp39o1cNHgypgC7zFPeSK
tiGnkhSrerK8LwTF4jpaJYb8EQhX5pEZKS64zqNm/3WAuMu3NdEXAqHtBzdXsCgm/ltrPI+0nOu2
mNpB2vc17Y8/5XKIKqu1+7TfHFzYjykMgSq74KN04bhSNID+AR1h+TCmIHUIorWRWt8E0Ui3WrXD
lz9lr6YKTppAkK1SqwcbwolLhXcuCsxpejKlZW1uaUsDZIu5g4XaczkhwTvju3Js9lWvH1nmz/nF
waSnTqasC1NyuL+c8QJr5p96OYRKOVvTaNoADpbuDwGo96xHPdwYZHP0UiHfy0p18EFIKNIbel6c
1bwrHPArUq+z0FFPA6eyuizvFJZJRVcFBM9D45+N/6yK0qvjT9jq4lTxbgLtqjDLA38Q9+KJUKhs
WL8pvYrJa2yr8yMAqf8dhoSSs8djpSu0WYIvjRDIjBt7RTFJXj40aUlPohSyxhqNKH52EDf4tzCj
HIY0UjhXcOQQMk5gOHHX8i52ThpeVkWHTTTCH7dA8g0HE1xIrsKIKN5u+Q/Ic3mS/bfnvikrF3Gx
RYQy5FPIRPGYxkx6JT4CtezCslCWVEj+JDEdyhdhnciM7PQ21NWfK2yoOICHkSkk8/Zn8jYtI9Ql
5KqyvtBaHKcc23InzwgCc3nfkz6LxiUWkZB3i/XPH/os/2kJR6gVwmPkqPdgpeTWOEwFZ7d4tNhI
qOcyxSvliwZOfSQLDsiwrWNWy53nohfKZuwmEIKutcBD6uhOmppipIj44Qx2EVNpijSuuDO6+GUE
AN3FH8fG1crNh1mL+C5v+F762dfeJPyaWFD1E9969wja8CgipYSRKasr8qvMw1lpS7Op4huwVA+v
RsegNHaiWpbDYbbeg4l5YfPPhsXqO66ka76a7GNq2rI+hRl230BMW6GwvYSmyEsCb2zkX7yPBTMU
wBdkWOjbvdkXRL1mnGkFXULR4URTEjiU+q37CRgxFcBKhhs5V5Yvj19mcBfTZNMPCJWXVPFH9b4P
PYAq8uIKs/mgsJ3gSqyTP8IF/vEs8fpEY4QKR9TekHEtr7XfOdxPaH2ynbazN/b++YbiSkqmBIkj
urD+7eGVvvOuiyu73NlnhO2xjLhw7cJ6yz9bFHhry2D5eWbNrC5bUohEpXssRoeoFQ4JzmX+JdC2
zBihyh32U2hDG9wpQ9WzmNCfZCdUARUqHKmzYQtIscTk8objyW1x3wj+r0XGCFkoNwWL8jQwmLUZ
fqUG6iNOooQeeXyn/5jxSqyLD//Y5SjBI4dxRmI0wlBxFDoORpuzgStZRys3fEHr48b/DLw6uV0i
ZK5ofKhVrpURfLqunBP+jbHnd+s/pQya3SlIOcRzhjZgJC0Ib9/XF/2aVQZaAvZNWW/VJ++lq/H2
vE2kUoprsqPF1OBIME+vd8GFlYNIF7XRemslwI68vxBNj8uNCrAXrzRLlBFHs9W9QvBeoaxg1OfQ
3VtvCRFS2jgjLOAlsg0mHgvvbmR6l+ZrlpzJyQ/uK3ydwZ7kRDwMwoWHyzcQ4Ps6iiV4ctzUHoiY
e0eLkyAeogiST6FO1S+3cbfXzo7m3VePoGZe+geLvkZ5ojx1/wl8JDMPdi0wjcNWDthfM7Q174EV
av4EoAammy8lJ8yW5wI6SYIvOmeduN/5/sTyw5Iq3wN+g3UsZ6XhjE18dUyyy1OMB7oRJWvmKLpN
pzZESG+85YdmsvBJrGZLAJZBB+kr6yYEKbf/kqCWWYHA63En+cfZrcbEmVJ5+nBm2V6VRWFg685R
V11aZr5YHGPkdFSzH1ZI2thffMFSksnYGRgB1WDLmUcdaAHhPRSbsal9kHFEi+vyQitPOK+/MIhn
yzodsa+Bi+gDIjkZ2+Suh5AYze7p8friqoZd+FlYdEqQdSs3k/7ZzH82+zHodf21OA75rSOJVuyZ
62L45arDar+QhA9D8iHUW4qWkai4zIaaS2e2iUlFfS6BmBvZK3UVVjdiccNhjY8deArxJYFQJ2MR
2DQLFSMiUkj28enDkEGGk2yJVpsSw6O+FX6wjufCUfUh0bgNEP5Q10suLMCfA5m/Sq4YNOUJLoC+
jPg055caDb2izi1ujlR4if/moEP8mAtZZrRFAfaMtCGZ9RZ3aR0oDGL/R95lbL/OXyzdMipJpbdG
isb/icRKk0PVKKvoaSHGnjzq5NbSA3QeGEEIXEr1ATSRJYiKGFCpATLaCAMl7A2RWk6LhCX1GEuk
1rpcDAvCjxShdnr9QZAwnnDG4AfscFBEr+YUK8iY/OMbpRhv+C3lAX7RicMGHcZBw6FG56sBRAf+
XLRXRRQQyJHBE5k5Tic4ih/S0DBEZI/4XHQxSp5dpepa+rAM3/8iqjKYkN94KZbo/acqIB7Ytafx
haxQ9seQ8bIQIqBpk5tvSjIrEj/m2VT5K93mSQxe4RrBaBEJojLkj5LQXLQfiy52XKLBLagzRY59
Z2OkrbIO96r5TEpGAdCrWwXytTy6Y1sEbCokXcLnv7K9FcMxNmeFl3Ry7a4OUsSuS9Lf2sCnvCMf
f2+DTJjkC0uNwGa/mOObj0UBtqbYk2r/4S0At9iaM22eNzTqvuBxU9eVf/b98bnYZoyHoGuyixWx
KGPyhgJIkVj4bOq3YXIBhna/rhgfNqaAHclCFIPFcam7WDsvuBN9DlmEk9AOUcNtQH+SI4uqha29
qQ0tV0Jm0OxDVKbRPL/IczOpjMkPW2FJpTp5Ek1zYsya+/v5+dsWjKOEG8VhqoLTGehDErX8ll2q
7qcuXP8l9SF7ELPLdExkfFRfgv5L9ocrthEJZ2TrDLdkfXTTXm6epNtYkIYFz/AA0jlhP0WzPloA
GfrqmqUaXEXpjc+8LIeTPjBkk+QguQYH3TeiZwbdoGtO4oBsuaW4KtSnOeRokk2PQJnVS18guXwJ
UrUDlYNfgmq2HXEbp3IIKogug9zNjyev0NT6tnXf2bRBaOFXX5tsEnmDDuCMEaiGkGKkA2lfHrpO
wKLlFYp9tMO1gfiq176SAfJw9mEhUFuaArZhFDDfKtMp8UotmHZjTGkUW50aLnjX+E1cl39Kn7fn
7VIa/oo23JM4ybKEB/CLQaZze8Lf6/S7dsWk8kv2hiJqbr4wKTkHIWvSjlrPSTdSG2nz/lbD4OH4
iYC/WmbS+TIIoUVgdoa/tbZyhHfBzPEWWHZo92iwy16jDwHiW7scuBWIKMr+3+vsftwGkD0GgS+e
FT4dp+UhdBxwnIMj//LHPnpONr6fjpMXq2+Z5qLAEdm9YV2DCxMsmVov/nW5WKMoPh/AfId7aVCl
lnmAVu9sYBxnTsbRZgLH4IvJYa/ppaXyyJjCJ4mecevlZaeY5oE6uGMkzCtnu1eGpvplqPdwcC5l
wS+6Vv/+ZYdQSV6YGb4SS2j5qbuJtTkWt0iIpSPVO7oUpw6ovBLYhNwQX+JNIxQbGQcIH5wQ1Xnx
ej2/2oHSaVNvTFpdYGN0dqBh9hnM745R0BFj4CmZmZxmhLNmbPt+QLOtc3npg5XOym91oglDfCxe
og67fuFMwrEldSymwR6M+zWxnp04Evc3r+xTrNrjCgrULRbi9AzCCxaL0GrJLtjLuPyX10Il/kfU
gSiQ8YJZBdux6o9Qe7ek8+hcwgptjtIfpz2y4lCAZVWZnpKSt6JjoDaFSMt8hu1Epczzsi8fl6mu
rmcZvBwRfRygneQFsYl+i+erMFAQ2fkNyainV2kq+MTb2529d1r1L8I03Rmh8zRqCMRSn0OVLx69
02uwHk2XrKAcAPMHtUoVNm9z1RMG2nkvo1dOkuRqD9CN/YeIBIsZWeqvZa1tE7FzvK6MKg7l00WN
Dh+znrOB95sygJonNsDe/KxDmNF4ghXyjhv9lTOno7vCtVVy2dhDfj8HzU0lvrnIGSkv4sw1nw+A
a00HXMfiCu0zDMK5fWIuCpyqjuBK+ibQvGgp7iA1ZySUYYBTHqMNlrLeZp0eeGCehJMQYSa/TCcK
r+64eP4B8dri6WiQnzQdXCtLYOWPFJPUWO/xBxVy1mVYarUxmLs+H/A55zB5NaETyIcalvafK63o
zqFbV+baB7Jt9bAtqVnA1eyDSy49hHjaN4QsBRLCN2Og3u61X5WmT8KuqEpEPl9dQMfJBx+upkxU
FqzSisETb1dmkelP4o0WnvJkUprzkv1W+aOLEy3r7ZuruEI0EfQfAFEXQdbDcGU9SUOgIQ89ThNG
Gfb9tdxskjzYGTF4ecejNOfDGot18BVdFY1TfrficHBVgVbHQfXlqdPCRKam9lbhUUzdu8XFsxos
UMkR+lh11hEiSlDSBrcpigaGnYPUBJyWHq7TVfoDsd6ctX2ypK1p66kSXVkvWynTRpW3T9ZizzKS
Fw1fGKBk+lrECKceWAWfE4WICpr8lDBFBrqKXhbFRkrazL7BjEkE7c7WmxKDHxBngLY3e4EuVOuX
ijonRUgXDb5QxKa/pF69QoIqE0qiMENH5tCRzkt2sF8IbuJEQVhzsgYJh6DqmVlYVZhwzI0jWKW0
bj43Ai1Sv+fdLpZigmSoXr1Uu8V5JO6fBHJFELM8TZPc07uGXba5Kj2vAnH/CvUfixrZYYm1FmE6
WAooYuyePChP/B17e2pCyqkUnTHi0ACvra6g8GT/k1eB0gR5U1xjmUeAmw2YM1gqZwnB3KTK2R/K
OnMjrUbXLu0jtRS6UqZdZC78oMDf/gkR6zPC/O/wBVlUiGmG8F266//PP+j4cPhtC0iaKbB5jioG
UZGVE2pslsVWKLqpWwJsXI7W5tciinu9z3Q3TCdUPxxoOfRVorfT5iMTUwR8Ird6uB3ZR7dxzaZU
PBnJxZKeK6Q5+8TIN01mO526KnWfhdsRdZpbNhsuTFWlmANzhAQu+ERi1aFSrAuIjJ++dDuUoiiB
m8wSQxlVgoKY9sWuSB3QyJMWv92Y0FtpF58PtQ7E4DSbkSLT/TrfhEt6cpzNGr0nuCHgJ0uNmiXH
qbw0wa3Entbfm/CouOe2blEc1CIYf//mH3l6lQVEHczRvMUscmDKIli8qxr7sVqxiv7lxeelG51g
mewMuoCmQ4LS7RactgllyhYzjqBycfWMn68DOPplcc1HJHHfScYx0Hx6aKUg6OJhcBQMyb7Ls34s
hAfB6DvRYNLH+S4wHlxoDtAfHJ/ePFcqfuxwAwilaSQDBHinmkMRn20peOuQZEv2hNvoWM9beTNc
lyz07BPJazjBWy3nKv1Tu6Zbp5bg/tEiATgiQWv8JpN25xv2m898c+5aZZr0/LBYEapwlM899yhh
iRms1Pfj2HU6xU2D4rhRb+M0RBF+HDaHnyij+D1unf8bPF04gb/WLB8R2xm+dJEtbVpFu3U7wPaE
EGxRWPi12G9pkui4rKOfqA+Q5fnmai+5DcBY7avNEl9i6bm1i20baSzoj6xc7CKWW5UzaOKcAWaj
ysgMIbQ+mUcecc8a6eMlygYz8c2ZenAATn7hwZBusQEwzKz+8AXnu8LsqKvMpJSQuLJl6+KMCyo0
GySYNpgyG4rNK2JwL/1EuqLoC1qelyWFN/mZGKZXJMGaTNJUyCVXJHi2Onaws1Qy0GnPJqrhtmxy
OOKQuin3LadECYf/ojYOKIww3ddx0IXbw5uEgWjIVm+oUCGfKeHSaVu0Z1ZJBYzov8EkXQ3AURu9
F6uo9N7ptwTOuWKUy5z3DFfEN67f6FVs5qLouzU7cu8ZT1HhivhfBfKpzOVnvPV9diqvInO/wDgR
lXLZ70Osh/U8PdlWgHtVgWR3hvERahblVXj7mVw7ZgrRabb5T/NNuFzoSq/OB+nC6XiOWyGhZyft
QQBmCLwKpR+th8PSjnkzzk9NE+HyH9tWKnv2uJOfB9h8y/DQFYmRUS64kObNqm/9m3cKnU+4SaQE
pjd0+xy8CyH3JD/4fvFxKYthNWRr5Mn7i1e4uDb32NN892IaDQCYUZu75jgzoYLtWW5aS5A6dLGD
q6VVoHchtxdA23rqgQ06tFLZtF1SXUHeNaQ7w0Lyh6IYwGFk0Y3i7olFf2U6JQVOG0KkHZmiyFxd
tSQ0UW0Qxsn5K2kCEAzmAEB1SIgQziqnH8Ow77kBVgaPY2Y8+sk1jCp87kga2fvG+Xzl/VT96xgl
O9dc1OLYZMbEKS6PO2Ci9Q3GhW/nUFEX52nWbU9WN7TQ4t/kq8vThNJJHW5tgTcxUBbBvtF3a7xL
KLU6WxMQl5IFvSNXFOoryGkXkiSCCkB/pnr550ixtfWIRbxq8RaZsKfBI42rbGTbM30aDDPfx1X8
stkDiKxHKaMKreTFGY+2xh7hHNfrJoeWo2y5bvPhBwx/J3TKfofaK4lRntgria4e5KaJzbC6gtRG
8DgjN0jvDGNK/pARr7vIgmGsEbcAC6DuYXovEKDcDXxZssbk9vKKvYOuSWddE170v4WimqFcxXYS
DGm18YBdDTETCLGcQb/PgligjyCuJ7cx2bWIl7xLo3s5/PNBTtZgF1kCOC1BzdhTLPa8Qr8KY0RZ
lNq68tlZRuJzeHxu2DwGvzgxPn0Xpg9XK79ct+XSarKkB8gbnTlnHzL6tJst/eJlIYcx3GgNUL+n
euJNCAahHUBcf75QGYBtynGz0dNpATBsZutw42cSgjEp7qtloeBqmMGbAy7ZbS5GhElMyX6H3Nc5
NYlKYVGXx2ZD1LoJOgUWKa9+Lcfv6dni6tDqL6Dc6jhZgUEgBWHhw1b6cadhGXKRwFefy2Ob+R0B
D8j/3byIwDxfa1hzTbHwgR2yHwELKcobx5LCtgVleuniKD3c7d0KkRwUefST8k3vQdqfsKI5L8lP
Magy64ia7Ockl1mkOsJWnMG9U+vumiN1fQ0WxDbxPhf6E4sY3mvuuSZoh7DsLehv7DTBxL3vkmwE
CY+3MpycMgc5c8FGTp8hI6Ek/k+l8J9X2pagkswjTfEVLQbZudqtlFWA6koHHO3M7VIhITvq+BUi
+Qx7tDmxBxjoi8QKmjF/itukyyuuSPZORZujGiDXJMiXKblFIuxDdIrlEBUF9HAPqmIWt6BZSxmb
mZgvv44X+nAUrpOJkAS7ceOo/iKSKuaZuwU0pCXy10yK8rYrX60dbNttoH4oIbxrQaAcGxCuAP7s
0RyhfW1jYInEmxzidjKwL3l9pM9XhhBuzCRazxBP7w8bVBJGtGbNf2ULrsIZx8TfLiAq6VhRWnlr
T5mzQ/iGFwvF/8DwVKXCnannRB6Y8z15ZrycCcUTbTrzupX5pOx+gNsbR+L5R3zwr44fVoAq9Vvr
fS8JmhG7osN+XYUYNyUJe28dXYL72BE3w0PC/aG57ApWsYERoNT2UL6s4h43B0xmCVlTC/vBBD3k
DldR5kOemroE7VcNtu8EYz0SZPABy/q9KHjM+2ViYt73cBOpH3/v4yDRWTD7sARagRsCUhxWmQNK
Pr0cKDfN9DPqDqwjC34LMCuX4YGaMPaWVAFZgXSBFupznZOe1jRceCBlnHT3H7Xcfe4Nu22bTuIK
U1duJEK82Q25QZZVp5CoNNE8tXb6MeYOk+XQ6kove4rNoZklGc2mCeuw7B3U5n+wTLpB9Ll2r8RT
oRPaP9rZQ2rHDQmd2UhmvjcoMrMV6TF+yRVph4G02G2IQGcpxig+GLsz0g+8upbX03B8rhBFl1DM
bet7yCKhgqwDHHnSJlKI3ZPZAF0MZ5ZD/LSGyAZnOi8KMoQLfJbB62/JMP2QtadppeCuX5SU7f4N
AGVSh52NAEJjO1bgJpZXaWXYkAEQvtyvJcwN4aU4u7clQWfdMRfzaFEW5c6AyeN+9AipDL0RekeP
C3IxLGvt2Ov/71taKJNkFJWxGfJI/3xRLdalisZdq7SqhIYv4Nf8+I7uiKHB8GsUMFvonISsv2aO
Uy7D2S+jqxCCKEWC9N3aorHfgzDZAXh7LGnRVB/ZtE1gLUFLn6uP1RrTV9+5qLY5btQJ0a9O4gBD
/Jy1vdwJHhbDczvArR6Zncn609RVpmKtTILt9GlYz9oD2xFaFviVXMgcPU6+hOTbPYHTwgLxf0ny
NhfLswsf4998so/etfS+OhwmRZsODGXNbQxbRIC/ZLqrJcNy8ZYsrZAVn5aVecjmDTUeLcRfJmOF
oykL9sF4y4g6zylcVCemQ7G4MDy7iYd3nwK2mda7il89ss+bcAFTON9v6PYqOBGSgDYqc5s73p8/
ULuuvkovE9X5H0792bTaGhMyByP/7zeJgrIKmzn/hUOARJoCWpgYPiC4e+jb9QvfzAL40JOPXb7Q
LyMAQQgBy8OazOojQPpyCGlLdLhp/iIMM4LjZFNJe/kXPODFDopFWiVIUzgNZhkiBB2hnAt66/b4
yAeYgW8Ehy9wRqnrD/bqaDd7siObjsSA+8d4+ZZMDUw7WyIPXXKHy7LkB3whNGqYYXTvRRLmtdB/
I9O/z17LxV9ix6GbyDSxHwfNoI0iOE/UMOsGvPsr16iqPUODhKj5o95AIrQO6Wpy+yZCM8WzBNPg
wpB1zG6TzOvOxQZFfpY+qYH+C18Ienj99GTWeZKDaTRL3zTlP39yojHRT1tYvj4Ad1baBrBug88q
nyw4WNK8YgxLHgbXd+Qa9bt4ZOQnPjG8VjcIq5SR2i7G0wJi1ExUb0VtdIgsEnM45XrM6l9bEl13
JKsCh7zq5hdUCvtrWN34G0ezHBiCb+ZIjECWwmNfvkxwhXhoE7FZjOYPTECONWWFgxf6JbmJQ/pC
dnilzFZQkmW+rVgK7UzW3deagF75I7tTSjEt0FQmq5hCgkHLXN5gqzXmuqn0EeVHBXQytLioLBfC
/upEjptRV+V49mVecr3+Cj7n6DnYVrywNVXLp0t2lqXF3loyj7SbtLcr/1UJCHd0+6qGKC57I61P
Td+y4eDxIwO2YmlO/N3xBwxHJt5emsJtLcouBnErppGvoJ1WBKDBPLxl99BCE3997FKaef2OXpMw
h1UxWD5CAGYZAuC2XSFJyo44JN9JCoVhLiJYvfFBBDtfepWn2djv0bgFIZnuz4byhROeJxChL1ch
8NEuM3p42ujs+znrM4PDFSdzsLHz9QMc5xGWZ0RNAynBpF31B0N5iQ+4JLkcvXdg067pIVZ8byqB
lzL56T4BY4a2hsFe/BtQi1P3KNwG/cqxVdmtnFthH/Uph8bgzQon0X2k69IeKhhHbTgPmGv6phJI
pXE61+CXAtT+pqR/1HgU8DKue2r1FY75Xadu6PsoYrPjVWKLqQ==
`protect end_protected
|
-- NEED RESULT: ARCH00164.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00164: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00164
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00164(ARCH00164)
-- ENT00164_Test_Bench(ARCH00164_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00164 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00164 ;
--
architecture ARCH00164 of ENT00164 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00164.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00164" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00164" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00164" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00164" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00164" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00164 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00164_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00164_Test_Bench ;
--
architecture ARCH00164_Test_Bench of ENT00164_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00164 ( ARCH00164 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00164_Test_Bench ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
i2mzeU6QCVUlRaOwzHOHtmNUcWYmAT+AF7sS/OQiTnMUHgzqvBXzGg25K/s1T4KNaKWeGHbEjPxj
5pIGW/ERNw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
TziN79oBOY8jpCxvFmTsaG9x2Wxvp0bJFS0k/PWEz1R/jFVoLOagNoWq/XP4YDlux4evT68noUO+
ITV62UAWVEmvOAqsoUv2evbvJ9eb1vyUch8XH2WvEqAN0z6JQJJHgRBV4I1wJRtLECVL9oLy7hsU
ka0tpXvq5o5Honv4rWo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UE9tFDT7Puo53H8z23Uuh591s58omFbKYVWIz4RS6L7YftCi+JPuSF4n02pDth7iFdgvHwcuxXyF
MI6yC/Oup3gukUYQEpZOZvtPTJrdeb2TiLOWiAq2SLREEt66BGmRo+d30RzLFZRJcaPsS5CnHwhZ
RByisi8I8zwWl0k+dwPwlR2S6QsGy0E/EQVV2yTW6UzgFCZSwaPbZ9D4U5nAxeBx0ykxqwaf1CSw
GEf32toN8cJpxtPA6kW+fq7vrQdxwOdqCZU/C858xjQEiQCsmvz8TTJRjniGz/5vO+qxruDO8okt
m2aIr/ikaNKYEpdauUXGyg7+kUIWbjNk9+V+og==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
EQ0dUAZyL3VPEdrJ7ufnkyChEQV0R06/sVE9Xgpm8pA5XJg11x7Yd5bM5jeNzQNbUkZ/4tOHDmkk
iwHfe+pC6o5kjon2kLubbfgr1RXGCqcmB1Zn/u5YbSsrSwBDJpil2a1sqye2pjF8WRIvtNiDlGi8
6f7W/C3vYMTYfV2QWlA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lqvCdrtKAFPGN4wq7Z75Bum/bhU5aJ8Ap5gRLSggMhxu+FYYehXMblm04b9RJW7R1pQWCUWfOQfh
cvsmNQwioLntRVvUAaxDf59LAu6m27QrEg74Diq/POdqjVJGruOCdz+BOdSMLOA2InulgQb3Tg3Z
nsj49dJ1K5dkrTksWotdJbOMl7iHsE3NRSIaR7b/bXBdFkGw09fFrzmpl5dYqecMh/9CwEK4MCCS
ikC/wLBchZRsgHC2soghYeMb/l8031qcRQmZz8Qk79lKLj8O4oqq2evj8uUAFKHV4D033nqcxk0s
3j7vyQOTwEHUCWpbzot4MFW1rv9H1eoInfINDQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10032)
`protect data_block
jeNwVcb9l06LQjyw1qQN1acLuaSld1ja6XaT2c8oHnCekZM0F1G25Havcz2W1eoDp+1g0OTY0iqW
dgULBCP3twdubYkbuzB+gmQBtrYGYnj6TSFpNT3CZBgXtebLRec7ifkvOqhJtzU368OOHUg28ule
Wd2jXluxzzb3yo6UmrdCEScR0RtOuHjRVbDlWaxai80NaP5QTsjOqwvRWermG9ihrcJcmtYxo0Aw
r5D/lFTuOQ6QgMuUjHSkW/3b3ZFHHnwd0sexPWzZ1/BQJgM0mAmX4yXHG8T8t+C00pAStf0sFsGK
sjaCwSxe3aDNEHm4A+dW9dW1BK4Fbc6wnqi5Y8LLLvlrk7rn4vc+kYWSTkXL8sJ7cLJukyex7Wts
0S4OCZ+N+B2epboVAwuwOxgDFhvojo8BY7FCh+1xDXV1eAdDx8dAuEJA9T93XLKCafl83prGU4j2
Wc6xgFZFnKezCHGczBfOZ4L+98P36NBGkUQFaMCgcEjnWa+6oxOFxY56aWLFImd6aEAuHyJq9rxk
2EbFstcbvjm4fty2BN7HkTaOjJY8dtmY/K0xDF0Yr5QyqSf+oUtv0Ylse5gRj85Ic1RZA529NqX6
xrv2OJ9ohE7FpxhXYBGKbEMhaOuFiupmtDuSMLXq7gCEZGnhDQemoZF5kH7Hz505YZNR7TJGoiq+
Mviv7YLPCipyzoutNHOXlXiwr/2Cjp1ubcmSk6+3gPju2y4ev7R9O4iHMefqw1faUy7od+JSstG+
5F/vYWNxE94LwHeSl9sMhBg+NpPF3tJRwAADNRZZ5Z6Jz4uxkIF1MC+hioLWABK2DQVyy5M9bZDS
RpGdXBtE/hhlMpwbEvQWJykuKChgTbE8nqCWcoRZyWW9dbEPOLYZj4FCmdPJ0oVjr4xye+lhKDxb
FU3a/Zr1rQlcg3RVKzOrVE2wPPYY815V8+PlsKuZQhtl09UEglco2OLZRtcIQVT/vDU7Z9DOjltD
hYJaX1CX2hrYFQpfSizF/N1lnqEtGG6zGsa9j6C9kPxOriNMGKh/xWExK3sOdeXR7SPekEAYkPzr
e5xIlHfa8McTDtUxIQ0pGj3ounfNdYUtmeQ+UVoPzvAG/BSr51yh88CHCltfkCUJAJlYEIeWFwQ4
KsXeVteEVCt9X08Ni0XfBL7ws+XaqvJya8vyCbWMMQztGpGDwUl7VpDvdec+AxoaRbU6VxiRFzvZ
sy4DUGONvIgdhHAVEm4umyM6GgM6exzHMJa8D2CagHK7PrxwPtwTgk8fVR0vuGgz9I6P01oHK4xC
JDdRFcbRYPtMscBwDV16tD/L2y56RaDvMNHULHLQ/DwGUVa2QxxHTambSReSpnzU9bcED1DzZZmX
Z7D6WmFdg5zX/O/2fI1xZ8TdoqAWu9YOuns1+tVGSztIghKBKrUhOo8CL0TDqEs+e/AXlmIQW07X
lXJOR6yFNNdY0gsOSGYCXgk4yC7lQY8X9zDMW8jelTup9cPzD/9M9J3LHrwx5IcDWSWvi9V6rPXb
DFwjhpmMT1Oy2BUVAUxegV/shUkonVSyLpxViF8e2OzY1ZdNKTBzJP4mQh9xCk+Ef9uiFTVWM2hz
qztdZ2OoMgAd9YGSouJkU0kL8dR5mcTFjQS8WdgJZBNLoAKrTN1kMjQA3YCfaF3vT52eCGoNMZXD
1u0beqwwe7HWATmPWRnMuWVz1MnwO2IlqrzebuugFzKRC0Y5hxJQjcXOcIPswmeN2CBsdFO8BuGo
2kHCto1XrW6oFuzxXTPBUdCRMQnYd+n877UP4Hmyy4vcVQX1AiBWe/jjXW/gpYsdS0AX4QkvGVoG
aMlbi7hcd1o8DYnzO/sN+1FvN6kwJ07ZGp5SDhmYTbBGhzFue16HN2TMJ06D/JNY7SzZnzqHjgjw
VwM7avSqHx1w5QMIL+k8eolsKhmncbtOqyLIZtBjXmGkWq1PnXix9Mt++wWZUtBCdZ790oCmyx0a
ef6YU5BSFOpC4AiwAt+CgQHjg8k2u6MaIPWag+7vymNx5lvcVmjoG4WdQHJRs4MaxjZcHpvEiH42
RRUFmnU1/ShmekcVDLFPOvSgcU/12yjKoXFGJcDEUJ3chJmFi9u4AEPZMvr7wi2f3gIR2lxZKVxr
sGsg6hmPkdiVu/AjWRJHLuDROAF24x/UUTQ3Y3Z9nup0FnL1oJ3bWifZTVhLHpjaA4+49elvX9B9
lupuf0XLU48ZqJGsJKuK1A0dOZxXg0XcMuriwHpXxKjUoHYPT3+tJWQMcEc0fhZ6LaDA6NxJpjxG
Yd7s3B9G2VyYLwm87HmCHD2v7iBq/u1K8ik2Tl5qrUPyb027Lzs1lEQTVxrTtis6eOGBUOHPfnjl
Q0TsJ9wIB8bKHtShH7L05DQpFW3sQ1DDBKbHgemca0jaMYgpeI2nUMaN19o0hb7/sdHQrVyxlIHS
FVas2/f41CLdfazpNCnWb0sMMK09lKXo58ktQ4bY/QjTtJDcuemARZ54gbMwmsDDzxa9lGthvgSu
exVexIDSl+AxZmWiXVgNKNlZIRFUJ63iwBdFFmvN89Ca7J1EPJNcGZMSsCZeJUyYownH6ruoN1JE
SBOcuP4uRh+j4MNhEwJf1Rj9X6OsdnKNWnIILFm5wAGrRucRLa23bGp0T+B8BAGD7z5LyhJtiF+m
bjlqkddjeOfbQ32g80JFBgMpQM/JESjD4AKspDStDAy599715KSJHnSlie43x3zPzvM3WuwLOT3c
frTPHMXxJn8RrigKQKkmGYCXiY8O6fsv42vKZJWVz85bIVU7mlvYhOCqkZPojgiTsBXlZvMpP0dW
Zfcg8nw5NCQFrUMrkv70yBnrNCgMMml2dq6UV/8sxQ3+M/zX7f7d7xoHGP/4u4/eX2S2G83Bv3Fo
IhsGA624BZV29DskkOz/gaj+fiRmxTmVo4wyNh5OQ1DsrZa5UdscO/enwJAbbZP45w8bcYrFTSi7
J3n6Bc2a16TkC0Imf/KXrXxl31YZ+q193HVO/h9W3qI4s5yNIiOXODma3X5BntkLgLH6k1PmgmdD
9SI9yuBiyl+HZAgwR5KRG5elbgAbUN6jppz+ANoLWUppgx6Zpqi6PXGFLqjKipin3FoAAcAMNM7B
dh29DnRlm8nSoEsc3B0FFkBcjV9wKNhvFKdyXjQNjRi4/8aJsFm9X6Xcrpl/ed4fmTvlDZtfwRle
F+uIALfpkNmxvyXo/YcovguTWUGG/J59N+wIaG931wznkz3XRFgQq46lmHD0zfveaQ/+FYFqUqV2
ZlWMbJ0le32lx7ImRkiReACoIjO+DPZm29NPGHPS8HwRu7f4lSkVfwQXO8oMX8uK6pULYy2ubj/3
1biNiW2Pd95WuqfK36DgmyXam0CHfhA16Nmsf+8PpItDlI6xq3ExXMnnyeX3E7iGlceqCYT/cCxq
bjNpZw1LnMyVWszDTTyYgIVP8HdfazgpM14YUwrhVWO80aWfP9VOFW8Xn950BmFn5AohjzqqopCK
AKcwTlMg6BNniBnMJEzjcLew76IHti2oM3iD2pkew2iWj7ywFzrugmpg/2LnBaZsDVfIuXclA+OA
Fx8TnDY8tvwFhET62GrmYEeCqpUpEsgGZgK7r4q8My7yOWF1IzdwcSK9bCYxZcxUryhdU/qyl/54
zIiC7wuOklU1j6IrVZa7c9GfIjfH4avLDlV6hpsxCLXxhp1rygAmmASDZREg+7H8+GBL3hw+gDrm
ZwPZH+uHrU2JLj/fX58BMni1GvDFWXTuhOUJUs0wsKRBcCVgaXoGFkJs/jwlzVNKe1r2JkmseFFe
B0WZVZR/vVggeJ4+N352oYlNmYQlTicSM/e6bPtssmM9+3lAWUUvGj4hOgSoDUu0bKlWBuSbExkE
kzy8L/lXcY9k/OlU3fRmUurfzzEpx4EwBHvhY+AXhPRK8ewMkRuCyomTSt6wUdB4KmAzVcA9fNWz
R9rJUfoFfQfDnTZ0d0HrZFNSniIocUbm45+B+CpioIy1fLtjRJpOKMPvvF+44TjI2cN4885ilv1V
XlejlsYKhxRLOBsZ8cLqs3F54HlC59mHmJgkxJJxKjF5skeaaJ9OGuAaom5VbN+hyKWHVXNhTHlW
/uHnyLRj7QvW557LgNn62nbIlAPDfiB2a6sTluHfKoD0WYI6UWL/mDidxfvVip/InMRpv8+q1iZm
xKivxe99nQw7QZhOzqmBODROEgk6cS1HJPk+UOhYSzekzZtpKgN6uvFwcCf+hFvbx/3Zl5nyJyHr
o4Q8/W+4+0Hm886n/QSC1CURkZD/iTxmcm5zopUW6Mpn6/f9OS3H/J+tgTZJFy+zc8Km4ubP3WxD
HVph3hX2lSV9RWDsUB2KOp3hVcVOh6elzqMarjIrGDlrfchONZGuH5dUtsgS5kOaxn/s8d/ptkn1
DDldZYxaygHBZ/Dvb83CDp5F5/7tX21gNXs6filAd7sqOH2N6X43+XlOuLhKTUqAuywynkVATrXh
hudjdoe/hTNne73G0jucgHtgnvig7XebaT4jnqoUIou7Q3tOMuYeW94xIVAU5b20BXhtcHDUk7UI
xf1aqRcmtBVrjD9fr7IxJIBia4xNxOgZjBlHPume12QJCKKdmI3N9DMeOdYEp/eB6w5YMYqBaJIZ
yJrYf+gQWiI2r1clCfJVcNvDL5thzgY7lbBrChgBg4eWKl10H2Ws+WD1rLhW8Gf0mIRrHz8Lk8I7
bl3t00muy47aB3900Yn5Ozrcb/HwbZ4F0SnAybQpWXs3L72/1Lebe+raWuYHnNuWoIKpZtZxpBiC
AQaFUEO+JJwblmZanxUmWOz80H7qCYzurpa2LLC3H6WcopuNd6uzGFDDtYtqkCxHy836wtfLNRO7
tHF/T5NRXtZDyOOSdP6aEPhCl83kmy74FfkyN7n82/Es/HXqNxFmHDccR60l0RCPVSUP7ypjRPI7
iZX+sLrXc1GBPk/V+iqAYrYWAwPIynH1wYWGW5XrSJXDQZ8THfL4rCX0TEcvupytz7h+VscFONK2
0x1qhL+PGJbZ5Z8zH0x/sXZVsSCBswuEJh/lFUcpXbdVh9tgHaifP1N/CsK2lRkPtP/3F1tA41q/
NsYTvZC77QJTFOSDSxwPYLMi5hVEQCsBVasJZmQZa2RhegPTn06jfGs3gt6Mu6m8ysuggs67wYbO
u1bSum7vzRW/rAlDw4P8T2QGUtFKVZit0ZSZKJg9Gu26AjIof7M47WxtqUoUJKr2aJv0LliwGqJw
cCUIiAPozJqvNEqY3Cy+1a4KhfYys6WVA4NPMQ8I4/DiypP2ygKmj/9Knvsr1QrEiXyDYDTbldPd
hyiLfBPSb1wQ3Vkbv4jPfILBcImvJV5b5Fq93qqNcK61wqnzJikHYu8LjEKGCFR7vVNrkQCe2oDM
0gV63w7NEoIYIykGF3AoaeFkN7wS1RdXlKRUZP59b0VkTUu64+NsgdbfwQZIqeWzKRoxmkuGqCFK
X4GjuBnflh+gfDN9q+Yjk0QzjSYMTDimyEMNB1dhD0JtijDuRV8c5V4ZZj/POL5LLb8X+44af6ga
VIEMh380Vd+d3l+3HcdRZSW5natpB7eDaGmn+g3SnyYzqTU7cQsUXH7jG7VwpSs2hT3SCUENUi4f
Kb7fVvgeURHWfExcmZFE1F9b71E+P+KrDs4KczJC43TKjsqwO3Vv3RCWgLGz11hMLsXyglM8khXv
6Jrcc0EllqjPMi3wXyGreUiPHg3/BmwRaZgSd67rlUIW/T+kR3HMuqcZVsPe++H+rD/T2LcUCmDM
Pnv8W1o3Cmqy7ZNKqyHUKZ08uuh9zwEILTtAQqWDoTKCJBaDoP/NPokemAMRK35glp19vPzmDp8S
6qrZ/2lHXzOrVLB70fMjMWETYwvS2YUa9dfX/ApIIqkXX+rLusp4hO5Y4il5b4gKMOBxloIdvPUP
yQDXTmwSiMa3QIgM17gct2hdHwuxCYs2Wu+k50ToMu+etPUNsqqXR2EiuzRQwaeYtqVgfm9sHZBg
pRsE0r8U+tdbD7DUqOfugamzYG8n45wRan9T5zXPFHlIbCUghBE4qjV9L6/l8aNjmzuUNqQpnnkb
Zio4Z7+l5qHJU1Bqwnalf4YA+rrwKbk4psWI1c9bLwYPTU/JDbAC4+6AKq14eFQP6ERCKWlrJa5g
+GodZWQbpl0Pa6gblGuqENslcznXxgxPl0hHVpTAU0DGHHWltjzSf0LFDl7HFvUniopplyKaktEc
CPrySD+aSk761+R9F1cvjfXhkbIkTecFfMvQjrzjaSRNeMMkLRexhZohX2W30ypF5ECcU+4bZDcJ
WRhCo4OS6zCIXCHyeRUyvfNqCCk4cN4o9tKPfAOxxaWGztCTODfgbBJdnMHnyy3JOp0sRBwEJmU6
9UYgBZWpm/ZcQkbQMoaEb28/OULejE0qaWDEBD5GiZt2PvufjgawsyoU8bltXFSx1AzrbvBi9GT8
xmjqV3zZfHO7P8h2paPnHI0tH/uR2uQim6mA0QmBnltwcul5MkU7/cVnhWA/Sirv7a1XJD1NplGC
5ddzzCTSxaKPu54x5jSfx1BRrnqvGabhSPp0su2JGH3LdVCTb6xoPp2gh3bLuFks2KFv8mHx+yw4
eLYZpQv8o2knd8wMrokzadn3DRmnonliPAO1JSimyq4ZP5nmHOtxOra6z4XqUlRbqIaZGh7q5cQP
Bq4cdtmPDXeC0OmFDDfGnsA7jSdf2fQoS7KyO9ukPRKp4IuRVJKbZ8hHulTIl/YPI7vXKA+woMuj
thxPlhJoiazP54ithTQH6Cqt4y71lH+cTAo0J+m+QrR5l6mUFLGAbAF+6LIPeObAw3MFRNoqw6Fp
BgRU7yiNWhxLIBj9hT48iduH/bnJim58Kn0dBEVHTS58DW3eNbMTSMKyQ+o2ZWKc3i4shNTdOV/b
gjN75PsRjHeKlGpWQhP/T4GJnQSTYYEBHNL0zyqB4VYZMT8GMngthIFGfmMGDqkC26T+ujiKAGdc
dYwReaikjF8PAKW7K9QvjEYkc6bCJXrjhHsU6MJMXG2iYzOsuTaXbN7Cbl/n+Hw/WP74pfUEgafV
b6HplSsMOCDCo/EzhLC8HjW8nDZOEmwSrUgamjKTIB1n/OaKspKHoL8lHaXYrd8OJ/X8wh2c9ARw
MExJUbK3nlx3lMSAyMkS7PvuaBFnqF2ZqkckEJ/Bir/E5plMGtQhV9c/7qza+J0BRcWIFTf6HyI2
LoGg5YThGKAaWaXf6zl9A81R31REZjy84o2UaoSns08X3NGvMdBHK3oCkcGQzCICaGyMyiIXJ+Bw
mFhxV5wwMtXWpTvKi6rEVHw25blQafNO6vWo5HAe+udcAFJbtq6IRlB1c75x+RkDRna0iBCDnlsF
sI3a4WnrVoEEayca39OHqCXfvLc6Bju945ElZU+8/+bs1wDAFlLZiv7Nl1W6pTtOgCvLli6+MYmJ
5WL2BuoyJsrE0PrtHKc/1GzvexDuxnsq7FbUHY0HU2cs8PU6/zCSOnoI3m5PODl6R2GUEC4TMFx/
dW1LZF403HoFrNPe9dUpSdFcSaz8TwT+m6vd2Xz7oDXfgfzP6DcDzmUTaIT/pjzmGgH7HTqkXEXy
sJ/AmmGqBOXuFD8CEGM2kf1KDrDh2B+KUZcmaGQJQ1NdKV+OZo45xij9WRmLAKXlcQLzlZPYEyG8
Y+xGghAKTnsT5Rt1vOFZr7DH8OCiqUEl/b3A9xv7oIo4oNLF/vCr/44xjXu9CLlUyHhZpVtR1C8l
I8fFOjhwOf2CAYPgTn1InrwO9KNxnNr2UzXdTEjZriq2MKQq8PFkS6AHE3Mlu9ConVezqNiPdEMf
Nu/OTptnnN3RTShsQ35U6WATCabzAC8jdzlFfZ0wMJDUHamJIfbNP9WGm77spvf6DYNMqAf7V60i
1uaqPj2c6ZUeLEbS2QIZN/YXJmr01A4mcBOrmzUSMWvWKsTmm0BolMbUft+r/jfEqeNG/bu9ZZ+I
lAhLS54GcN9E3QTrJrzQq8TAaQj363KCVws/TtPOhr2KW7JWVs+9TDr6eJ4zCkwiyXyL+kaM4m3n
L8qfyLf79Gp0DSU64mq7OzjDaZ8hg9ZfVvtSLCVaxdZARnEyz5WPID6vuXIARF777QobWmpU6FPD
QdiMdjlfTM4fiy18SHLxnnIaLH/su4ktNnOvdM8TicfezwEjtWxNL9khQGv3VgnyJZOg51LdTxVv
5WfKNRCMXR2OCdYkuUg98hih/EtXeMJqyykS+WMBEwMWK+UhyZFg7Pgd40G0dms8bMlbw3mozY7I
b5SkbvVKfhe9nawVRNkNMkinlEyDKX2ELqhSX5i6D5GNoG1DjKXDIhL5te8azt+TwHPN43ecR6EJ
Hs4ogWhz7h8KFuuzExmENcS4oljp2mKeHJmGjLUI6qxab6PVgwy/MxMHeAXv+sMR4UPhyLUM9hGm
eFUR3Ez5ysIOyNPFt2AB6QZY3YUPqY58KeMTR7nuZx6MIK6ZnRGxtjROEPSfHbkGXGapOy6y0TVB
FJe073w1tHNaTh7jnRQMEhbzoykjLWUnLb0345/7zD3lTBm6YmhSbxkvlcThGfrQZw3cuB8ydBMS
78jUDvl73edK9ckKl4R2hjI+iGTHmsxBvQdnBiJiYnXv/CgC5CdKT5RAYaEP1BiWNpVxeO30TlYz
K/BvqLUEXTwxT74LD8E74MDez++LDtjfMd142fKcxtB7XNnFKlgzeDBOpF7rNaUsRlFEVKKS1nO/
2LT3lHnxhuFEo+rg/WvzrwDE+MB5GOY09PNEnmn9Ld4QtzUIV/yZlpbq+VykYZyJ0FuJzTQJpK2S
bac+pS2KbVPBd5gSsZIOtJ0Hm87btaGSlioXRiyx6gefHQdBxgty9oUFp0YG6LRa59mybC366P6S
U2OVrExzyAv629LcB6NVmf+eunyrs4f4oM9je74LVBrV+JX9tO8ClU+CCEbo+/zQiEVv8ewjzvHF
qV6ROPqfkxfg+9bWjOCDVAKFAHlQHffe7B4E2j0ldJWOL9OsCXM7XE/L/8YqaCwR6S8Vw1lsPMRs
SfXUUCU+BMNjQM55Ksf+Tlyen5TTqzSKUmvmOwr2bt2q6gSBXZFLeNuNrDteCsiSbHiY+RIoBP4D
6a9PIN2L4dAJiUQfK58Qoc18yGzR08M6XIIc/bo9TQUQHasCGZjC7mh3j6PBf0xkkWVRuIp8Q5CU
iHdzy3Q2RYce+TTJV8gnWpGf0mMJqeOOlqIpfsisItP+wzn59Mu/TrP1Z2n5HAquiiQ+FZFHvBtg
u6x5ilR1v1IE+5RBP10OLN0uTYu/2rJStzKWIVJxCMyMsUXA89q9tFYxADOw+uM8ZCUUuR8IB68S
ip3gM4yfRjsrkQEN0L02/wnSi6Gx1FRyxW5pikSGQshJFX0J3jWRMwb0KxxBP79F+1a/ISEtIoR4
ZTdSFRBC1sNHbZRP3Z5A4PKWDsCeLtpynHR5nE/mEP4OsEDlFnQxu3lPFZoX1QoyoMi4ea/nI9tu
uCtTP01w/R/I2ve61dztsnfvOEc+Hb/Y72j/BlBsS0z8I86+EHcpKIM1fbIWjaH1l+P6Yf6sN6Im
zyO50EziV0Eh12KpCpDO2O+Ce3oJVZZ8/Uv3JrVeRfT5QA5JR4qkkJ+Ya9g21hAEcoRf0e3XfTJk
YVARc0pVfgst1O5tiISWGTpYqga9AQqRQX3HNTaMQafdaaw0kLj/bjTlhhKawWqS0lBncZ3RO3LG
sGmpKRSFCTIXzFUtwWgJX+kcQWoNohagCspC2ah+VY76X7KrWxq1jMzezzsrIMhyFVkovcZDmSBc
ywSrQ2ECxpWiWCN3l+JHoklyMl52iq6e6lt4afAUtutRE1r9BV6MD7fP2xGcURQ5yqKfiO5Qc0mS
tgAWPCsjJsYAjzN1gR6lsHsZHIJcSK8RBiW51U3yHL3e3d9S5qFmL/iv+tVSV8XrI8lKV9ldwlKC
D1lmyQvL4sGwZ+RQ3PU55jSseFgFwnsCsi+5rwDujP2kscGWgnA9EeHT2NNbZOyg7V1or2EtA4Aa
34x4/+UL3ssW5VFXy+Ehnz5D38GjEMuv8GlTjQsg8uA+cFJZdq6xd2jIF9reKbRWwcnqVm73l7ys
6IzOAtrK/ouwisnmznsYdbjd0/TGnBvCKGIw9HxTQ6/oIvnel6EgHg1+lLlZaqUamFIxuOjtcgK/
5sZWh+rY4DrjDU7RsylRvFWhWK5+v7S6opvxJwdqIbw9AgBB7UEghHlrjocfieTSTfQabJ4gyMNv
XnmVZDMhawNWhoUmwlNXbWIzqrby8mfIbNbiiUOuP996uNVJEP9QFFWkHkUcNRY8ekTDZm20kTzG
NBoWcM1c2hlQqvhgwFGGrTWZVFmDIjVATzGvUjBLqH4rfW4Vjr9QXx9S8lYF/F1SqhoKkRxzYrEl
ufeXuxYhmTc86VjsWqLSxTFtUm4Hez0kTI1Iij8OCbrci0tah7jIG8EGN9uwOpV+rsRY4Y+5Wkz7
8ee+5fuk66M+l8WvQBsykNSgXp+IsOWuWUwxhTVlim2bY3/y5WDOhqStoccZuRALSKq4v+oudA4v
9HtTI8j8M0j/s/O8trynZVOsSr3dTemoK7r1PV5rR1Qy9/kMjHHUiPeguruChhnUHpwxVE1Ynt25
tLh9ktjt0/QdtGwegBY42qaydV/JITGmd4dAiu4zxJ1bMeurdGiEb9kIWfKx3OkTfaZwYNUiIVSh
IWIkPwRc6PX71yxpKsk7vLUUvBslSROsAQaKk70ojfHqRyF8mQmu3pN0AC5rNlv3wsI9t8GXZ6vS
Tzlt0PkXWMPhikeuJD2cAZK1wvQwHRjN8+YEElz07kJm1pqMZI0H7E8IWypcapZ5bpyUks1bZAC8
MYC3Y+xQs9aAQP7e5Bk/RwFK5gUkMejzbIRTz3TA6o6U5sOW6wyYc3LNkc6OoEMnnfYpoZtn7P5M
aO5Zurnjg0cVArkwiv9P6+iEJGZTqk8DlHoX9xs2AoKIeBwH52FyIfDdCX9LqYy90iX6LeeanTt7
QqyXAARv16f9/dqcZhvU9xb1QRJUPrTHko46m6jlT/67nhMTtAHiDd8YIh0vmVK8pUOZmK2j2PGz
X9LPO2RNwBagVO44xqmCNXgskIdSg3+8UKQ6wyNzrSNMZ0E+9ghg6k39lwratAm15WAa67MxpG0z
GTIKrcmqAdnajxzGIQSGlHRgmO3E5v/IyDjpVuKq5emmfFBGnWxY4G39fP2eJNZ2V/Tvi43VE9+2
fSRwJzZ1o+b+HtnGxrcJ9Kc43kl4sE25GwWZKPZWIuYp2AwgWQnCYk5Bc4qLBSiWRVtD/SExT9lm
laJujJ+Jz/vuYBGkF5/oFZqrhFgV+TVSnn7B6RYpSAYYzVC0d4QZfNtDuqPJYYpWcTpiyHzXyc2A
Wi8WbuDIY4Ard9TO6u5NdSTDxsLnvKxO0lzN77wrrwq4aO5dhGHDs5BTJuA4mt0I1kYBByo3VTbI
TyVziuv4AjRQwnmhPUSqgJWkNDuGwhOsuP7elJJdjiBbm0Cf46j3w1NL2z+IC4NrjzyO+jtdUwIq
9n5zwsZNdIHYry/86EwR52uyixPqp+3hF4l6VZJmnHNMXSxwBC1P3RYCmoE2seqPXyMyjpopzk8b
Vus4RhAGSEyILpGJlSYpmnhegfbrqeubZ9lHakIcsa5v3tGNs9CcKympOGA0nzAy87QCNRm4Jn0f
yhA3bwA/Pd85U5xKoVUDDuMK9Hdm4myCxiydcXWSp5fM/1R1FUtqS2L6YOxPKxoEtSITrRJyXUyq
kQro3WeeBOOTFtHKxLKlFkW6GQRdENCkOWi6T0HSoiDS+gz+5LK3cStM2JHWH87LqAaQikfd7MmE
V/D0ygrf+oadJEXfOzKs2ZRwai9cjA72A0pPVy9AGrDOiGmxxUwfL4j+oTgY23wKJsD9soAKBR5b
kQyi4QUtPiOTSKtxPyWJdfoXPmHaQzD1lAYAu8aKI7MJTlmU+8kljiVtnHGUkjhDV3dTsuxtL0HJ
Z4pyYat4UxRQBUCdWZ1pY3jgyZb8S1Bec99fIUEOhZxMSBLEBzhfnkDPE98zfHkxzN9mX1w+7RAg
TmMR7McMp28ofnbByOi1X1PXUuo1BP51A1wEv43hxNihFq4z/ei99nK5RFGY99TqXl1O/DC0+r4Y
mWMpKanJBzush95XU9PyZB2r7vdgs7PU0EOJ3ELRwbzgfbkDKQoRbccLu+tLqB3Fn4X0ZrHGk9zD
SphJleNVTZiMneMO3It50se62ho8AXWu6INNUHi7kE4Ho6u3T6lwXBSx3qgx83HGNkQ993BPltCR
JIyqw84UHN4qp3aXBwDOuwgI9sO3syWlhZSYaO9v7ZhAAAGlEbFiuFdP7r5YVvq5TsNuUiyje+4l
tdoTFmRIgIWRO28/GVCJEnUmsTANQcB0V+zsuPtD5o4UN+spYj1xbm+MkxA7KZFm8j3Bp5Rs2a/R
x2vPrv9sIIIbYAQFDzu6GOe9uoTZtHujgDS2/LlVZepEZwpOopZErrY/3OMSH740EyzvRFdjLztP
vjDrh2iPM3OWPt5UFQkcmPvsqPrG1+t1YZNA6tiWIawctm70L1DH9K+UgagYrKQyFTUJzPWvw2Wi
SdbM+pYd3hlnug+eyBZPeQQzv7eVIXV8YKe1zucNw6NxyBc+cL9x/KSx8LWDyGiozqj4LDY8TKWL
AtFeBwc7XniUvqsJbMgb8uYmiDWRONmr9E6kKYvy31qVs7ttjY2bt6MCrw75r1cU196EJ16kolqB
qQiI2UpEi/Ihw5+kwWbi7U1sIRcpFL7GFPg4H0x1ZBMloxOXVDPTSm875n03kjLp8tWYRJEn/d2Q
185pvz9ilsanvkWW4Igeur6/DgbbA/0nKN7IL3n4cbhDffmmlyhTejk+BX4e6pT28omR2wWtkB+f
gkeRgXYiDIyahSU0f6Ewzot3BND/G3CTn66zHbCWwYap5b8MBOsjTl74XguZJZupzA0fyInk1jay
SMZW+Rp0NAr8mgWmcGQyaBaImsUwvBc8cShKDiIElFm9V/dcKoHzbt2bU938ZQU3MSiqgkN3Bv7j
rv0DtWcejoYqcA46SX0rQVfcwA4tb/xfJSaaKXV9NE3g7eYEzpuhUZ7gtIkUrWoV9h0IgHtwXYiS
bqm4LtKEUmxhE3Bk8Ral71MQ4kN9rdcpTGWMtni92rHN/uL1z1WuSS9ZT5V5ZrqnqdDxReeo1clV
TspL2635mPFDNsAhgRo5L/VXpiDJoc8Bchd+pmNWIb+DkiCUPql775Sbqu8fsnESR97t+gn2Xdcc
675aCuxXSRyc2IjmjT9sDYbFqAdx14yISmBzxwJIWkq8rRkqTyMtrXO+0LHwp4FQh98Q1sTP68jn
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:15:11 05/08/2015
-- Design Name:
-- Module Name: gray2angleinc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gray2angleinc is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
bit_in : in STD_LOGIC_VECTOR (0 downto 0);
ok_bit_in : in STD_LOGIC;
modulation : in STD_LOGIC_VECTOR (2 downto 0);
anginc_out : out STD_LOGIC_VECTOR (2 downto 0);
ok_anginc_out : out STD_LOGIC);
end gray2angleinc;
architecture Behavioral of gray2angleinc is
type estado is ( bit_0,
bit_1,
bit_2,
salida_valida );
signal estado_actual : estado;
signal estado_nuevo : estado;
signal anginc_int, p_anginc_int : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
anginc_out <= anginc_int;
comb : process ( estado_actual, bit_in, ok_bit_in, anginc_int, modulation)
begin
p_anginc_int <= anginc_int;
ok_anginc_out <= '0';
estado_nuevo <= estado_actual;
case estado_actual is
when bit_0 =>
if ok_bit_in = '1' then
p_anginc_int(2) <= bit_in(0);
if modulation = "100" then
-- gray a decimal multiplicado por 4 (desplazamiento bits izq *2)
-- p_anginc_int(2) <= bit_in; --(gray a decimal) *2
p_anginc_int ( 1 downto 0 ) <= "00";
estado_nuevo <= salida_valida;
else
-- p_anginc_int(0) <= bit_in;
estado_nuevo <= bit_1;
end if;
end if;
when bit_1 =>
if ok_bit_in = '1' then
p_anginc_int(1) <= anginc_int(2) xor bit_in(0);
if modulation = "010" then
-- gray a decimal multiplicado por 2 (desplazamiento bits izq)
---- p_anginc_int(2) <= anginc_int(0);
-- p_anginc_int(1) <= anginc_int(0) xor bit_in;
p_anginc_int(0) <= '0';
estado_nuevo <= salida_valida;
else
-- p_anginc_int(1) <= bit_in;
estado_nuevo <= bit_2;
end if;
end if;
when bit_2 =>
p_anginc_int(0) <= anginc_int(1) xor bit_in(0);
if ok_bit_in = '1' then
-- gray a decimal
-- p_anginc_int(2) <= bit_in; --bin2 = gray2
-- p_anginc_int(1) <= anginc_int(1) xor bit_in; --bin1 = gray1 xor bin2(=gray2)
-- p_anginc_int(0) <= anginc_int(0) xor anginc_int(1) xor bit_in; --bin0 = gray0 xor bin1(=gray1 xor bin2)
estado_nuevo <= salida_valida;
end if;
when salida_valida =>
ok_anginc_out <= '1';
estado_nuevo <= bit_0;
end case;
end process;
sinc : process ( reset, clk )
begin
if ( reset = '1' ) then
anginc_int <= "000";
estado_actual <= bit_0;
elsif ( rising_edge(clk) ) then
anginc_int <= p_anginc_int;
estado_actual <= estado_nuevo;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin2BCDDecoder is
port( inBin : in std_logic_vector (6 downto 0);
outBCD: out std_logic_vector(3 downto 0);
outBCD2:out std_logic_vector(3 downto 0));
end Bin2BCDDecoder;
architecture Behavioral of Bin2BCDDecoder is
signal n,l,m : natural;
begin
n <= to_integer(unsigned(inBin));
outBCD2 <= "0000" when n<10 else
"0001" when n<20 else
"0010" when n<30 else
"0011" when n<40 else
"0100" when n<50 else
"0101" when n<60 else
"0110" when n<70 else
"0111" when n<80 else
"1000" when n<90 else
"1001";
l <= 0 when n<10 else
10 when n<20 else
20 when n<30 else
30 when n<40 else
40 when n<50 else
50 when n<60 else
60 when n<70 else
70 when n<80 else
80 when n<90 else
90;
m <= n-l;
outBCD <= "0000" when m=0 else
"0001" when m=1 else
"0010" when m=2 else
"0011" when m=3 else
"0100" when m=4 else
"0101" when m=5 else
"0110" when m=6 else
"0111" when m=7 else
"1000" when m=8 else
"1001";
end Behavioral; |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.