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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test_signext IS
END ENTITY;
ARCHITECTURE test_signext_arq OF test_signext is
COMPONENT signext IS
PORT( a: IN std_logic_vector(15 DOWNTO 0);
y: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT;
SIGNAL a: std_logic_vector(15 DOWNTO 0) := x"FFFA";
SIGNAL y: std_logic_vector(31 DOWNTO 0);
BEGIN
ronda1: signext PORT MAP (a, y);
a <= x"1111" AFTER 5 fs, x"22FB" AFTER 10 fs, x"AA91" AFTER 15 fs;
END test_signext_arq;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
use work.net_config.all;
entity sampling_shell is
generic (
num_samplers : integer := 4;
tau : positive := 20;
num_observers : natural := 16
);
port (
clk, reset : in std_ulogic;
observed_joints : in state_array2_t(1 to num_observers, 1 to num_samplers);
joint_counters : out joint_counter_array_t(1 to num_observers);
systime : out systime_t
);
end sampling_shell;
architecture rtl of sampling_shell is
------------------------------------------------------------
--function init_seeds
--return lfsr_state_array_t is
--variable seed1, seed2 : positive;
--variable rand : real;
--variable int_rand : integer;
--variable rv : lfsr_state_array_t(1 to num_samplers);
--begin
--for i in rv'range loop
--uniform(seed1, seed2, rand);
--int_rand := integer(rand*(2.0**lfsr_width-1.0));
--rv(i) := std_logic_vector(to_unsigned(int_rand, rv(i)'length));
--end loop;
--return rv;
--end function init_seeds;
------------------------------------------------------------
-- TODO initialise constants
--constant seeds : lfsr_state_array_t(1 to num_samplers) := init_seeds;
signal state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
net: entity work.sampling_network(rtl)
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => open,
systime => systime,
state => state,
membranes => open,
fires => open,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
------------------------------------------------------------
gen_observers: for observer_i in 1 to num_observers generate
signal observe_state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
process ( observed_joints )
begin
for i in 1 to num_samplers loop
observe_state(i) <= observed_joints(observer_i, i);
end loop;
end process;
------------------------------------------------------------
obs: entity work.observer(rtl)
generic map (
num_samplers => num_samplers,
counter_width => joint_counter_width
)
port map (
clk => clk,
reset => reset,
state => state,
observe_state => observe_state,
count => joint_counters(observer_i),
saturated => open
);
end generate gen_observers;
------------------------------------------------------------
end rtl;
-- vim: set et fenc= ff=unix sts=0 sw=2 ts=2 :
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2536.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n03i02536ent IS
END c07s03b05x00p13n03i02536ent;
ARCHITECTURE c07s03b05x00p13n03i02536arch OF c07s03b05x00p13n03i02536ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (1 to 6) ;
subtype T3 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T3 := (2,3,6) ;
BEGIN
V1 := T2 (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n03i02536 - A check is made that for each element of the operand there is a matching element of the target subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n03i02536arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2536.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n03i02536ent IS
END c07s03b05x00p13n03i02536ent;
ARCHITECTURE c07s03b05x00p13n03i02536arch OF c07s03b05x00p13n03i02536ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (1 to 6) ;
subtype T3 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T3 := (2,3,6) ;
BEGIN
V1 := T2 (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n03i02536 - A check is made that for each element of the operand there is a matching element of the target subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n03i02536arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2536.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n03i02536ent IS
END c07s03b05x00p13n03i02536ent;
ARCHITECTURE c07s03b05x00p13n03i02536arch OF c07s03b05x00p13n03i02536ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (1 to 6) ;
subtype T3 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T3 := (2,3,6) ;
BEGIN
V1 := T2 (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n03i02536 - A check is made that for each element of the operand there is a matching element of the target subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n03i02536arch;
|
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_slave is
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
spi_cs : in std_ulogic;
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
data : out std_ulogic_vector(7 downto 0);
data_is_id : out std_ulogic;
data_valid : out std_ulogic;
input_state : in std_ulogic;
input_state_valid : in std_ulogic;
cmd_done : in std_ulogic
);
end spi_slave;
architecture rtl of spi_slave is
type STATEMACHINE_BIT_STEP_TYPE is
(
SMB_IDLE, SMB_GET_DATA_BIT, SMB_WAIT_CLK_LOW
);
type STATEMACHINE_MAIN_STEP_TYPE is
(
SM_WAIT_CS_LOW, SM_GET_ID, SM_GET_DATA
);
type REG_TYPE is record
smb_step : STATEMACHINE_BIT_STEP_TYPE;
sm_step : STATEMACHINE_MAIN_STEP_TYPE;
spi_byte : std_ulogic_vector(7 downto 0);
spi_byte_done : std_ulogic;
bit_idx : natural;
input_state : std_ulogic;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
smb_step => SMB_IDLE,
sm_step => SM_WAIT_CS_LOW,
spi_byte => (others => '0'),
spi_byte_done => '0',
bit_idx => 0,
input_state => '0'
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R, spi_cs, spi_clk, spi_mosi, input_state, input_state_valid, cmd_done)
begin
NxR <= R;
NxR.spi_byte_done <= '0';
data <= (others => '0');
data_is_id <= '0';
data_valid <= '0';
case R.smb_step is
when SMB_GET_DATA_BIT =>
if(spi_clk = '1')then
NxR.smb_step <= SMB_WAIT_CLK_LOW;
NxR.spi_byte(R.bit_idx) <= spi_mosi;
end if;
when SMB_WAIT_CLK_LOW =>
if(spi_clk = '0')then
NxR.smb_step <= SMB_GET_DATA_BIT;
if(R.bit_idx = 0)then
NxR.smb_step <= SMB_IDLE;
NxR.bit_idx <= 7;
NxR.spi_byte_done <= '1';
else
NxR.bit_idx <= R.bit_idx - 1;
end if;
if(R.bit_idx = 1)then
spi_miso <= R.input_state;
else
spi_miso <= '0';
end if;
end if;
when others =>
NxR.smb_step <= SMB_IDLE;
NxR.bit_idx <= 7;
NxR.spi_byte_done <= '0';
end case;
case R.sm_step is
when SM_WAIT_CS_LOW =>
if(spi_cs = '0')then
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_ID;
end if;
when SM_GET_ID =>
if(R.spi_byte_done = '1')then
data <= R.spi_byte;
data_is_id <= '1';
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_DATA;
end if;
when SM_GET_DATA =>
if(R.spi_byte_done = '1')then
data <= R.spi_byte;
data_valid <= '1';
NxR.smb_step <= SMB_GET_DATA_BIT;
end if;
when others =>
NxR.sm_step <= SM_WAIT_CS_LOW;
end case;
if(input_state_valid = '1')then
NxR.input_state <= input_state;
end if;
if(cmd_done = '1')then
NxR.input_state <= '0';
NxR.smb_step <= SMB_GET_DATA_BIT;
NxR.sm_step <= SM_GET_ID;
end if;
if(spi_cs = '1')then
NxR.smb_step <= SMB_IDLE;
NxR.sm_step <= SM_WAIT_CS_LOW;
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_fall : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 63 := 0;
signal phase_l : integer range 0 to 63 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
constant c_sample : integer := 6;
constant c_probe_end : integer := 11;
constant c_sample_vic : integer := 10;
constant c_io : integer := 19;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
phi2_fall <= phi2_d and not phi2_c;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- if (phi2_rec_i='0' and allow_tick_h) or
-- (phi2_rec_i='1' and allow_tick_l) then
-- phi2_rec_i <= PHI2;
-- end if;
-- related to rising edge
-- if then -- rising edge
if ((edge_recover = '1') and (phase_l = 24)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 63 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 46 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 63 then
phase_l <= phase_l + 1;
end if;
if phase_l = 46 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
if phase_h = 0 then
inhibit <= serve_en_i;
elsif phase_h = c_sample then
inhibit <= '0';
end if;
do_sample_addr <= '0';
if phase_h = timing_addr then
do_sample_addr <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
if serve_vic='1' then
if phase_l = (c_sample_vic - c_memdelay) then
inhibit <= serve_en_i;
elsif phase_l = (c_sample_vic - 1) then
do_sample_addr <= '1';
end if;
end if;
if phase_l = c_sample_vic then
inhibit <= '0';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 63;
phase_l <= 63;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
|
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Fullrounds is
port(
Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4 : out std_logic_vector(63 downto 0));
end entity Fullrounds;
architecture structural of Fullrounds is
signal RoundNr_0, RoundNr_1, RoundNr_2 : std_logic_vector(3 downto 0);
signal SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4 : std_logic_vector(63 downto 0);
signal SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4 : std_logic_vector(63 downto 0);
signal SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4 : std_logic_vector(63 downto 0);
signal DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4 : std_logic_vector(63 downto 0);
signal DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4 : std_logic_vector(63 downto 0);
begin
-- declare and connect all sub entities
sbox1: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr_0,
SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4);
difflayer1: entity work.FullDiffusionLayer port map(SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4,
DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4);
sbox2: entity work.Sbox port map(DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4,RoundNr_1,
SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4);
difflayer2: entity work.FullDiffusionLayer port map(SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4,
DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4);
sbox3: entity work.Sbox port map(DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4,RoundNr_2,
SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4);
difflayer3: entity work.FullDiffusionLayer port map(SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4,
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4);
roundnrgen: process(RoundNr) is
variable RoundNrInt : std_logic_vector(3 downto 0);
begin
RoundNrInt := RoundNr;
RoundNr_0 <= RoundNrInt;
RoundNr_1 <= std_logic_vector(unsigned(RoundNrInt) + 1);
RoundNr_2 <= std_logic_vector(unsigned(RoundNrInt) + 2);
end process;
end architecture structural;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_mmc of tb_elem is
for behav
for dut_b : chip
use configuration work.chip_mmc_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
end for;
end tb_elem_behav_mmc;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_REQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_req is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end arp_req;
architecture Behavioral of arp_req is
type req_state_t is (IDLE, LOOKUP, WAIT_REPLY, PAUSE1, PAUSE2, PAUSE3);
type set_cntr_t is (HOLD, CLR, INCR);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
signal l_arp_req_req_ip : std_logic_vector(31 downto 0); -- local network IP address for resolution
begin
default_GW: if (not no_default_gateway) generate
default_gw_comb_p: process (arp_req_req.ip, nwk_gateway, nwk_mask) is
begin -- process default_gw_comb_p
-- translate IP addresses to local IP address if necessary
if ((nwk_mask and arp_req_req.ip) = (nwk_mask and nwk_gateway)) then
-- on local network
l_arp_req_req_ip <= arp_req_req.ip;
else
-- on remote network
l_arp_req_req_ip <= nwk_gateway;
end if;
end process default_gw_comb_p;
end generate default_GW;
no_default_GW: if (no_default_gateway) generate
no_default_gw_comb_p: process (arp_req_req.ip) is
begin -- process no_default_gw_comb_p
l_arp_req_req_ip <= arp_req_req.ip;
end process no_default_gw_comb_p;
end generate no_default_GW;
req_combinatorial : process (
arp_entry_cache.ip, arp_entry_cache.mac, arp_nwk_result.entry, arp_nwk_result.entry.ip,
arp_nwk_result.entry.mac, arp_nwk_result.status, arp_req_req.lookup_req,
arp_store_result.entry, arp_store_result.entry.mac, arp_store_result.status, cache_valid,
clear_cache, freq_scaler, l_arp_req_req_ip, nwk_rx_cntr, req_ip_addr, req_state,
timeout_reg, timer)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when others =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
if arp_nwk_result.entry.ip = req_ip_addr then
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
when error =>
set_timeout <= SET;
when others =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= l_arp_req_req_ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_REQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_req is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end arp_req;
architecture Behavioral of arp_req is
type req_state_t is (IDLE, LOOKUP, WAIT_REPLY, PAUSE1, PAUSE2, PAUSE3);
type set_cntr_t is (HOLD, CLR, INCR);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
signal l_arp_req_req_ip : std_logic_vector(31 downto 0); -- local network IP address for resolution
begin
default_GW: if (not no_default_gateway) generate
default_gw_comb_p: process (arp_req_req.ip, nwk_gateway, nwk_mask) is
begin -- process default_gw_comb_p
-- translate IP addresses to local IP address if necessary
if ((nwk_mask and arp_req_req.ip) = (nwk_mask and nwk_gateway)) then
-- on local network
l_arp_req_req_ip <= arp_req_req.ip;
else
-- on remote network
l_arp_req_req_ip <= nwk_gateway;
end if;
end process default_gw_comb_p;
end generate default_GW;
no_default_GW: if (no_default_gateway) generate
no_default_gw_comb_p: process (arp_req_req.ip) is
begin -- process no_default_gw_comb_p
l_arp_req_req_ip <= arp_req_req.ip;
end process no_default_gw_comb_p;
end generate no_default_GW;
req_combinatorial : process (
arp_entry_cache.ip, arp_entry_cache.mac, arp_nwk_result.entry, arp_nwk_result.entry.ip,
arp_nwk_result.entry.mac, arp_nwk_result.status, arp_req_req.lookup_req,
arp_store_result.entry, arp_store_result.entry.mac, arp_store_result.status, cache_valid,
clear_cache, freq_scaler, l_arp_req_req_ip, nwk_rx_cntr, req_ip_addr, req_state,
timeout_reg, timer)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when others =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
if arp_nwk_result.entry.ip = req_ip_addr then
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
when error =>
set_timeout <= SET;
when others =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= l_arp_req_req_ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:20 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_stub.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "lms_pcore,Vivado 2017.3";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_521 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_521;
architecture augh of sub_521 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_521 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_521;
architecture augh of sub_521 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14000)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: vmm_readout.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_readout is
Port (
vmm_data0 : in std_logic; -- Single-ended data0 from VMM
vmm_data1 : in std_logic; -- Single-ended data1 from VMM
clk_10_phase45 : in std_logic; -- Used to clock checking for data process
clk_50 : in std_logic; -- Used to clock word readout process
clk_200 : in std_logic; -- Used for fast ILA signal sampling
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- To be used trigger
ethernet_fifo_wr_en : out std_logic; -- To be used to for ethernet to software readout
latency : in std_logic_vector(15 downto 0);
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
vmm_cktk : out std_logic; -- Strobe to VMM CKTK
acq_rst_from_data0 : out std_logic; -- Send a soft reset when done
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmm_wen : out std_logic;
vmm_ena : out std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(63 downto 0);
vmmEventDone : out std_logic
);
end vmm_readout;
architecture Behavioral of vmm_readout is
-- readoutControlProc
signal reading_out_word : std_logic := '0';
-- tokenProc
signal dt_state : std_logic_vector( 3 DOWNTO 0 ) := ( others => '0' );
signal vmm_wen_1_i : std_logic := '0';
signal vmm_ena_1_i : std_logic := '0';
signal vmm_cktk_1_i : std_logic := '0';
signal ethernet_fifo_wr_en_i: std_logic := '0'; -- Not used
-- signal trig_latency_counter : std_logic_vector( 15 DOWNTO 0 ) := ( others => '0' );
-- signal trig_latency : std_logic_vector( 15 DOWNTO 0 ) := x"008C"; -- x"008C"; 700ns @200MHz (User defined)
signal latency_i : integer := 7;
signal latencyCnt : integer := 0;
signal NoFlg_counter : integer := 0; -- Counter of CKTKs
signal NoFlg : integer := 2; -- How many (#+1) CKTKs before soft reset (User defined)
signal vmmEventDone_i : std_logic := '0';
signal trigger_pulse_i : std_logic := '0';
signal hitsLen_cnt : integer := 0;
signal hitsLenMax : integer := 150;
-- readoutProc
signal dt_done : std_logic := '1';
signal vmm_data_buf_i : std_logic_vector( 37 DOWNTO 0 ) := ( others => '0' );
signal dt_cntr_intg : integer := 0;
signal dt_cntr_intg0 : integer := 0;
signal dt_cntr_intg1 : integer := 0;
signal vmm_ckdt_1_i : std_logic;
signal dataBitRead : integer := 0;
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 DOWNTO 0);
-- Internal signal direct assign from ports
signal vmm_data0_i : std_logic := '0';
signal vmm_data1_i : std_logic := '0';
signal daq_enable_i : std_logic := '0';
begin
readoutControlProc: process(clk_200, daq_enable_i, dt_done, vmm_data0_i)
begin
if (dt_done = '1') then
reading_out_word <= '0'; -- readoutProc done, stop it
end if;
if (vmm_data0_i = '1') then
reading_out_word <= '1'; -- new data, trigger readoutProc
end if;
end process;
-- by using this clock the CKTK strobe has f=5MHz (T=200ns, D=50%, phase=45deg)
tokenProc: process(clk_10_phase45, daq_enable_i, dt_done, vmm_data0_i, trigger_pulse)
begin
if (rising_edge(clk_10_phase45)) then
if (daq_enable_i = '1') then
case dt_state is
when x"0" =>
vmmEventDone_i <= '0';
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '1';
latencyCnt <= 0;
if (trigger_pulse_i = '1') then
vmm_cktk_1_i <= '0';
ethernet_fifo_wr_en_i <= '0';
dt_state <= x"1";
end if;
when x"1" =>
if (latencyCnt = latency_i) then
dt_state <= x"2";
else
latencyCnt <= latencyCnt + 1;
end if;
when x"2" =>
vmm_cktk_1_i <= '0';
dt_state <= x"3";
when x"3" =>
if (reading_out_word /= '1') then
vmm_cktk_1_i <= '1';
hitsLen_cnt <= hitsLen_cnt + 1;
dt_state <= x"4";
else
NoFlg_counter <= 0;
dt_state <= x"6";
end if;
when x"4" =>
vmm_cktk_1_i <= '0';
dt_state <= x"5";
when x"5" =>
if (vmm_data0_i = '1') then -- Data presence: wait to read out
NoFlg_counter <= 0;
dt_state <= x"6";
else
if (NoFlg_counter = NoFlg) then
dt_state <= x"7"; -- If NoFlg = 4 : time to soft reset and transmit data
else
dt_state <= x"3"; -- Send new CKTK strobe
end if;
NoFlg_counter <= NoFlg_counter + 1;
end if;
when x"6" => -- Wait until word readout is done
if (dt_done = '1') then
if hitsLen_cnt >= hitsLenMax then -- Maximum UDP packet length reached
dt_state <= x"7";
else
dt_state <= x"3"; -- Issue new CKTK strobe
end if;
end if;
when x"7" => -- Start the soft reset sequence, there is still a chance
if (reading_out_word /= '1') then -- of getting data at this point so check that before soft reset
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '0';
dt_state <= x"8";
else
NoFlg_counter <= 0;
dt_state <= x"6";
end if;
when x"8" =>
vmm_wen_1_i <= '1';
vmm_ena_1_i <= '0';
hitsLen_cnt <= 0;
dt_state <= x"9";
when others =>
vmmEventDone_i <= '1';
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '0';
NoFlg_counter <= 0;
ethernet_fifo_wr_en_i <= '1';
dt_state <= x"0";
end case;
else
vmm_ena_1_i <= '0';
vmm_wen_1_i <= '0';
end if;
end if;
end process;
-- by using this clock the CKDT strobe has f=25MHz (T=40ns, D=50%, phase=0deg) to click in data0 and data1
readoutProc: process(clk_50, reading_out_word)
begin
if rising_edge(clk_50) then
if (reading_out_word = '1') then
case dt_cntr_intg is
when 0 => -- Initiate values
dt_done <= '0';
vmm_data_buf <= (others => '0');
dt_cntr_intg <= dt_cntr_intg + 1;
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
vmm_ckdt_1_i <= '0'; -- Go for the first ckdt
when 1 =>
vmm_ckdt_1_i <= '1';
dt_cntr_intg <= dt_cntr_intg + 1;
when 2 => -- 19 ckdt and collect data
vmm_ckdt_1_i <= '0';
if (dataBitRead /= 19) then
vmm_data_buf(dt_cntr_intg0) <= vmm_data0;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1;
vmm_data_buf_i <= vmm_data_buf;
dt_cntr_intg <= 1;
dataBitRead <= dataBitRead + 1;
else
vmm_data_buf(dt_cntr_intg0) <= vmm_data0;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1;
vmm_data_buf_i <= vmm_data_buf;
dataBitRead <= 1;
dt_cntr_intg <= 3;
end if;
dt_cntr_intg0 <= dt_cntr_intg0 + 2;
dt_cntr_intg1 <= dt_cntr_intg1 + 2;
when 3 =>
vmmWordReady_i <= '0';
-- daqFIFO_din_i <= b"000" & b"111" & vmm_data_buf(25 downto 0) & b"0000" & b"1010101010101010" & vmm_data_buf(37 downto 26);
vmmWord_i <= b"00" & vmm_data_buf(25 downto 18) & vmm_data_buf(37 downto 26) & vmm_data_buf(17 downto 8) & b"000000000000000000000000" & vmm_data_buf(7 downto 2) & vmm_data_buf(1) & vmm_data_buf(0);
-- TDO & Gray & PDO & & Address & Threshold & Flag;
dt_cntr_intg <= dt_cntr_intg + 1;
when 4 =>
vmmWordReady_i <= '1';
dt_cntr_intg <= dt_cntr_intg + 1;
when others => -- Word read
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
dt_cntr_intg <= 0;
vmmWordReady_i <= '0';
dt_done <= '1';
end case;
else
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
dt_cntr_intg <= 0;
end if;
end if;
end process;
vmm_cktk <= vmm_cktk_1_i; -- Used
vmm_ckdt <= vmm_ckdt_1_i; -- Used
vmm_wen <= vmm_wen_1_i; -- Used
vmm_ena <= vmm_ena_1_i; -- Used
daq_enable_i <= daq_enable; -- Used
vmm_data0_i <= vmm_data0; -- Used
vmm_data1_i <= vmm_data1; -- Used
vmmWordReady <= vmmWordReady_i; -- Used
vmmWord <= vmmWord_i; -- Used
vmmEventDone <= vmmEventDone_i; -- Used
trigger_pulse_i <= trigger_pulse; -- Used
latency_i <= to_integer(unsigned(latency));
end behavioral; |
library ieee;
use ieee.std_logic_1164.all;
entity asgn08 is
port (clk : std_logic;
ce : std_logic;
s0 : std_logic;
r : out std_logic_vector (65 downto 0));
end asgn08;
architecture behav of asgn08 is
begin
r (0) <= '1';
process (clk) is
begin
if rising_edge(clk) and ce = '1' then
if s0 = '1' then
r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
r (65) <= '1';
else
r (8 downto 5) <= x"7";
r (65) <= '0';
end if;
end if;
end process;
end behav;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myAnd2;
architecture behavioral of myAnd2 is
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal nandOut: std_logic;
begin
myNand2_1: myNand2 port map(a => a, b => b, s => nandOut);
myNot_1: myNot port map(a => nandOut, s => s);
end behavioral;
|
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package;
|
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package;
|
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package;
|
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_expand is
end test_expand;
architecture behavior of test_expand is
--component declaration of the unit under test
signal data_in: std_logic_vector(0 to 31);
signal data_out: std_logic_vector(0 to 47);
begin
uut:entity expand port map(data_in,data_out);
testprocess: process is
begin
data_in<="11110000101010101111000010101010";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := inferred;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
end package;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := inferred;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
end package;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_20_07 is
end entity ch_20_07;
----------------------------------------------------------------
architecture test of ch_20_07 is
component multiplier is
end component multiplier;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
type orientation_type is (up, down, left, right);
attribute cell_allocation : string;
attribute cell_position : coordinate;
attribute cell_orientation : orientation_type;
-- code from book:
attribute cell_allocation of mult : label is "wallace_tree_multiplier";
attribute cell_position of mult : label is ( 1200 um, 4500 um );
attribute cell_orientation of mult : label is down;
-- end of code from book
begin
mult : component multiplier;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_20_07 is
end entity ch_20_07;
----------------------------------------------------------------
architecture test of ch_20_07 is
component multiplier is
end component multiplier;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
type orientation_type is (up, down, left, right);
attribute cell_allocation : string;
attribute cell_position : coordinate;
attribute cell_orientation : orientation_type;
-- code from book:
attribute cell_allocation of mult : label is "wallace_tree_multiplier";
attribute cell_position of mult : label is ( 1200 um, 4500 um );
attribute cell_orientation of mult : label is down;
-- end of code from book
begin
mult : component multiplier;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_20_07 is
end entity ch_20_07;
----------------------------------------------------------------
architecture test of ch_20_07 is
component multiplier is
end component multiplier;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
type orientation_type is (up, down, left, right);
attribute cell_allocation : string;
attribute cell_position : coordinate;
attribute cell_orientation : orientation_type;
-- code from book:
attribute cell_allocation of mult : label is "wallace_tree_multiplier";
attribute cell_position of mult : label is ( 1200 um, 4500 um );
attribute cell_orientation of mult : label is down;
-- end of code from book
begin
mult : component multiplier;
end architecture test;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionMemory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instructionMemory_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instructionMemory_synth_ARCH OF instructionMemory_synth IS
COMPONENT instructionMemory_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
ENA => ENA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
ADDRA_SHIFT(31 DOWNTO 2) <= ADDRA(29 DOWNTO 0) ;
ADDRA_SHIFT(1 DOWNTO 0) <= (OTHERS=> '0' );
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_SHIFT_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ADDRA_SHIFT_R <= ADDRA_SHIFT AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instructionMemory_exdes PORT MAP (
--Port A
ENA => ENA_R,
ADDRA => ADDRA_SHIFT_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_GAUSS_COE_tb_synth;
ARCHITECTURE ROM_GAUSS_COE_synth_ARCH OF ROM_GAUSS_COE_tb_synth IS
COMPONENT ROM_GAUSS_COE_exdes
PORT (
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL WE : STD_LOGIC:='0';
SIGNAL WE_R : STD_LOGIC:='0';
SIGNAL SPO: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL D: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_R: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_EN: STD_LOGIC:='0';
SIGNAL CHECKER_EN_R: STD_LOGIC:='0';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_GAUSS_COE_TB_STIM_GEN_INST:ENTITY work.ROM_GAUSS_COE_TB_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
D => D,
WE => WE,
DATA_IN => SPO_R,
CHECK_DATA => CHECKER_EN
);
DMG_DATA_CHECKER_INST: ENTITY work.ROM_GAUSS_COE_TB_CHECKER
GENERIC MAP (
WRITE_WIDTH => 135,
READ_WIDTH => 135 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WE_R <= '0' AFTER 50 ns;
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
D_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WE_R <= WE AFTER 50 ns;
SPO_R <= SPO AFTER 50 ns;
D_R <= D AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_GAUSS_COE_exdes PORT MAP (
CLK => CLKA,
WE => WE_R,
SPO => SPO,
A => ADDR_R,
D => D_R
);
END ARCHITECTURE;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_generic_queue_pkg is
generic (type t_generic_element;
scope : string := C_SCOPE;
GC_QUEUE_COUNT_MAX : natural := 1000;
GC_QUEUE_COUNT_THRESHOLD : natural := 950);
-- When find_* doesn't find a match, they return C_NO_MATCH.
constant C_NO_MATCH : integer := -1;
-- A generic queue for verification
type t_generic_queue is protected
procedure add(
constant instance : in integer;
constant element : in t_generic_element);
procedure add(
constant element : in t_generic_element);
procedure put(
constant instance : in integer;
constant element : in t_generic_element);
procedure put(
constant element : in t_generic_element);
impure function get(
constant instance : in integer)
return t_generic_element;
impure function get(
constant dummy : in t_void)
return t_generic_element;
impure function is_empty(
constant instance : in integer)
return boolean;
impure function is_empty(
constant dummy : in t_void)
return boolean;
procedure set_scope(
constant instance : in integer;
constant scope : in string);
procedure set_scope(
constant scope : in string);
procedure set_name(
constant name : in string);
impure function get_scope(
constant instance : in integer)
return string;
impure function get_scope(
constant dummy : in t_void)
return string;
impure function get_count(
constant instance : in integer)
return natural;
impure function get_count(
constant dummy : in t_void)
return natural;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural);
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural);
impure function get_queue_count_threshold(
constant instance : in integer) return natural;
impure function get_queue_count_threshold(
constant dummy : in t_void) return natural;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void) return t_alert_level;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level);
impure function get_queue_count_max(
constant instance : in integer) return natural;
impure function get_queue_count_max(
constant dummy : in t_void) return natural;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural);
procedure set_queue_count_max(
constant queue_count_max : in natural);
procedure flush(
constant instance : in integer);
procedure flush(
constant dummy : in t_void);
procedure reset(
constant instance : in integer);
procedure reset(
constant dummy : in t_void);
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
);
procedure delete(
constant element : in t_generic_element
);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant instance : in integer
) return t_generic_element;
impure function peek(
constant dummy : in t_void
) return t_generic_element;
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant instance : in integer
) return t_generic_element;
impure function fetch(
constant dummy : in t_void
) return t_generic_element;
impure function find_position(
constant element : in t_generic_element) return integer;
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean;
impure function exists(
constant element : in t_generic_element
) return boolean;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive) return integer;
impure function get_entry_num(
constant position_val : in positive) return integer;
procedure print_queue(
constant instance : in integer);
procedure print_queue(
constant dummy : in t_void);
end protected;
end package ti_generic_queue_pkg;
package body ti_generic_queue_pkg is
type t_generic_queue is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is
record
entry_num : natural;
next_element : t_element_ptr;
element_data : t_generic_element;
end record;
type t_element_ptr_array is array(integer range 1 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr;
type t_string_array is array(integer range 1 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH);
variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry
variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry
variable vr_num_elements_in_queue : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0);
-- Scope variables
variable vr_scope : t_string_array := (others => (others => NUL));
variable vr_scope_is_defined : boolean_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
-- Name variables
variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL);
variable vr_name_is_defined : boolean := false;
variable vr_queue_count_max : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX);
variable vr_queue_count_threshold : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD);
variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING;
variable vr_entry_num : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert
-- Fill level alert
type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY);
constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY;
variable vr_queue_count_threshold_triggered : boolean_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
------------------------------------------------------------------------------------------------------
--
-- Helper methods (not visible from outside)
--
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- Helper method: Check if an Alert shall be triggered (to be called before adding another entry)
------------------------------------------------------------------------------------------------------
procedure perform_pre_add_checks (
constant instance : in integer
) is
begin
if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then
if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then
alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance));
vr_queue_count_threshold_triggered(instance) := true;
end if;
end if;
end procedure;
------------------------------------------------------------------------------------------------------
-- Helper method: Iterate through all entries, and match the one with element_data = element
-- This also works if the element is a record or array, whereas all entries/indexes must match
------------------------------------------------------------------------------------------------------
procedure match_element_data (
instance : in integer; -- Queue instance
element : in t_generic_element; -- Element to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr -- valid if found_match=true
) is
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
if vr_num_elements_in_queue(instance) > 0 then
-- Search from front to back element
v_element_ptr := vr_first_element(instance);
loop
if v_element_ptr.element_data = element then -- Element matched entry
found_match := true;
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else -- No match.
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop;
end if;
end procedure;
-- Find and return entry that matches the identifier
procedure match_identifier (
instance : in integer; -- Queue instance
identifier_option : in t_identifier_option; -- Determines what 'identifier' means
identifier : in positive; -- Identifier value to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr; -- valid if found_match=true
preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr
) is
-- Search from front to back element. Init pointers/counters to the first entry:
variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
preceding_element_ptr := null;
-- If queue is not empty and indentifier in valid range
if (vr_num_elements_in_queue(instance) > 0) and
((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or
(identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then
loop
-- For each element in queue:
-- Check if POSITION or ENTRY_NUM matches v_element_ptr
if (identifier_option = POSITION) and (v_position_ctr = identifier) then
found_match := true;
end if;
if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then
found_match := true;
end if;
if found_match then
-- This element matched. Done searching.
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else
-- No match.
if v_element_ptr.next_element = null then
-- report "last v_position_ctr = " & to_string(v_position_ctr);
exit; -- Last entry. All queue entries have been searched through.
end if;
preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop; -- for each element in queue
end if; -- Not empty
end procedure;
------------------------------------------------------------------------------------------------------
--
-- Public methods, visible from outside
--
------------------------------------------------------------------------------------------------------
-- add : Insert element in the back of queue, i.e. at the highest position
procedure add(
constant instance : in integer;
constant element : in t_generic_element
) is
constant proc_name : string := "add";
variable v_previous_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
-- Increment vr_entry_num
vr_entry_num(instance) := vr_entry_num(instance)+1;
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_queue(instance) > 0 then
v_previous_ptr := vr_last_element(instance);
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list
else -- List is empty
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list.
end if;
-- Increment number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1;
end procedure;
procedure add(
constant element : in t_generic_element
) is
begin
add(1, element);
end procedure;
procedure put(
constant instance : in integer;
constant element : in t_generic_element
) is
begin
add(instance, element);
end procedure;
procedure put(
constant element : in t_generic_element
) is
begin
put(1, element);
end procedure;
impure function get(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance);
end function;
impure function get(
constant dummy : in t_void
) return t_generic_element is
begin
return get(1);
end function;
procedure flush(
constant instance : in integer
) is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue", "???", ID_NEVER);
-- Deallocate all entries in the list
-- Setting the last element to null and iterating over the queue until finding the null element
vr_last_element(instance) := null;
while vr_first_element(instance) /= null loop
v_to_be_deallocated_ptr := vr_first_element(instance);
vr_first_element(instance) := vr_first_element(instance).next_element;
DEALLOCATE(v_to_be_deallocated_ptr);
end loop;
-- Reset the queue counter
vr_num_elements_in_queue(instance) := 0;
vr_queue_count_threshold_triggered(instance) := false;
end procedure;
procedure flush(
constant dummy : in t_void
) is
begin
flush(1);
end procedure;
procedure reset(
constant instance : in integer) is
begin
flush(instance);
vr_entry_num(instance) := 0; -- Incremented before first insert
end procedure;
procedure reset(
constant dummy : in t_void) is
begin
reset(1);
end procedure;
impure function is_empty(
constant instance : in integer
) return boolean is
begin
if vr_num_elements_in_queue(instance) = 0 then
return true;
else
return false;
end if;
end function;
impure function is_empty(
constant dummy : in t_void
) return boolean is
begin
return is_empty(1);
end function;
procedure set_scope(
constant instance : in integer;
constant scope : in string) is
begin
if instance = ALL_INSTANCES then
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH));
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined := (others => true);
else
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH);
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined(instance) := true;
end if;
end procedure;
procedure set_scope(
constant scope : in string) is
begin
set_scope(1, scope);
end procedure;
procedure set_name(
constant name : in string) is
begin
vr_name(1 to name'length) := name;
vr_name_is_defined := true;
end procedure;
impure function get_scope(
constant instance : in integer
) return string is
begin
return to_string(vr_scope(instance));
end function;
impure function get_scope(
constant dummy : in t_void
) return string is
begin
return get_scope(1);
end function;
impure function get_count(
constant instance : in integer
) return natural is
begin
return vr_num_elements_in_queue(instance);
end function;
impure function get_count(
constant dummy : in t_void
) return natural is
begin
return get_count(1);
end function;
impure function get_queue_count_max(
constant instance : in integer
) return natural is
begin
return vr_queue_count_max(instance);
end function;
impure function get_queue_count_max(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_max(1);
end function;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural
) is
begin
vr_queue_count_max(instance) := queue_count_max;
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER);
end procedure;
procedure set_queue_count_max(
constant queue_count_max : in natural
) is
begin
set_queue_count_max(1, queue_count_max);
end procedure;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural
) is
begin
vr_queue_count_threshold(instance) := queue_count_alert_level;
end procedure;
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural
) is
begin
set_queue_count_threshold(1, queue_count_alert_level);
end procedure;
impure function get_queue_count_threshold(
constant instance : in integer
) return natural is
begin
return vr_queue_count_threshold(instance);
end function;
impure function get_queue_count_threshold(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_threshold(1);
end function;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void
) return t_alert_level is
begin
return vr_queue_count_threshold_severity;
end function;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level) is
begin
vr_queue_count_threshold_severity := alert_level;
end procedure;
----------------------------------------------------
-- Insert:
----------------------------------------------------
-- Inserts element into the queue after the matching entry with specified identifier:
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element)
is
constant proc_name : string := "insert";
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_found_match : boolean;
variable v_matched_position : integer;
begin
-- pre insert checks
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER);
if identifier_option = POSITION then
check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER);
end if;
-- Search from front to back element.
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Make new element
vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num
-- POSITION: insert at matched position
if identifier_option = POSITION then
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr,
element_data => element);
-- if match is first element
if v_preceding_element_ptr = null then
vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list
else
v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
--ENTRY_NUM: insert at position after match
else
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr.next_element,
element_data => element);
v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements
elsif identifier_option = ENTRY_NUM then
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier) &
", element...", scope);
end if;
end if;
end procedure;
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element) is
begin
insert(1, identifier_option, identifier, element);
end procedure;
----------------------------------------------------
-- delete:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
constant proc_name : string := "delete";
variable v_matched_element_ptr : t_element_ptr; -- The element being deleted
variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
variable v_deletes_remaining : integer;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
-- delete based on POSITION :
-- Note that when deleting the first position, all above positions are decremented by one.
-- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- Find min position
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier_min,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first
while v_deletes_remaining > 0 loop
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
v_deletes_remaining := v_deletes_remaining - 1;
-- Prepare next iteration:
-- Next element to delete:
if v_deletes_remaining > 0 then
if (v_preceding_element_ptr = null) then
-- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry.
v_element_to_delete_ptr := vr_first_element(instance);
else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element
v_element_to_delete_ptr := v_preceding_element_ptr.next_element;
end if;
end if;
end loop;
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier_min), scope);
end if;
end if; -- v_found_match
-- delete based on ENTRY_NUM :
-- Unlike position, an entry's Entry_num is stable when deleting other entries
-- Entry_num is not necessarily increasing as we follow next_element pointers.
-- This means that we must do a complete search for each entry we want to delete
elsif (identifier_option = ENTRY_NUM) then
check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- For each entry to delete, find it based on entry_num , then delete it
for identifier in identifier_min to identifier_max loop
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier), scope);
end if;
end if; -- v_found_match
end loop;
end if; -- identifier_option
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
begin
delete(1, identifier_option, identifier_min, identifier_max);
end procedure;
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
) is
variable v_entry_num : integer:= find_entry_num(element);
begin
delete(instance, POSITION, v_entry_num, v_entry_num);
end procedure;
procedure delete(
constant element : in t_generic_element
) is
begin
delete(1, element);
end procedure;
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
case range_option is
when SINGLE =>
delete(instance, identifier_option, identifier, identifier);
when AND_LOWER =>
delete(instance, identifier_option, 1, identifier);
when AND_HIGHER =>
if identifier_option = POSITION then
delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance));
elsif identifier_option = ENTRY_NUM then
delete(instance, identifier_option, identifier, vr_entry_num(instance));
end if;
end case;
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
delete(1, identifier_option, identifier, range_option);
end procedure;
----------------------------------------------------
-- peek:
----------------------------------------------------
-- Read the entry matching the identifier, but don't remove it.
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "peek";
variable v_matched_element_data : t_generic_element; -- Return value
variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_matched_element_data := v_matched_element_ptr.element_data;
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return peek(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function peek(
constant instance : in integer
) return t_generic_element is
begin
return peek(instance, POSITION, 1);
end function;
impure function peek(
constant dummy : in t_void
) return t_generic_element is
begin
return peek(1);
end function;
----------------------------------------------------
-- Fetch:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "fetch";
variable v_matched_element_ptr : t_element_ptr; -- The element being fetched
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Keep info about element before removing it from queue
v_matched_element_data := v_matched_element_ptr.element_data;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_matched_element_ptr);
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return fetch(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function fetch(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance, POSITION, 1);
end function;
impure function fetch(
constant dummy : in t_void
) return t_generic_element is
begin
return fetch(1);
end function;
-- Returns position of entry if found, else C_NO_MATCH.
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element --
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
-- Don't include this check, because we may want to use exists() on an empty queue.
-- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_matched_position;
else
return C_NO_MATCH;
end if;
end function;
impure function find_position(
constant element : in t_generic_element
) return integer is
begin
return find_position(1, element);
end function;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean is
begin
return (find_position(instance, element) /= C_NO_MATCH);
end function;
impure function exists(
constant element : in t_generic_element
) return boolean is
begin
return exists(1, element);
end function;
-- Returns entry number or position to entry if found, else C_NO_MATCH.
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_element_ptr.entry_num;
else
return C_NO_MATCH;
end if;
end function;
impure function find_entry_num(
constant element : in t_generic_element
) return integer is
begin
return find_entry_num(1, element);
end function;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive
) return integer is
variable v_found_match : boolean;
variable v_matched_position : integer;
variable v_matched_element_ptr : t_element_ptr;
variable v_preceding_element_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => POSITION ,
identifier => position_val,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
return v_matched_element_ptr.entry_num;
else
return -1;
end if;
end function get_entry_num;
impure function get_entry_num(
constant position_val : in positive
) return integer is
begin
return get_entry_num(1, position_val);
end function get_entry_num;
-- for debugging:
-- print each entry's position and entry_num
procedure print_queue(
constant instance : in integer
)
is
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
-- Search from front to back element. Initalise pointers/counters to the first entry:
v_element_ptr := vr_first_element(instance);
loop
log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope);
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end loop;
end procedure;
procedure print_queue(
constant dummy : in t_void) is
begin
print_queue(1);
end procedure;
end protected body;
end package body ti_generic_queue_pkg;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 1K program for KCPSM6 in a 7-Series device using a
RAMB18E1 primitive.
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 1K program for KCPSM6 in a 7-Series device using a
-- RAMB18E1 primitive.
--
-- Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
-- expansion with minimum changes being required to the hardware description.
-- Only the lower 10-bits of the address are actually used for the 1K address range
-- 000 to 3FF hex.
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_1K_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(13 downto 0);
signal data_in_a : std_logic_vector(17 downto 0);
signal data_out_a : std_logic_vector(17 downto 0);
signal address_b : std_logic_vector(13 downto 0);
signal data_in_b : std_logic_vector(17 downto 0);
signal data_out_b : std_logic_vector(17 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(3 downto 0);
--
begin
--
address_a <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a <= "0000000000000000" & address(11 downto 10);
--
address_b <= "11111111111111";
data_in_b <= data_out_b(17 downto 0);
enable_b <= '0';
we_b <= "0000";
clk_b <= '0';
--
--
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
;
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
;
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\PC_Incrementer.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: PC_Incrementer
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/PC Incrementer
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY PC_Incrementer IS
PORT( jmp_offset : IN std_logic_vector(7 DOWNTO 0); -- int8
PC_current : IN std_logic_vector(7 DOWNTO 0); -- uint8
PC_next : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END PC_Incrementer;
ARCHITECTURE rtl OF PC_Incrementer IS
-- Signals
SIGNAL jmp_offset_signed : signed(7 DOWNTO 0); -- int8
SIGNAL PC_current_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL PC_next_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL add_cast : signed(8 DOWNTO 0); -- sfix9
SIGNAL add_temp : signed(8 DOWNTO 0); -- sfix9
BEGIN
jmp_offset_signed <= signed(jmp_offset);
PC_current_unsigned <= unsigned(PC_current);
--MATLAB Function 'CPU_Subsystem_8_bit/PC Incrementer': '<S9>:1'
-- PC incrementer increments the PC with jmp_offset
-- HDL specific fimath
--'<S9>:1:12'
add_cast <= signed(resize(PC_current_unsigned, 9));
add_temp <= resize(jmp_offset_signed, 9) + add_cast;
PC_next_tmp <= unsigned(add_temp(7 DOWNTO 0));
PC_next <= std_logic_vector(PC_next_tmp);
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetFSM is
port( xin : in std_logic;
yout : out std_logic;
clk : in std_logic
);
end SeqDetFSM;
architecture MealyArch of SeqDetFSM is
type Tstate is (S0, S1, S2, S3);
signal pState, nState : Tstate;
begin
clkproc: process(clk)
begin
if(rising_edge(clk)) then
pState <= nState;
end if;
end process;
combProcess: process(xin, pState)
begin
yout <= '0';
case pState is
when S0=>
if(xin='1') then
nState <= S1;
else
nState <= S0;
end if;
when S1=>
if(xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S2=>
if(xin='1') then
nState <= S3;
else
nState <= S0;
end if;
when S3=>
if(xin='1') then
nState <= S1;
yout <= '1';
else
nState <= S2;
end if;
when others =>
nState <= S0;
end case;
end process;
end MealyArch;
architecture MooreArch of SeqDetFSM is
type Tstate is (S0, S1, S2, S3, S4, S5);
signal pState, nState : Tstate;
begin
clkproc: process(clk)
begin
if(rising_edge(clk)) then
pState <= nState;
end if;
end process;
combProcess: process(xin, pState)
begin
yout <= '0';
case pState is
when S0=>
if(Xin='1') then
nState <= S1;
else
nState <= S5;
end if;
when S1 =>
if(Xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S2 =>
if(Xin='1') then
nState <= S3;
else
nState <= S5;
end if;
when S3 =>
if(Xin='1') then
nState <= S4;
else
nState <= S2;
end if;
when S4 =>
yout <= '1';
if(Xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S5 =>
if(Xin='1') then
nState <= S1;
else
nState <= S5;
end if;
when others =>
nState <= S0;
end case;
end process;
end MooreArch; |
library ieee;
use ieee.std_logic_1164.all;
entity ent is end entity;
architecture a of ent is
begin
process is
alias logic is std_ulogic;
function fun return string is
variable v : std_ulogic_vector(0 to 3);
begin
if ( v = x"7" ) then return "was 7";
else return "not 7"; end if;
end function;
begin
report "yo: " & fun; wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is end entity;
architecture a of ent is
begin
process is
alias logic is std_ulogic;
function fun return string is
variable v : std_ulogic_vector(0 to 3);
begin
if ( v = x"7" ) then return "was 7";
else return "not 7"; end if;
end function;
begin
report "yo: " & fun; wait;
end process;
end architecture;
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_incr_counter
--=================================================================================================
entity wf_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity wf_incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sparcv8_v6_monociclo_tb IS
END sparcv8_v6_monociclo_tb;
ARCHITECTURE behavior OF sparcv8_v6_monociclo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sparcv8_v6_monociclo
PORT(
clk : IN std_logic;
reset : IN std_logic;
alurs : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal alurs : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sparcv8_v6_monociclo PORT MAP (
clk => clk,
reset => reset,
alurs => alurs
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait;
end process;
END;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => W_0,
W_0init => 7.635e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcm_1,
Wcm_1init => 4.67e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcmout_1,
Wcmout_1init => 4.975e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_timerA.vhd
--!
--! @brief fpgaMSP430 Timer A top-level
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_timerA is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
aclk_en : in std_logic; --! ACLK enable (from CPU)
smclk_en : in std_logic; --! SMCLK enable (from CPU)
dbg_freeze : in std_logic; --! Freeze Timer A counter
inclk : in std_logic; --! INCLK external timer clock (SLOW)
irq_ta0_acc : in std_logic; --! Interrupt request TACCR0 accepted
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
ta_cci0a : in std_logic; --! Timer A capture 0 input A
ta_cci0b : in std_logic; --! Timer A capture 0 input B
ta_cci1a : in std_logic; --! Timer A capture 1 input A
ta_cci1b : in std_logic; --! Timer A capture 1 input B
ta_cci2a : in std_logic; --! Timer A capture 2 input A
ta_cci2b : in std_logic; --! Timer A capture 2 input B
taclk : in std_logic; --! TACLK external timer clock (SLOW)
--! OUTPUTs
irq_ta0 : out std_logic; --! Timer A interrupt: TACCR0
irq_ta1 : out std_logic; --! Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
ta_out0 : out std_logic; --! Timer A output 0
ta_out0_en : out std_logic; --! Timer A output 0 enable
ta_out1 : out std_logic; --! Timer A output 1
ta_out1_en : out std_logic; --! Timer A output 1 enable
ta_out2 : out std_logic; --! Timer A output 2
ta_out2_en : out std_logic --! Timer A output 2 enable
);
end entity fmsp_timerA;
architecture RTL of fmsp_timerA is
--=============================================================================
--! 1) PARAMETER DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000100000000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 7;
--! Register addresses offset
constant TACTL : integer := 096; --! 'h60,
constant TAR : integer := 112; --! 'h70,
constant TACCTL0 : integer := 098; --! 'h62,
constant TACCR0 : integer := 114; --! 'h72,
constant TACCTL1 : integer := 100; --! 'h64,
constant TACCR1 : integer := 116; --! 'h74,
constant TACCTL2 : integer := 102; --! 'h66,
constant TACCR2 : integer := 118; --! 'h76,
constant TAIV : integer := 046; --! 'h2E;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
--! Timer A: TACCTLx Capture/Compare Control Register
constant TACLR : integer := 2;
constant TAIE : integer := 1;
constant TAIFG : integer := 0;
--! constant TACMx 15 downto 14
--! constant TACCISx 13 downto 12
constant TASCS : integer := 11;
constant TASCCI : integer := 10;
constant TACAP : integer := 8;
--! constant TAOUTMODx 7 downto 5
constant TACCIE : integer := 4;
constant TACCI : integer := 3;
constant TAOUT : integer := 2;
constant TACOV : integer := 1;
constant TACCIFG : integer := 0;
constant capture_unit_nb : integer := 3;
type array_ofregisters is array(0 to capture_unit_nb-1) of std_logic_vector(15 downto 0);
type array_ofunsigneds is array(0 to capture_unit_nb-1) of unsigned(15 downto 0);
type fmsp_timerA_in_type is record
aclk_en : std_logic; --! ACLK enable (from CPU)
smclk_en : std_logic; --! SMCLK enable (from CPU)
dbg_freeze : std_logic; --! Freeze Timer A counter
irq_ta0_acc : std_logic; --! Interrupt request TACCR0 accepted
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
taclk_s : std_logic;
inclk_s : std_logic;
--! Shared
ta_ccixa : std_logic_vector(2 downto 0); --! Timer capture input A
ta_ccixb : std_logic_vector(2 downto 0); --! Timer capture input B
ccix_s : std_logic_vector(2 downto 0);
end record;
type reg_type is record
tactl : std_logic_vector(9 downto 0);
tar : unsigned(15 downto 0);
taclk_dly : std_logic;
inclk_dly : std_logic;
clk_div : unsigned(2 downto 0);
tar_dir : std_logic;
--! Shared
tacctlx : array_ofregisters;
taccrx : array_ofunsigneds;
sccix : std_logic_vector(2 downto 0);
ccix_dly : std_logic_vector(2 downto 0);
ccix_evt_s : std_logic_vector(2 downto 0);
ccix_sync : std_logic_vector(2 downto 0);
capx_taken : std_logic_vector(2 downto 0);
ta_outx : std_logic_vector(2 downto 0);
end record;
signal d : fmsp_timerA_in_type;
signal r : reg_type := ( tactl => "0000000000",
tar => x"0000",
taclk_dly => '0',
inclk_dly => '0',
clk_div => "000",
tar_dir => '0',
tacctlx => (Others => x"0000"),
taccrx => (Others => x"0000"),
sccix => "000",
ccix_dly => "000",
ccix_evt_s => "000",
ccix_sync => "000",
capx_taken => "000",
ta_outx => "000"
);
signal rin : reg_type;
signal cci : std_logic_vector(2 downto 0) := "000";
begin
d.aclk_en <= aclk_en;
d.smclk_en <= smclk_en;
d.dbg_freeze <= dbg_freeze;
d.irq_ta0_acc <= irq_ta0_acc;
-- d.taclk <= taclk;
-- d.inclk <= inclk;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
d.ta_ccixa(0) <= ta_cci0a;
d.ta_ccixb(0) <= ta_cci0b;
d.ta_ccixa(1) <= ta_cci1a;
d.ta_ccixb(1) <= ta_cci1b;
d.ta_ccixa(2) <= ta_cci2a;
d.ta_ccixb(2) <= ta_cci2b;
COMB : process (d, r)
variable v : reg_type;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
variable v_tactl_wr : std_logic;
variable v_ta_clr : std_logic;
variable v_taifg_set : std_logic;
variable v_taifg_clr : std_logic;
--! TAR Register
variable v_tar_wr : std_logic;
variable v_tar_clk : std_logic;
variable v_tar_clr : std_logic;
variable v_tar_inc : std_logic;
variable v_tar_dec : std_logic;
variable v_tar_add : unsigned(15 downto 0);
variable v_tar_nxt : unsigned(15 downto 0);
--! TACCTL0 Register
variable v_tacctlx_wr : std_logic_vector(2 downto 0);
variable v_ccifgx_set : std_logic_vector(2 downto 0);
variable v_covx_set : std_logic_vector(2 downto 0);
variable v_ccix : std_logic_vector(2 downto 0);
variable v_tacctlx_full : array_ofregisters;
--! TACCR0 Register
variable v_taccrx_wr : std_logic_vector(2 downto 0);
variable v_ccix_cap : std_logic_vector(2 downto 0);
variable v_equx : std_logic_vector(2 downto 0);
--! Input selection
-- variable v_ccix : std_logic_vector(2 downto 0);
--! Capture mode
variable v_ccix_evt : std_logic_vector(2 downto 0);
--! Generate final capture command
-- variable v_ccix_cap : std_logic_vector(2 downto 0);
--! Generate capture overflow flag
variable v_capx_taken_clr : std_logic_vector(2 downto 0);
-- variable v_covx_set : std_logic_vector(2 downto 0);
--! Output unit 0
variable v_ta_outx_mode0 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode1 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode2 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode3 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode4 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode5 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode6 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode7 : std_logic_vector(2 downto 0);
variable v_ta_outx_nxt : std_logic_vector(2 downto 0);
variable v_ta_outx_en : std_logic_vector(2 downto 0);
--! 9) Timer A interrupt generation
-- variable v_ccifgx_set : std_logic_vector(2 downto 0);
--! TAIV Register
variable v_taiv : std_logic_vector(3 downto 0);
variable v_ccifg1_clr : std_logic;
variable v_ccifg2_clr : std_logic;
variable v_ccifgx_clr : std_logic_vector(2 downto 0);
-- variable v_taifg_clr : std_logic;
--! Data output mux
variable v_tactl_rd : std_logic_vector(15 downto 0);
variable v_tar_rd : std_logic_vector(15 downto 0);
variable v_tacctl0_rd : std_logic_vector(15 downto 0);
variable v_taccr0_rd : std_logic_vector(15 downto 0);
variable v_tacctl1_rd : std_logic_vector(15 downto 0);
variable v_taccr1_rd : std_logic_vector(15 downto 0);
variable v_tacctl2_rd : std_logic_vector(15 downto 0);
variable v_taccr2_rd : std_logic_vector(15 downto 0);
variable v_taiv_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
--! Clock edge detection (TACLK & INCLK)
variable v_taclk_en : std_logic;
variable v_inclk_en : std_logic;
--! Timer clock input mux
variable v_sel_clk : std_logic;
--! Generate update pluse for the counter (<=> divided clock)
-- variable v_tar_clk : std_logic;
-- --! Time counter control signals
-- variable v_tar_clr : std_logic;
-- variable v_tar_inc : std_logic;
-- variable v_tar_dec : std_logic;
--! 9) Timer A interrupt generation
-- variable v_taifg_set : std_logic;
variable v_irq_ta0 : std_logic;
variable v_irq_ta1 : std_logic;
--! Timer A: TACTL Control Register
alias a_TACTL_TASSELx : std_logic_vector(1 downto 0) is r.tactl(9 downto 8);
alias a_TACTL_TAIDx : std_logic_vector(1 downto 0) is r.tactl(7 downto 6);
alias a_TACTL_TAMCx : std_logic_vector(1 downto 0) is r.tactl(5 downto 4);
alias a_TACTL_TACLR : std_logic is r.tactl(2);
alias a_TACTL_TAIE : std_logic is r.tactl(1);
alias a_TACTL_TAIFG : std_logic is r.tactl(0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 1) REGISTER DECODER
--============================================================================
--! Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_write := v_reg_sel and (d.per_we(0) or d.per_we(1));
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 3) REGISTERS
--============================================================================
v_tactl_wr := v_reg_wr(TACTL);
v_ta_clr := v_tactl_wr and d.per_din(TACLR);
v_tar_wr := v_reg_wr(TAR);
--! TAIV Register
--------------------
if ( (r.tacctlx(1)(TACCIFG) = '1') and (r.tacctlx(1)(TACCIE) = '1') ) then
v_taiv := x"2";
elsif ( (r.tacctlx(2)(TACCIFG) = '1') and (r.tacctlx(2)(TACCIE) = '1') ) then
v_taiv := x"4";
elsif ( (r.tactl(TAIFG) = '1') and (r.tactl(TAIE) = '1') ) then
v_taiv := x"A";
else
v_taiv := x"0";
end if;
v_ccifg1_clr := '0';
v_ccifg2_clr := '0';
v_taifg_clr := '0';
if (v_taiv = x"2") then
v_ccifg1_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
if (v_taiv = x"4") then
v_ccifg2_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
if (v_taiv = x"A") then
v_taifg_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
--============================================================================
--! 5) Timer A counter control
--============================================================================
--! Clock edge detection (TACLK & INCLK)
-------------------------------------------------------------
v.taclk_dly := d.taclk_s;
v_taclk_en := d.taclk_s and not(r.taclk_dly);
v.inclk_dly := d.inclk_s;
v_inclk_en := d.inclk_s and not(r.inclk_dly);
--! Timer clock input mux
-------------------------------------------------------------
if (r.tactl(9 downto 8) = "00") then
v_sel_clk := v_taclk_en;
elsif (r.tactl(9 downto 8) = "01") then
v_sel_clk := d.aclk_en;
elsif (r.tactl(9 downto 8) = "10") then
v_sel_clk := d.smclk_en;
else
v_sel_clk := v_inclk_en;
end if;
--! Generate update pulse for the counter (<=> divided clock)
-------------------------------------------------------------
if (r.tactl(7 downto 6) = "00") then
v_tar_clk := v_sel_clk;
elsif (r.tactl(7 downto 6) = "01") then
v_tar_clk := v_sel_clk and r.clk_div(0);
elsif (r.tactl(7 downto 6) = "10") then
v_tar_clk := v_sel_clk and r.clk_div(0) and r.clk_div(1);
else
v_tar_clk := v_sel_clk and r.clk_div(0) and r.clk_div(1) and r.clk_div(2);
end if;
--! Time counter control signals
-------------------------------------------------------------
v_tar_clr := '0';
if ( ( (r.tactl(5 downto 4) = "01") and (r.tar >= r.taccrx(0)) )
or ( (r.tactl(5 downto 4) = "11") and (r.taccrx(0) = x"0000") ) ) then
v_tar_clr := '1';
end if;
v_tar_dec := '0';
if ( (r.tar_dir = '1')
or ( (r.tactl(5 downto 4) = "11") and (r.tar >= r.taccrx(0)) ) ) then
v_tar_dec := '1';
end if;
v_tar_inc := '0';
if ( (r.tactl(5 downto 4) = "01")
or (r.tactl(5 downto 4) = "01")
or ( (r.tactl(5 downto 4) = "11") and (not(v_tar_dec) = '1') ) ) then
v_tar_inc := '1';
end if;
if ( (v_tar_clk or v_ta_clr) = '1' ) then
v.clk_div := "000";
elsif ( (r.tactl(5 downto 4) /= "00") and (v_sel_clk = '1') ) then
v.clk_div := r.clk_div + TO_UNSIGNED(1,3);
end if;
if ( v_ta_clr = '1' ) then
v.tar_dir := '0';
elsif (r.tactl(5 downto 4) = "11") then
if ( (r.tar = x"0001") and (not(v_tar_clk) = '1') ) then
v.tar_dir := '0';
elsif (r.tar >= r.taccrx(0)) then
v.tar_dir := '1';
end if;
else
v.tar_dir := '0';
end if;
--! TAR Register
-------------------
if (v_tar_inc = '1') then
v_tar_add := x"0001";
elsif (v_tar_dec = '1') then
v_tar_add := x"FFFF";
else
v_tar_add := x"0000";
end if;
if (v_tar_clr = '1') then
v_tar_nxt := x"0000";
else
v_tar_nxt := r.tar + v_tar_add;
end if;
if (v_tar_wr = '1') then
v.tar := UNSIGNED(d.per_din);
elsif ((v_tar_clk and not(d.dbg_freeze)) = '1') then
v.tar := v_tar_nxt;
end if;
--============================================================================
--! 9) Timer A interrupt generation
--============================================================================
if ( ( (r.tactl(5 downto 4) = "01") and (r.tar = r.taccrx(0)) ) or
( (r.tactl(5 downto 4) = "10") and (r.tar = x"ffff") ) or
( (r.tactl(5 downto 4) = "11") and (v_tar_nxt = x"0000") and (v_tar_dec = '1') ) ) then
v_taifg_set := v_tar_clk;
else
v_taifg_set := '0';
end if;
--! TACTL Register
-------------------
if (v_tactl_wr = '1') then
v.tactl := ( (d.per_din(9 downto 0) and "1111110011") or ("000000000" & v_taifg_set) )
and ("111111111" & not(v_taifg_clr));
else
v.tactl := ( r.tactl or ("000000000" & v_taifg_set) )
and ("111111111" & not(v_taifg_clr));
end if;
--============================================================================
--! 7) Timer A capture logic
--============================================================================
for i in 0 to capture_unit_nb-1 loop
--! Input selection
--------------------
if (r.tacctlx(i)(13 downto 12) = "00") then
v_ccix(i) := d.ta_ccixa(i);
elsif (r.tacctlx(i)(13 downto 12) = "01") then
v_ccix(i) := d.ta_ccixb(i);
elsif (r.tacctlx(i)(13 downto 12) = "10") then
v_ccix(i) := '0';
else
v_ccix(i) := '1';
end if;
v.ccix_dly(i) := d.ccix_s(i);
--! Timer A comparator
v_equx(i) := '0';
if ( (v_tar_nxt = r.taccrx(i)) and (r.tar /= r.taccrx(i)) ) then
v_equx(i) := '1';
end if;
--! Generate SCCIx
--------------------
if ((v_tar_clk and v_equx(i)) = '1') then
v.sccix(i) := d.ccix_s(i);
end if;
--! Capture mode
--------------------
if (r.tacctlx(i)(15 downto 14) = "00") then
v_ccix_evt(i) := '0';
elsif (r.tacctlx(i)(15 downto 14) = "01") then
v_ccix_evt(i) := d.ccix_s(i) and not( r.ccix_dly(i)); --! Rising edge
elsif (r.tacctlx(i)(15 downto 14) = "10") then
v_ccix_evt(i) := not( d.ccix_s(i) ) and r.ccix_dly(i); --! Falling edge
else
v_ccix_evt(i) := d.ccix_s(i) xor r.ccix_dly(i); --! Both edges
end if;
--! Event Synchronization
-------------------------
if (v_tar_clk = '1') then
v.ccix_evt_s(i) := '0';
elsif (v_ccix_evt(i) = '1') then
v.ccix_evt_s(i) := '1';
end if;
if (v_tar_clk = '1') then
v.ccix_sync(i) := (v_tar_clk and r.ccix_evt_s(i)) or (v_tar_clk and v_ccix_evt(i) and not(r.ccix_evt_s(i)));
end if;
--! Generate final capture command
-------------------------------------
if (r.tacctlx(i)(TASCS) = '1') then
v_ccix_cap(i) := r.ccix_sync(i);
else
v_ccix_cap(i) := r.ccix_evt_s(i);
end if;
--! Generate capture overflow flag
-------------------------------------
v_capx_taken_clr(i) := v_reg_rd(TACCR0+(i*2)) or (v_tacctlx_wr(i) and v.tacctlx(i)(TACOV) and not(d.per_din(TACOV)));
if (v_ccix_cap(i) = '1') then
v.capx_taken(i) := '1';
elsif (v_capx_taken_clr(i) = '1') then
v.capx_taken(i) := '0';
end if;
v_covx_set(i) := r.capx_taken(i) and v_ccix_cap(i) and not(v_reg_rd(TACCR0+(i*2)));
if (r.tacctlx(i)(TACAP) = '1') then
v_ccifgx_set(i) := v_ccix_cap(i);
elsif (r.tactl(5 downto 4) /= "00") then
v_ccifgx_set(i) := v_tar_clk and v_equx(i);
else
v_ccifgx_set(i) := '0';
end if;
end loop;
v_ccifgx_clr(0) := d.irq_ta0_acc;
v_ccifgx_clr(1) := v_ccifg1_clr;
v_ccifgx_clr(2) := v_ccifg2_clr;
for i in 0 to capture_unit_nb-1 loop
v_tacctlx_wr(i) := v_reg_wr((TACCTL0+(i*2)));
--! TACCTLx Registers
if (v_tacctlx_wr(i) = '1') then
v.tacctlx(i) := ( (d.per_din and x"F9F7") or ("00000000000000" & v_covx_set(i) & v_ccifgx_set(i)) )
and ("111111111111111" & not(v_ccifgx_clr(i)));
else
v.tacctlx(i) := ( r.tacctlx(i) or ("00000000000000" & v_covx_set(i) & v_ccifgx_set(i)) )
and ("111111111111111" & not(v_ccifgx_clr(i)));
end if;
v_tacctlx_full(i) := r.tacctlx(i) or ("00000" & r.sccix(i) & "000000" & d.ccix_s(i) & "000");
--! TACCRx Registers
--------------------
v_taccrx_wr(i) := v_reg_wr((TACCR0+(i*2)));
if (v_taccrx_wr(i) = '1') then
v.taccrx(i) := UNSIGNED(d.per_din);
elsif (v_ccix_cap(i) = '1') then
v.taccrx(i) := r.tar;
end if;
end loop;
--============================================================================
--! 9) Timer A interrupt generation
--============================================================================
v_irq_ta0 := r.tacctlx(0)(TACCIFG) and r.tacctlx(0)(TACCIE);
v_irq_ta1 := (r.tactl(TAIFG) and r.tactl(TAIE))
or (r.tacctlx(1)(TACCIFG) and r.tacctlx(1)(TACCIE))
or (r.tacctlx(2)(TACCIFG) and r.tacctlx(2)(TACCIE));
--============================================================================
--! 8) Timer A output unit
--============================================================================
for i in 0 to capture_unit_nb-1 loop
v_ta_outx_mode0(i) := r.tacctlx(i)(TAOUT); --! Output
if (v_equx(i) = '1') then --! Set
v_ta_outx_mode1(i) := '1';
else
v_ta_outx_mode1(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle/Reset
v_ta_outx_mode2(i) := not(r.ta_outx(i));
elsif (v_equx(0) = '1') then
v_ta_outx_mode2(i) := '0';
else
v_ta_outx_mode2(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Set/Reset
v_ta_outx_mode3(i) := '1';
elsif (v_equx(0) = '1') then
v_ta_outx_mode3(i) := '0';
else
v_ta_outx_mode3(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle
v_ta_outx_mode4(i) := not(r.ta_outx(i));
else
v_ta_outx_mode4(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Reset
v_ta_outx_mode5(i) := '0';
else
v_ta_outx_mode5(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle/Set
v_ta_outx_mode6(i) := not(r.ta_outx(i));
elsif (v_equx(0) = '1') then
v_ta_outx_mode6(i) := '1';
else
v_ta_outx_mode6(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Reset/Set
v_ta_outx_mode7(i) := '0';
elsif (v_equx(0) = '1') then
v_ta_outx_mode7(i) := '1';
else
v_ta_outx_mode7(i) := r.ta_outx(i);
end if;
if (r.tacctlx(i)(7 downto 5) = "000") then
v_ta_outx_nxt(i) := v_ta_outx_mode0(i);
elsif (r.tacctlx(i)(7 downto 5) = "001") then
v_ta_outx_nxt(i) := v_ta_outx_mode1(i);
elsif (r.tacctlx(i)(7 downto 5) = "010") then
v_ta_outx_nxt(i) := v_ta_outx_mode2(i);
elsif (r.tacctlx(i)(7 downto 5) = "011") then
v_ta_outx_nxt(i) := v_ta_outx_mode3(i);
elsif (r.tacctlx(i)(7 downto 5) = "100") then
v_ta_outx_nxt(i) := v_ta_outx_mode4(i);
elsif (r.tacctlx(i)(7 downto 5) = "101") then
v_ta_outx_nxt(i) := v_ta_outx_mode5(i);
elsif (r.tacctlx(i)(7 downto 5) = "110") then
v_ta_outx_nxt(i) := v_ta_outx_mode6(i);
else
v_ta_outx_nxt(i) := v_ta_outx_mode7(i);
end if;
if ( (r.tacctlx(i)(7 downto 5) = "001") and (v_ta_clr = '1') ) then
v.ta_outx(i) := '0';
elsif (v_tar_clk = '1') then
v.ta_outx(i) := v_ta_outx_nxt(i);
end if;
v_ta_outx_en(i) := not(r.tacctlx(i)(TACAP));
end loop;
--============================================================================
--! 4) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_tactl_rd := word_per_select_dout( TACTL, v_reg_rd, ("000000" & r.tactl) );
v_tar_rd := word_per_select_dout( TAR, v_reg_rd, STD_LOGIC_VECTOR(r.tar) );
v_tacctl0_rd := word_per_select_dout( TACCTL0, v_reg_rd, v_tacctlx_full(0) );
v_taccr0_rd := word_per_select_dout( TACCR0, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(0)) );
v_tacctl1_rd := word_per_select_dout( TACCTL1, v_reg_rd, v_tacctlx_full(1) );
v_taccr1_rd := word_per_select_dout( TACCR1, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(1)) );
v_tacctl2_rd := word_per_select_dout( TACCTL2, v_reg_rd, v_tacctlx_full(2) );
v_taccr2_rd := word_per_select_dout( TACCR2, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(2)) );
v_taiv_rd := word_per_select_dout( TAIV, v_reg_rd, (x"000" & v_taiv) );
v_per_dout := v_tactl_rd or
v_tar_rd or
v_tacctl0_rd or
v_taccr0_rd or
v_tacctl1_rd or
v_taccr1_rd or
v_tacctl2_rd or
v_taccr2_rd or
v_taiv_rd;
--! drive register inputs
rin <= v;
--! drive module outputs
cci <= v_ccix;
irq_ta0 <= v_irq_ta0; --! Timer A interrupt: TACCR0
irq_ta1 <= v_irq_ta1; --! Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout <= v_per_dout; --! Peripheral data output
ta_out0 <= r.ta_outx(0); --! Timer A output 0
ta_out0_en <= v_ta_outx_en(0); --! Timer A output 0 enable
ta_out1 <= r.ta_outx(1); --! Timer A output 1
ta_out1_en <= v_ta_outx_en(1); --! Timer A output 1 enable
ta_out2 <= r.ta_outx(2); --! Timer A output 2
ta_out2_en <= v_ta_outx_en(2); --! Timer A output 2 enable
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( tactl => "0000000000",
tar => x"0000",
taclk_dly => '0',
inclk_dly => '0',
clk_div => "000",
tar_dir => '0',
tacctlx => (Others => x"0000"),
taccrx => (Others => x"0000"),
sccix => "000",
ccix_dly => "000",
ccix_evt_s => "000",
ccix_sync => "000",
capx_taken => "000",
ta_outx => "000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
--! CCIx synchronization
sync_cell_cci0 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(0),
data_out => d.ccix_s(0)
);
sync_cell_cci1 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(1),
data_out => d.ccix_s(1)
);
sync_cell_cci2 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(2),
data_out => d.ccix_s(2)
);
--! Synchronization
sync_cell_taclk : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => taclk,
data_out => d.taclk_s
);
sync_cell_inclk : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => inclk,
data_out => d.inclk_s
);
end RTL; --! fmsp_timerA
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture queue_server of test_bench is
use qsim.qsim_types.all;
use random.random.all;
signal source_arc, queue_arc, server_arc : arc_type;
signal server_ready : boolean;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
queue1 : entity qsim.queue(behavior)
generic map ( name => "queue1",
time_unit => ns,
info_file_name => "queue1.dat" )
port map ( in_arc => source_arc,
out_arc => queue_arc, out_ready => server_ready,
info_detail => info_detail );
server1 : entity qsim.server(behavior)
generic map ( name => "server1",
distribution => fixed, mean_service_time => 120 ns,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "server1.dat" )
port map ( in_arc => queue_arc, in_ready => server_ready,
out_arc => server_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => server_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
queue_monitor : process is
variable L : line;
begin
wait on queue_arc;
write(L, string'("queue_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, queue_arc.token, ns);
writeline(output, L);
end process queue_monitor;
server_monitor : process is
variable L : line;
begin
wait on server_arc;
write(L, string'("server_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, server_arc.token, ns);
writeline(output, L);
end process server_monitor;
end architecture queue_server;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture queue_server of test_bench is
use qsim.qsim_types.all;
use random.random.all;
signal source_arc, queue_arc, server_arc : arc_type;
signal server_ready : boolean;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
queue1 : entity qsim.queue(behavior)
generic map ( name => "queue1",
time_unit => ns,
info_file_name => "queue1.dat" )
port map ( in_arc => source_arc,
out_arc => queue_arc, out_ready => server_ready,
info_detail => info_detail );
server1 : entity qsim.server(behavior)
generic map ( name => "server1",
distribution => fixed, mean_service_time => 120 ns,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "server1.dat" )
port map ( in_arc => queue_arc, in_ready => server_ready,
out_arc => server_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => server_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
queue_monitor : process is
variable L : line;
begin
wait on queue_arc;
write(L, string'("queue_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, queue_arc.token, ns);
writeline(output, L);
end process queue_monitor;
server_monitor : process is
variable L : line;
begin
wait on server_arc;
write(L, string'("server_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, server_arc.token, ns);
writeline(output, L);
end process server_monitor;
end architecture queue_server;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture queue_server of test_bench is
use qsim.qsim_types.all;
use random.random.all;
signal source_arc, queue_arc, server_arc : arc_type;
signal server_ready : boolean;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
queue1 : entity qsim.queue(behavior)
generic map ( name => "queue1",
time_unit => ns,
info_file_name => "queue1.dat" )
port map ( in_arc => source_arc,
out_arc => queue_arc, out_ready => server_ready,
info_detail => info_detail );
server1 : entity qsim.server(behavior)
generic map ( name => "server1",
distribution => fixed, mean_service_time => 120 ns,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "server1.dat" )
port map ( in_arc => queue_arc, in_ready => server_ready,
out_arc => server_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => server_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
queue_monitor : process is
variable L : line;
begin
wait on queue_arc;
write(L, string'("queue_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, queue_arc.token, ns);
writeline(output, L);
end process queue_monitor;
server_monitor : process is
variable L : line;
begin
wait on server_arc;
write(L, string'("server_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, server_arc.token, ns);
writeline(output, L);
end process server_monitor;
end architecture queue_server;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
use ieee.std_logic_textio.all;
entity DDR2SIM is
end entity;
architecture TESTBENCH of DDR2SIM is
component DDR2_CONTROL is
port
(
pll_lock:in std_logic;
clk_control_p,clk_control_n,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='0';
bank:out std_logic_vector(2 downto 0);
addr:out std_logic_vector(12 downto 0);
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='0';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end component;
component DDR2 is
port
(
ck:in std_logic;
ck_n:in std_logic;
cke:in std_logic;
cs_n:in std_logic;
ras_n:in std_logic;
cas_n:in std_logic;
we_n:in std_logic;
dm_rdqs:inout std_logic_vector(1 downto 0);
ba:in std_logic_vector(2 downto 0);
addr:in std_logic_vector(12 downto 0);
dq:inout std_logic_vector(15 downto 0);
dqs:inout std_logic_vector(1 downto 0);
dqs_n:inout std_logic_vector(1 downto 0);
rdqs_n:out std_logic_vector(1 downto 0);
odt:in std_logic
);
end component;
signal clk_c_0,clk_c_90,clk_c_180,clk_c_270,clk_d_0,clk_d_180,pll_lock:std_logic;
signal ddr_clk,ddr_clk_n:std_logic;
signal cke,n_cs,n_ras,n_cas,n_we:std_logic;
signal dm:std_logic_vector(1 downto 0);
signal dqs,dqs_in,dqs_out:std_logic_vector(1 downto 0);
signal dqs_en:std_logic;
signal odt:std_logic;
signal bank:std_logic_vector(2 downto 0);
signal addr:std_logic_vector(12 downto 0);
signal data,data_in,data_out:std_logic_vector(15 downto 0);
signal data_en:std_logic;
signal ram_reset:std_logic;
signal wr_rqu,rd_rqu:std_logic;
signal wr_ready,rd_ready:std_logic;
signal wr_end,rd_end:std_logic;
signal ot_dm:std_logic_vector(1 downto 0);
signal wr_num,rd_num:std_logic_vector(15 downto 0);
signal ot_data_in,ot_data_out:std_logic_vector(15 downto 0);
signal ot_bank:std_logic_vector(2 downto 0);
signal ot_addr_row:std_logic_vector(12 downto 0);
signal ot_addr_col:std_logic_vector(9 downto 0);
signal dqs_n,rdqs_n:std_logic_vector(1 downto 0);
constant clk_period:time:=6000 ps;
constant clk_period2:time:=3000 ps;
signal clk_self:std_logic;
begin
DDR2C:DDR2_CONTROL
port map
(
pll_lock=>pll_lock,
clk_control_p=>clk_c_0,clk_control_n=>clk_c_180,clk_out_p=>clk_c_0,clk_out_n=>clk_c_180,
clk_data=>clk_d_0,
clk=>ddr_clk,n_clk=>ddr_clk_n,
cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we,
udm=>dm(1),ldm=>dm(0),
udqs_in=>dqs_in(1),ldqs_in=>dqs_in(0),
udqs_out=>dqs_out(1),ldqs_out=>dqs_out(0),
dqs_en=>dqs_en,
odt=>odt,
bank=>bank,addr=>addr,
ram_data_in=>data_in(15 downto 0),
ram_data_out=>data_out(15 downto 0),
ram_data_en=>data_en,
ram_reset=>ram_reset,
wr_rqu=>wr_rqu,rd_rqu=>rd_rqu,
wr_ready=>wr_ready,rd_ready=>rd_ready,
wr_end=>wr_end,rd_end=>rd_end,
udm_in=>ot_dm(1),ldm_in=>ot_dm(0),
write_num=>wr_num,read_num=>rd_num,
bank_other=>ot_bank,
addr_other_row=>ot_addr_row,
addr_other_col=>ot_addr_col,
data_other_in=>ot_data_in,
data_other_out=>ot_data_out
);
DDR2M:DDR2
port map
(
ck=>ddr_clk,
ck_n=>ddr_clk_n,
cke=>cke,
cs_n=>n_cs,
ras_n=>n_ras,
cas_n=>n_cas,
we_n=>n_we,
dm_rdqs=>dm,
ba=>bank,
addr=>addr,
dq=>data,
dqs=>dqs,
dqs_n=>dqs_n,
rdqs_n=>rdqs_n,
odt=>odt
);
clk_0:process
begin
clk_c_0<='1';
wait for clk_period/2;
clk_c_0<='0';
wait for clk_period/2;
end process;
clk_180:process
begin
clk_c_180<='0';
wait for clk_period/2;
clk_c_180<='1';
wait for clk_period/2;
end process;
clk_90:process
begin
wait for clk_period/4;
clk_c_90<='0';
wait for clk_period/2;
clk_c_90<='1';
wait for clk_period/4;
end process;
clk_270:process
begin
wait for clk_period/4;
clk_c_270<='1';
wait for clk_period/2;
clk_c_270<='0';
wait for clk_period/4;
end process;
clk_data_0:process
begin
clk_d_0<='1';
clk_self<='1';
wait for clk_period2/2;
clk_d_0<='0';
clk_self<='0';
wait for clk_period2/2;
end process;
clk_data_180:process
begin
clk_d_180<='0';
wait for clk_period2/2;
clk_d_180<='1';
wait for clk_period2/2;
end process;
pll_lock<='1';
with dqs_en select
dqs(1) <= dqs_out(1) when '1',
'Z' when others;
dqs_in(1)<=dqs(1);
with dqs_en select
dqs(0) <= dqs_out(0) when '1',
'Z' when others;
dqs_in(0)<=dqs(0);
with data_en select
data <= data_out when '1',
"ZZZZZZZZZZZZZZZZ" when others;
data_in<=data;
main:process
file ddr2_data_text_w,ddr2_data_text_r,ddr2_data_text_st:text;
variable fstin,fstout,fstst:FILE_OPEN_STATUS;
variable ddr2_data_line:line;
variable ddr2_data_sim:std_logic_vector(15 downto 0);
variable ddr2_row_sim:std_logic_vector(12 downto 0);
variable ddr2_col_sim:std_logic_vector(9 downto 0);
variable ddr2_bank_sim:std_logic_vector(2 downto 0);
variable con:integer range 0 to 7:=0;
begin
file_open(fstst ,ddr2_data_text_st ,"textfile_st.dat",read_mode);
file_open(fstin ,ddr2_data_text_r ,"textfile_r.dat",read_mode);
file_open(fstout ,ddr2_data_text_w ,"textfile_w.dat",write_mode);
while (con<6) loop
wait until rising_edge(clk_self); --每个时钟读一行
--------write--------
if con=0 then
if not endfile(ddr2_data_text_st) then
ot_dm<="00";
wr_num<=x"0080";
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_bank_sim);
ot_bank<=ddr2_bank_sim;
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_col_sim);
ot_addr_col<=ddr2_col_sim;
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_row_sim);
ot_addr_row<=ddr2_row_sim;
wr_rqu<='1';
con:=con+1;
else
file_close(ddr2_data_text_st);
file_open(fstst ,ddr2_data_text_st ,"textfile_st.dat",read_mode);
con:=3;
end if;
elsif con=1 then
if wr_ready='1' then
readline(ddr2_data_text_r,ddr2_data_line);
read(ddr2_data_line,ddr2_data_sim);
if ddr2_data_sim=x"FFFF" then
con:=con+1;
else
ot_data_in<=ddr2_data_sim;
end if;
end if;
elsif con=2 then
if wr_end='1' then
wr_rqu<='0';
con:=0;
end if;
--------read--------
elsif con=3 then
if not endfile(ddr2_data_text_st) then
ot_dm<="00";
rd_num<=x"0080";
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_bank_sim);
ot_bank<=ddr2_bank_sim;
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_col_sim);
ot_addr_col<=ddr2_col_sim;
readline(ddr2_data_text_st,ddr2_data_line);
read(ddr2_data_line,ddr2_row_sim);
ot_addr_row<=ddr2_row_sim;
rd_rqu<='1';
con:=con+1;
else
con:=6;
end if;
elsif con=4 then
if rd_ready='1' then
ddr2_data_sim:=ot_data_out;
write(ddr2_data_line,ddr2_data_sim);
writeline(ddr2_data_text_w,ddr2_data_line);
con:=5;
end if;
elsif con=5 then
if rd_ready='1' then
ddr2_data_sim:=ot_data_out;
if ddr2_data_sim="ZZZZZZZZZZZZZZZZ" or ddr2_data_sim="XXXXXXXXXXXXXXXX" then
null;
else
write(ddr2_data_line,ddr2_data_sim);
writeline(ddr2_data_text_w,ddr2_data_line);
end if;
elsif rd_end='1' then
rd_rqu<='0';
con:=3;
end if;
end if;
end loop;
file_close(ddr2_data_text_st);
file_close(ddr2_data_text_r);
file_close(ddr2_data_text_w);
wait;
end process;
end TESTBENCH; |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instr_Mem1.vhd when simulating
-- the core, Instr_Mem1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instr_Mem1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instr_Mem1;
ARCHITECTURE Instr_Mem1_a OF Instr_Mem1 IS
-- synthesis translate_off
COMPONENT wrapped_Instr_Mem1
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instr_Mem1 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instr_Mem1.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instr_Mem1
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END Instr_Mem1_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instr_Mem1.vhd when simulating
-- the core, Instr_Mem1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instr_Mem1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instr_Mem1;
ARCHITECTURE Instr_Mem1_a OF Instr_Mem1 IS
-- synthesis translate_off
COMPONENT wrapped_Instr_Mem1
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instr_Mem1 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instr_Mem1.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instr_Mem1
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END Instr_Mem1_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_mod8 is
port(clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(2 downto 0);
fim : out std_logic);
end contador_mod8;
architecture exemplo of contador_mod8 is
signal IQ: unsigned(2 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if clock'event and clock = '1' then
if zera = '1' then
IQ <= (others => '0');
elsif conta = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 7 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This implements a fast serial port with help from an AVR. It also includes
-- some code from spi_sd_card.vhd to support MMFS (bit-banged SD card interface)
-- and UPURS (bit-banged serial)
-- Addresses used:
-- &FCA0 = serial TX/RX (for HostFS)
-- &FCA1 = serial status (for HostFS)
-- &FCA2 = serial2 TX/RX
-- &FCA3 = serial2 status
-- &FC71 = Plus 1 parallel data register (for MMFS)
-- &FC72 = Plus 1 serial data register (for MMFS)
entity serial_sd_adapter is
generic (
-- Use the avr_INT pin
include_avr_int : boolean := false;
-- '1' to include the ROM at &FD00
include_rom : boolean := false;
-- Include SD pins
include_sd : boolean := true;
-- '1' to include the Plus 1 SD card interface
include_bitbang_sd : boolean := true;
-- '1' to include the pass-through SD card interface via the AVR
include_avr_sd : boolean := false;
-- '1' to include the second serial port
include_second_serial : std_logic := '0'
);
Port (
-- Pins that connect to the BBC 1MHz Bus
bbc_A : in std_logic_vector(7 downto 0);
bbc_D : inout std_logic_vector(7 downto 0);
bbc_nPGFC : in std_logic;
bbc_nPGFD : in std_logic;
bbc_1MHZE : in std_logic;
bbc_RnW : in std_logic;
bbc_nIRQ : in std_logic;
bbc_nNMI : in std_logic;
bbc_nRESET : in std_logic;
-- AVR interface: MISO, MOSI, SCK, /SS, INT.
-- The first four are a standard SPI port, with the AVR as
-- controller and CPLD as peripheral. INT is an output from the CPLD
-- that goes high when we have a byte to send to the AVR.
avr_INT : out std_logic;
avr_MISC1 : in std_logic;
avr_MISO : out std_logic;
avr_MOSI : in std_logic;
avr_SCK : in std_logic;
avr_nSD_SEL : in std_logic;
avr_nSS : in std_logic;
-- SD interface: MISO, MOSI, SCK, /SS
-- These are wired to the pins on the micro SD card socket.
sd_MISO : in std_logic;
sd_MOSI : out std_logic;
sd_SCK : out std_logic;
sd_nSS : out std_logic
);
end serial_sd_adapter;
architecture Behavioural of serial_sd_adapter is
-- 1MHz Bus helpers
signal latched_nPGFC : std_logic := '1';
signal latched_nPGFD : std_logic := '1';
---- Fast SPI port (peripheral, for AVR) ----
signal int_avr_MISO : std_logic; -- output to AVR
signal nAVR_SPI_REG_ACCESS : std_logic; -- '0' when A = &FCA0;
signal nAVR_SPI_STATUS_REG_ACCESS : std_logic; -- '0' when A = &FCA1;
signal nAVR_SPI_REG2_ACCESS : std_logic; -- '0' when A = &FCA2;
signal nAVR_SPI_STATUS_REG2_ACCESS : std_logic; -- '0' when A = &FCA3;
-- we use a toggle synchronizer to know if the buffer is full or empty.
-- RECEPTION FROM AVR TO CPLD+ELK:
-- on the avr side, it's safe to receive a byte if avr_RXD_state = elk_RXD_state_sync
-- on the elk side, it's safe to read a byte if elk_RXD_state != avr_RXD_state_sync
-- we just use a single flip flop to synchronize in each case, because there's always
-- a longish settling time.
-- TRANSMISSION FROM ELK+CPLD TO AVR:
-- it's safe to accept a byte from the elk for transmission if elk_TXD_state == avr_TXD_state_sync
-- it's safe to transmit a byte to the avr if avr_TXD_state != elk_TXD_state_sync
-- TODO could maybe save 9 registers here with a single fast clock
signal avr_RXD_state : std_logic := '0'; -- toggles whenever the CPLD receives a byte from the AVR
signal avr_RXD_state_sync : std_logic := '0'; -- avr_RXD_state synchronized to bbc_1MHZE
signal elk_RXD_state : std_logic := '0'; -- toggles when the elk reads a byte
signal elk_RXD_state_sync : std_logic := '0'; -- elk_RXD_state synchronized to avr_SCK
signal avr_RXD2_state : std_logic := '0'; -- toggles whenever the CPLD receives a byte from the AVR
signal avr_RXD2_state_sync : std_logic := '0'; -- avr_RXD_state synchronized to bbc_1MHZE
signal elk_RXD2_state : std_logic := '0'; -- toggles when the elk reads a byte
signal elk_RXD2_state_sync : std_logic := '0'; -- elk_RXD_state synchronized to avr_SCK
signal avr_TXD_state : std_logic := '0'; -- toggles whenever the CPLD sends a byte to the AVR
signal avr_TXD_state_sync : std_logic := '0'; -- avr_TXD_state synchronized to bbc_1MHZE
signal elk_TXD_state : std_logic := '0'; -- toggles when the elk writes a byte
signal elk_TXD_state_sync : std_logic := '0'; -- elk_TXD_state synchronized to avr_SCK
signal avr_RXD : std_logic_vector(7 downto 0); -- byte received from AVR
signal avr_RXD2 : std_logic_vector(7 downto 0); -- byte received from AVR
signal avr_TXD : std_logic_vector(7 downto 0); -- next byte to transmit / being transmitted to AVR
signal avr_TXD_port_sel : std_logic := '0'; -- which port the next byte is for
-- signals used during an SPI transaction
signal avr_spi_SHIFT : std_logic_vector(7 downto 0); -- SPI shift register
signal avr_spi_bit_count : std_logic_vector(3 downto 0); -- SPI bit counter for transfers
signal avr_spi_receiving : std_logic := '0'; -- copy bits into avr_RXD and toggle avr_RXD_state when done
signal avr_spi_port_sel : std_logic := '0'; -- port 0 or 1
signal avr_spi_transmitting : std_logic := '0'; -- toggle avr_TXD_state when done
---- SPI (controller, for SD card) ---
signal bitbang_MOSI : std_logic := '1';
signal bitbang_SCK : std_logic := '1';
signal bitbang_nSS : std_logic := '0';
---- Plus 1 workalike registers ----
-- chip selects
signal nDATA_REG_ACCESS : std_logic; -- '0' when A = &FC71
signal nSTATUS_REG_ACCESS : std_logic; -- '0' when A = &FC72
---- ROM ----
signal ROM_D : std_logic_vector(7 downto 0);
begin
-- Multiplex MISO between SD card and avr SPI module
avr_MISO <= 'Z' when avr_nSS = '1' else
sd_MISO when include_avr_sd and avr_nSD_SEL = '0' else
int_avr_MISO;
-- Multiplex SD card SPI port between AVR and BBC
gen_sd_pins : if include_sd generate
sd_nSS <= avr_nSS when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_nSS when include_bitbang_sd
else 'Z';
sd_MOSI <= avr_MOSI when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_MOSI when include_bitbang_sd
else 'Z';
sd_SCK <= avr_SCK when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_SCK when include_bitbang_sd
else 'Z';
end generate;
---- Fast SPI peripheral for AVR ---
nAVR_SPI_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A0") else '1';
nAVR_SPI_STATUS_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A1") else '1';
nAVR_SPI_REG2_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A2") else '1';
nAVR_SPI_STATUS_REG2_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A3") else '1';
gen_avr_INT : if include_avr_int generate
avr_INT <= '1' when (elk_TXD_state /= avr_TXD_state_sync) else '0';
end generate;
---- Plus 1 parallel port emulation ----
nDATA_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"71") else '1';
nSTATUS_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"72") else '1';
---- ROM from rom_fd00.vhd ----
gen_rom : if include_rom generate
rom_fd00 : entity RomFD00
port map (
A => bbc_A,
D => ROM_D
);
end generate;
---- Data bus ----
bbc_D <=
-- AVR SPI data
avr_RXD when (nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '1') else
avr_RXD2 when (include_second_serial = '1' and nAVR_SPI_REG2_ACCESS = '0' and bbc_RnW = '1') else
-- AVR SPI status
"000000" & (elk_TXD_state xnor avr_TXD_state_sync) & (elk_RXD_state xor avr_RXD_state_sync)
when (nAVR_SPI_STATUS_REG_ACCESS = '0' and bbc_RnW = '1') else
"000000" & (elk_TXD_state xnor avr_TXD_state_sync) & (elk_RXD2_state xor avr_RXD2_state_sync)
when (include_second_serial = '1' and nAVR_SPI_STATUS_REG2_ACCESS = '0' and bbc_RnW = '1') else
-- Plus 1 parallel port
sd_MISO & "0000000" when (include_bitbang_sd and nSTATUS_REG_ACCESS = '0' and bbc_RnW = '1') else
-- ROM on &FDxx
ROM_D when include_rom and latched_nPGFD = '0' and bbc_RnW = '1' else
-- default
"ZZZZZZZZ";
-- AVR SPI clock domain
process (avr_nSS, avr_SCK)
begin
-- RISING EDGE of avr_SCK: read avr_MOSI
if avr_nSS = '1' then
-- asynchronous reset (must not happen on an avr_SCK edge)
avr_spi_bit_count <= x"0";
elsif rising_edge(avr_SCK) then
-- increment the count each time
avr_spi_bit_count <= std_logic_vector(unsigned(avr_spi_bit_count) + 1);
-- clock in a bit, depending on avr_spi_bit_count
if avr_spi_bit_count = x"0" then
-- synchronize elk_RXD_state and elk_TXD_state
elk_RXD_state_sync <= elk_RXD_state;
elk_RXD2_state_sync <= elk_RXD2_state;
elk_TXD_state_sync <= elk_TXD_state;
elsif avr_spi_bit_count = x"5" then
avr_spi_port_sel <= avr_MOSI;
elsif avr_spi_bit_count = x"6" then
-- SPI is big-endian, so we want to ignore incoming bits 0-5.
-- bit 6 (1) tells us if the remote wants to send a byte
avr_spi_receiving <= (
avr_MOSI -- '1' if the remote has a byte for us
and (
(
-- byte sent from AVR to serial port 0
(not include_second_serial or not avr_spi_port_sel)
and (avr_RXD_state xnor elk_RXD_state_sync)
) or (
-- byte sent from AVR to serial port 1
include_second_serial and avr_spi_port_sel and
(avr_RXD2_state xnor elk_RXD2_state_sync)
)
) -- '1' if we have room in our buffer
);
elsif avr_spi_bit_count = x"7" then
-- bit 7 (0) tells us if the remote is capable of receiving a byte
avr_spi_transmitting <= (
avr_MOSI -- '1' if the remote has buffer space
and (avr_TXD_state xor elk_TXD_state_sync) -- '1' if we have a byte to transmit
);
-- copy avr_TXD into the shift register if it's safe
if avr_TXD_state /= elk_TXD_state_sync then
avr_spi_SHIFT <= avr_TXD;
end if;
elsif avr_spi_bit_count(3) = '1' then
-- clock in a bit if we have buffer space
avr_spi_SHIFT <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
if avr_spi_bit_count = x"F" then
if avr_spi_receiving = '1' then
avr_RXD_state <= not avr_RXD_state;
if avr_spi_port_sel = '0' then
avr_RXD <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
else
avr_RXD2 <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
end if;
end if;
if avr_spi_transmitting = '1' then
avr_TXD_state <= not avr_TXD_state;
end if;
end if;
end if;
end if;
-- FALLING EDGE of avr_SCK: write int_avr_MISO
if avr_nSS = '1' then
elsif falling_edge(avr_SCK) then
-- We always update MISO on an avr_SCK falling edge.
if avr_spi_bit_count = x"5" then
-- '0' or '1' depending which port our outgoing byte is for
int_avr_MISO <= avr_TXD_port_sel;
elsif avr_spi_bit_count = x"6" then
-- '1' if we have a byte to send to the AVR
int_avr_MISO <= avr_TXD_state xor elk_TXD_state_sync;
elsif avr_spi_bit_count = x"7" then
-- '1' if we can accept a byte from the AVR
int_avr_MISO <= avr_RXD_state xnor elk_RXD_state_sync;
elsif avr_spi_bit_count(3) = '1' then
int_avr_MISO <= avr_spi_SHIFT(7);
end if;
end if;
end process;
-- Electron clock domain
process (bbc_1MHZE)
begin
-- The 1MHz Bus is glitchy, so we need to latch chip enables
if rising_edge(bbc_1MHZE) then
latched_nPGFC <= bbc_nPGFC;
latched_nPGFD <= bbc_nPGFD;
end if;
if falling_edge(bbc_1MHZE) then
-- AVR SPI registers
avr_RXD_state_sync <= avr_RXD_state;
avr_TXD_state_sync <= avr_TXD_state;
if nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '0' and elk_TXD_state = avr_TXD_state_sync then
-- we're writing to the TXD register (first serial port)
avr_TXD <= bbc_D;
avr_TXD_port_sel <= '0';
elk_TXD_state <= not elk_TXD_state;
end if;
if include_second_serial = '1' and nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '0' and elk_TXD_state = avr_TXD_state_sync then
-- we're writing to the TXD register (second serial port)
avr_TXD <= bbc_D;
avr_TXD_port_sel <= '1';
elk_TXD_state <= not elk_TXD_state;
end if;
if nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '1' and elk_RXD_state /= avr_RXD_state_sync then
-- the electron just read avr_RXD
elk_RXD_state <= not elk_RXD_state;
end if;
if include_second_serial = '1' and nAVR_SPI_REG2_ACCESS = '0' and bbc_RnW = '1' and elk_RXD2_state /= avr_RXD2_state_sync then
-- the electron just read avr_RXD
elk_RXD2_state <= not elk_RXD2_state;
end if;
if nAVR_SPI_STATUS_REG_ACCESS = '0' and bbc_RnW = '0' then
-- we never write to the status register
end if;
-- Bit-banged SPI
if include_bitbang_sd and nDATA_REG_ACCESS = '0' and bbc_RnW = '0' then
-- handle write to &FC71
bitbang_MOSI <= bbc_D(0);
bitbang_SCK <= bbc_D(1);
end if;
end if;
end process;
end Behavioural;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Counter60 is
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Entity Counter60;
Architecture ArchCounter60 of Counter60 is
Begin
Process(clk, rst)
Variable tlow:std_logic_vector(3 downto 0);
Variable thigh:std_logic_vector(2 downto 0);
Begin
If rst = '1' then
tlow := (Others => '0' );
thigh := (Others => '0' );
Elsif clk'event and clk='1' Then
co<='0';
If en = '1' Then
If tlow < 10 Then
tlow := tlow + 1;
End If;
If tlow = 10 Then
thigh := thigh + 1;
tlow := (Others => '0' );
End If;
If thigh = 6 Then
thigh := (Others => '0');
co<='1';
End If;
h<=thigh;
l<=tlow;
End If;
End If;
End Process;
End Architecture;
|
--+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcidec.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: PCI decoder and PCI signals loader. |
--| * LoaD signals: "ad" -> adr, cbe -> cmd. |
--| * Decode memory and configuration space. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcidec is
generic (
BARS : string := "1BARMEM"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- pci
ad_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
idsel_i : in std_logic;
-- control
bar0_i : in std_logic_vector(31 downto 9);
memEN_i : in std_logic;
ioEN_i : in std_logic;
pciadrLD_i : in std_logic;
adrcfg_o : out std_logic;
adrmem_o : out std_logic;
adr_o : out std_logic_vector(24 downto 0);
cmd_o : out std_logic_vector(3 downto 0)
);
end pcidec;
architecture rtl of pcidec is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal adr : std_logic_vector(31 downto 0);
signal cmd : std_logic_vector(3 downto 0);
signal idsel_s : std_logic;
signal a1 : std_logic;
signal a0 : std_logic;
begin
--+-------------------------------------------------------------------------+
--| Load PCI Signals |
--+-------------------------------------------------------------------------+
PCILD: process( rst_i, clk_i, ad_i, cbe_i, idsel_i )
begin
if( rst_i = '1' ) then
adr <= ( others => '1' );
cmd <= ( others => '1' );
idsel_s <= '0';
elsif( rising_edge(clk_i) ) then
if ( pciadrLD_i = '1' ) then
adr <= ad_i;
cmd <= cbe_i;
idsel_s <= idsel_i;
end if;
end if;
end process PCILD;
--+-------------------------------------------------------------------------+
--| Decoder |
--+-------------------------------------------------------------------------+
barmem_g: if (BARS="1BARMEM") generate
adrmem_o <= '1' when ( ( memEN_i = '1' )
and ( adr(31 downto 25) = bar0_i(31 downto 25) )
and ( adr(1 downto 0) = "00" )
and ( cmd(3 downto 1) = "011" ) )
else '0';
end generate;
bario_g: if (BARS="1BARIO") generate
adrmem_o <= '1' when ( ( ioEN_i = '1' )
and ( adr(31 downto 16) = "0000000000000000")
and ( adr(15 downto 9) = bar0_i(15 downto 9) )
and ( cmd(3 downto 1) = "001" ) )
else '0';
end generate;
adrcfg_o <= '1' when ( ( idsel_s = '1' )
and ( adr(1 downto 0) = "00" )
and ( cmd(3 downto 1) = "101" ) )
else '0';
--+-------------------------------------------------------------------------+
--| Adresses WB A(1)/A(0) |
--+-------------------------------------------------------------------------+
barmema1a0_g: if (BARS="1BARMEM") generate
a1 <= cbe_i(1) and cbe_i(0);
a0 <= cbe_i(2) and cbe_i(0);
end generate;
barioa1a0_g: if (BARS="1BARIO") generate
a1 <= adr(1);
a0 <= adr(0);
end generate;
--+-------------------------------------------------------------------------+
--| Other outs |
--+-------------------------------------------------------------------------+
adr_o <= adr(24 downto 2) & a1 & a0;
cmd_o <= cmd;
end rtl;
|
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(10 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(10 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(6 downto 0);
signal uart_read2 : std_logic;
signal reg_debug : std_logic_vector(7 downto 0);
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(10 downto 0) :=
-- "01010110110"; -- 80MHz / 11520Hz
-- "01010001011"; -- 75MHz / 11520Hz
-- "01001011111"; -- 70MHz / 11520Hz
-- "01000111100"; -- 66MHz / 11520Hz
-- "01000110100"; -- 65MHz / 11520Hz
-- "01000010010"; -- 60MHz / 11520Hz
-- "00111101110"; -- 57MHz / 11520Hz
-- "00111011101"; -- 55MHz / 11520Hz
"00110110010"; -- 50MHz / 11520Hz
-- "0100011110"; -- 33MHz / 2/57600Hz = 0x11e
-- "10101101101"; -- 80MHz / 57600Hz = 0x56D
-- "1101100100"; -- 50MHz / 57600Hz = 0x364
-- "00110110010"; -- 25MHz / 57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; -- 12.5MHz /57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(10 downto 0);
read_value_reg <= ONES(read_value_reg'length-1 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(10 downto 0);
data_save_reg <= ZERO(17 downto 0);
reg_debug <= ZERO(7 downto 0); -- FOR DEBUGGING PURPOSE ONLY
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(10 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
reg_debug <= data_in; -- FOR DEBUGGING PURPOSE ONLY
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(10 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(10 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(10 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or (enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synopsys synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable hex_output_line : line; -- BLG
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
write(hex_output_line, c); -- BLG
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(output, hex_output_line); -- BLG
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; -- uart_sel
end if; -- rising_edge(clk)
end process; -- uart_proc
end generate; -- uart_logger
-- synopsys synthesis_on
end; --architecture logic
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff0;
ARCHITECTURE SYN OF lpm_dff0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
sub_wire2 <= data;
sub_wire3(0) <= sub_wire2;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
data => sub_wire3,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff0;
ARCHITECTURE SYN OF lpm_dff0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
sub_wire2 <= data;
sub_wire3(0) <= sub_wire2;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
data => sub_wire3,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff0;
ARCHITECTURE SYN OF lpm_dff0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
sub_wire2 <= data;
sub_wire3(0) <= sub_wire2;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
data => sub_wire3,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.01.2017 10:50:44
-- Design Name:
-- Module Name: Echantilloneur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Echantilloneur is
Port ( S_E : in STD_LOGIC;
CLK : in STD_LOGIC;
Q_E : out STD_LOGIC :='0');
end Echantilloneur;
architecture Behavioral of Echantilloneur is
signal A : integer := 0;
begin
process(S_E, CLK)
begin
if CLK'event and CLK = '1' then
if A>100000 then
A <= 0;
Q_E <= S_E;
else
A <= A+1;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01003pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01003pkg;
use work.c06s03b00x00p09n01i01003pkg.all;
ENTITY c06s03b00x00p09n01i01003ent IS
END c06s03b00x00p09n01i01003ent;
ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
BEGIN
TESTING: PROCESS
subtype ST8 is E.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01003arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01003pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01003pkg;
use work.c06s03b00x00p09n01i01003pkg.all;
ENTITY c06s03b00x00p09n01i01003ent IS
END c06s03b00x00p09n01i01003ent;
ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
BEGIN
TESTING: PROCESS
subtype ST8 is E.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01003arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01003pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01003pkg;
use work.c06s03b00x00p09n01i01003pkg.all;
ENTITY c06s03b00x00p09n01i01003ent IS
END c06s03b00x00p09n01i01003ent;
ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
BEGIN
TESTING: PROCESS
subtype ST8 is E.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01003arch;
|
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: Adrian Byszuk ([email protected])
--
-- Design Name:
-- Module Name: bpm_pcie_k7 - Behavioral
-- Project Name:
-- Target Devices: XC7K350T on KC705 devkit
-- Tool versions: ISE 14.4, ISE 14.6
-- Description: This is TOP module for the versatile firmware for PCIe communication.
-- It provides DMA engine with scatter-gather (linked list) functionality.
-- DDR memory is supported through BAR2. Wishbone endpoint is accessible through BAR3.
--
-- Dependencies: Xilinx PCIe core for 7 series. Xilinx DDR core for 7 series.
--
-- Revision: 2.00 - Original file completely rewritten by abyszuk.
--
-- Revision 1.00 - File Released
--
-- Additional Comments: This file can be used both as TOP module for independent operation, or
-- instantiated in another projects. To use it in your project, change INSTANTIATED generic to
-- "TRUE" and uncomment relevant interface sections in entity declaration. ATTENTION: you also
-- have to comment out dummy signal with names exactly the same as port names (it was necessary so
-- that XST won't complain about missing signal names).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bpm_pcie_k7 is
generic (
SIMULATION : string := "FALSE";
INSTANTIATED : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 512;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
sys_clk_p : in std_logic; --100 MHz PCIe Clock
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end entity bpm_pcie_k7;
architecture Behavioral of bpm_pcie_k7 is
constant DDR_ADDR_WIDTH : integer := 28;
component pcie_core
generic (
PL_FAST_TRAIN : string := "FALSE";
PCIE_EXT_CLK : string := "FALSE";
UPSTREAM_FACING : string := "TRUE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
-------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
-------------------------------------------------------------------------------------------------------------------
pci_exp_txp : out std_logic_vector(3 downto 0);
pci_exp_txn : out std_logic_vector(3 downto 0);
pci_exp_rxp : in std_logic_vector(3 downto 0);
pci_exp_rxn : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 2. Clocking Interface --
-------------------------------------------------------------------------------------------------------------------
PIPE_PCLK_IN : in std_logic;
PIPE_RXUSRCLK_IN : in std_logic;
PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0);
PIPE_DCLK_IN : in std_logic;
PIPE_USERCLK1_IN : in std_logic;
PIPE_USERCLK2_IN : in std_logic;
PIPE_OOBCLK_IN : in std_logic;
PIPE_MMCM_LOCK_IN : in std_logic;
PIPE_TXOUTCLK_OUT : out std_logic;
PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
PIPE_GEN3_OUT : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 3. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out : out std_logic;
user_reset_out : out std_logic;
user_lnk_up : out std_logic;
-- TX
tx_buf_av : out std_logic_vector(5 downto 0);
tx_cfg_req : out std_logic;
tx_err_drop : out std_logic;
s_axis_tx_tready : out std_logic;
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
s_axis_tx_tlast : in std_logic;
s_axis_tx_tvalid : in std_logic;
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
tx_cfg_gnt : in std_logic;
-- RX
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
m_axis_rx_tlast : out std_logic;
m_axis_rx_tvalid : out std_logic;
m_axis_rx_tready : in std_logic;
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
rx_np_ok : in std_logic;
rx_np_req : in std_logic;
-- Flow Control
fc_cpld : out std_logic_vector(11 downto 0);
fc_cplh : out std_logic_vector(7 downto 0);
fc_npd : out std_logic_vector(11 downto 0);
fc_nph : out std_logic_vector(7 downto 0);
fc_pd : out std_logic_vector(11 downto 0);
fc_ph : out std_logic_vector(7 downto 0);
fc_sel : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 4. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EP and RP --
---------------------------------------------------------------------
cfg_mgmt_do : out std_logic_vector (31 downto 0);
cfg_mgmt_rd_wr_done : out std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_pmcsr_pme_status : out std_logic;
cfg_received_func_lvl_rst : out std_logic;
-- Management Interface
cfg_mgmt_di : in std_logic_vector (31 downto 0);
cfg_mgmt_byte_en : in std_logic_vector (3 downto 0);
cfg_mgmt_dwaddr : in std_logic_vector (9 downto 0);
cfg_mgmt_wr_en : in std_logic;
cfg_mgmt_rd_en : in std_logic;
cfg_mgmt_wr_readonly : in std_logic;
-- Error Reporting Interface
cfg_err_ecrc : in std_logic;
cfg_err_ur : in std_logic;
cfg_err_cpl_timeout : in std_logic;
cfg_err_cpl_unexpect : in std_logic;
cfg_err_cpl_abort : in std_logic;
cfg_err_posted : in std_logic;
cfg_err_cor : in std_logic;
cfg_err_atomic_egress_blocked : in std_logic;
cfg_err_internal_cor : in std_logic;
cfg_err_malformed : in std_logic;
cfg_err_mc_blocked : in std_logic;
cfg_err_poisoned : in std_logic;
cfg_err_norecovery : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy : out std_logic;
cfg_err_locked : in std_logic;
cfg_err_acs : in std_logic;
cfg_err_internal_uncor : in std_logic;
cfg_trn_pending : in std_logic;
cfg_pm_halt_aspm_l0s : in std_logic;
cfg_pm_halt_aspm_l1 : in std_logic;
cfg_pm_force_state_en : in std_logic;
cfg_pm_force_state : std_logic_vector(1 downto 0);
cfg_dsn : std_logic_vector(63 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt : in std_logic;
cfg_interrupt_rdy : out std_logic;
cfg_interrupt_assert : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_interrupt_stat : in std_logic;
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_to_turnoff : out std_logic;
cfg_turnoff_ok : in std_logic;
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_pm_wake : in std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
cfg_pm_send_pme_to : in std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
cfg_ds_function_number : in std_logic_vector(2 downto 0);
cfg_mgmt_wr_rw1c_as_rw : in std_logic;
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_bridge_serr_en : out std_logic;
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
cfg_root_control_syserr_corr_err_en : out std_logic;
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
cfg_root_control_syserr_fatal_err_en : out std_logic;
cfg_root_control_pme_int_en : out std_logic;
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_corr_err_received : out std_logic;
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
cfg_aer_rooterr_fatal_err_received : out std_logic;
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pm_as_nak : out std_logic;
cfg_msg_received_pm_pme : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_int_a : out std_logic;
cfg_msg_received_assert_int_b : out std_logic;
cfg_msg_received_assert_int_c : out std_logic;
cfg_msg_received_assert_int_d : out std_logic;
cfg_msg_received_deassert_int_a : out std_logic;
cfg_msg_received_deassert_int_b : out std_logic;
cfg_msg_received_deassert_int_c : out std_logic;
cfg_msg_received_deassert_int_d : out std_logic;
cfg_msg_received_setslotpowerlimit : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_auton : in std_logic;
pl_upstream_prefer_deemph : in std_logic;
pl_sel_lnk_rate : out std_logic;
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_phy_lnk_up : out std_logic;
pl_tx_pm_state : out std_logic_vector(2 downto 0);
pl_rx_pm_state : out std_logic_vector(1 downto 0);
pl_link_upcfg_cap : out std_logic;
pl_link_gen2_cap : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_directed_change_done : out std_logic;
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst : out std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
pl_transmit_hot_rst : in std_logic;
pl_downstream_deemph_source : in std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 6. AER interface --
-------------------------------------------------------------------------------------------------------------------
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_err_aer_headerlog_set : out std_logic;
cfg_aer_ecrc_check_en : out std_logic;
cfg_aer_ecrc_gen_en : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 7. VC interface --
-------------------------------------------------------------------------------------------------------------------
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
pipe_mmcm_rst_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic);
end component;
component ddr_core
generic(
SIM_BYPASS_INIT_CAL : string;
SIMULATION : string;
RST_ACT_LOW : integer
);
port(
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic
);
end component ddr_core;
-- -----------------------------------------------------------------------
-- DDR SDRAM control module
-- -----------------------------------------------------------------------
component bram_DDRs_Control_loopback
generic (
C_ASYNFIFO_WIDTH : integer;
P_SIMULATION : boolean
);
port (
DDR_wr_sof : in std_logic;
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_FA : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_sof : in std_logic;
DDR_rdc_eof : in std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_FA : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : out std_logic;
DDR_Blinker : out std_logic;
mem_clk : in std_logic;
user_clk : in std_logic;
Sim_Zeichen : out std_logic;
user_reset : in std_logic
);
end component;
component DDR_Transact
generic (
SIMULATION : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
DDR_UI_DATAWIDTH : integer;
DDR_DQ_WIDTH : integer;
DEVICE_TYPE : string -- "VIRTEX6"
-- "KINTEX7"
-- "ARTIX7"
);
port (
--ext logic interface to memory core
-- memory controller interface --
memc_ui_clk : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_UI_DATAWIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ext logic interface
-- PCIE interface
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--/PCIE interface
-- Common interface
DDR_Ready : out std_logic;
-- DDR core UI
app_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : out std_logic_vector(2 downto 0);
app_en : out std_logic;
app_wdf_data : out std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_wdf_end : out std_logic;
app_wdf_mask : out std_logic_vector((DDR_UI_DATAWIDTH)/8-1 downto 0);
app_wdf_wren : out std_logic;
app_rd_data : in std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_rd_data_end : in std_logic;
app_rd_data_valid : in std_logic;
app_rdy : in std_logic;
app_wdf_rdy : in std_logic;
ui_clk : in std_logic;
ui_clk_sync_rst : in std_logic;
init_calib_complete : in std_logic;
--clocking & reset
user_clk : in std_logic;
user_reset : in std_logic
);
end component;
signal DDR_wr_sof : std_logic;
signal DDR_wr_eof : std_logic;
signal DDR_wr_v : std_logic;
signal DDR_wr_Shift : std_logic;
signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full : std_logic;
signal DDR_rdc_sof : std_logic;
signal DDR_rdc_eof : std_logic;
signal DDR_rdc_v : std_logic;
signal DDR_rdc_Shift : std_logic;
signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full : std_logic;
signal DDR_FIFO_RdEn : std_logic;
signal DDR_FIFO_Empty : std_logic;
signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Ready : std_logic;
-- -----------------------------------------------------------------------
-- Wishbone interface module
-- -----------------------------------------------------------------------
component wb_transact is
port (
-- PCIE user clk
user_clk : in std_logic;
-- Write port
wr_we : in std_logic;
wr_sof : in std_logic;
wr_eof : in std_logic;
wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full : out std_logic;
-- Read command port
rdc_sof : in std_logic;
rdc_v : in std_logic;
rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full : out std_logic;
rd_tout : in std_logic;
-- Read data port
rd_ren : in std_logic;
rd_empty : out std_logic;
rd_dout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk : in std_logic;
wb_rst : in std_logic;
addr_o : out std_logic_vector(28 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
we_o : out std_logic;
sel_o : out std_logic_vector(0 downto 0);
stb_o : out std_logic;
ack_i : in std_logic;
cyc_o : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end component;
signal wbone_clk : std_logic;
signal wb_wr_we : std_logic;
signal wb_wr_wsof : std_logic;
signal wb_wr_weof : std_logic;
signal wb_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_wr_pfull : std_logic;
signal wb_wr_full : std_logic;
signal wb_rdc_sof : std_logic;
signal wb_rdc_v : std_logic;
signal wb_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full : std_logic;
signal wb_timeout : std_logic;
signal wb_rdd_ren : std_logic;
signal wb_rdd_dout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdd_pempty : std_logic;
signal wb_rdd_empty : std_logic;
signal wbone_rst : std_logic;
signal wb_fifo_rst : std_logic;
signal wbone_addr : std_logic_vector(28 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
port (
-- Wishbone interface
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full : in std_logic;
wb_FIFO_Rst : out std_logic;
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
wb_timeout : out std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR control interface
DDR_Ready : in std_logic;
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Transaction layer interface
user_lnk_up : in std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
user_clk : in std_logic;
user_reset : in std_logic;
m_axis_rx_tvalid : in std_logic;
s_axis_tx_tready : in std_logic;
m_axis_rx_tlast : in std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
pcie_link_width : in std_logic_vector(5 downto 0);
localId : in std_logic_vector(15 downto 0);
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(6 downto 0);
s_axis_tx_tvalid : out std_logic;
m_axis_rx_tready : out std_logic;
s_axis_tx_tlast : out std_logic;
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- TRN Layer signals
signal tx_err_drop : std_logic;
signal tx_cfg_gnt : std_logic;
signal fc_cpld : std_logic_vector (12-1 downto 0);
signal fc_cplh : std_logic_vector (8-1 downto 0);
signal fc_npd : std_logic_vector (12-1 downto 0);
signal fc_nph : std_logic_vector (8-1 downto 0);
signal fc_pd : std_logic_vector (12-1 downto 0);
signal fc_ph : std_logic_vector (8-1 downto 0);
signal fc_sel : std_logic_vector (3-1 downto 0);
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal tx_cfg_req : std_logic;
signal pl_initial_link_width : std_logic_vector (3-1 downto 0);
signal pl_lane_reversal_mode : std_logic_vector (2-1 downto 0);
signal pl_link_gen2_cap : std_logic;
signal pl_link_partner_gen2_supported : std_logic;
signal pl_link_upcfg_cap : std_logic;
signal pl_ltssm_state : std_logic_vector (6-1 downto 0);
signal pl_received_hot_rst : std_logic;
signal pl_sel_lnk_rate : std_logic;
signal pl_sel_lnk_width : std_logic_vector (2-1 downto 0);
signal pl_directed_link_auton : std_logic;
signal pl_directed_link_change : std_logic_vector (2-1 downto 0);
signal pl_directed_link_speed : std_logic;
signal pl_directed_link_width : std_logic_vector (2-1 downto 0);
signal pl_upstream_prefer_deemph : std_logic;
-- Wires used for external clocking connectivity
signal PIPE_PCLK_IN : std_logic := '0';
signal PIPE_RXUSRCLK_IN : std_logic := '0';
signal PIPE_RXOUTCLK_IN : std_logic_vector(3 downto 0) := (others => '0');
signal PIPE_DCLK_IN : std_logic := '0';
signal PIPE_USERCLK1_IN : std_logic := '0';
signal PIPE_USERCLK2_IN : std_logic := '0';
signal PIPE_OOBCLK_IN : std_logic := '0';
signal PIPE_MMCM_LOCK_IN : std_logic := '0';
signal PIPE_TXOUTCLK_OUT : std_logic;
signal PIPE_RXOUTCLK_OUT : std_logic_vector(3 downto 0);
signal PIPE_PCLK_SEL_OUT : std_logic_vector(3 downto 0);
signal PIPE_GEN3_OUT : std_logic;
----------------------------------------------------
signal user_reset_int1 : std_logic;
signal user_lnk_up_int1 : std_logic;
signal user_clk : std_logic;
signal user_reset : std_logic;
signal user_lnk_up : std_logic;
signal s_axis_tx_tdata : std_logic_vector(63 downto 0);
signal s_axis_tx_tkeep : std_logic_vector(7 downto 0);
signal s_axis_tx_tlast : std_logic;
signal s_axis_tx_tvalid : std_logic;
signal s_axis_tx_tready : std_logic;
signal s_axis_tx_tuser : std_logic_vector(3 downto 0);
signal s_axis_tx_tdsc : std_logic;
signal s_axis_tx_terrfwd : std_logic;
signal tx_buf_av : std_logic_vector(5 downto 0);
signal m_axis_rx_tdata : std_logic_vector(63 downto 0);
signal m_axis_rx_tkeep : std_logic_vector(7 downto 0);
signal m_axis_rx_tlast : std_logic;
signal m_axis_rx_tvalid : std_logic;
signal m_axis_rx_tready : std_logic;
signal m_axis_rx_terrfwd : std_logic;
signal m_axis_rx_tuser : std_logic_vector(21 downto 0);
signal rx_np_ok : std_logic;
signal rx_np_req : std_logic;
signal m_axis_rx_tbar_hit : std_logic_vector(6 downto 0);
signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_mgmt_rd_wr_done : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_byte_en : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_en : std_logic;
signal cfg_mgmt_rd_en : std_logic;
signal cfg_err_cor : std_logic;
signal cfg_err_ur : std_logic;
signal cfg_err_cpl_rdy : std_logic;
signal cfg_err_ecrc : std_logic;
signal cfg_err_cpl_timeout : std_logic;
signal cfg_err_cpl_abort : std_logic;
signal cfg_err_cpl_unexpect : std_logic;
signal cfg_err_posted : std_logic;
signal cfg_err_locked : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_interrupt : std_logic;
signal cfg_interrupt_rdy : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_turnoff_ok : std_logic;
signal cfg_to_turnoff : std_logic;
signal cfg_pm_wake : std_logic;
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
signal cfg_trn_pending : std_logic;
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal fast_train_simulation_only : std_logic;
signal two_plm_auto_config : std_logic_vector(1 downto 0);
signal cfg_mgmt_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_readonly : std_logic;
signal cfg_err_atomic_egress_blocked : std_logic;
signal cfg_err_internal_cor : std_logic;
signal cfg_err_malformed : std_logic;
signal cfg_err_mc_blocked : std_logic;
signal cfg_err_poisoned : std_logic;
signal cfg_err_norecovery : std_logic;
signal cfg_err_acs : std_logic;
signal cfg_err_internal_uncor : std_logic;
signal cfg_err_aer_headerlog : std_logic_vector(127 downto 0);
signal cfg_aer_interrupt_msgnum : std_logic_vector(4 downto 0);
signal cfg_err_aer_headerlog_set : std_logic;
signal cfg_aer_ecrc_check_en : std_logic;
signal cfg_aer_ecrc_gen_en : std_logic;
signal cfg_pm_halt_aspm_l0s : std_logic;
signal cfg_pm_halt_aspm_l1 : std_logic;
signal cfg_pm_force_state_en : std_logic;
signal cfg_pm_force_state : std_logic_vector(1 downto 0);
signal cfg_interrupt_stat : std_logic;
signal cfg_pciecap_interrupt_msgnum : std_logic_vector(4 downto 0);
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal sys_reset_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector(5 downto 0);
----- DDR core User Interface signals -----------------------
signal app_addr : std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal ddr_ui_clk : std_logic;
signal ddr_ui_reset : std_logic;
signal ddr_calib_done : std_logic;
begin
sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_rst_n
);
pcieclk_ibuf : IBUFDS_GTE2
port map (
O => sys_clk_c,
ODIV2 => open,
I => sys_clk_p,
IB => sys_clk_n,
CEB => '0'
);
cfg_err_cor <= '0';
cfg_err_ur <= '0';
cfg_err_ecrc <= '0';
cfg_err_cpl_timeout <= '0';
cfg_err_cpl_abort <= '0';
cfg_err_cpl_unexpect <= '0';
cfg_err_posted <= '1';
cfg_err_locked <= '1';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_trn_pending <= '0';
cfg_pm_wake <= '0';
--
fc_sel <= (others => '0');
pl_directed_link_auton <= '0';
pl_directed_link_change <= (others => '0');
pl_directed_link_speed <= '0';
pl_directed_link_width <= (others => '0');
pl_upstream_prefer_deemph <= '0';
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
--
cfg_di <= (others => '0');
cfg_dwaddr <= (others => '1');
cfg_mgmt_byte_en <= (others => '0');
cfg_mgmt_wr_en <= '0';
cfg_mgmt_rd_en <= '0';
cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
cfg_turnoff_ok <= '1';
localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
pcie_link_width <= cfg_lstatus(9 downto 4);
user_lnk_up_int_i : FDPE
generic map (
INIT => '0'
)
port map (
Q => user_lnk_up,
D => user_lnk_up_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
user_reset_i : FDPE
generic map (
INIT => '1'
)
port map (
Q => user_reset,
D => user_reset_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
-- --------------------------------------------------------------
-- --------------------------------------------------------------
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN,
PCIE_EXT_CLK => "FALSE",
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
--------------------------------------------------------------------------------------------------------------------
--TX
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- RX
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-------------------------------------------------------------------------------------------------------------------
-- 2. Clocking Interface - For Partial Reconfig Support --
-------------------------------------------------------------------------------------------------------------------
PIPE_PCLK_IN => PIPE_PCLK_IN,
PIPE_RXUSRCLK_IN => PIPE_RXUSRCLK_IN,
PIPE_RXOUTCLK_IN => PIPE_RXOUTCLK_IN,
PIPE_DCLK_IN => PIPE_DCLK_IN,
PIPE_USERCLK1_IN => PIPE_USERCLK1_IN,
PIPE_USERCLK2_IN => PIPE_USERCLK2_IN,
PIPE_OOBCLK_IN => PIPE_OOBCLK_IN,
PIPE_MMCM_LOCK_IN => PIPE_MMCM_LOCK_IN,
PIPE_TXOUTCLK_OUT => PIPE_TXOUTCLK_OUT,
PIPE_RXOUTCLK_OUT => PIPE_RXOUTCLK_OUT,
PIPE_PCLK_SEL_OUT => PIPE_PCLK_SEL_OUT,
PIPE_GEN3_OUT => PIPE_GEN3_OUT,
-------------------------------------------------------------------------------------------------------------------
-- 3. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out => user_clk ,
user_reset_out => user_reset_int1,
user_lnk_up => user_lnk_up_int1,
-- TX
tx_buf_av => tx_buf_av ,
tx_cfg_req => tx_cfg_req ,
tx_err_drop => tx_err_drop ,
s_axis_tx_tready => s_axis_tx_tready ,
s_axis_tx_tdata => s_axis_tx_tdata ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
s_axis_tx_tuser => s_axis_tx_tuser,
tx_cfg_gnt => tx_cfg_gnt ,
-- RX
m_axis_rx_tdata => m_axis_rx_tdata ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
m_axis_rx_tuser => m_axis_rx_tuser,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
-- Flow Control
fc_cpld => fc_cpld ,
fc_cplh => fc_cplh ,
fc_npd => fc_npd ,
fc_nph => fc_nph ,
fc_pd => fc_pd ,
fc_ph => fc_ph ,
fc_sel => fc_sel ,
-------------------------------------------------------------------------------------------------------------------
-- 4. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EP and RP --
---------------------------------------------------------------------
cfg_mgmt_do => open ,
cfg_mgmt_rd_wr_done => open ,
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => cfg_dcommand2 ,
cfg_pcie_link_state => cfg_pcie_link_state ,
cfg_pmcsr_pme_en => open ,
cfg_pmcsr_pme_status => open ,
cfg_pmcsr_powerstate => open ,
cfg_received_func_lvl_rst => open ,
cfg_mgmt_di => cfg_mgmt_di ,
cfg_mgmt_byte_en => cfg_mgmt_byte_en ,
cfg_mgmt_dwaddr => cfg_mgmt_dwaddr ,
cfg_mgmt_wr_en => cfg_mgmt_wr_en ,
cfg_mgmt_rd_en => cfg_mgmt_rd_en ,
cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly ,
cfg_err_ecrc => cfg_err_ecrc ,
cfg_err_ur => cfg_err_ur ,
cfg_err_cpl_timeout => cfg_err_cpl_timeout ,
cfg_err_cpl_unexpect => cfg_err_cpl_unexpect ,
cfg_err_cpl_abort => cfg_err_cpl_abort ,
cfg_err_posted => cfg_err_posted ,
cfg_err_cor => cfg_err_cor ,
cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked ,
cfg_err_internal_cor => cfg_err_internal_cor ,
cfg_err_malformed => cfg_err_malformed ,
cfg_err_mc_blocked => cfg_err_mc_blocked ,
cfg_err_poisoned => cfg_err_poisoned ,
cfg_err_norecovery => cfg_err_norecovery ,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
cfg_err_locked => cfg_err_locked ,
cfg_err_acs => cfg_err_acs ,
cfg_err_internal_uncor => cfg_err_internal_uncor ,
cfg_trn_pending => cfg_trn_pending ,
cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s ,
cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1 ,
cfg_pm_force_state_en => cfg_pm_force_state_en ,
cfg_pm_force_state => cfg_pm_force_state ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_assert => cfg_interrupt_assert ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_stat => cfg_interrupt_stat ,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum ,
cfg_to_turnoff => cfg_to_turnoff ,
cfg_turnoff_ok => cfg_turnoff_ok ,
cfg_bus_number => cfg_bus_number ,
cfg_device_number => cfg_device_number ,
cfg_function_number => cfg_function_number ,
cfg_pm_wake => cfg_pm_wake ,
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
cfg_pm_send_pme_to => '0' ,
cfg_ds_bus_number => x"00" ,
cfg_ds_device_number => "00000" ,
cfg_ds_function_number => "000" ,
cfg_mgmt_wr_rw1c_as_rw => '0' ,
cfg_msg_received => open ,
cfg_msg_data => open ,
cfg_bridge_serr_en => open ,
cfg_slot_control_electromech_il_ctl_pulse => open ,
cfg_root_control_syserr_corr_err_en => open ,
cfg_root_control_syserr_non_fatal_err_en => open ,
cfg_root_control_syserr_fatal_err_en => open ,
cfg_root_control_pme_int_en => open ,
cfg_aer_rooterr_corr_err_reporting_en => open ,
cfg_aer_rooterr_non_fatal_err_reporting_en => open ,
cfg_aer_rooterr_fatal_err_reporting_en => open ,
cfg_aer_rooterr_corr_err_received => open ,
cfg_aer_rooterr_non_fatal_err_received => open ,
cfg_aer_rooterr_fatal_err_received => open ,
cfg_msg_received_err_cor => open ,
cfg_msg_received_err_non_fatal => open ,
cfg_msg_received_err_fatal => open ,
cfg_msg_received_pm_as_nak => open ,
cfg_msg_received_pm_pme => open ,
cfg_msg_received_pme_to_ack => open ,
cfg_msg_received_assert_int_a => open ,
cfg_msg_received_assert_int_b => open ,
cfg_msg_received_assert_int_c => open ,
cfg_msg_received_assert_int_d => open ,
cfg_msg_received_deassert_int_a => open ,
cfg_msg_received_deassert_int_b => open ,
cfg_msg_received_deassert_int_c => open ,
cfg_msg_received_deassert_int_d => open ,
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
pl_sel_lnk_rate => pl_sel_lnk_rate ,
pl_sel_lnk_width => pl_sel_lnk_width ,
pl_ltssm_state => pl_ltssm_state ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
pl_phy_lnk_up => open ,
pl_tx_pm_state => open ,
pl_rx_pm_state => open ,
cfg_dsn => cfg_dsn ,
pl_link_upcfg_cap => pl_link_upcfg_cap ,
pl_link_gen2_cap => pl_link_gen2_cap ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_initial_link_width => pl_initial_link_width ,
pl_directed_change_done => open ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst => pl_received_hot_rst ,
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
pl_transmit_hot_rst => '0' ,
pl_downstream_deemph_source => '0' ,
-------------------------------------------------------------------------------------------------------------------
-- 6. AER interface --
-------------------------------------------------------------------------------------------------------------------
cfg_err_aer_headerlog => cfg_err_aer_headerlog ,
cfg_aer_interrupt_msgnum => cfg_aer_interrupt_msgnum ,
cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set ,
cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en ,
cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en ,
-------------------------------------------------------------------------------------------------------------------
-- 7. VC interface --
-------------------------------------------------------------------------------------------------------------------
cfg_vc_tcvc_map => open ,
-------------------------------------------------------------------------------------------------------------------
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
pipe_mmcm_rst_n => sys_reset_n_c,
sys_clk => sys_clk_c ,
sys_rst_n => sys_reset_n_c
);
-- ---------------------------------------------------------------
-- tlp control module
-- ---------------------------------------------------------------
-- workaround pcie core bug
--m_axis_rx_tkeep(7 downto 1) <= X"0" & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0);
theTlpControl :
tlpControl
port map (
-- Wishbone FIFO interface
wb_FIFO_we => wb_wr_we , -- OUT std_logic;
wb_FIFO_wsof => wb_wr_wsof , -- OUT std_logic;
wb_FIFO_weof => wb_wr_weof , -- OUT std_logic;
wb_FIFO_din => wb_wr_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full => wb_wr_full,
wb_FIFO_re => wb_rdd_ren , -- OUT std_logic;
wb_FIFO_empty => wb_rdd_empty , -- IN std_logic;
wb_FIFO_qout => wb_rdd_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, --out std_logic;
wb_rdc_v => wb_rdc_v, --out std_logic;
wb_rdc_din => wb_rdc_din, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --in std_logic;
wb_timeout => wb_timeout,
wb_FIFO_Rst => wb_fifo_rst, -- OUT std_logic;
-------------------
-- DDR Interface
DDR_Ready => DDR_Ready , -- IN std_logic;
DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
DDR_wr_v => DDR_wr_v , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-------------------
-- Transaction Interface
user_lnk_up => user_lnk_up ,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
s_axis_tx_tdsc => s_axis_tx_tdsc ,
tx_buf_av => tx_buf_av ,
s_axis_tx_terrfwd => s_axis_tx_terrfwd ,
user_clk => user_clk ,
user_reset => user_reset ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
s_axis_tx_tready => s_axis_tx_tready ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_terrfwd => m_axis_rx_terrfwd ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tdata => m_axis_rx_tdata ,
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_assert => cfg_interrupt_assert ,
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tdata => s_axis_tx_tdata ,
cfg_dcommand => cfg_dcommand ,
pcie_link_width => pcie_link_width ,
localId => localId
);
-- -----------------------------------------------------------------------
-- DDR SDRAM: control module
-- -----------------------------------------------------------------------
LoopBack_BRAM_Off : if not USE_LOOPBACK_TEST generate
DDRs_ctrl_module : DDR_Transact
generic map (
SIMULATION => SIMULATION,
DATA_WIDTH => C_DBUS_WIDTH,
ADDR_WIDTH => DDR_ADDR_WIDTH,
DDR_UI_DATAWIDTH => DDR_PAYLOAD_WIDTH,
DDR_DQ_WIDTH => DDR_DQ_WIDTH,
DEVICE_TYPE => "KINTEX7"
)
port map(
memc_ui_clk => memc_ui_clk, --: out std_logic;
memc_cmd_rdy => memc_cmd_rdy, --: out std_logic;
memc_cmd_en => memc_cmd_en, --: in std_logic;
memc_cmd_instr => memc_cmd_instr, --: in std_logic_vector(2 downto 0);
memc_cmd_addr => memc_cmd_addr, --: in std_logic_vector(31 downto 0);
memc_wr_en => memc_wr_en, --: in std_logic;
memc_wr_end => memc_wr_end, --: in std_logic;
memc_wr_mask => memc_wr_mask, --: in std_logic_vector(64/8-1 downto 0);
memc_wr_data => memc_wr_data, --: in std_logic_vector(64-1 downto 0);
memc_wr_rdy => memc_wr_rdy, --: out std_logic;
memc_rd_data => memc_rd_data, --: out std_logic_vector(64-1 downto 0);
memc_rd_valid => memc_rd_valid, --: out std_logic;
memarb_acc_req => memarb_acc_req, --: in std_logic;
memarb_acc_gnt => memarb_acc_gnt, --: out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready, -- OUT std_logic;
-- DDR core User Interface signals
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
init_calib_complete => ddr_calib_done,
--clocking & reset
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
LoopBack_BRAM_On : if USE_LOOPBACK_TEST generate
DDRs_ctrl_module :
bram_DDRs_Control_loopback
generic map (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => false
)
port map(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_FA => '0', -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_FA => '0', -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => open, -- OUT std_logic;
mem_clk => user_clk , -- IN
user_clk => user_clk , -- IN std_logic;
Sim_Zeichen => open , -- OUT std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
Wishbone_intf :
wb_transact
port map(
-- PCIE user clk
user_clk => user_clk, --in std_logic;
-- Write port
wr_we => wb_wr_we, --in std_logic;
wr_sof => wb_wr_wsof, --in std_logic;
wr_eof => wb_wr_weof, --in std_logic;
wr_din => wb_wr_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full => wb_wr_full, --out std_logic;
-- Read command port
rdc_sof => wb_rdc_sof, --in std_logic;
rdc_v => wb_rdc_v, --in std_logic;
rdc_din => wb_rdc_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full => wb_rdc_full,--out std_logic;
rd_tout => wb_timeout,
-- Read data port
rd_ren => wb_rdd_ren, --in std_logic;
rd_empty => wb_rdd_empty, --out std_logic;
rd_dout => wb_rdd_dout, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk => wbone_clk, --in std_logic;
wb_rst => wbone_rst, --in std_logic;
addr_o => wbone_addr(28 downto 0), --out std_logic_vector(31 downto 0);
dat_i => wbone_mdin, --in std_logic_vector(63 downto 0);
dat_o => wbone_mdout, --out std_logic_vector(63 downto 0);
we_o => wbone_we, --out std_logic;
sel_o => wbone_sel, --out std_logic_vector(0 downto 0);
stb_o => wbone_stb, --out std_logic;
ack_i => wbone_ack, --in std_logic;
cyc_o => wbone_cyc, --out std_logic;
--RESET from PCIe
rst => user_reset --in std_logic
);
wbone_clk <= CLK_I;
wbone_rst <= RST_I;
wbone_mdin <= DAT_I;
wbone_ack <= ACK_I;
ADDR_O <= wbone_addr;
DAT_O <= wbone_mdout;
WE_O <= wbone_we;
SEL_O <= wbone_sel(0);
STB_O <= wbone_stb;
CYC_O <= wbone_cyc;
ext_rst_o <= wb_fifo_rst;
u_ddr_core : ddr_core
generic map (
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
RST_ACT_LOW => 1
)
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => ddr_calib_done,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => app_sr_active,
app_ref_req => '0',
app_ref_ack => app_ref_ack,
app_zq_req => '0',
app_zq_ack => app_zq_ack,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
-- System Clock Ports
sys_clk_p => ddr_sys_clk_p,
sys_clk_n => ddr_sys_clk_n,
-- Reference Clock Ports
--clk_ref_i => ddr_ref_clk,
sys_rst => sys_reset_n_c
);
memc_ui_rst <= ddr_ui_reset;
end Behavioral;
|
library ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity testeabc is
port( clk : in std_logic;
reset : in std_logic;
breakIn : in std_logic;
mudouClock : in std_logic;
breakOut : out std_logic
);
end testeabc;
ARCHITECTURE ab of testeabc is
begin
process(clk, reset)
variable estadoAnterior : std_logic;
variable estado : std_logic_vector(3 downto 0);
begin
if(reset = '1') then
estadoAnterior := '0';
estado := x"0";
elsif(clk'event and clk = '1') then
if(estado = x"0") then
if(breakIn = not estadoAnterior) then
breakOut <= '1';
end if;
if(mudouClock = '0') then -- mudouClock = 0 -> clock manual
estado := x"1";
end if;
elsif (estado = x"1") then
if(mudouClock = '1') then
estadoAnterior := breakIn;
estado := x"0";
breakOut <= '0';
end if;
end if;
end if;
end process;
end ab;
|
library ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity testeabc is
port( clk : in std_logic;
reset : in std_logic;
breakIn : in std_logic;
mudouClock : in std_logic;
breakOut : out std_logic
);
end testeabc;
ARCHITECTURE ab of testeabc is
begin
process(clk, reset)
variable estadoAnterior : std_logic;
variable estado : std_logic_vector(3 downto 0);
begin
if(reset = '1') then
estadoAnterior := '0';
estado := x"0";
elsif(clk'event and clk = '1') then
if(estado = x"0") then
if(breakIn = not estadoAnterior) then
breakOut <= '1';
end if;
if(mudouClock = '0') then -- mudouClock = 0 -> clock manual
estado := x"1";
end if;
elsif (estado = x"1") then
if(mudouClock = '1') then
estadoAnterior := breakIn;
estado := x"0";
breakOut <= '0';
end if;
end if;
end if;
end process;
end ab;
|
library ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity testeabc is
port( clk : in std_logic;
reset : in std_logic;
breakIn : in std_logic;
mudouClock : in std_logic;
breakOut : out std_logic
);
end testeabc;
ARCHITECTURE ab of testeabc is
begin
process(clk, reset)
variable estadoAnterior : std_logic;
variable estado : std_logic_vector(3 downto 0);
begin
if(reset = '1') then
estadoAnterior := '0';
estado := x"0";
elsif(clk'event and clk = '1') then
if(estado = x"0") then
if(breakIn = not estadoAnterior) then
breakOut <= '1';
end if;
if(mudouClock = '0') then -- mudouClock = 0 -> clock manual
estado := x"1";
end if;
elsif (estado = x"1") then
if(mudouClock = '1') then
estadoAnterior := breakIn;
estado := x"0";
breakOut <= '0';
end if;
end if;
end if;
end process;
end ab;
|
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