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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1758.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p02n01i01758ent IS
END c09s05b01x00p02n01i01758ent;
ARCHITECTURE c09s05b01x00p02n01i01758arch OF c09s05b01x00p02n01i01758ent IS
signal A,B : bit;
BEGIN
CONSIG: A <= transport '1' when B = '1' else
transport '0'; -- Failure_here
-- an option not allowed.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b01x00p02n01i01758 - An option can not insert in conditional waveforms."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b01x00p02n01i01758arch;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.3.6 drop iist
-- 2018-09-22 1050 1.3.5 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.4 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.3.3 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-01-29 847 1.3.2 add sys_conf_ibd_deuna
-- 2016-05-28 770 1.3.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2014-12-22 619 1.1.2 add _rbmon_awidth
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
-- 2008-02-23 118 1.1 add memory config
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte
--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : natural := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
end package sys_conf;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_177 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_177;
architecture augh of add_177 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_177 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_177;
architecture augh of add_177 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
use work.pico_cpu.all;
entity PicoCPU is
port(
rst: in std_logic;
clk: in std_logic;
FlagOut: out std_logic_vector ( 3 downto 0);
output: out std_logic_vector ( CPU_Bitwidth-1 downto 0)
);
end PicoCPU;
architecture RTL of PicoCPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal Instr: std_logic_vector (CPU_Instwidth-1 downto 0):= (others=>'0');
signal InstrAdd , Mem_Rd_Address, Mem_Wrt_Address, DPUData, MEMDATA, DPU_Result: std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0');
signal MemRW: std_logic := '0';
signal DPUFlags: std_logic_vector (3 downto 0):= (others=>'0');
signal DPUCommand : std_logic_vector (10 downto 0):= (others=>'0');
signal Reg_in_sel: std_logic_vector (7 downto 0):= (others=>'0');
signal Reg_out_sel: std_logic_vector (2 downto 0):= (others=>'0');
begin
---------------------------------------------
-- component instantiation
---------------------------------------------
ControlUnit_comp: ControlUnit
generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth)
port map (rst, clk, Instr ,InstrAdd , Mem_Rd_Address, Mem_Wrt_Address , MemRW, DPUFlags, DPUData,DPUCommand,Reg_in_sel,Reg_out_sel,DPU_Result);
--instruction memory
InstMem_comp: InstMem
generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth)
port map (InstrAdd,Instr);
--datapath unit
DPU_comp: DPU
generic map (BitWidth => CPU_Bitwidth)
port map (MEMDATA, DPUData, clk,DPUCommand,Reg_in_sel,Reg_out_sel,rst,DPUFlags,DPU_Result);
--memory
Mem_comp: Mem
generic map (BitWidth => CPU_Bitwidth)
port map (Mem_Rd_Address, DPU_Result, Mem_Wrt_Address, clk,MemRW , rst , MEMDATA);
FlagOut <= DPUFlags;
output <= DPU_Result;
end RTL;
|
-- https://github.com/ghdl/ghdl/issues/2097
library IEEE;
context IEEE.IEEE_std_context;
package my_fixed_pkg is new IEEE.fixed_generic_pkg;
--!
library IEEE;
context IEEE.IEEE_std_context;
library work;
use work.my_fixed_pkg.all;
entity ieee9 is
end;
architecture arch of ieee9 is
begin
process
subtype stype is sfixed(7 downto -8);
-- Subtype not allowed as size_res argument of to_sfixed:
-- constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(-9.96484375, stype));
-- Therefore, a variable needs to be created:
variable fmt : stype;
constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(-9.96484375, fmt));
variable sfmt : fmt'subtype;
procedure report_sfixed(arg: sfixed) is begin report to_string(to_real(arg)); end procedure;
begin
report_sfixed(stype(input));
report_sfixed(stype(signed(input)));
-- CRASH
report_sfixed(fmt'subtype(input));
-- CRASH
report_sfixed(fmt'subtype(signed(input)));
-- CRASH
--report to_string(fmt'subtype);
-- However, sfmt, which is declared using fmt'subtype, does work
sfmt := stype(input);
report_sfixed(sfmt);
wait;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx" and "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_loopback_tb is
end entity uart_loopback_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_loopback_tb is
-- component ports
signal txd : std_logic;
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal rxd : std_logic := '1';
signal data_recv : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut_tx : entity work.uart_tx
port map (
txd_p => txd,
data_p => data_out,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
dut_rx : entity work.uart_rx
port map (
rxd_p => rxd,
data_p => data_recv,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
disable_p => '0',
clk => clk);
rxd <= txd;
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 60 ns;
end process bitclock;
clk_rx_en <= '1';
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data_out <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data_out <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data_out <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data_out <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data_out <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx" and "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_loopback_tb is
end entity uart_loopback_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_loopback_tb is
-- component ports
signal txd : std_logic;
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal rxd : std_logic := '1';
signal data_recv : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut_tx : entity work.uart_tx
port map (
txd_p => txd,
data_p => data_out,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
dut_rx : entity work.uart_rx
port map (
rxd_p => rxd,
data_p => data_recv,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
disable_p => '0',
clk => clk);
rxd <= txd;
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 60 ns;
end process bitclock;
clk_rx_en <= '1';
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data_out <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data_out <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data_out <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data_out <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data_out <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
|
------------------------------------------------------------------------------
-- priority encoder with mask input and match output
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity match_encoder is
port
(
i_multi_match : in std_logic_vector(31 downto 0);
i_mask : in std_logic_vector(31 downto 0);
o_match : out std_logic;
o_match_addr : out std_logic_vector(4 downto 0)
);
-- force priority encoder macro extraction:
--
-- attribute priority_extract: string;
-- attribute priority_extract of match_encoder: entity is "force";
end entity;
architecture imp of match_encoder is
signal m : std_logic_vector(31 downto 0);
begin
m <= i_multi_match and i_mask;
o_match <= '0' when m = X"00000000" else '1';
o_match_addr <= "00000" when m( 0) = '1' else
"00001" when m( 1) = '1' else
"00010" when m( 2) = '1' else
"00011" when m( 3) = '1' else
"00100" when m( 4) = '1' else
"00101" when m( 5) = '1' else
"00110" when m( 6) = '1' else
"00111" when m( 7) = '1' else
"01000" when m( 8) = '1' else
"01001" when m( 9) = '1' else
"01010" when m(10) = '1' else
"01011" when m(11) = '1' else
"01100" when m(12) = '1' else
"01101" when m(13) = '1' else
"01110" when m(14) = '1' else
"01111" when m(15) = '1' else
"10000" when m(16) = '1' else
"10001" when m(17) = '1' else
"10010" when m(18) = '1' else
"10011" when m(19) = '1' else
"10100" when m(20) = '1' else
"10101" when m(21) = '1' else
"10110" when m(22) = '1' else
"10111" when m(23) = '1' else
"11000" when m(24) = '1' else
"11001" when m(25) = '1' else
"11010" when m(26) = '1' else
"11011" when m(27) = '1' else
"11100" when m(28) = '1' else
"11101" when m(29) = '1' else
"11110" when m(30) = '1' else
"11111" when m(31) = '1' else
"-----";
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix
-- system_ov7670_controller_1_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package iec_bus_bfm_pkg is
type t_iec_bus_bfm_object;
type p_iec_bus_bfm_object is access t_iec_bus_bfm_object;
type t_iec_status is (ok, no_devices, no_response, timeout, no_eoi_ack);
type t_iec_state is (idle, talker, listener);
type t_iec_command is (none, send_atn, send_msg, atn_to_listen, send_drf);
type t_iec_data is array(natural range <>) of std_logic_vector(7 downto 0);
type t_iec_message is record
data : t_iec_data(0 to 256);
len : integer;
end record;
type t_iec_to_bfm is
record
command : t_iec_command;
end record;
type t_iec_from_bfm is
record
busy : boolean;
end record;
constant c_iec_to_bfm_init : t_iec_to_bfm := (
command => none );
constant c_iec_from_bfm_init : t_iec_from_bfm := (
busy => false );
type t_iec_bus_bfm_object is record
next_bfm : p_iec_bus_bfm_object;
name1 : string(1 to 256);
name2 : string(1 to 256);
-- interface to the user
status : t_iec_status;
state : t_iec_state;
stopped : boolean;
sample_time : time;
-- buffer
msg_buf : t_iec_message;
-- internal to bfm
to_bfm : t_iec_to_bfm;
-- internal from bfm
from_bfm : t_iec_from_bfm;
end record;
constant c_atn_to_ckl : time := 5 us;
constant c_atn_resp_max : time := 1000 us;
constant c_non_eoi : time := 40 us;
constant c_clk_low : time := 50 us;
constant c_clk_high : time := 50 us;
constant c_frame_hs_max : time := 1000 us;
constant c_frame_release : time := 20 us;
constant c_byte_to_byte : time := 100 us;
constant c_eoi_min : time := 200 us;
constant c_eoi : time := 500 us; -- was 250
constant c_eoi_hold : time := 60 us;
constant c_tlkr_resp_dly : time := 60 us; -- max
constant c_talk_atn_rel : time := 30 us;
constant c_talk_atn_ack : time := 250 us; -- ?
constant c_fast_serial : time := 10 us;
------------------------------------------------------------------------------------
shared variable iec_bus_bfms : p_iec_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_iec_bus_bfm(name1, name2 : string; variable pntr: inout p_iec_bus_bfm_object);
procedure bind_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
------------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_drf(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0);
atn_off : boolean := false);
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string);
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message);
procedure iec_print_message(variable msg : inout t_iec_message);
end iec_bus_bfm_pkg;
package body iec_bus_bfm_pkg is
procedure register_iec_bus_bfm(name1, name2 : string;
variable pntr : inout p_iec_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_iec_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name1(name1'range) := name1;
pntr.name2(name2'range) := name2;
pntr.status := ok;
pntr.state := idle;
pntr.stopped := false; -- active;
pntr.sample_time := 1 us;
pntr.to_bfm := c_iec_to_bfm_init;
pntr.from_bfm := c_iec_from_bfm_init;
-- add this pointer to the head of the linked list
if iec_bus_bfms = null then -- first entry
iec_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := iec_bus_bfms;
iec_bus_bfms := pntr;
end if;
end register_iec_bus_bfm;
procedure bind_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
variable p : p_iec_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := iec_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name1(named'range) = named or p.name2(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_iec_bus_bfm;
------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.stopped := true;
end procedure;
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := talker;
end procedure;
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := listener;
end procedure;
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0);
atn_off : boolean := false) is
begin
bfm.msg_buf.data(0) := byte;
bfm.msg_buf.len := 1;
if atn_off then
bfm.msg_buf.data(1) := X"01";
else
bfm.msg_buf.data(1) := X"00";
end if;
bfm.to_bfm.command := send_atn;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := atn_to_listen;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_drf(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := send_drf;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message) is
begin
bfm.msg_buf := msg;
bfm.to_bfm.command := send_msg;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string) is
variable leng : integer;
begin
leng := msg'length;
for i in 1 to leng loop
bfm.msg_buf.data(i-1) := std_logic_vector(to_unsigned(character'pos(msg(i)), 8));
end loop;
bfm.msg_buf.len := leng;
iec_send_message(bfm, bfm.msg_buf);
end procedure;
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message) is
begin
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.state = listener loop
wait for bfm.sample_time;
end loop;
msg := bfm.msg_buf;
end procedure;
procedure iec_print_message(variable msg : inout t_iec_message) is
variable L : line;
variable c : character;
begin
for i in 0 to msg.len-1 loop
c := character'val(to_integer(unsigned(msg.data(i))));
write(L, c);
end loop;
writeline(output, L);
end procedure;
end;
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iec_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity iec_bus_bfm is
generic (g_given_name : string := "iec_bfm");
port (
iec_clock : inout std_logic;
iec_data : inout std_logic;
iec_atn : inout std_logic;
iec_srq : inout std_logic );
end entity;
architecture bfm of iec_bus_bfm is
shared variable this : p_iec_bus_bfm_object := null;
signal bound : boolean := false;
signal clk_i : std_logic;
signal clk_o : std_logic;
signal data_i : std_logic;
signal data_o : std_logic;
signal atn_i : std_logic;
signal atn_o : std_logic;
signal srq_i : std_logic;
signal srq_o : std_logic;
signal fast_byte : std_logic_vector(7 downto 0) := X"00";
signal fast_byte_available : boolean;
signal fast_byte_reset : boolean;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_iec_bus_bfm(iec_bus_bfm'path_name, g_given_name, this);
bound <= true;
wait;
end process;
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
srq_i <= iec_srq and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_srq <= '0' when srq_o='0' else 'H';
-- |<--------- Byte sent under attention (to devices) ------------>|
--
-- ___ ____ _____ _____
-- ATN |________________________________________________________|
-- : :
-- ___ ______ ________ ___ ___ ___ ___ ___ ___ ___ ___ :
-- CLK : |_____| |_| |_| |_| |_| |_| |_| |_| |_| |______________ _____
-- : : : : :
-- : Tat : :Th: Tne : : Tf : Tr :
-- ____ ________ : : :___________________________________:____:
-- DATA ___|\\\\\__:__| |__||__||__||__||__||__||__||__| |_________ _____
-- : 0 1 2 3 4 5 6 7 :
-- : LSB MSB :
-- : : :
-- : : Data Valid Listener: Data Accepted
-- : Listener READY-FOR-DATA
protocol: process
procedure do_send_atn is
begin
atn_o <= '0';
wait for c_atn_to_ckl;
clk_o <= '0';
if data_i='1' then
wait until data_i='0' for c_atn_resp_max;
end if;
if data_i='1' then
this.status := no_devices;
return;
end if;
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= this.msg_buf.data(0)(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_frame_release;
if this.msg_buf.data(1)(0) = '1' then
atn_o <= '1';
end if;
end procedure;
procedure send_byte(byte : std_logic_vector(7 downto 0)) is
begin
atn_o <= '1';
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
end procedure;
procedure end_handshake(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
-- wait for c_eoi;
-- data_o <= '0';
-- wait for c_eoi_hold;
-- data_o <= '1';
wait until data_i='0' for c_eoi; -- wait for 250 �s to see that listener has acked eoi
if data_i='1' then
this.status := no_eoi_ack;
return;
end if;
wait until data_i='1'; -- wait for listener to be ready again
wait for c_tlkr_resp_dly;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
clk_o <= '1';
end procedure;
procedure do_send_drf is
begin
for i in 0 to 7 loop
srq_o <= '0';
wait for c_fast_serial;
srq_o <= '1';
wait for c_fast_serial;
end loop;
end procedure;
procedure talk_atn_turnaround is
begin
report "Start ATN Turnaround.";
atn_o <= '1';
wait for c_talk_atn_rel;
clk_o <= '1';
data_o <= '0';
wait for c_talk_atn_rel;
if clk_i /= '0' then
wait until clk_i = '0';
end if;
report "We are now listener.";
this.state := listener;
this.msg_buf.len := 0; -- clear buffer for incoming data
end procedure;
procedure receive_byte is
variable b : std_logic_vector(7 downto 0);
variable eoi : boolean;
-- variable c : character;
-- variable L : LINE;
begin
eoi := false;
if clk_i='0' then
wait until clk_i='1';
end if;
fast_byte_reset <= true;
wait for c_clk_low; -- dummy
data_o <= '1';
fast_byte_reset <= false;
-- check for end of message handshake (data pulses low after >200 �s for >60 �s)
wait until clk_i = '0' for c_eoi_min;
if clk_i='1' then -- eoi timeout
eoi := true;
-- ack eoi
data_o <= '0';
wait for c_eoi_hold;
data_o <= '1';
end if;
L1: for i in 0 to 7 loop
wait until clk_i='1' or fast_byte_available;
if fast_byte_available then
b := fast_byte;
exit L1;
end if;
b(i) := data_i;
end loop;
if not fast_byte_available then
wait until clk_i='0';
else
wait for c_fast_serial;
end if;
this.msg_buf.data(this.msg_buf.len) := b;
this.msg_buf.len := this.msg_buf.len + 1;
if eoi then
this.state := idle;
data_o <= '1';
else
data_o <= '0';
end if;
end procedure;
begin
atn_o <= '1';
data_o <= '1';
clk_o <= '1';
srq_o <= '1';
wait until bound;
while not this.stopped loop
wait for this.sample_time;
case this.to_bfm.command is
when none =>
null;
when send_atn =>
this.from_bfm.busy := true;
do_send_atn;
this.from_bfm.busy := false;
when send_msg =>
this.from_bfm.busy := true;
if this.msg_buf.len > 1 then
L1: for i in 0 to this.msg_buf.len-2 loop
send_byte(this.msg_buf.data(i));
if this.status /= ok then
exit L1;
end if;
end loop;
end if;
assert this.status = ok
report "Sending data message failed."
severity error;
end_handshake(this.msg_buf.data(this.msg_buf.len-1));
assert this.status = ok
report "Sending data message failed (Last Byte)."
severity error;
this.from_bfm.busy := false;
when atn_to_listen =>
this.from_bfm.busy := true;
talk_atn_turnaround;
this.from_bfm.busy := false;
when send_drf =>
this.from_bfm.busy := true;
do_send_drf;
this.from_bfm.busy := false;
end case;
this.to_bfm.command := none;
if this.state = listener then
receive_byte;
end if;
end loop;
wait;
end process;
process(srq_i, fast_byte_reset)
variable cnt : integer := 0;
begin
if fast_byte_reset then
cnt := 7;
fast_byte_available <= false;
elsif rising_edge(srq_i) then
if cnt >= 0 then
fast_byte(cnt) <= data_i;
end if;
if cnt = 0 then
fast_byte_available <= true;
end if;
cnt := cnt - 1;
end if;
end process;
-- if in idle state, and atn_i becomes '0', then become device and listen
-- but that is only needed for devices... (not for the controller)
-- if listener (means that I am addressed), listen to all bytes
-- if end of message is detected, switch back to idle state.
end architecture;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity clock_generator_vvc is
generic (
GC_INSTANCE_IDX : natural := 1;
GC_CLOCK_NAME : string := "clk";
GC_CLOCK_PERIOD : time := 10 ns;
GC_CLOCK_HIGH_TIME : time := 5 ns;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : out std_logic
);
begin
assert (GC_CLOCK_NAME'length <= C_MAX_VVC_NAME_LENGTH) report "Clock name is too long (max " & to_string(C_MAX_VVC_NAME_LENGTH) & " characters)" severity ERROR;
end entity clock_generator_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of clock_generator_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
signal clock_ena : boolean := false;
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_clock_generator_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_clock_generator_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_clock_generator_transaction_info(GC_INSTANCE_IDX);
alias clock_name : string is vvc_config.clock_name;
alias clock_period : time is vvc_config.clock_period;
alias clock_high_time : time is vvc_config.clock_high_time;
impure function get_clock_name
return string is
begin
return clock_name(1 to pos_of_leftmost(NUL, clock_name, clock_name'length));
end function;
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, C_VOID_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Config initializer
-- - Set up the VVC specific config fields
--========================================================================================================================
config_initializer : process
begin
loop
wait for 0 ns;
exit when shared_uvvm_state = PHASE_B;
end loop;
clock_name := (others => NUL);
clock_name(1 to GC_CLOCK_NAME'length) := GC_CLOCK_NAME;
clock_period := GC_CLOCK_PERIOD;
clock_high_time := GC_CLOCK_HIGH_TIME;
wait;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity. Note that clock generator VVC activity is not included in the resetting of the VVC activity register!
-- update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity. Note that clock generator VVC activity is not included in the resetting of the VVC activity register!
-- update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when START_CLOCK =>
if clock_ena then
tb_error("Clock " & clock_name & " already running. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= true;
wait for 0 ns;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' started", C_SCOPE);
end if;
when STOP_CLOCK =>
if not clock_ena then
tb_error("Clock '" & clock_name & "' already stopped. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= false;
if clk then
wait until not clk;
end if;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' stopped", C_SCOPE);
end if;
when SET_CLOCK_PERIOD =>
clock_period := v_cmd.clock_period;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' period set to " & to_string(clock_period), C_SCOPE);
when SET_CLOCK_HIGH_TIME =>
clock_high_time := v_cmd.clock_high_time;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' high time set to " & to_string(clock_high_time), C_SCOPE);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
--========================================================================================================================
-- Clock Generator process
-- - Process that generates the clock signal
--========================================================================================================================
clock_generator : process
variable v_clock_period : time;
variable v_clock_high_time : time;
begin
wait for 0 ns; -- wait for clock_ena to be set
loop
if not clock_ena then
clk <= '0';
wait until clock_ena;
end if;
-- Clock period is sampled so it won't change during a clock cycle and potentialy introduce negative time in
-- last wait statement
v_clock_period := clock_period;
v_clock_high_time := clock_high_time;
if v_clock_high_time >= v_clock_period then
tb_error(clock_name & ": clock period must be larger than clock high time; clock period: " & to_string(v_clock_period) & ", clock high time: " & to_string(clock_high_time), C_SCOPE);
end if;
clk <= '1';
wait for v_clock_high_time;
clk <= '0';
wait for (v_clock_period - v_clock_high_time);
end loop;
end process;
--========================================================================================================================
end architecture behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2pbw
-- File: syncram_2pbw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection and 8-bit write
-- strobes
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram_2pbw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram_2pbw is
constant nctrl : integer := abits*2 + 2 + 2*dbits/8;
signal dataoutx : std_logic_vector((dbits -1) downto 0);
signal databp, testdata : std_logic_vector((dbits -1) downto 0);
signal renable2 : std_logic_vector((dbits/8-1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
constant iwrfst : integer := (1-syncram_2p_write_through(tech)) * wrfst;
signal xrenable,xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xrenable <= renable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
s2pbw : if has_sram_2pbw(tech) = 1 generate
no_wrfst : if iwrfst = 0 generate
scanbp : if SCANTESTBP generate
comb : process (waddress, raddress, datain, renable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(1 downto 0) & write & renable & raddress & waddress;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then databp <= testdata; end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0 : grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(3), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
-- Write contention check (if applicable)
wcheck : for i in 0 to dbits/8-1 generate
renable2(i) <= '0' when ((sepclk = 0 and syncram_2p_dest_rw_collision(tech) = 1) and
(renable(i) and write(i)) = '1' and raddress = waddress) else renable(i);
end generate;
end generate;
wrfst_gen : if iwrfst = 1 generate
-- No risk for read/write contention. Register addresses and mux on comparator
no_contention_check : if syncram_2p_dest_rw_collision(tech) = 0 generate
wfrstblocknoc : block
type wrfst_type is record
raddr : std_logic_vector((abits-1) downto 0);
waddr : std_logic_vector((abits-1) downto 0);
datain : std_logic_vector((dbits-1) downto 0);
write : std_logic_vector((dbits/8-1) downto 0);
renable : std_logic_vector((dbits/8-1) downto 0);
end record;
signal r : wrfst_type;
begin
comb : process(r, dataoutx, testin) begin
for i in 0 to dbits/8-1 loop
if (SCANTESTBP and (testin(3) = '1')) or
(((r.write(i) and r.renable(i)) = '1') and (r.raddr = r.waddr)) then
dataout(i*8+7 downto i*8) <= r.datain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
r.raddr <= raddress; r.waddr <= waddress;
r.datain <= datain; r.write <= write;
r.renable <= renable;
end if;
end process;
end block wfrstblocknoc;
renable2 <= renable;
end generate;
-- Risk of read/write contention. Use same comparator to gate read enable
-- and mux data.
contention_safe : if syncram_2p_dest_rw_collision(tech) /= 0 generate
wfrstblockc : block
signal col, mux : std_logic_vector((dbits/8-1) downto 0);
signal rdatain : std_logic_vector((dbits-1) downto 0);
begin
comb : process(mux, renable, write, raddress, waddress, rdatain,
dataoutx, testin)
begin
for i in 0 to dbits/8-1 loop
col(i) <= '0'; renable2(i) <= renable(i);
if (write(i) and renable(i)) = '1' and raddress = waddress then
col(i) <= '1'; renable2(i) <= '0';
end if;
if (SCANTESTBP and (testin(3) = '1')) or mux(i) = '1' then
dataout(i*8+7 downto i*8) <= rdatain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
rdatain <= datain; mux <= col;
end if;
end process;
end block wfrstblockc;
end generate;
end generate wrfst_gen;
custominx <= (others => '0');
nocust: if has_sram_2pbw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_2p_be generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2pbw: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram_2pbw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
generic_check : process
begin
assert sepclk = 0 or wrfst = 0
report "syncram_2pbw: Write-first not supported for RAM with separate clocks"
severity failure;
wait;
end process;
-- pragma translate_on
end generate;
nos2pbw : if has_sram_2pbw(tech) /= 1 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram_2p generic map (tech, abits, 8, sepclk, wrfst, testen, words, custombits)
port map (rclk, renable(i), raddress, dataout(i*8+7 downto i*8), wclk, write(i),
waddress, datain(i*8+7 downto i*8), testin
);
end generate;
end generate;
end;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity DEBOUNCER is
port (
CLK : in std_logic;
BUTTON : in std_logic;
DOUT : out std_logic
);
end entity DEBOUNCER;
architecture BEHAVIORAL of DEBOUNCER is
signal counter, ncounter : std_logic_vector(23 downto 0) := x"000000";
signal buttonhistory, nbuttonhistory : std_logic_vector(1 downto 0) := "00";
signal nexthistory : std_logic := '0';
begin
ncounter <= x"FFFFFF" when counter=x"FFFFFF" and BUTTON='1' else
x"000000" when counter=x"000000" and BUTTON='0' else
counter + 1 when BUTTON='1' else
counter - 1;
nexthistory <= '0' when counter=x"000000" else
'1';
nbuttonhistory <= nexthistory & buttonhistory(1);
DOUT <= '1' when buttonhistory="01" else
'0';
process (CLK) is
begin
if (rising_edge(CLK)) then
counter <= ncounter;
buttonhistory <= nbuttonhistory;
end if;
end process;
end architecture BEHAVIORAL;
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_8x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A107: buffer std_logic
);
end x25_8x;
architecture x25_8x_behav of x25_8x is
signal a1a,a2a,a3a,a4a,a5a,a6a,a7a,a8a,a9a,a10a,a11a,a12a,a13a,a14a,a15a,a16a,a17a,a18a,a19a,a20a,a21a,a22a,a23a,a24a,a25a,a26a,a27a,a28a,a29a,a30a,a31a,a32a,a33a,a34a,a35a,a36a,a37a,a38a,a39a,a40a,a41a,a42a,a43a,a44a,a45a,a46a,a47a,a48a,a49a,a50a,a51a,a52a,a53a,a54a,a55a,a56a,a57a,a58a,a59a,a60a,a61a,a62a,a63a,a64a,a65a,a66a,a67a,a68a,a69a,a70a,a71a,a72a,a73a,a74a,a75a,a76a,a77a,a78a,a79a,a80a,a81a,a82a,a83a,a84a,a85a,a86a,a87a,a88a,a89a,a90a,a91a,a92a,a93a,a94a,a95a,a96a,a97a,a98a,a99a,a100a,a101a,a102a,a103a,a104a,a105a,a106a,a107a,a108a,a109a,a110a,a111a,a112a,a113a,a114a,a115a,a116a,a117a,a118a,a119a,a120a,a121a,a122a,a123a,a124a,a125a,a126a,a127a,a128a,a129a,a130a,a131a,a132a,a133a,a134a,a135a,a136a,a137a,a138a,a139a,a140a,a141a,a142a,a143a,a144a,a145a,a146a,a147a,a148a,a149a,a150a,a151a,a152a,a153a,a154a,a155a,a156a,a157a,a158a,a159a,a160a,a161a,a162a,a163a,a164a,a165a,a168a,a172a,a173a,a174a,a177a,a181a,a182a,a183a,a184a,a187a,a191a,a192a,a193a,a196a,a200a,a201a,a202a,a203a,a204a,a207a,a211a,a212a,a213a,a216a,a220a,a221a,a222a,a223a,a226a,a230a,a231a,a232a,a236a,a237a,a241a,a242a,a243a,a244a,a245a,a246a,a249a,a253a,a254a,a255a,a258a,a262a,a263a,a264a,a265a,a268a,a272a,a273a,a274a,a277a,a281a,a282a,a283a,a284a,a285a,a288a,a292a,a293a,a294a,a297a,a301a,a302a,a303a,a304a,a307a,a311a,a312a,a313a,a317a,a318a,a322a,a323a,a324a,a325a,a326a,a327a,a328a,a331a,a335a,a336a,a337a,a340a,a344a,a345a,a346a,a347a,a350a,a354a,a355a,a356a,a359a,a363a,a364a,a365a,a366a,a367a,a370a,a374a,a375a,a376a,a379a,a383a,a384a,a385a,a386a,a389a,a393a,a394a,a395a,a399a,a400a,a404a,a405a,a406a,a407a,a408a,a409a,a412a,a416a,a417a,a418a,a421a,a425a,a426a,a427a,a428a,a431a,a435a,a436a,a437a,a441a,a442a,a446a,a447a,a448a,a449a,a450a,a453a,a457a,a458a,a459a,a462a,a466a,a467a,a468a,a469a,a472a,a476a,a477a,a478a,a482a,a483a,a487a,a488a,a489a,a490a,a491a,a492a,a493a,a498a,a501a,a504a,a507a,a510a,a513a,a516a,a519a,a522a,a525a,a529a,a530a,a534a,a535a,a539a,a540a,a544a,a545a,a549a,a550a,a554a,a555a,a559a,a560a,a564a,a565a,a569a,a570a,a574a,a575a,a579a,a580a,a584a,a585a,a589a,a590a,a594a,a595a,a599a,a600a,a604a,a605a,a609a,a610a,a614a,a615a,a619a,a620a,a624a,a625a,a629a,a630a,a634a,a635a,a639a,a640a,a644a,a645a,a649a,a650a,a654a,a655a,a659a,a660a,a664a,a665a,a669a,a670a,a674a,a675a,a679a,a680a,a684a,a685a,a689a,a690a,a694a,a695a,a699a,a700a,a704a,a705a,a709a,a710a,a713a,a716a,a717a,a721a,a722a,a725a,a728a,a729a,a733a,a734a,a737a,a740a,a741a,a745a,a746a,a749a,a752a,a753a,a757a,a758a,a761a,a764a,a765a,a769a,a770a,a773a,a776a,a777a,a780a,a783a,a784a,a787a,a790a,a791a,a794a,a797a,a798a,a801a,a804a,a805a,a808a,a811a,a812a,a815a,a818a,a819a,a822a,a825a,a826a,a829a,a832a,a833a,a836a,a839a,a840a,a843a,a846a,a847a,a850a,a853a,a854a,a857a,a860a,a861a,a864a,a867a,a868a,a871a,a874a,a875a,a878a,a881a,a882a,a885a,a888a,a889a,a892a,a895a,a896a,a899a,a902a,a903a,a906a,a909a,a910a,a913a,a916a,a917a,a920a,a923a,a924a,a927a,a930a,a931a,a934a,a937a,a938a,a941a,a944a,a945a,a948a,a951a,a952a,a955a,a958a,a959a,a962a,a965a,a966a,a969a,a972a,a973a,a976a,a979a,a980a,a983a,a986a,a987a,a990a,a993a,a994a,a997a,a1000a,a1001a,a1004a,a1007a,a1008a,a1011a,a1014a,a1015a,a1018a,a1021a,a1022a,a1025a,a1028a,a1029a,a1032a,a1035a,a1036a,a1039a,a1042a,a1043a,a1046a,a1049a,a1050a,a1053a,a1056a,a1057a,a1060a,a1063a,a1064a,a1067a,a1070a,a1071a,a1074a,a1077a,a1078a,a1081a,a1084a,a1085a,a1088a,a1091a,a1092a,a1095a,a1098a,a1099a,a1102a,a1105a,a1106a,a1109a,a1112a,a1113a,a1116a,a1119a,a1120a,a1123a,a1126a,a1127a,a1130a,a1133a,a1134a,a1137a,a1140a,a1141a,a1144a,a1147a,a1148a,a1151a,a1154a,a1155a,a1158a,a1161a,a1162a,a1165a,a1168a,a1169a,a1172a,a1175a,a1176a,a1179a,a1182a,a1183a,a1186a,a1189a,a1190a,a1193a,a1196a,a1197a,a1200a,a1203a,a1204a,a1207a,a1210a,a1211a,a1214a,a1217a,a1218a,a1221a,a1224a,a1225a,a1228a,a1231a,a1232a,a1235a,a1238a,a1239a,a1242a,a1245a,a1246a,a1249a,a1252a,a1253a,a1256a,a1259a,a1260a,a1263a,a1266a,a1267a,a1270a,a1273a,a1274a,a1277a,a1280a,a1281a,a1284a,a1287a,a1288a,a1291a,a1294a,a1295a,a1298a,a1301a,a1302a,a1305a,a1308a,a1309a,a1312a,a1315a,a1316a,a1319a,a1322a,a1323a,a1326a,a1329a,a1330a,a1333a,a1337a,a1338a,a1339a,a1342a,a1345a,a1346a,a1349a,a1353a,a1354a,a1355a,a1358a,a1361a,a1362a,a1365a,a1369a,a1370a,a1371a,a1374a,a1377a,a1378a,a1381a,a1385a,a1386a,a1387a,a1390a,a1393a,a1394a,a1397a,a1401a,a1402a,a1403a,a1406a,a1409a,a1410a,a1413a,a1417a,a1418a,a1419a,a1422a,a1425a,a1426a,a1429a,a1433a,a1434a,a1435a,a1438a,a1441a,a1442a,a1445a,a1449a,a1450a,a1451a,a1454a,a1457a,a1458a,a1461a,a1465a,a1466a,a1467a,a1470a,a1473a,a1474a,a1477a,a1481a,a1482a,a1483a,a1486a,a1489a,a1490a,a1493a,a1497a,a1498a,a1499a,a1502a,a1505a,a1506a,a1509a,a1513a,a1514a,a1515a,a1518a,a1521a,a1522a,a1525a,a1529a,a1530a,a1531a,a1534a,a1537a,a1538a,a1541a,a1545a,a1546a,a1547a,a1550a,a1553a,a1554a,a1557a,a1561a,a1562a,a1563a,a1566a,a1569a,a1570a,a1573a,a1577a,a1578a,a1579a,a1582a,a1585a,a1586a,a1589a,a1593a,a1594a,a1595a,a1598a,a1601a,a1602a,a1605a,a1609a,a1610a,a1611a,a1614a,a1617a,a1618a,a1621a,a1625a,a1626a,a1627a,a1630a,a1633a,a1634a,a1637a,a1641a,a1642a,a1643a,a1646a,a1649a,a1650a,a1653a,a1657a,a1658a,a1659a,a1662a,a1665a,a1666a,a1669a,a1673a,a1674a,a1675a,a1678a,a1681a,a1682a,a1685a,a1689a,a1690a,a1691a,a1694a,a1697a,a1698a,a1701a,a1705a,a1706a,a1707a,a1710a,a1714a,a1715a,a1716a,a1719a,a1723a,a1724a,a1725a,a1728a,a1732a,a1733a,a1734a,a1737a,a1741a,a1742a,a1743a,a1746a,a1750a,a1751a,a1752a,a1755a,a1759a,a1760a,a1761a,a1764a,a1768a,a1769a,a1770a,a1773a,a1777a,a1778a,a1779a,a1782a,a1786a,a1787a,a1788a,a1791a,a1795a,a1796a,a1797a,a1800a,a1804a,a1805a,a1806a,a1809a,a1813a,a1814a,a1815a,a1818a,a1822a,a1823a,a1824a,a1827a,a1831a,a1832a,a1833a,a1836a,a1840a,a1841a,a1842a,a1845a,a1849a,a1850a,a1851a,a1854a,a1858a,a1859a,a1860a,a1863a,a1867a,a1868a,a1869a,a1872a,a1876a,a1877a,a1878a,a1881a,a1885a,a1886a,a1887a,a1890a,a1894a,a1895a,a1896a,a1899a,a1903a,a1904a,a1905a,a1908a,a1912a,a1913a,a1914a,a1917a,a1921a,a1922a,a1923a,a1926a,a1930a,a1931a,a1932a,a1935a,a1939a,a1940a,a1941a,a1944a,a1948a,a1949a,a1950a,a1953a,a1957a,a1958a,a1959a,a1962a,a1966a,a1967a,a1968a,a1971a,a1975a,a1976a,a1977a,a1980a,a1984a,a1985a,a1986a,a1989a,a1993a,a1994a,a1995a,a1998a,a2002a,a2003a,a2004a,a2007a,a2011a,a2012a,a2013a,a2016a,a2020a,a2021a,a2022a,a2025a,a2029a,a2030a,a2031a,a2034a,a2038a,a2039a,a2040a,a2043a,a2047a,a2048a,a2049a,a2052a,a2056a,a2057a,a2058a,a2061a,a2065a,a2066a,a2067a,a2070a,a2074a,a2075a,a2076a,a2079a,a2083a,a2084a,a2085a,a2088a,a2092a,a2093a,a2094a,a2097a,a2101a,a2102a,a2103a,a2106a,a2110a,a2111a,a2112a,a2115a,a2119a,a2120a,a2121a,a2124a,a2128a,a2129a,a2130a,a2133a,a2137a,a2138a,a2139a,a2142a,a2146a,a2147a,a2148a,a2151a,a2155a,a2156a,a2157a,a2160a,a2164a,a2165a,a2166a,a2169a,a2173a,a2174a,a2175a,a2178a,a2182a,a2183a,a2184a,a2187a,a2191a,a2192a,a2193a,a2196a,a2200a,a2201a,a2202a,a2205a,a2209a,a2210a,a2211a,a2214a,a2218a,a2219a,a2220a,a2223a,a2227a,a2228a,a2229a,a2232a,a2236a,a2237a,a2238a,a2241a,a2245a,a2246a,a2247a,a2250a,a2254a,a2255a,a2256a,a2259a,a2263a,a2264a,a2265a,a2268a,a2272a,a2273a,a2274a,a2277a,a2281a,a2282a,a2283a,a2286a,a2290a,a2291a,a2292a,a2295a,a2299a,a2300a,a2301a,a2304a,a2308a,a2309a,a2310a,a2313a,a2317a,a2318a,a2319a,a2322a,a2326a,a2327a,a2328a,a2331a,a2335a,a2336a,a2337a,a2340a,a2344a,a2345a,a2346a,a2349a,a2353a,a2354a,a2355a,a2358a,a2362a,a2363a,a2364a,a2368a,a2369a,a2373a,a2374a,a2375a,a2378a,a2382a,a2383a,a2384a,a2388a,a2389a,a2393a,a2394a,a2395a,a2398a,a2402a,a2403a,a2404a,a2408a,a2409a,a2413a,a2414a,a2415a,a2418a,a2422a,a2423a,a2424a,a2428a,a2429a,a2433a,a2434a,a2435a,a2438a,a2442a,a2443a,a2444a,a2448a,a2449a,a2453a,a2454a,a2455a,a2458a,a2462a,a2463a,a2464a,a2468a,a2469a,a2473a,a2474a,a2475a,a2478a,a2482a,a2483a,a2484a,a2488a,a2489a,a2493a,a2494a,a2495a,a2498a,a2502a,a2503a,a2504a,a2508a,a2509a,a2513a,a2514a,a2515a,a2518a,a2522a,a2523a,a2524a,a2528a,a2529a,a2533a,a2534a,a2535a,a2538a,a2542a,a2543a,a2544a,a2548a,a2549a,a2553a,a2554a,a2555a,a2558a,a2562a,a2563a,a2564a,a2568a,a2569a,a2573a,a2574a,a2575a,a2578a,a2582a,a2583a,a2584a,a2588a,a2589a,a2593a,a2594a,a2595a,a2598a,a2602a,a2603a,a2604a,a2608a,a2609a,a2613a,a2614a,a2615a,a2618a,a2622a,a2623a,a2624a,a2628a,a2629a,a2633a,a2634a,a2635a,a2638a,a2642a,a2643a,a2644a,a2648a,a2649a,a2653a,a2654a,a2655a,a2658a,a2662a,a2663a,a2664a,a2668a,a2669a,a2673a,a2674a,a2675a,a2678a,a2682a,a2683a,a2684a,a2688a,a2689a,a2693a,a2694a,a2695a,a2698a,a2702a,a2703a,a2704a,a2708a,a2709a,a2713a,a2714a,a2715a,a2718a,a2722a,a2723a,a2724a,a2728a,a2729a,a2733a,a2734a,a2735a,a2738a,a2742a,a2743a,a2744a,a2748a,a2749a,a2753a,a2754a,a2755a,a2758a,a2762a,a2763a,a2764a,a2768a,a2769a,a2773a,a2774a,a2775a,a2778a,a2782a,a2783a,a2784a,a2788a,a2789a,a2793a,a2794a,a2795a,a2798a,a2802a,a2803a,a2804a,a2808a,a2809a,a2813a,a2814a,a2815a,a2818a,a2822a,a2823a,a2824a,a2828a,a2829a,a2833a,a2834a,a2835a,a2839a,a2840a,a2844a,a2845a,a2846a,a2850a,a2851a,a2855a,a2856a,a2857a,a2861a,a2862a,a2866a,a2867a,a2868a,a2872a,a2873a,a2877a,a2878a,a2879a,a2883a,a2884a,a2888a,a2889a,a2890a,a2894a,a2895a,a2899a,a2900a,a2901a,a2905a,a2906a,a2910a,a2911a,a2912a,a2916a,a2917a,a2921a,a2922a,a2923a,a2927a,a2928a,a2932a,a2933a,a2934a,a2938a,a2939a,a2943a,a2944a,a2945a,a2949a,a2950a,a2954a,a2955a,a2956a,a2960a,a2961a,a2965a,a2966a,a2967a,a2971a,a2972a,a2976a,a2977a,a2978a,a2982a,a2983a,a2987a,a2988a,a2989a,a2993a,a2994a,a2998a,a2999a,a3000a,a3004a,a3005a,a3009a,a3010a,a3011a,a3015a,a3016a,a3020a,a3021a,a3022a,a3026a,a3027a,a3031a,a3032a,a3033a,a3037a,a3038a,a3042a,a3043a,a3044a,a3048a,a3049a,a3053a,a3054a,a3055a,a3059a,a3060a,a3064a,a3065a,a3066a,a3070a,a3071a,a3075a,a3076a,a3077a,a3081a,a3082a,a3086a,a3087a,a3088a,a3092a,a3093a,a3097a,a3098a,a3099a: std_logic;
begin
A107 <=( a493a ) or ( a328a );
a1a <=( a3099a and a3088a );
a2a <=( a3077a and a3066a );
a3a <=( a3055a and a3044a );
a4a <=( a3033a and a3022a );
a5a <=( a3011a and a3000a );
a6a <=( a2989a and a2978a );
a7a <=( a2967a and a2956a );
a8a <=( a2945a and a2934a );
a9a <=( a2923a and a2912a );
a10a <=( a2901a and a2890a );
a11a <=( a2879a and a2868a );
a12a <=( a2857a and a2846a );
a13a <=( a2835a and a2824a );
a14a <=( a2815a and a2804a );
a15a <=( a2795a and a2784a );
a16a <=( a2775a and a2764a );
a17a <=( a2755a and a2744a );
a18a <=( a2735a and a2724a );
a19a <=( a2715a and a2704a );
a20a <=( a2695a and a2684a );
a21a <=( a2675a and a2664a );
a22a <=( a2655a and a2644a );
a23a <=( a2635a and a2624a );
a24a <=( a2615a and a2604a );
a25a <=( a2595a and a2584a );
a26a <=( a2575a and a2564a );
a27a <=( a2555a and a2544a );
a28a <=( a2535a and a2524a );
a29a <=( a2515a and a2504a );
a30a <=( a2495a and a2484a );
a31a <=( a2475a and a2464a );
a32a <=( a2455a and a2444a );
a33a <=( a2435a and a2424a );
a34a <=( a2415a and a2404a );
a35a <=( a2395a and a2384a );
a36a <=( a2375a and a2364a );
a37a <=( a2355a and a2346a );
a38a <=( a2337a and a2328a );
a39a <=( a2319a and a2310a );
a40a <=( a2301a and a2292a );
a41a <=( a2283a and a2274a );
a42a <=( a2265a and a2256a );
a43a <=( a2247a and a2238a );
a44a <=( a2229a and a2220a );
a45a <=( a2211a and a2202a );
a46a <=( a2193a and a2184a );
a47a <=( a2175a and a2166a );
a48a <=( a2157a and a2148a );
a49a <=( a2139a and a2130a );
a50a <=( a2121a and a2112a );
a51a <=( a2103a and a2094a );
a52a <=( a2085a and a2076a );
a53a <=( a2067a and a2058a );
a54a <=( a2049a and a2040a );
a55a <=( a2031a and a2022a );
a56a <=( a2013a and a2004a );
a57a <=( a1995a and a1986a );
a58a <=( a1977a and a1968a );
a59a <=( a1959a and a1950a );
a60a <=( a1941a and a1932a );
a61a <=( a1923a and a1914a );
a62a <=( a1905a and a1896a );
a63a <=( a1887a and a1878a );
a64a <=( a1869a and a1860a );
a65a <=( a1851a and a1842a );
a66a <=( a1833a and a1824a );
a67a <=( a1815a and a1806a );
a68a <=( a1797a and a1788a );
a69a <=( a1779a and a1770a );
a70a <=( a1761a and a1752a );
a71a <=( a1743a and a1734a );
a72a <=( a1725a and a1716a );
a73a <=( a1707a and a1698a );
a74a <=( a1691a and a1682a );
a75a <=( a1675a and a1666a );
a76a <=( a1659a and a1650a );
a77a <=( a1643a and a1634a );
a78a <=( a1627a and a1618a );
a79a <=( a1611a and a1602a );
a80a <=( a1595a and a1586a );
a81a <=( a1579a and a1570a );
a82a <=( a1563a and a1554a );
a83a <=( a1547a and a1538a );
a84a <=( a1531a and a1522a );
a85a <=( a1515a and a1506a );
a86a <=( a1499a and a1490a );
a87a <=( a1483a and a1474a );
a88a <=( a1467a and a1458a );
a89a <=( a1451a and a1442a );
a90a <=( a1435a and a1426a );
a91a <=( a1419a and a1410a );
a92a <=( a1403a and a1394a );
a93a <=( a1387a and a1378a );
a94a <=( a1371a and a1362a );
a95a <=( a1355a and a1346a );
a96a <=( a1339a and a1330a );
a97a <=( a1323a and a1316a );
a98a <=( a1309a and a1302a );
a99a <=( a1295a and a1288a );
a100a <=( a1281a and a1274a );
a101a <=( a1267a and a1260a );
a102a <=( a1253a and a1246a );
a103a <=( a1239a and a1232a );
a104a <=( a1225a and a1218a );
a105a <=( a1211a and a1204a );
a106a <=( a1197a and a1190a );
a107a <=( a1183a and a1176a );
a108a <=( a1169a and a1162a );
a109a <=( a1155a and a1148a );
a110a <=( a1141a and a1134a );
a111a <=( a1127a and a1120a );
a112a <=( a1113a and a1106a );
a113a <=( a1099a and a1092a );
a114a <=( a1085a and a1078a );
a115a <=( a1071a and a1064a );
a116a <=( a1057a and a1050a );
a117a <=( a1043a and a1036a );
a118a <=( a1029a and a1022a );
a119a <=( a1015a and a1008a );
a120a <=( a1001a and a994a );
a121a <=( a987a and a980a );
a122a <=( a973a and a966a );
a123a <=( a959a and a952a );
a124a <=( a945a and a938a );
a125a <=( a931a and a924a );
a126a <=( a917a and a910a );
a127a <=( a903a and a896a );
a128a <=( a889a and a882a );
a129a <=( a875a and a868a );
a130a <=( a861a and a854a );
a131a <=( a847a and a840a );
a132a <=( a833a and a826a );
a133a <=( a819a and a812a );
a134a <=( a805a and a798a );
a135a <=( a791a and a784a );
a136a <=( a777a and a770a );
a137a <=( a765a and a758a );
a138a <=( a753a and a746a );
a139a <=( a741a and a734a );
a140a <=( a729a and a722a );
a141a <=( a717a and a710a );
a142a <=( a705a and a700a );
a143a <=( a695a and a690a );
a144a <=( a685a and a680a );
a145a <=( a675a and a670a );
a146a <=( a665a and a660a );
a147a <=( a655a and a650a );
a148a <=( a645a and a640a );
a149a <=( a635a and a630a );
a150a <=( a625a and a620a );
a151a <=( a615a and a610a );
a152a <=( a605a and a600a );
a153a <=( a595a and a590a );
a154a <=( a585a and a580a );
a155a <=( a575a and a570a );
a156a <=( a565a and a560a );
a157a <=( a555a and a550a );
a158a <=( a545a and a540a );
a159a <=( a535a and a530a );
a160a <=( a525a and a522a );
a161a <=( a519a and a516a );
a162a <=( a513a and a510a );
a163a <=( a507a and a504a );
a164a <=( a501a and a498a );
a165a <=( A266 and (not A265) );
a168a <=( a164a ) or ( a165a );
a172a <=( a161a ) or ( a162a );
a173a <=( a163a ) or ( a172a );
a174a <=( a173a ) or ( a168a );
a177a <=( a159a ) or ( a160a );
a181a <=( a156a ) or ( a157a );
a182a <=( a158a ) or ( a181a );
a183a <=( a182a ) or ( a177a );
a184a <=( a183a ) or ( a174a );
a187a <=( a154a ) or ( a155a );
a191a <=( a151a ) or ( a152a );
a192a <=( a153a ) or ( a191a );
a193a <=( a192a ) or ( a187a );
a196a <=( a149a ) or ( a150a );
a200a <=( a146a ) or ( a147a );
a201a <=( a148a ) or ( a200a );
a202a <=( a201a ) or ( a196a );
a203a <=( a202a ) or ( a193a );
a204a <=( a203a ) or ( a184a );
a207a <=( a144a ) or ( a145a );
a211a <=( a141a ) or ( a142a );
a212a <=( a143a ) or ( a211a );
a213a <=( a212a ) or ( a207a );
a216a <=( a139a ) or ( a140a );
a220a <=( a136a ) or ( a137a );
a221a <=( a138a ) or ( a220a );
a222a <=( a221a ) or ( a216a );
a223a <=( a222a ) or ( a213a );
a226a <=( a134a ) or ( a135a );
a230a <=( a131a ) or ( a132a );
a231a <=( a133a ) or ( a230a );
a232a <=( a231a ) or ( a226a );
a236a <=( a128a ) or ( a129a );
a237a <=( a130a ) or ( a236a );
a241a <=( a125a ) or ( a126a );
a242a <=( a127a ) or ( a241a );
a243a <=( a242a ) or ( a237a );
a244a <=( a243a ) or ( a232a );
a245a <=( a244a ) or ( a223a );
a246a <=( a245a ) or ( a204a );
a249a <=( a123a ) or ( a124a );
a253a <=( a120a ) or ( a121a );
a254a <=( a122a ) or ( a253a );
a255a <=( a254a ) or ( a249a );
a258a <=( a118a ) or ( a119a );
a262a <=( a115a ) or ( a116a );
a263a <=( a117a ) or ( a262a );
a264a <=( a263a ) or ( a258a );
a265a <=( a264a ) or ( a255a );
a268a <=( a113a ) or ( a114a );
a272a <=( a110a ) or ( a111a );
a273a <=( a112a ) or ( a272a );
a274a <=( a273a ) or ( a268a );
a277a <=( a108a ) or ( a109a );
a281a <=( a105a ) or ( a106a );
a282a <=( a107a ) or ( a281a );
a283a <=( a282a ) or ( a277a );
a284a <=( a283a ) or ( a274a );
a285a <=( a284a ) or ( a265a );
a288a <=( a103a ) or ( a104a );
a292a <=( a100a ) or ( a101a );
a293a <=( a102a ) or ( a292a );
a294a <=( a293a ) or ( a288a );
a297a <=( a98a ) or ( a99a );
a301a <=( a95a ) or ( a96a );
a302a <=( a97a ) or ( a301a );
a303a <=( a302a ) or ( a297a );
a304a <=( a303a ) or ( a294a );
a307a <=( a93a ) or ( a94a );
a311a <=( a90a ) or ( a91a );
a312a <=( a92a ) or ( a311a );
a313a <=( a312a ) or ( a307a );
a317a <=( a87a ) or ( a88a );
a318a <=( a89a ) or ( a317a );
a322a <=( a84a ) or ( a85a );
a323a <=( a86a ) or ( a322a );
a324a <=( a323a ) or ( a318a );
a325a <=( a324a ) or ( a313a );
a326a <=( a325a ) or ( a304a );
a327a <=( a326a ) or ( a285a );
a328a <=( a327a ) or ( a246a );
a331a <=( a82a ) or ( a83a );
a335a <=( a79a ) or ( a80a );
a336a <=( a81a ) or ( a335a );
a337a <=( a336a ) or ( a331a );
a340a <=( a77a ) or ( a78a );
a344a <=( a74a ) or ( a75a );
a345a <=( a76a ) or ( a344a );
a346a <=( a345a ) or ( a340a );
a347a <=( a346a ) or ( a337a );
a350a <=( a72a ) or ( a73a );
a354a <=( a69a ) or ( a70a );
a355a <=( a71a ) or ( a354a );
a356a <=( a355a ) or ( a350a );
a359a <=( a67a ) or ( a68a );
a363a <=( a64a ) or ( a65a );
a364a <=( a66a ) or ( a363a );
a365a <=( a364a ) or ( a359a );
a366a <=( a365a ) or ( a356a );
a367a <=( a366a ) or ( a347a );
a370a <=( a62a ) or ( a63a );
a374a <=( a59a ) or ( a60a );
a375a <=( a61a ) or ( a374a );
a376a <=( a375a ) or ( a370a );
a379a <=( a57a ) or ( a58a );
a383a <=( a54a ) or ( a55a );
a384a <=( a56a ) or ( a383a );
a385a <=( a384a ) or ( a379a );
a386a <=( a385a ) or ( a376a );
a389a <=( a52a ) or ( a53a );
a393a <=( a49a ) or ( a50a );
a394a <=( a51a ) or ( a393a );
a395a <=( a394a ) or ( a389a );
a399a <=( a46a ) or ( a47a );
a400a <=( a48a ) or ( a399a );
a404a <=( a43a ) or ( a44a );
a405a <=( a45a ) or ( a404a );
a406a <=( a405a ) or ( a400a );
a407a <=( a406a ) or ( a395a );
a408a <=( a407a ) or ( a386a );
a409a <=( a408a ) or ( a367a );
a412a <=( a41a ) or ( a42a );
a416a <=( a38a ) or ( a39a );
a417a <=( a40a ) or ( a416a );
a418a <=( a417a ) or ( a412a );
a421a <=( a36a ) or ( a37a );
a425a <=( a33a ) or ( a34a );
a426a <=( a35a ) or ( a425a );
a427a <=( a426a ) or ( a421a );
a428a <=( a427a ) or ( a418a );
a431a <=( a31a ) or ( a32a );
a435a <=( a28a ) or ( a29a );
a436a <=( a30a ) or ( a435a );
a437a <=( a436a ) or ( a431a );
a441a <=( a25a ) or ( a26a );
a442a <=( a27a ) or ( a441a );
a446a <=( a22a ) or ( a23a );
a447a <=( a24a ) or ( a446a );
a448a <=( a447a ) or ( a442a );
a449a <=( a448a ) or ( a437a );
a450a <=( a449a ) or ( a428a );
a453a <=( a20a ) or ( a21a );
a457a <=( a17a ) or ( a18a );
a458a <=( a19a ) or ( a457a );
a459a <=( a458a ) or ( a453a );
a462a <=( a15a ) or ( a16a );
a466a <=( a12a ) or ( a13a );
a467a <=( a14a ) or ( a466a );
a468a <=( a467a ) or ( a462a );
a469a <=( a468a ) or ( a459a );
a472a <=( a10a ) or ( a11a );
a476a <=( a7a ) or ( a8a );
a477a <=( a9a ) or ( a476a );
a478a <=( a477a ) or ( a472a );
a482a <=( a4a ) or ( a5a );
a483a <=( a6a ) or ( a482a );
a487a <=( a1a ) or ( a2a );
a488a <=( a3a ) or ( a487a );
a489a <=( a488a ) or ( a483a );
a490a <=( a489a ) or ( a478a );
a491a <=( a490a ) or ( a469a );
a492a <=( a491a ) or ( a450a );
a493a <=( a492a ) or ( a409a );
a498a <=( (not A266) and A265 );
a501a <=( A268 and A267 );
a504a <=( (not A266) and A265 );
a507a <=( A269 and A267 );
a510a <=( A200 and (not A199) );
a513a <=( A233 and (not A232) );
a516a <=( A166 and A168 );
a519a <=( A233 and (not A232) );
a522a <=( A167 and A168 );
a525a <=( A233 and (not A232) );
a529a <=( A232 and A200 );
a530a <=( (not A199) and a529a );
a534a <=( A235 and A234 );
a535a <=( (not A233) and a534a );
a539a <=( A232 and A200 );
a540a <=( (not A199) and a539a );
a544a <=( A236 and A234 );
a545a <=( (not A233) and a544a );
a549a <=( A201 and (not A200) );
a550a <=( A199 and a549a );
a554a <=( A233 and (not A232) );
a555a <=( A202 and a554a );
a559a <=( A201 and (not A200) );
a560a <=( A199 and a559a );
a564a <=( A233 and (not A232) );
a565a <=( A203 and a564a );
a569a <=( A232 and A166 );
a570a <=( A168 and a569a );
a574a <=( A235 and A234 );
a575a <=( (not A233) and a574a );
a579a <=( A232 and A166 );
a580a <=( A168 and a579a );
a584a <=( A236 and A234 );
a585a <=( (not A233) and a584a );
a589a <=( A199 and A166 );
a590a <=( A168 and a589a );
a594a <=( A299 and (not A298) );
a595a <=( A200 and a594a );
a599a <=( (not A200) and A166 );
a600a <=( A168 and a599a );
a604a <=( A299 and (not A298) );
a605a <=( (not A201) and a604a );
a609a <=( (not A199) and A166 );
a610a <=( A168 and a609a );
a614a <=( A299 and (not A298) );
a615a <=( (not A200) and a614a );
a619a <=( A232 and A167 );
a620a <=( A168 and a619a );
a624a <=( A235 and A234 );
a625a <=( (not A233) and a624a );
a629a <=( A232 and A167 );
a630a <=( A168 and a629a );
a634a <=( A236 and A234 );
a635a <=( (not A233) and a634a );
a639a <=( A199 and A167 );
a640a <=( A168 and a639a );
a644a <=( A299 and (not A298) );
a645a <=( A200 and a644a );
a649a <=( (not A200) and A167 );
a650a <=( A168 and a649a );
a654a <=( A299 and (not A298) );
a655a <=( (not A201) and a654a );
a659a <=( (not A199) and A167 );
a660a <=( A168 and a659a );
a664a <=( A299 and (not A298) );
a665a <=( (not A200) and a664a );
a669a <=( A167 and A169 );
a670a <=( (not A170) and a669a );
a674a <=( A233 and (not A232) );
a675a <=( A166 and a674a );
a679a <=( (not A167) and A169 );
a680a <=( (not A170) and a679a );
a684a <=( A233 and (not A232) );
a685a <=( (not A166) and a684a );
a689a <=( A167 and (not A169) );
a690a <=( A170 and a689a );
a694a <=( A233 and (not A232) );
a695a <=( (not A166) and a694a );
a699a <=( (not A167) and (not A169) );
a700a <=( A170 and a699a );
a704a <=( A233 and (not A232) );
a705a <=( A166 and a704a );
a709a <=( (not A200) and A166 );
a710a <=( A168 and a709a );
a713a <=( (not A203) and (not A202) );
a716a <=( A299 and (not A298) );
a717a <=( a716a and a713a );
a721a <=( (not A200) and A167 );
a722a <=( A168 and a721a );
a725a <=( (not A203) and (not A202) );
a728a <=( A299 and (not A298) );
a729a <=( a728a and a725a );
a733a <=( (not A166) and (not A167) );
a734a <=( A170 and a733a );
a737a <=( A200 and (not A199) );
a740a <=( A299 and (not A298) );
a741a <=( a740a and a737a );
a745a <=( (not A168) and A169 );
a746a <=( A170 and a745a );
a749a <=( A200 and (not A199) );
a752a <=( A299 and (not A298) );
a753a <=( a752a and a749a );
a757a <=( (not A166) and (not A167) );
a758a <=( (not A169) and a757a );
a761a <=( A200 and (not A199) );
a764a <=( A299 and (not A298) );
a765a <=( a764a and a761a );
a769a <=( (not A168) and (not A169) );
a770a <=( (not A170) and a769a );
a773a <=( A200 and (not A199) );
a776a <=( A299 and (not A298) );
a777a <=( a776a and a773a );
a780a <=( (not A200) and A199 );
a783a <=( A202 and A201 );
a784a <=( a783a and a780a );
a787a <=( (not A233) and A232 );
a790a <=( A235 and A234 );
a791a <=( a790a and a787a );
a794a <=( (not A200) and A199 );
a797a <=( A202 and A201 );
a798a <=( a797a and a794a );
a801a <=( (not A233) and A232 );
a804a <=( A236 and A234 );
a805a <=( a804a and a801a );
a808a <=( (not A200) and A199 );
a811a <=( A203 and A201 );
a812a <=( a811a and a808a );
a815a <=( (not A233) and A232 );
a818a <=( A235 and A234 );
a819a <=( a818a and a815a );
a822a <=( (not A200) and A199 );
a825a <=( A203 and A201 );
a826a <=( a825a and a822a );
a829a <=( (not A233) and A232 );
a832a <=( A236 and A234 );
a833a <=( a832a and a829a );
a836a <=( A166 and A168 );
a839a <=( A200 and A199 );
a840a <=( a839a and a836a );
a843a <=( (not A299) and A298 );
a846a <=( A301 and A300 );
a847a <=( a846a and a843a );
a850a <=( A166 and A168 );
a853a <=( A200 and A199 );
a854a <=( a853a and a850a );
a857a <=( (not A299) and A298 );
a860a <=( A302 and A300 );
a861a <=( a860a and a857a );
a864a <=( A166 and A168 );
a867a <=( (not A201) and (not A200) );
a868a <=( a867a and a864a );
a871a <=( (not A299) and A298 );
a874a <=( A301 and A300 );
a875a <=( a874a and a871a );
a878a <=( A166 and A168 );
a881a <=( (not A201) and (not A200) );
a882a <=( a881a and a878a );
a885a <=( (not A299) and A298 );
a888a <=( A302 and A300 );
a889a <=( a888a and a885a );
a892a <=( A166 and A168 );
a895a <=( (not A200) and (not A199) );
a896a <=( a895a and a892a );
a899a <=( (not A299) and A298 );
a902a <=( A301 and A300 );
a903a <=( a902a and a899a );
a906a <=( A166 and A168 );
a909a <=( (not A200) and (not A199) );
a910a <=( a909a and a906a );
a913a <=( (not A299) and A298 );
a916a <=( A302 and A300 );
a917a <=( a916a and a913a );
a920a <=( A167 and A168 );
a923a <=( A200 and A199 );
a924a <=( a923a and a920a );
a927a <=( (not A299) and A298 );
a930a <=( A301 and A300 );
a931a <=( a930a and a927a );
a934a <=( A167 and A168 );
a937a <=( A200 and A199 );
a938a <=( a937a and a934a );
a941a <=( (not A299) and A298 );
a944a <=( A302 and A300 );
a945a <=( a944a and a941a );
a948a <=( A167 and A168 );
a951a <=( (not A201) and (not A200) );
a952a <=( a951a and a948a );
a955a <=( (not A299) and A298 );
a958a <=( A301 and A300 );
a959a <=( a958a and a955a );
a962a <=( A167 and A168 );
a965a <=( (not A201) and (not A200) );
a966a <=( a965a and a962a );
a969a <=( (not A299) and A298 );
a972a <=( A302 and A300 );
a973a <=( a972a and a969a );
a976a <=( A167 and A168 );
a979a <=( (not A200) and (not A199) );
a980a <=( a979a and a976a );
a983a <=( (not A299) and A298 );
a986a <=( A301 and A300 );
a987a <=( a986a and a983a );
a990a <=( A167 and A168 );
a993a <=( (not A200) and (not A199) );
a994a <=( a993a and a990a );
a997a <=( (not A299) and A298 );
a1000a <=( A302 and A300 );
a1001a <=( a1000a and a997a );
a1004a <=( (not A168) and A169 );
a1007a <=( (not A166) and A167 );
a1008a <=( a1007a and a1004a );
a1011a <=( A200 and (not A199) );
a1014a <=( A299 and (not A298) );
a1015a <=( a1014a and a1011a );
a1018a <=( (not A168) and A169 );
a1021a <=( A166 and (not A167) );
a1022a <=( a1021a and a1018a );
a1025a <=( A200 and (not A199) );
a1028a <=( A299 and (not A298) );
a1029a <=( a1028a and a1025a );
a1032a <=( A169 and (not A170) );
a1035a <=( A166 and A167 );
a1036a <=( a1035a and a1032a );
a1039a <=( (not A233) and A232 );
a1042a <=( A235 and A234 );
a1043a <=( a1042a and a1039a );
a1046a <=( A169 and (not A170) );
a1049a <=( A166 and A167 );
a1050a <=( a1049a and a1046a );
a1053a <=( (not A233) and A232 );
a1056a <=( A236 and A234 );
a1057a <=( a1056a and a1053a );
a1060a <=( A169 and (not A170) );
a1063a <=( A166 and A167 );
a1064a <=( a1063a and a1060a );
a1067a <=( A200 and A199 );
a1070a <=( A299 and (not A298) );
a1071a <=( a1070a and a1067a );
a1074a <=( A169 and (not A170) );
a1077a <=( A166 and A167 );
a1078a <=( a1077a and a1074a );
a1081a <=( (not A201) and (not A200) );
a1084a <=( A299 and (not A298) );
a1085a <=( a1084a and a1081a );
a1088a <=( A169 and (not A170) );
a1091a <=( A166 and A167 );
a1092a <=( a1091a and a1088a );
a1095a <=( (not A200) and (not A199) );
a1098a <=( A299 and (not A298) );
a1099a <=( a1098a and a1095a );
a1102a <=( A169 and (not A170) );
a1105a <=( (not A166) and (not A167) );
a1106a <=( a1105a and a1102a );
a1109a <=( (not A233) and A232 );
a1112a <=( A235 and A234 );
a1113a <=( a1112a and a1109a );
a1116a <=( A169 and (not A170) );
a1119a <=( (not A166) and (not A167) );
a1120a <=( a1119a and a1116a );
a1123a <=( (not A233) and A232 );
a1126a <=( A236 and A234 );
a1127a <=( a1126a and a1123a );
a1130a <=( A169 and (not A170) );
a1133a <=( (not A166) and (not A167) );
a1134a <=( a1133a and a1130a );
a1137a <=( A200 and A199 );
a1140a <=( A299 and (not A298) );
a1141a <=( a1140a and a1137a );
a1144a <=( A169 and (not A170) );
a1147a <=( (not A166) and (not A167) );
a1148a <=( a1147a and a1144a );
a1151a <=( (not A201) and (not A200) );
a1154a <=( A299 and (not A298) );
a1155a <=( a1154a and a1151a );
a1158a <=( A169 and (not A170) );
a1161a <=( (not A166) and (not A167) );
a1162a <=( a1161a and a1158a );
a1165a <=( (not A200) and (not A199) );
a1168a <=( A299 and (not A298) );
a1169a <=( a1168a and a1165a );
a1172a <=( (not A168) and (not A169) );
a1175a <=( A166 and A167 );
a1176a <=( a1175a and a1172a );
a1179a <=( A200 and (not A199) );
a1182a <=( A299 and (not A298) );
a1183a <=( a1182a and a1179a );
a1186a <=( (not A169) and A170 );
a1189a <=( (not A166) and A167 );
a1190a <=( a1189a and a1186a );
a1193a <=( (not A233) and A232 );
a1196a <=( A235 and A234 );
a1197a <=( a1196a and a1193a );
a1200a <=( (not A169) and A170 );
a1203a <=( (not A166) and A167 );
a1204a <=( a1203a and a1200a );
a1207a <=( (not A233) and A232 );
a1210a <=( A236 and A234 );
a1211a <=( a1210a and a1207a );
a1214a <=( (not A169) and A170 );
a1217a <=( (not A166) and A167 );
a1218a <=( a1217a and a1214a );
a1221a <=( A200 and A199 );
a1224a <=( A299 and (not A298) );
a1225a <=( a1224a and a1221a );
a1228a <=( (not A169) and A170 );
a1231a <=( (not A166) and A167 );
a1232a <=( a1231a and a1228a );
a1235a <=( (not A201) and (not A200) );
a1238a <=( A299 and (not A298) );
a1239a <=( a1238a and a1235a );
a1242a <=( (not A169) and A170 );
a1245a <=( (not A166) and A167 );
a1246a <=( a1245a and a1242a );
a1249a <=( (not A200) and (not A199) );
a1252a <=( A299 and (not A298) );
a1253a <=( a1252a and a1249a );
a1256a <=( (not A169) and A170 );
a1259a <=( A166 and (not A167) );
a1260a <=( a1259a and a1256a );
a1263a <=( (not A233) and A232 );
a1266a <=( A235 and A234 );
a1267a <=( a1266a and a1263a );
a1270a <=( (not A169) and A170 );
a1273a <=( A166 and (not A167) );
a1274a <=( a1273a and a1270a );
a1277a <=( (not A233) and A232 );
a1280a <=( A236 and A234 );
a1281a <=( a1280a and a1277a );
a1284a <=( (not A169) and A170 );
a1287a <=( A166 and (not A167) );
a1288a <=( a1287a and a1284a );
a1291a <=( A200 and A199 );
a1294a <=( A299 and (not A298) );
a1295a <=( a1294a and a1291a );
a1298a <=( (not A169) and A170 );
a1301a <=( A166 and (not A167) );
a1302a <=( a1301a and a1298a );
a1305a <=( (not A201) and (not A200) );
a1308a <=( A299 and (not A298) );
a1309a <=( a1308a and a1305a );
a1312a <=( (not A169) and A170 );
a1315a <=( A166 and (not A167) );
a1316a <=( a1315a and a1312a );
a1319a <=( (not A200) and (not A199) );
a1322a <=( A299 and (not A298) );
a1323a <=( a1322a and a1319a );
a1326a <=( A166 and A168 );
a1329a <=( (not A202) and (not A200) );
a1330a <=( a1329a and a1326a );
a1333a <=( A298 and (not A203) );
a1337a <=( A301 and A300 );
a1338a <=( (not A299) and a1337a );
a1339a <=( a1338a and a1333a );
a1342a <=( A166 and A168 );
a1345a <=( (not A202) and (not A200) );
a1346a <=( a1345a and a1342a );
a1349a <=( A298 and (not A203) );
a1353a <=( A302 and A300 );
a1354a <=( (not A299) and a1353a );
a1355a <=( a1354a and a1349a );
a1358a <=( A167 and A168 );
a1361a <=( (not A202) and (not A200) );
a1362a <=( a1361a and a1358a );
a1365a <=( A298 and (not A203) );
a1369a <=( A301 and A300 );
a1370a <=( (not A299) and a1369a );
a1371a <=( a1370a and a1365a );
a1374a <=( A167 and A168 );
a1377a <=( (not A202) and (not A200) );
a1378a <=( a1377a and a1374a );
a1381a <=( A298 and (not A203) );
a1385a <=( A302 and A300 );
a1386a <=( (not A299) and a1385a );
a1387a <=( a1386a and a1381a );
a1390a <=( (not A167) and A170 );
a1393a <=( (not A199) and (not A166) );
a1394a <=( a1393a and a1390a );
a1397a <=( A298 and A200 );
a1401a <=( A301 and A300 );
a1402a <=( (not A299) and a1401a );
a1403a <=( a1402a and a1397a );
a1406a <=( (not A167) and A170 );
a1409a <=( (not A199) and (not A166) );
a1410a <=( a1409a and a1406a );
a1413a <=( A298 and A200 );
a1417a <=( A302 and A300 );
a1418a <=( (not A299) and a1417a );
a1419a <=( a1418a and a1413a );
a1422a <=( (not A167) and A170 );
a1425a <=( A199 and (not A166) );
a1426a <=( a1425a and a1422a );
a1429a <=( A201 and (not A200) );
a1433a <=( A299 and (not A298) );
a1434a <=( A202 and a1433a );
a1435a <=( a1434a and a1429a );
a1438a <=( (not A167) and A170 );
a1441a <=( A199 and (not A166) );
a1442a <=( a1441a and a1438a );
a1445a <=( A201 and (not A200) );
a1449a <=( A299 and (not A298) );
a1450a <=( A203 and a1449a );
a1451a <=( a1450a and a1445a );
a1454a <=( A169 and A170 );
a1457a <=( (not A199) and (not A168) );
a1458a <=( a1457a and a1454a );
a1461a <=( A298 and A200 );
a1465a <=( A301 and A300 );
a1466a <=( (not A299) and a1465a );
a1467a <=( a1466a and a1461a );
a1470a <=( A169 and A170 );
a1473a <=( (not A199) and (not A168) );
a1474a <=( a1473a and a1470a );
a1477a <=( A298 and A200 );
a1481a <=( A302 and A300 );
a1482a <=( (not A299) and a1481a );
a1483a <=( a1482a and a1477a );
a1486a <=( A169 and A170 );
a1489a <=( A199 and (not A168) );
a1490a <=( a1489a and a1486a );
a1493a <=( A201 and (not A200) );
a1497a <=( A299 and (not A298) );
a1498a <=( A202 and a1497a );
a1499a <=( a1498a and a1493a );
a1502a <=( A169 and A170 );
a1505a <=( A199 and (not A168) );
a1506a <=( a1505a and a1502a );
a1509a <=( A201 and (not A200) );
a1513a <=( A299 and (not A298) );
a1514a <=( A203 and a1513a );
a1515a <=( a1514a and a1509a );
a1518a <=( A169 and (not A170) );
a1521a <=( A166 and A167 );
a1522a <=( a1521a and a1518a );
a1525a <=( (not A202) and (not A200) );
a1529a <=( A299 and (not A298) );
a1530a <=( (not A203) and a1529a );
a1531a <=( a1530a and a1525a );
a1534a <=( A169 and (not A170) );
a1537a <=( (not A166) and (not A167) );
a1538a <=( a1537a and a1534a );
a1541a <=( (not A202) and (not A200) );
a1545a <=( A299 and (not A298) );
a1546a <=( (not A203) and a1545a );
a1547a <=( a1546a and a1541a );
a1550a <=( (not A167) and (not A169) );
a1553a <=( (not A199) and (not A166) );
a1554a <=( a1553a and a1550a );
a1557a <=( A298 and A200 );
a1561a <=( A301 and A300 );
a1562a <=( (not A299) and a1561a );
a1563a <=( a1562a and a1557a );
a1566a <=( (not A167) and (not A169) );
a1569a <=( (not A199) and (not A166) );
a1570a <=( a1569a and a1566a );
a1573a <=( A298 and A200 );
a1577a <=( A302 and A300 );
a1578a <=( (not A299) and a1577a );
a1579a <=( a1578a and a1573a );
a1582a <=( (not A167) and (not A169) );
a1585a <=( A199 and (not A166) );
a1586a <=( a1585a and a1582a );
a1589a <=( A201 and (not A200) );
a1593a <=( A299 and (not A298) );
a1594a <=( A202 and a1593a );
a1595a <=( a1594a and a1589a );
a1598a <=( (not A167) and (not A169) );
a1601a <=( A199 and (not A166) );
a1602a <=( a1601a and a1598a );
a1605a <=( A201 and (not A200) );
a1609a <=( A299 and (not A298) );
a1610a <=( A203 and a1609a );
a1611a <=( a1610a and a1605a );
a1614a <=( (not A169) and A170 );
a1617a <=( (not A166) and A167 );
a1618a <=( a1617a and a1614a );
a1621a <=( (not A202) and (not A200) );
a1625a <=( A299 and (not A298) );
a1626a <=( (not A203) and a1625a );
a1627a <=( a1626a and a1621a );
a1630a <=( (not A169) and A170 );
a1633a <=( A166 and (not A167) );
a1634a <=( a1633a and a1630a );
a1637a <=( (not A202) and (not A200) );
a1641a <=( A299 and (not A298) );
a1642a <=( (not A203) and a1641a );
a1643a <=( a1642a and a1637a );
a1646a <=( (not A169) and (not A170) );
a1649a <=( (not A199) and (not A168) );
a1650a <=( a1649a and a1646a );
a1653a <=( A298 and A200 );
a1657a <=( A301 and A300 );
a1658a <=( (not A299) and a1657a );
a1659a <=( a1658a and a1653a );
a1662a <=( (not A169) and (not A170) );
a1665a <=( (not A199) and (not A168) );
a1666a <=( a1665a and a1662a );
a1669a <=( A298 and A200 );
a1673a <=( A302 and A300 );
a1674a <=( (not A299) and a1673a );
a1675a <=( a1674a and a1669a );
a1678a <=( (not A169) and (not A170) );
a1681a <=( A199 and (not A168) );
a1682a <=( a1681a and a1678a );
a1685a <=( A201 and (not A200) );
a1689a <=( A299 and (not A298) );
a1690a <=( A202 and a1689a );
a1691a <=( a1690a and a1685a );
a1694a <=( (not A169) and (not A170) );
a1697a <=( A199 and (not A168) );
a1698a <=( a1697a and a1694a );
a1701a <=( A201 and (not A200) );
a1705a <=( A299 and (not A298) );
a1706a <=( A203 and a1705a );
a1707a <=( a1706a and a1701a );
a1710a <=( (not A168) and A169 );
a1714a <=( (not A199) and (not A166) );
a1715a <=( A167 and a1714a );
a1716a <=( a1715a and a1710a );
a1719a <=( A298 and A200 );
a1723a <=( A301 and A300 );
a1724a <=( (not A299) and a1723a );
a1725a <=( a1724a and a1719a );
a1728a <=( (not A168) and A169 );
a1732a <=( (not A199) and (not A166) );
a1733a <=( A167 and a1732a );
a1734a <=( a1733a and a1728a );
a1737a <=( A298 and A200 );
a1741a <=( A302 and A300 );
a1742a <=( (not A299) and a1741a );
a1743a <=( a1742a and a1737a );
a1746a <=( (not A168) and A169 );
a1750a <=( A199 and (not A166) );
a1751a <=( A167 and a1750a );
a1752a <=( a1751a and a1746a );
a1755a <=( A201 and (not A200) );
a1759a <=( A299 and (not A298) );
a1760a <=( A202 and a1759a );
a1761a <=( a1760a and a1755a );
a1764a <=( (not A168) and A169 );
a1768a <=( A199 and (not A166) );
a1769a <=( A167 and a1768a );
a1770a <=( a1769a and a1764a );
a1773a <=( A201 and (not A200) );
a1777a <=( A299 and (not A298) );
a1778a <=( A203 and a1777a );
a1779a <=( a1778a and a1773a );
a1782a <=( (not A168) and A169 );
a1786a <=( (not A199) and A166 );
a1787a <=( (not A167) and a1786a );
a1788a <=( a1787a and a1782a );
a1791a <=( A298 and A200 );
a1795a <=( A301 and A300 );
a1796a <=( (not A299) and a1795a );
a1797a <=( a1796a and a1791a );
a1800a <=( (not A168) and A169 );
a1804a <=( (not A199) and A166 );
a1805a <=( (not A167) and a1804a );
a1806a <=( a1805a and a1800a );
a1809a <=( A298 and A200 );
a1813a <=( A302 and A300 );
a1814a <=( (not A299) and a1813a );
a1815a <=( a1814a and a1809a );
a1818a <=( (not A168) and A169 );
a1822a <=( A199 and A166 );
a1823a <=( (not A167) and a1822a );
a1824a <=( a1823a and a1818a );
a1827a <=( A201 and (not A200) );
a1831a <=( A299 and (not A298) );
a1832a <=( A202 and a1831a );
a1833a <=( a1832a and a1827a );
a1836a <=( (not A168) and A169 );
a1840a <=( A199 and A166 );
a1841a <=( (not A167) and a1840a );
a1842a <=( a1841a and a1836a );
a1845a <=( A201 and (not A200) );
a1849a <=( A299 and (not A298) );
a1850a <=( A203 and a1849a );
a1851a <=( a1850a and a1845a );
a1854a <=( A169 and (not A170) );
a1858a <=( A199 and A166 );
a1859a <=( A167 and a1858a );
a1860a <=( a1859a and a1854a );
a1863a <=( A298 and A200 );
a1867a <=( A301 and A300 );
a1868a <=( (not A299) and a1867a );
a1869a <=( a1868a and a1863a );
a1872a <=( A169 and (not A170) );
a1876a <=( A199 and A166 );
a1877a <=( A167 and a1876a );
a1878a <=( a1877a and a1872a );
a1881a <=( A298 and A200 );
a1885a <=( A302 and A300 );
a1886a <=( (not A299) and a1885a );
a1887a <=( a1886a and a1881a );
a1890a <=( A169 and (not A170) );
a1894a <=( (not A200) and A166 );
a1895a <=( A167 and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A298 and (not A201) );
a1903a <=( A301 and A300 );
a1904a <=( (not A299) and a1903a );
a1905a <=( a1904a and a1899a );
a1908a <=( A169 and (not A170) );
a1912a <=( (not A200) and A166 );
a1913a <=( A167 and a1912a );
a1914a <=( a1913a and a1908a );
a1917a <=( A298 and (not A201) );
a1921a <=( A302 and A300 );
a1922a <=( (not A299) and a1921a );
a1923a <=( a1922a and a1917a );
a1926a <=( A169 and (not A170) );
a1930a <=( (not A199) and A166 );
a1931a <=( A167 and a1930a );
a1932a <=( a1931a and a1926a );
a1935a <=( A298 and (not A200) );
a1939a <=( A301 and A300 );
a1940a <=( (not A299) and a1939a );
a1941a <=( a1940a and a1935a );
a1944a <=( A169 and (not A170) );
a1948a <=( (not A199) and A166 );
a1949a <=( A167 and a1948a );
a1950a <=( a1949a and a1944a );
a1953a <=( A298 and (not A200) );
a1957a <=( A302 and A300 );
a1958a <=( (not A299) and a1957a );
a1959a <=( a1958a and a1953a );
a1962a <=( A169 and (not A170) );
a1966a <=( A199 and (not A166) );
a1967a <=( (not A167) and a1966a );
a1968a <=( a1967a and a1962a );
a1971a <=( A298 and A200 );
a1975a <=( A301 and A300 );
a1976a <=( (not A299) and a1975a );
a1977a <=( a1976a and a1971a );
a1980a <=( A169 and (not A170) );
a1984a <=( A199 and (not A166) );
a1985a <=( (not A167) and a1984a );
a1986a <=( a1985a and a1980a );
a1989a <=( A298 and A200 );
a1993a <=( A302 and A300 );
a1994a <=( (not A299) and a1993a );
a1995a <=( a1994a and a1989a );
a1998a <=( A169 and (not A170) );
a2002a <=( (not A200) and (not A166) );
a2003a <=( (not A167) and a2002a );
a2004a <=( a2003a and a1998a );
a2007a <=( A298 and (not A201) );
a2011a <=( A301 and A300 );
a2012a <=( (not A299) and a2011a );
a2013a <=( a2012a and a2007a );
a2016a <=( A169 and (not A170) );
a2020a <=( (not A200) and (not A166) );
a2021a <=( (not A167) and a2020a );
a2022a <=( a2021a and a2016a );
a2025a <=( A298 and (not A201) );
a2029a <=( A302 and A300 );
a2030a <=( (not A299) and a2029a );
a2031a <=( a2030a and a2025a );
a2034a <=( A169 and (not A170) );
a2038a <=( (not A199) and (not A166) );
a2039a <=( (not A167) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( A298 and (not A200) );
a2047a <=( A301 and A300 );
a2048a <=( (not A299) and a2047a );
a2049a <=( a2048a and a2043a );
a2052a <=( A169 and (not A170) );
a2056a <=( (not A199) and (not A166) );
a2057a <=( (not A167) and a2056a );
a2058a <=( a2057a and a2052a );
a2061a <=( A298 and (not A200) );
a2065a <=( A302 and A300 );
a2066a <=( (not A299) and a2065a );
a2067a <=( a2066a and a2061a );
a2070a <=( (not A168) and (not A169) );
a2074a <=( (not A199) and A166 );
a2075a <=( A167 and a2074a );
a2076a <=( a2075a and a2070a );
a2079a <=( A298 and A200 );
a2083a <=( A301 and A300 );
a2084a <=( (not A299) and a2083a );
a2085a <=( a2084a and a2079a );
a2088a <=( (not A168) and (not A169) );
a2092a <=( (not A199) and A166 );
a2093a <=( A167 and a2092a );
a2094a <=( a2093a and a2088a );
a2097a <=( A298 and A200 );
a2101a <=( A302 and A300 );
a2102a <=( (not A299) and a2101a );
a2103a <=( a2102a and a2097a );
a2106a <=( (not A168) and (not A169) );
a2110a <=( A199 and A166 );
a2111a <=( A167 and a2110a );
a2112a <=( a2111a and a2106a );
a2115a <=( A201 and (not A200) );
a2119a <=( A299 and (not A298) );
a2120a <=( A202 and a2119a );
a2121a <=( a2120a and a2115a );
a2124a <=( (not A168) and (not A169) );
a2128a <=( A199 and A166 );
a2129a <=( A167 and a2128a );
a2130a <=( a2129a and a2124a );
a2133a <=( A201 and (not A200) );
a2137a <=( A299 and (not A298) );
a2138a <=( A203 and a2137a );
a2139a <=( a2138a and a2133a );
a2142a <=( (not A169) and A170 );
a2146a <=( A199 and (not A166) );
a2147a <=( A167 and a2146a );
a2148a <=( a2147a and a2142a );
a2151a <=( A298 and A200 );
a2155a <=( A301 and A300 );
a2156a <=( (not A299) and a2155a );
a2157a <=( a2156a and a2151a );
a2160a <=( (not A169) and A170 );
a2164a <=( A199 and (not A166) );
a2165a <=( A167 and a2164a );
a2166a <=( a2165a and a2160a );
a2169a <=( A298 and A200 );
a2173a <=( A302 and A300 );
a2174a <=( (not A299) and a2173a );
a2175a <=( a2174a and a2169a );
a2178a <=( (not A169) and A170 );
a2182a <=( (not A200) and (not A166) );
a2183a <=( A167 and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( A298 and (not A201) );
a2191a <=( A301 and A300 );
a2192a <=( (not A299) and a2191a );
a2193a <=( a2192a and a2187a );
a2196a <=( (not A169) and A170 );
a2200a <=( (not A200) and (not A166) );
a2201a <=( A167 and a2200a );
a2202a <=( a2201a and a2196a );
a2205a <=( A298 and (not A201) );
a2209a <=( A302 and A300 );
a2210a <=( (not A299) and a2209a );
a2211a <=( a2210a and a2205a );
a2214a <=( (not A169) and A170 );
a2218a <=( (not A199) and (not A166) );
a2219a <=( A167 and a2218a );
a2220a <=( a2219a and a2214a );
a2223a <=( A298 and (not A200) );
a2227a <=( A301 and A300 );
a2228a <=( (not A299) and a2227a );
a2229a <=( a2228a and a2223a );
a2232a <=( (not A169) and A170 );
a2236a <=( (not A199) and (not A166) );
a2237a <=( A167 and a2236a );
a2238a <=( a2237a and a2232a );
a2241a <=( A298 and (not A200) );
a2245a <=( A302 and A300 );
a2246a <=( (not A299) and a2245a );
a2247a <=( a2246a and a2241a );
a2250a <=( (not A169) and A170 );
a2254a <=( A199 and A166 );
a2255a <=( (not A167) and a2254a );
a2256a <=( a2255a and a2250a );
a2259a <=( A298 and A200 );
a2263a <=( A301 and A300 );
a2264a <=( (not A299) and a2263a );
a2265a <=( a2264a and a2259a );
a2268a <=( (not A169) and A170 );
a2272a <=( A199 and A166 );
a2273a <=( (not A167) and a2272a );
a2274a <=( a2273a and a2268a );
a2277a <=( A298 and A200 );
a2281a <=( A302 and A300 );
a2282a <=( (not A299) and a2281a );
a2283a <=( a2282a and a2277a );
a2286a <=( (not A169) and A170 );
a2290a <=( (not A200) and A166 );
a2291a <=( (not A167) and a2290a );
a2292a <=( a2291a and a2286a );
a2295a <=( A298 and (not A201) );
a2299a <=( A301 and A300 );
a2300a <=( (not A299) and a2299a );
a2301a <=( a2300a and a2295a );
a2304a <=( (not A169) and A170 );
a2308a <=( (not A200) and A166 );
a2309a <=( (not A167) and a2308a );
a2310a <=( a2309a and a2304a );
a2313a <=( A298 and (not A201) );
a2317a <=( A302 and A300 );
a2318a <=( (not A299) and a2317a );
a2319a <=( a2318a and a2313a );
a2322a <=( (not A169) and A170 );
a2326a <=( (not A199) and A166 );
a2327a <=( (not A167) and a2326a );
a2328a <=( a2327a and a2322a );
a2331a <=( A298 and (not A200) );
a2335a <=( A301 and A300 );
a2336a <=( (not A299) and a2335a );
a2337a <=( a2336a and a2331a );
a2340a <=( (not A169) and A170 );
a2344a <=( (not A199) and A166 );
a2345a <=( (not A167) and a2344a );
a2346a <=( a2345a and a2340a );
a2349a <=( A298 and (not A200) );
a2353a <=( A302 and A300 );
a2354a <=( (not A299) and a2353a );
a2355a <=( a2354a and a2349a );
a2358a <=( (not A167) and A170 );
a2362a <=( (not A200) and A199 );
a2363a <=( (not A166) and a2362a );
a2364a <=( a2363a and a2358a );
a2368a <=( A298 and A202 );
a2369a <=( A201 and a2368a );
a2373a <=( A301 and A300 );
a2374a <=( (not A299) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A167) and A170 );
a2382a <=( (not A200) and A199 );
a2383a <=( (not A166) and a2382a );
a2384a <=( a2383a and a2378a );
a2388a <=( A298 and A202 );
a2389a <=( A201 and a2388a );
a2393a <=( A302 and A300 );
a2394a <=( (not A299) and a2393a );
a2395a <=( a2394a and a2389a );
a2398a <=( (not A167) and A170 );
a2402a <=( (not A200) and A199 );
a2403a <=( (not A166) and a2402a );
a2404a <=( a2403a and a2398a );
a2408a <=( A298 and A203 );
a2409a <=( A201 and a2408a );
a2413a <=( A301 and A300 );
a2414a <=( (not A299) and a2413a );
a2415a <=( a2414a and a2409a );
a2418a <=( (not A167) and A170 );
a2422a <=( (not A200) and A199 );
a2423a <=( (not A166) and a2422a );
a2424a <=( a2423a and a2418a );
a2428a <=( A298 and A203 );
a2429a <=( A201 and a2428a );
a2433a <=( A302 and A300 );
a2434a <=( (not A299) and a2433a );
a2435a <=( a2434a and a2429a );
a2438a <=( A169 and A170 );
a2442a <=( (not A200) and A199 );
a2443a <=( (not A168) and a2442a );
a2444a <=( a2443a and a2438a );
a2448a <=( A298 and A202 );
a2449a <=( A201 and a2448a );
a2453a <=( A301 and A300 );
a2454a <=( (not A299) and a2453a );
a2455a <=( a2454a and a2449a );
a2458a <=( A169 and A170 );
a2462a <=( (not A200) and A199 );
a2463a <=( (not A168) and a2462a );
a2464a <=( a2463a and a2458a );
a2468a <=( A298 and A202 );
a2469a <=( A201 and a2468a );
a2473a <=( A302 and A300 );
a2474a <=( (not A299) and a2473a );
a2475a <=( a2474a and a2469a );
a2478a <=( A169 and A170 );
a2482a <=( (not A200) and A199 );
a2483a <=( (not A168) and a2482a );
a2484a <=( a2483a and a2478a );
a2488a <=( A298 and A203 );
a2489a <=( A201 and a2488a );
a2493a <=( A301 and A300 );
a2494a <=( (not A299) and a2493a );
a2495a <=( a2494a and a2489a );
a2498a <=( A169 and A170 );
a2502a <=( (not A200) and A199 );
a2503a <=( (not A168) and a2502a );
a2504a <=( a2503a and a2498a );
a2508a <=( A298 and A203 );
a2509a <=( A201 and a2508a );
a2513a <=( A302 and A300 );
a2514a <=( (not A299) and a2513a );
a2515a <=( a2514a and a2509a );
a2518a <=( A169 and (not A170) );
a2522a <=( (not A200) and A166 );
a2523a <=( A167 and a2522a );
a2524a <=( a2523a and a2518a );
a2528a <=( A298 and (not A203) );
a2529a <=( (not A202) and a2528a );
a2533a <=( A301 and A300 );
a2534a <=( (not A299) and a2533a );
a2535a <=( a2534a and a2529a );
a2538a <=( A169 and (not A170) );
a2542a <=( (not A200) and A166 );
a2543a <=( A167 and a2542a );
a2544a <=( a2543a and a2538a );
a2548a <=( A298 and (not A203) );
a2549a <=( (not A202) and a2548a );
a2553a <=( A302 and A300 );
a2554a <=( (not A299) and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A169 and (not A170) );
a2562a <=( (not A200) and (not A166) );
a2563a <=( (not A167) and a2562a );
a2564a <=( a2563a and a2558a );
a2568a <=( A298 and (not A203) );
a2569a <=( (not A202) and a2568a );
a2573a <=( A301 and A300 );
a2574a <=( (not A299) and a2573a );
a2575a <=( a2574a and a2569a );
a2578a <=( A169 and (not A170) );
a2582a <=( (not A200) and (not A166) );
a2583a <=( (not A167) and a2582a );
a2584a <=( a2583a and a2578a );
a2588a <=( A298 and (not A203) );
a2589a <=( (not A202) and a2588a );
a2593a <=( A302 and A300 );
a2594a <=( (not A299) and a2593a );
a2595a <=( a2594a and a2589a );
a2598a <=( (not A167) and (not A169) );
a2602a <=( (not A200) and A199 );
a2603a <=( (not A166) and a2602a );
a2604a <=( a2603a and a2598a );
a2608a <=( A298 and A202 );
a2609a <=( A201 and a2608a );
a2613a <=( A301 and A300 );
a2614a <=( (not A299) and a2613a );
a2615a <=( a2614a and a2609a );
a2618a <=( (not A167) and (not A169) );
a2622a <=( (not A200) and A199 );
a2623a <=( (not A166) and a2622a );
a2624a <=( a2623a and a2618a );
a2628a <=( A298 and A202 );
a2629a <=( A201 and a2628a );
a2633a <=( A302 and A300 );
a2634a <=( (not A299) and a2633a );
a2635a <=( a2634a and a2629a );
a2638a <=( (not A167) and (not A169) );
a2642a <=( (not A200) and A199 );
a2643a <=( (not A166) and a2642a );
a2644a <=( a2643a and a2638a );
a2648a <=( A298 and A203 );
a2649a <=( A201 and a2648a );
a2653a <=( A301 and A300 );
a2654a <=( (not A299) and a2653a );
a2655a <=( a2654a and a2649a );
a2658a <=( (not A167) and (not A169) );
a2662a <=( (not A200) and A199 );
a2663a <=( (not A166) and a2662a );
a2664a <=( a2663a and a2658a );
a2668a <=( A298 and A203 );
a2669a <=( A201 and a2668a );
a2673a <=( A302 and A300 );
a2674a <=( (not A299) and a2673a );
a2675a <=( a2674a and a2669a );
a2678a <=( (not A169) and A170 );
a2682a <=( (not A200) and (not A166) );
a2683a <=( A167 and a2682a );
a2684a <=( a2683a and a2678a );
a2688a <=( A298 and (not A203) );
a2689a <=( (not A202) and a2688a );
a2693a <=( A301 and A300 );
a2694a <=( (not A299) and a2693a );
a2695a <=( a2694a and a2689a );
a2698a <=( (not A169) and A170 );
a2702a <=( (not A200) and (not A166) );
a2703a <=( A167 and a2702a );
a2704a <=( a2703a and a2698a );
a2708a <=( A298 and (not A203) );
a2709a <=( (not A202) and a2708a );
a2713a <=( A302 and A300 );
a2714a <=( (not A299) and a2713a );
a2715a <=( a2714a and a2709a );
a2718a <=( (not A169) and A170 );
a2722a <=( (not A200) and A166 );
a2723a <=( (not A167) and a2722a );
a2724a <=( a2723a and a2718a );
a2728a <=( A298 and (not A203) );
a2729a <=( (not A202) and a2728a );
a2733a <=( A301 and A300 );
a2734a <=( (not A299) and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( (not A169) and A170 );
a2742a <=( (not A200) and A166 );
a2743a <=( (not A167) and a2742a );
a2744a <=( a2743a and a2738a );
a2748a <=( A298 and (not A203) );
a2749a <=( (not A202) and a2748a );
a2753a <=( A302 and A300 );
a2754a <=( (not A299) and a2753a );
a2755a <=( a2754a and a2749a );
a2758a <=( (not A169) and (not A170) );
a2762a <=( (not A200) and A199 );
a2763a <=( (not A168) and a2762a );
a2764a <=( a2763a and a2758a );
a2768a <=( A298 and A202 );
a2769a <=( A201 and a2768a );
a2773a <=( A301 and A300 );
a2774a <=( (not A299) and a2773a );
a2775a <=( a2774a and a2769a );
a2778a <=( (not A169) and (not A170) );
a2782a <=( (not A200) and A199 );
a2783a <=( (not A168) and a2782a );
a2784a <=( a2783a and a2778a );
a2788a <=( A298 and A202 );
a2789a <=( A201 and a2788a );
a2793a <=( A302 and A300 );
a2794a <=( (not A299) and a2793a );
a2795a <=( a2794a and a2789a );
a2798a <=( (not A169) and (not A170) );
a2802a <=( (not A200) and A199 );
a2803a <=( (not A168) and a2802a );
a2804a <=( a2803a and a2798a );
a2808a <=( A298 and A203 );
a2809a <=( A201 and a2808a );
a2813a <=( A301 and A300 );
a2814a <=( (not A299) and a2813a );
a2815a <=( a2814a and a2809a );
a2818a <=( (not A169) and (not A170) );
a2822a <=( (not A200) and A199 );
a2823a <=( (not A168) and a2822a );
a2824a <=( a2823a and a2818a );
a2828a <=( A298 and A203 );
a2829a <=( A201 and a2828a );
a2833a <=( A302 and A300 );
a2834a <=( (not A299) and a2833a );
a2835a <=( a2834a and a2829a );
a2839a <=( A167 and (not A168) );
a2840a <=( A169 and a2839a );
a2844a <=( (not A200) and A199 );
a2845a <=( (not A166) and a2844a );
a2846a <=( a2845a and a2840a );
a2850a <=( A298 and A202 );
a2851a <=( A201 and a2850a );
a2855a <=( A301 and A300 );
a2856a <=( (not A299) and a2855a );
a2857a <=( a2856a and a2851a );
a2861a <=( A167 and (not A168) );
a2862a <=( A169 and a2861a );
a2866a <=( (not A200) and A199 );
a2867a <=( (not A166) and a2866a );
a2868a <=( a2867a and a2862a );
a2872a <=( A298 and A202 );
a2873a <=( A201 and a2872a );
a2877a <=( A302 and A300 );
a2878a <=( (not A299) and a2877a );
a2879a <=( a2878a and a2873a );
a2883a <=( A167 and (not A168) );
a2884a <=( A169 and a2883a );
a2888a <=( (not A200) and A199 );
a2889a <=( (not A166) and a2888a );
a2890a <=( a2889a and a2884a );
a2894a <=( A298 and A203 );
a2895a <=( A201 and a2894a );
a2899a <=( A301 and A300 );
a2900a <=( (not A299) and a2899a );
a2901a <=( a2900a and a2895a );
a2905a <=( A167 and (not A168) );
a2906a <=( A169 and a2905a );
a2910a <=( (not A200) and A199 );
a2911a <=( (not A166) and a2910a );
a2912a <=( a2911a and a2906a );
a2916a <=( A298 and A203 );
a2917a <=( A201 and a2916a );
a2921a <=( A302 and A300 );
a2922a <=( (not A299) and a2921a );
a2923a <=( a2922a and a2917a );
a2927a <=( (not A167) and (not A168) );
a2928a <=( A169 and a2927a );
a2932a <=( (not A200) and A199 );
a2933a <=( A166 and a2932a );
a2934a <=( a2933a and a2928a );
a2938a <=( A298 and A202 );
a2939a <=( A201 and a2938a );
a2943a <=( A301 and A300 );
a2944a <=( (not A299) and a2943a );
a2945a <=( a2944a and a2939a );
a2949a <=( (not A167) and (not A168) );
a2950a <=( A169 and a2949a );
a2954a <=( (not A200) and A199 );
a2955a <=( A166 and a2954a );
a2956a <=( a2955a and a2950a );
a2960a <=( A298 and A202 );
a2961a <=( A201 and a2960a );
a2965a <=( A302 and A300 );
a2966a <=( (not A299) and a2965a );
a2967a <=( a2966a and a2961a );
a2971a <=( (not A167) and (not A168) );
a2972a <=( A169 and a2971a );
a2976a <=( (not A200) and A199 );
a2977a <=( A166 and a2976a );
a2978a <=( a2977a and a2972a );
a2982a <=( A298 and A203 );
a2983a <=( A201 and a2982a );
a2987a <=( A301 and A300 );
a2988a <=( (not A299) and a2987a );
a2989a <=( a2988a and a2983a );
a2993a <=( (not A167) and (not A168) );
a2994a <=( A169 and a2993a );
a2998a <=( (not A200) and A199 );
a2999a <=( A166 and a2998a );
a3000a <=( a2999a and a2994a );
a3004a <=( A298 and A203 );
a3005a <=( A201 and a3004a );
a3009a <=( A302 and A300 );
a3010a <=( (not A299) and a3009a );
a3011a <=( a3010a and a3005a );
a3015a <=( A167 and (not A168) );
a3016a <=( (not A169) and a3015a );
a3020a <=( (not A200) and A199 );
a3021a <=( A166 and a3020a );
a3022a <=( a3021a and a3016a );
a3026a <=( A298 and A202 );
a3027a <=( A201 and a3026a );
a3031a <=( A301 and A300 );
a3032a <=( (not A299) and a3031a );
a3033a <=( a3032a and a3027a );
a3037a <=( A167 and (not A168) );
a3038a <=( (not A169) and a3037a );
a3042a <=( (not A200) and A199 );
a3043a <=( A166 and a3042a );
a3044a <=( a3043a and a3038a );
a3048a <=( A298 and A202 );
a3049a <=( A201 and a3048a );
a3053a <=( A302 and A300 );
a3054a <=( (not A299) and a3053a );
a3055a <=( a3054a and a3049a );
a3059a <=( A167 and (not A168) );
a3060a <=( (not A169) and a3059a );
a3064a <=( (not A200) and A199 );
a3065a <=( A166 and a3064a );
a3066a <=( a3065a and a3060a );
a3070a <=( A298 and A203 );
a3071a <=( A201 and a3070a );
a3075a <=( A301 and A300 );
a3076a <=( (not A299) and a3075a );
a3077a <=( a3076a and a3071a );
a3081a <=( A167 and (not A168) );
a3082a <=( (not A169) and a3081a );
a3086a <=( (not A200) and A199 );
a3087a <=( A166 and a3086a );
a3088a <=( a3087a and a3082a );
a3092a <=( A298 and A203 );
a3093a <=( A201 and a3092a );
a3097a <=( A302 and A300 );
a3098a <=( (not A299) and a3097a );
a3099a <=( a3098a and a3093a );
end x25_8x_behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: defmst
-- File: defmst.vhd
-- Author: Edvin Catovic, Gaisler Research
-- Description: Default AHB master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
entity ahbdefmst is
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end;
architecture rtl of ahbdefmst is
begin
ahbmo.hbusreq <= '0';
ahbmo.hlock <= '0';
ahbmo.htrans <= HTRANS_IDLE;
ahbmo.haddr <= (others => '0');
ahbmo.hwrite <= '0';
ahbmo.hsize <= (others => '0');
ahbmo.hburst <= (others => '0');
ahbmo.hprot <= (others => '0');
ahbmo.hwdata <= (others => '0');
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= (others => (others => '0'));
ahbmo.hindex <= hindex;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, we, valid, spi_clk, spi_mosi, spi_miso: std_logic := '0';
signal input, output: std_logic_vector(7 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
we <= '0', '1' after 1000 ns, '0' after 1100 ns;
spi_miso <= '1';
input <= x"a1";
spi_core: entity work.spi_master
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clock,
rst_i => reset,
data_i => input,
data_o => output,
data_valid_o => valid,
wren_i => we,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
end tb;
|
-- Hecho para ser visto con tab size = 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pong is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
segs: OUT std_logic_vector (6 downto 0);
altavoz: OUT std_logic;
hSync: OUT std_logic;
Vsync: OUT std_logic;
R: OUT std_logic_vector (2 downto 0); -- alconversor D/A
G: OUT std_logic_vector (2 downto 0); -- alconversor D/A
B: OUT std_logic_vector (2 downto 0); -- alconversor D/A
outTeclaQ: OUT std_logic
);
end pong;
architecture Behavioral of pong is
component ps2KeyboardInterface
port ( clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
end component;
type fsmEstados is (pulsadas, despulsadas);
signal estado: fsmEstados;
--señales PS2
signal newData, newDataAck: std_logic;
signal scancode: std_logic_vector (7 downto 0);
--señales VGA
signal senialHSync, senialVSync: std_logic;
signal finPixelCont: std_logic;
signal cuentaPixelCont: std_logic_vector (10 downto 0);
signal cuentaLineCont: std_logic_vector (9 downto 0);
signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic;
signal Rcampo: std_logic_vector (2 downto 0);
signal Gcampo: std_logic_vector (2 downto 0);
signal Bcampo: std_logic_vector (2 downto 0);
signal Rpalas: std_logic_vector (2 downto 0);
signal Gpalas: std_logic_vector (2 downto 0);
signal Bpalas: std_logic_vector (2 downto 0);
signal Rpelota: std_logic_vector (2 downto 0);
signal Gpelota: std_logic_vector (2 downto 0);
signal Bpelota: std_logic_vector (2 downto 0);
--señales control
signal pixelPalaIzq: std_logic_vector (6 downto 0); --102 pixeles (1100110)
signal pixelPalaDer: std_logic_vector (6 downto 0); --102 pixeles
signal pixelPelotaVer: std_logic_vector (6 downto 0); --102 pixeles
signal pixelPelotaHor: std_logic_vector (7 downto 0); --153 pixeles (10011001)
signal arribaPalaIzq: std_logic;
signal abajoPalaIzq: std_logic;
signal arribaPalaDer: std_logic;
signal abajoPalaDer: std_logic;
signal horizontalPelota: std_logic; -- 1 = derecha , 0 = izquieda
signal verticalPelota: std_logic; -- 1 = abajo , 0 = arriba
signal moverPelota: std_logic;
signal cuenta1dec: STD_LOGIC_VECTOR(22 downto 0); --contador1decima
signal finCuenta1Dec: STD_LOGIC;
--señales teclas
signal teclaQ: std_logic;
signal clTeclaQ: std_logic;
signal ldTeclaQ: std_logic;
signal teclaA: std_logic;
signal clTeclaA: std_logic;
signal ldTeclaA: std_logic;
signal teclaP: std_logic;
signal clTeclaP: std_logic;
signal ldTeclaP: std_logic;
signal teclaL: std_logic;
signal clTeclaL: std_logic;
signal ldTeclaL: std_logic;
signal teclaSPC: std_logic;
signal clTeclaSPC: std_logic;
signal ldTeclaSPC: std_logic;
--señales sonido
signal ldScancode: std_logic;
signal buzz,onda,silencio: std_logic;
signal cuentaOscilador: std_logic_vector(17 downto 0);
signal clOscilador: std_logic;
--señales depuracion
signal st : std_logic_vector (2 downto 0);
begin
interfazPS2: ps2KeyboardInterface port map (
rst => reset,
clk => clk,
ps2Clk => ps2Clk,
ps2Data => ps2Data,
data => scancode,
newData => newData,
newDataAck => newDataAck
);
hSync <= senialHSync;
vSync <= senialVSync;
pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rcampo,Rpelota,
Rpalas,Gcampo,Gpelota,Gpalas,Bcampo,Bpelota,Bpalas)
begin
--cont mod 1589 (pixelCont para sincronismo horizontal)
if (cuentaPixelCont = "11000110100") then
finPixelCont <= '1';
else
finPixelCont <= '0';
end if;
if(reset = '0')then
cuentaPixelCont <= (others => '0');
finPixelCont <= '0';
elsif(clk'event and clk = '1') then
if (cuentaPixelCont /= "11000110100") then --1588
cuentaPixelCont <= cuentaPixelCont + '1';
elsif (cuentaPixelCont = "11000110100") then
cuentaPixelCont <= (others => '0');
end if;
end if;
--cont mod 528 (lineCont para sincronismo vertical)
if(reset = '0')then
cuentaLineCont <= (others => '0');
elsif(clk'event and clk = '1') then
if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527
cuentaLineCont <= cuentaLineCont + '1';
elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then
cuentaLineCont <= (others => '0');
end if;
end if;
--comparaciones
if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if;
if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if;
if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if;
if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if;
if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if;
if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if;
senialHSync <= comp2 nand comp3;
senialVSync <= comp5 nand comp6;
if (senialHSync = '0' or senialVSync = '0') then --no pinta
R <= "000";
G <= "000";
B <= "000";
else
R(2) <= ( (not (comp1 or comp4)) and (Rcampo(2) or Rpalas(2) or Rpelota(2)) );
R(1) <= ( (not (comp1 or comp4)) and (Rcampo(1) or Rpalas(1) or Rpelota(1)) );
R(0) <= ( (not (comp1 or comp4)) and (Rcampo(0) or Rpalas(0) or Rpelota(0)) );
G(2) <= ( (not (comp1 or comp4)) and (Gcampo(2) or Gpalas(2) or Gpelota(2)) );
G(1) <= ( (not (comp1 or comp4)) and (Gcampo(1) or Gpalas(1) or Gpelota(1)) );
G(0) <= ( (not (comp1 or comp4)) and (Gcampo(0) or Gpalas(0) or Gpelota(0)) );
B(2) <= ( (not (comp1 or comp4)) and (Bcampo(2) or Bpalas(2) or Bpelota(2)) );
B(1) <= ( (not (comp1 or comp4)) and (Bcampo(1) or Bpalas(1) or Bpelota(1)) );
B(0) <= ( (not (comp1 or comp4)) and (Bcampo(0) or Bpalas(0) or Bpelota(0)) );
end if;
-- --para pintar un damero y probar la generación de hSync y vSync:
-- R(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- R(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- R(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
end process;
--########################## PINTAR JUEGO ###############################--
-- vertical: 479 limite de pixeles visibles
-- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4
-- 1 pixeles -> x
-- horizontal: 1257 limite de pixeles visibles
-- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8
-- 1 pixeles -> x
pintarCampo: process(cuentaLineCont,cuentaPixelCont)
begin
-- inicializacion
Rcampo <= "000";
Gcampo <= "000";
Bcampo <= "000";
--linea continua superior
if (cuentaLineCont(9 downto 2) = 8) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
--red
if (cuentaPixelCont(10 downto 3) = 76) then --mitad del campo,pintar la red
if ( (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) <= 16) or
(cuentaLineCont(9 downto 2) > 23 and cuentaLineCont(9 downto 2) <= 31) or
(cuentaLineCont(9 downto 2) > 39 and cuentaLineCont(9 downto 2) <= 47) or
(cuentaLineCont(9 downto 2) > 55 and cuentaLineCont(9 downto 2) <= 63) or
(cuentaLineCont(9 downto 2) > 71 and cuentaLineCont(9 downto 2) <= 79) or
(cuentaLineCont(9 downto 2) > 87 and cuentaLineCont(9 downto 2) <= 95) or
(cuentaLineCont(9 downto 2) > 103 and cuentaLineCont(9 downto 2) <= 111)
) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
end if;
--linea continua inferior
if (cuentaLineCont(9 downto 2) = 112) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
end process pintarCampo;
pintarPalas: process(cuentaLineCont,cuentaPixelCont,pixelPalaIzq,pixelPalaDer)
begin
-- inicializacion
Rpalas <= "000";
Gpalas <= "000";
Bpalas <= "000";
--pala izquierda
if (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaPixelCont(10 downto 3) = 8) then --linea de la pala
if (cuentaLineCont(9 downto 2) >= pixelPalaIzq and
cuentaLineCont(9 downto 2) <= pixelPalaIzq+16) then--la pala en si (longitud pala= 16)
Rpalas <= "111";
Gpalas <= "111";
Bpalas <= "111";
end if;
end if;
end if;
--pala derecha
if (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaPixelCont(10 downto 3) = 145) then --linea de la pala
if (cuentaLineCont(9 downto 2) >= pixelPalaDer and
cuentaLineCont(9 downto 2) <= pixelPalaDer+16) then --la pala en si (longitud pala= 16)
Rpalas <= "111";
Gpalas <= "111";
Bpalas <= "111";
end if;
end if;
end if;
end process pintarPalas;
pintarPelota: process(cuentaLineCont,cuentaPixelCont,pixelPelotaVer,pixelPelotaHor)
begin
-- inicializacion
Rpelota <= "000";
Gpelota <= "000";
Bpelota <= "000";
--pelota
if (cuentaLineCont(9 downto 2) > 8 and
cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaLineCont(9 downto 2) = pixelPelotaVer and
cuentaPixelCont(10 downto 3) = pixelPelotaHor) then --la pelota en si
Rpelota <= "000";--Rpelota <= "111";
Gpelota <= "111";
Bpelota <= "000";--Bpelota <= "111";
end if;
end if;
end process pintarPelota;
--#########################################################################--
contadorMediaDecima: process(reset,clk,cuenta1dec) --contador mod 5.000.000 (de 0 a 4.999.999)
begin
if (cuenta1dec = "10011000100101100111111") then
finCuenta1Dec <= '1';
else
finCuenta1Dec <= '0';
end if;
if(reset = '0')then
cuenta1dec <= (others => '0');
finCuenta1Dec <= '0';
elsif(clk'event and clk = '1') then
if (cuenta1dec /= "10011000100101100111111") then
cuenta1dec <= cuenta1dec + 1;
elsif (cuenta1dec = "10011000100101100111111") then
cuenta1dec <= (others => '0');
end if;
end if;
end process contadorMediaDecima;
palas: process(clk,reset,arribaPalaIzq,abajoPalaIzq,pixelPalaIzq,arribaPalaDer,
abajoPalaDer,pixelPalaDer)
begin
--pala izq: cont mod 102 y pala der: cont mod 102
if(reset = '0')then
pixelPalaIzq <= "0110100"; --en medio: (120/2)-8 = 52
pixelPalaDer <= "0110100"; --en medio: (120/2)-8 = 52
elsif(clk'event and clk = '1') then
if (finCuenta1Dec = '1') then
--pala izq
if (arribaPalaIzq = '1' and (pixelPalaIzq > 9) and (pixelPalaIzq /= 9)) then --si orden=arriba and (todavia puede subir)
pixelPalaIzq <= pixelPalaIzq - '1';
end if;
if (abajoPalaIzq = '1' and (pixelPalaIzq < (111 -16)) and (pixelPalaIzq /= 111-16)) then --si orden=abajo and (todavia puede bajar)
pixelPalaIzq <= pixelPalaIzq + '1';
end if;
--pala der
if (arribaPalaDer = '1' and (pixelPalaDer > 9) and (pixelPalaDer /= 9)) then --si orden=arriba and (todavia puede subir)
pixelPalaDer <= pixelPalaDer - '1';
end if;
if (abajoPalaDer = '1' and (pixelPalaDer < (111 -16)) and (pixelPalaDer /= 111-16)) then --si orden=abajo and (todavia puede bajar)
pixelPalaDer <= pixelPalaDer + '1';
end if;
end if;
if (teclaSPC = '1') then
pixelPalaIzq <= "0110100"; --en medio: (120/2)-8 = 52
pixelPalaDer <= "0110100"; --en medio: (120/2)-8 = 52
end if;
end if;
end process palas;
pelota: process(clk,reset,verticalPelota,horizontalPelota,pixelPelotaHor,pixelPelotaVer)
begin
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then
pixelPelotaVer <= "0111001"; --en medio: (120/2) = aprox 57
pixelPelotaHor <= "01000110"; --en medio: (153/2) = aprox 76. la ponemos a la izq, en 70
elsif (clk'event and clk = '1') then
if(finCuenta1Dec = '1' and moverPelota = '1') then
--contador vertical
if (verticalPelota = '0') then
pixelPelotaVer <= pixelPelotaVer - '1'; --va hacia arriba
else
pixelPelotaVer <= pixelPelotaVer + '1'; --va hacia abajo
end if;
--contador horizontal
if (horizontalPelota = '0') then
pixelPelotaHor <= pixelPelotaHor - '1'; --va hacia izquierda
else
pixelPelotaHor <= pixelPelotaHor + '1'; --va hacia derecha
end if;
end if;
if (teclaSPC = '1') then
pixelPelotaVer <= "0111001"; --en medio: (120/2) = aprox 57
pixelPelotaHor <= "01000110"; --en medio: (153/2) = aprox 76. la ponemos a la izq, en 70
end if;
end if;
--controlador de movimiento
if (reset = '0')then
moverPelota <= '1';
horizontalPelota <= '1';
verticalPelota <= '1';
buzz <= '0';
elsif (clk'event and clk = '1') then
if (finCuenta1Dec='1') then --chequeo de colision
buzz <= '0';
--pala izquierda
if (pixelPelotaHor = 10) then --esta enfrente de la pala
if (pixelPelotaVer >= pixelPalaIzq and pixelPelotaVer <= pixelPalaIzq+16 ) then --choca con la pala
horizontalPelota <= '1';
buzz <= '1';
end if;
end if;
--pala derecha
if (pixelPelotaHor = 143) then --esta enfrente de la pala
if (pixelPelotaVer >= pixelPalaDer and pixelPelotaVer <= pixelPalaDer+16 ) then --choca con la pala
horizontalPelota <= '0';
buzz <= '1';
end if;
end if;
--campo arriba
if (pixelPelotaVer = 10) then --esta enfrente de la barrera =10
verticalPelota <= '1';
buzz <= '1';
end if;
--campo abajo
if (pixelPelotaVer = 110) then --esta enfrente de la barrera =110
verticalPelota <= '0';
buzz <= '1';
end if;
--fuera
if (pixelPelotaHor = 1 or pixelPelotaHor = 155) then
moverPelota <= '0';
buzz <= '1';
end if;
if (teclaSPC = '1') then
moverPelota <= '1';
horizontalPelota <= '1';
verticalPelota <= '1';
buzz <= '0';
end if;
end if;
end if;
end process pelota;
--maquina de estados con registros de flags-------------------------------------------------
controladorEstados: process (clk, reset, newData, scancode)
begin
if(reset = '0') then
estado <= pulsadas;
elsif (clk'event and clk = '1') then
estado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego
case estado is
when pulsadas =>
estado <= pulsadas;
if (newData = '1' and scancode = "11110000") then --11110000: F0
estado <= despulsadas;
end if;
when despulsadas =>
estado <= despulsadas;
if (newData = '1') then
estado <= pulsadas;
end if;
end case;
end if;
end process;
generadorSalidaMealy: process (newDataAck, scancode, estado, newData)
begin
newDataAck <= '0';
clTeclaQ <= '0';
clTeclaA <= '0';
clTeclaP <= '0';
clTeclaL <= '0';
clTeclaSPC <= '0';
ldTeclaQ <= '0';
ldTeclaA <= '0';
ldTeclaP <= '0';
ldTeclaL <= '0';
ldTeclaSPC <= '0';
case estado is
when pulsadas =>
if (newData = '1') then --11110000: F0
case scancode is --registros de flags:
when "00010101" => ldTeclaQ <= '1'; clTeclaQ <= '0'; --Q=15
when "00011100" => ldTeclaA <= '1'; clTeclaA <= '0'; --A=1C
when "01001101" => ldTeclaP <= '1'; clTeclaP <= '0'; --P=4D
when "01001011" => ldTeclaL <= '1'; clTeclaL <= '0'; --L=4B
when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when despulsadas =>
if (newData = '1') then
case scancode is --registros de flags:
when "00010101" => ldTeclaQ <= '0'; clTeclaQ <= '1'; --Q=15
when "00011100" => ldTeclaA <= '0'; clTeclaA <= '1'; --A=1C
when "01001101" => ldTeclaP <= '0'; clTeclaP <= '1'; --P=4D
when "01001011" => ldTeclaL <= '0'; clTeclaL <= '1'; --L=4B
when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when others => null;
end case;
end process;
generadorSalidaMoore: process (estado) --genera st
begin
case estado is
when pulsadas =>
st <= "000";
when despulsadas =>
st <= "001";
end case;
end process;
conversor7seg: process(st)
begin
case st is
-- gfedcba
when "000" => segs <= "0111111"; -- cerrado: Locked
when "001" => segs <= "0000110";
when OTHERS => segs <= "1111001"; -- error
end case;
end process;
-----------------------------------------------------------------------------
outteclaQ <= teclaQ;
arribaPalaIzq <= teclaQ and not teclaA;
abajoPalaIzq <= teclaA;
arribaPalaDer <= teclaP and not teclaL;
abajoPalaDer <= teclaL;
biestableDTeclaQ: process(reset,clk,ldTeclaQ,clTeclaQ)
begin
if(reset = '0')then
teclaQ <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaQ = '1') then
teclaQ <= '0';
elsif (ldTeclaQ = '1') then
teclaQ <= '1';
end if;
end if;
end process biestableDTeclaQ;
biestableDTeclaA: process(reset,clk,ldTeclaA,clTeclaA)
begin
if(reset = '0')then
teclaA <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaA = '1') then
teclaA <= '0';
elsif (ldTeclaA = '1') then
teclaA <= '1';
end if;
end if;
end process biestableDTeclaA;
biestableDTeclaP: process(reset,clk,ldTeclaP,clTeclaP)
begin
if(reset = '0')then
teclaP <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaP = '1') then
teclaP <= '0';
elsif (ldTeclaP = '1') then
teclaP <= '1';
end if;
end if;
end process biestableDTeclaP;
biestableDTeclaL: process(reset,clk,ldTeclaL,clTeclaL)
begin
if(reset = '0')then
teclaL <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaL = '1') then
teclaL <= '0';
elsif (ldTeclaL = '1') then
teclaL <= '1';
end if;
end if;
end process biestableDTeclaL;
biestableDTeclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC)
begin
if(reset = '0')then
teclaSPC <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaSPC = '1') then
teclaSPC <= '0';
elsif (ldTeclaSPC = '1') then
teclaSPC <= '1';
end if;
end if;
end process biestableDTeclaSPC;
----- GENERACIÓN DE SONIDO --------------------------------------------------
oscilador18bits: process(clk,reset,clOscilador)
begin
if(reset = '0')then
cuentaOscilador <= (others => '0');
onda <= '0'; --reset biestable T
elsif(clk'event and clk = '1') then
if (clOscilador = '1') then
cuentaOscilador <= (others => '0');
onda <= not onda;
else
cuentaOscilador <= cuentaOscilador + 1;
end if;
end if;
end process oscilador18bits;
generadorSonido: process(clk,reset,cuentaOscilador,buzz,onda,silencio)
begin
if (cuentaOscilador = "010111010101001101") then -- comparador del oscilador
clOscilador <= '1';
else
clOscilador <= '0';
end if;
if (buzz = '0') then -- puerta NOR para generar silencio
silencio <= '1';
else
silencio <= '0';
end if;
altavoz <= onda or silencio; -- puerta OR para generar onda del sonido
end process generadorSonido;
----- FIN GENERACIÓN DE SONIDO ----------------------------------------------
end Behavioral;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(3 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 8,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE",
lpm_type => "LPM_CONSTANT",
lpm_width => 4
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "8"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
|
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: P2L deserializer (p2l_des_s6.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Takes the DDR P2L bus and converts to SDR that is synchronous
-- to the core clock. Spartan6 FPGAs version.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity p2l_des is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- P2L clock domain (DDR)
--
-- P2L inputs
p2l_valid_i : in std_logic;
p2l_dframe_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0);
---------------------------------------------------------
-- Core clock domain (SDR)
--
-- Deserialized output
p2l_valid_o : out std_logic;
p2l_dframe_o : out std_logic;
p2l_data_o : out std_logic_vector(31 downto 0)
);
end p2l_des;
architecture rtl of p2l_des is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_1_to_n_data_s2_se
generic (
USE_PD : boolean := false; -- Parameter to set generation of phase detector logic
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0); -- Input from se receiver pin
rxioclk : in std_logic; -- IO Clock network
rxserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset line
gclk : in std_logic; -- Global clock
bitslip : in std_logic; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0); -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0); -- Output data
-- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
debug : out std_logic_vector((2*D)+6 downto 0)) ;
end component serdes_1_to_n_data_s2_se;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of inputs and outputs
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal p2l_valid_v : std_logic_vector(0 downto 0);
signal p2l_dframe_v : std_logic_vector(0 downto 0);
signal p2l_valid_t : std_logic_vector(1 downto 0);
signal p2l_dframe_t : std_logic_vector(1 downto 0);
signal p2l_data_t : std_logic_vector(p2l_data_o'range);
signal p2l_valid_t2 : std_logic;
signal p2l_dframe_t2 : std_logic;
signal p2l_data_t2 : std_logic_vector(p2l_data_o'range);
signal p2l_data_bitslip : std_logic_vector(1 downto 0);
signal p2l_data_bitslip_p : std_logic;
--signal p2l_ctrl_v : std_logic_vector(1 downto 0);
--signal p2l_ctrl_t : std_logic_vector(3 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
gen_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- data input bit slip
------------------------------------------------------------------------------
p_din_bitslip : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_bitslip <= (others => '0');
elsif rising_edge(sys_clk_i) then
p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
end if;
end process p_din_bitslip;
p2l_data_bitslip_p <= p2l_data_bitslip(0) and not(p2l_data_bitslip(1));
------------------------------------------------------------------------------
-- data inputs
------------------------------------------------------------------------------
cmp_data_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => D)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_data_i,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0', --p2l_data_bitslip_p,
reset => rst,
data_out => p2l_data_t,
debug_in => "00",
debug => open);
------------------------------------------------------------------------------
-- dframe input
------------------------------------------------------------------------------
cmp_dframe_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_dframe_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_dframe_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_dframe_v(0) <= p2l_dframe_i;
------------------------------------------------------------------------------
-- valid input
------------------------------------------------------------------------------
cmp_valid_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_valid_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_valid_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_valid_v(0) <= p2l_valid_i;
p_in_sys_sync : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_o <= (others => '0');
p2l_dframe_o <= '0';
p2l_valid_o <= '0';
p2l_data_t2 <= (others => '0');
p2l_dframe_t2 <= '0';
p2l_valid_t2 <= '0';
elsif rising_edge(sys_clk_i) then
p2l_data_t2 <= p2l_data_t;
p2l_dframe_t2 <= p2l_dframe_t(0);
p2l_valid_t2 <= p2l_valid_t(0);
p2l_data_o <= p2l_data_t2;
p2l_dframe_o <= p2l_dframe_t2;
p2l_valid_o <= p2l_valid_t2;
end if;
end process p_in_sys_sync;
end rtl;
|
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: P2L deserializer (p2l_des_s6.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Takes the DDR P2L bus and converts to SDR that is synchronous
-- to the core clock. Spartan6 FPGAs version.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity p2l_des is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- P2L clock domain (DDR)
--
-- P2L inputs
p2l_valid_i : in std_logic;
p2l_dframe_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0);
---------------------------------------------------------
-- Core clock domain (SDR)
--
-- Deserialized output
p2l_valid_o : out std_logic;
p2l_dframe_o : out std_logic;
p2l_data_o : out std_logic_vector(31 downto 0)
);
end p2l_des;
architecture rtl of p2l_des is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_1_to_n_data_s2_se
generic (
USE_PD : boolean := false; -- Parameter to set generation of phase detector logic
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0); -- Input from se receiver pin
rxioclk : in std_logic; -- IO Clock network
rxserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset line
gclk : in std_logic; -- Global clock
bitslip : in std_logic; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0); -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0); -- Output data
-- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
debug : out std_logic_vector((2*D)+6 downto 0)) ;
end component serdes_1_to_n_data_s2_se;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of inputs and outputs
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal p2l_valid_v : std_logic_vector(0 downto 0);
signal p2l_dframe_v : std_logic_vector(0 downto 0);
signal p2l_valid_t : std_logic_vector(1 downto 0);
signal p2l_dframe_t : std_logic_vector(1 downto 0);
signal p2l_data_t : std_logic_vector(p2l_data_o'range);
signal p2l_valid_t2 : std_logic;
signal p2l_dframe_t2 : std_logic;
signal p2l_data_t2 : std_logic_vector(p2l_data_o'range);
signal p2l_data_bitslip : std_logic_vector(1 downto 0);
signal p2l_data_bitslip_p : std_logic;
--signal p2l_ctrl_v : std_logic_vector(1 downto 0);
--signal p2l_ctrl_t : std_logic_vector(3 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
gen_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- data input bit slip
------------------------------------------------------------------------------
p_din_bitslip : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_bitslip <= (others => '0');
elsif rising_edge(sys_clk_i) then
p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
end if;
end process p_din_bitslip;
p2l_data_bitslip_p <= p2l_data_bitslip(0) and not(p2l_data_bitslip(1));
------------------------------------------------------------------------------
-- data inputs
------------------------------------------------------------------------------
cmp_data_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => D)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_data_i,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0', --p2l_data_bitslip_p,
reset => rst,
data_out => p2l_data_t,
debug_in => "00",
debug => open);
------------------------------------------------------------------------------
-- dframe input
------------------------------------------------------------------------------
cmp_dframe_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_dframe_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_dframe_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_dframe_v(0) <= p2l_dframe_i;
------------------------------------------------------------------------------
-- valid input
------------------------------------------------------------------------------
cmp_valid_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_valid_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_valid_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_valid_v(0) <= p2l_valid_i;
p_in_sys_sync : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_o <= (others => '0');
p2l_dframe_o <= '0';
p2l_valid_o <= '0';
p2l_data_t2 <= (others => '0');
p2l_dframe_t2 <= '0';
p2l_valid_t2 <= '0';
elsif rising_edge(sys_clk_i) then
p2l_data_t2 <= p2l_data_t;
p2l_dframe_t2 <= p2l_dframe_t(0);
p2l_valid_t2 <= p2l_valid_t(0);
p2l_data_o <= p2l_data_t2;
p2l_dframe_o <= p2l_dframe_t2;
p2l_valid_o <= p2l_valid_t2;
end if;
end process p_in_sys_sync;
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package words is
type X01Z is ('X', '0', '1', 'Z');
type uword is array (0 to 31) of X01Z;
type uword_vector is array (natural range <>) of uword;
function resolve_word ( contribution : uword_vector ) return uword;
subtype word is resolve_word uword;
-- not in book
type ubyte is array (0 to 7) of X01Z;
-- end not in book
end package words;
--------------------------------------------------
package body words is
type table is array (X01Z, X01Z) of X01Z;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_word ( contribution : uword_vector ) return uword is
variable result : uword := (others => 'Z');
begin
for index in contribution'range loop
for element in uword'range loop
result(element) :=
resolution_table( result(element), contribution(index)(element) );
end loop;
end loop;
return result;
end function resolve_word;
end package body words;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package words is
type X01Z is ('X', '0', '1', 'Z');
type uword is array (0 to 31) of X01Z;
type uword_vector is array (natural range <>) of uword;
function resolve_word ( contribution : uword_vector ) return uword;
subtype word is resolve_word uword;
-- not in book
type ubyte is array (0 to 7) of X01Z;
-- end not in book
end package words;
--------------------------------------------------
package body words is
type table is array (X01Z, X01Z) of X01Z;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_word ( contribution : uword_vector ) return uword is
variable result : uword := (others => 'Z');
begin
for index in contribution'range loop
for element in uword'range loop
result(element) :=
resolution_table( result(element), contribution(index)(element) );
end loop;
end loop;
return result;
end function resolve_word;
end package body words;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package words is
type X01Z is ('X', '0', '1', 'Z');
type uword is array (0 to 31) of X01Z;
type uword_vector is array (natural range <>) of uword;
function resolve_word ( contribution : uword_vector ) return uword;
subtype word is resolve_word uword;
-- not in book
type ubyte is array (0 to 7) of X01Z;
-- end not in book
end package words;
--------------------------------------------------
package body words is
type table is array (X01Z, X01Z) of X01Z;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_word ( contribution : uword_vector ) return uword is
variable result : uword := (others => 'Z');
begin
for index in contribution'range loop
for element in uword'range loop
result(element) :=
resolution_table( result(element), contribution(index)(element) );
end loop;
end loop;
return result;
end function resolve_word;
end package body words;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := altera;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000017#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 1;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v3.1
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- ~~~~~~
-- - Initial release of v2.00.a
-- - Updated by pkaruna
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support in v3.1 version of the core
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_misc.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Bus2ip_rdce -- Read
-- Bus2ip_wrce -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-- Processor_clk -- in put same as processor clock
-- Processor_rst -- in put same as processor reset
-- Processor_ack -- input Connected to processor ACK
-- Interrupt_address -- output Connected to processor interrupt address pins
-- Interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- Processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_FAMILY : string := "virtex6";
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 0;
C_HAS_FAST : integer range 0 to 1 := 0;
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
);
port
(
-- Inputs
Clk : in std_logic; --- AXI Clock
Rst_n : in std_logic; --- active low AXI Reset
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(6 downto 0);
Bus2ip_rdce : in std_logic_vector(0 to 16);
Bus2ip_wrce : in std_logic_vector(0 to 16);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- active high MB rst, reset from MicroBlaze
Irq : out std_logic;
Processor_ack : in std_logic_vector(1 downto 0); --- added for fast interrupt mode
Interrupt_address : out std_logic_vector(31 downto 0); --- added for fast interrupt mode
--
Interrupt_address_in : in std_logic_vector(31 downto 0);
Processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Component Declarations
-- ======================
constant C_NUM_INTR : integer := C_NUM_INTR_INPUTS + C_NUM_SW_INTR;
constant RESET_ACTIVE : std_logic := '0';
CONSTANT INDEX_BIT : INTEGER := INTEGER(CEIL(LOG2(REAL(C_NUM_INTR+1))));
constant MICROBLAZE_FIXED_ADDRESS : std_logic_vector := X"00000010";
CONSTANT IVR_ALL_ONES : std_logic_vector(INDEX_BIT-1 downto 0) := (others => '1');
--- *** --- Decision is pending for logic used - mail sent to Bsb on 3rd Oct, 2012
CONSTANT C_USE_METHOD : integer := 1;
--- *** ---
-- Signal declaration
-- ==================
signal processor_rst_n : std_logic;
signal ack_b01 : std_logic;
signal first_ack : std_logic;
signal first_ack_active : std_logic;
signal second_ack : std_logic;
signal first_ack_sync : std_logic;
signal second_ack_sync : std_logic;
signal second_ack_sync_d1 : std_logic;
signal second_ack_sync_d2 : std_logic;
signal second_ack_sync_d3 : std_logic;
signal second_ack_sync_mb_clk : std_logic;
signal Irq_i : std_logic;
signal ivr_data_in : std_logic_vector(INDEX_BIT - 1 downto 0);
signal wr_data_int : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ivr : std_logic_vector(INDEX_BIT - 1 downto 0);
signal ivr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ilr : std_logic_vector(INDEX_BIT downto 0);
signal ilr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal imr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal imr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen_i : std_logic;
signal irq_gen : std_logic;
signal irq_gen_sync : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or_i : std_logic;
signal ack_or : std_logic;
signal ack_or_sync : std_logic;
signal read_ivar : std_logic;
signal write_ivar : std_logic;
signal isr_or : std_logic;
signal ivar_index_mb_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal ivar_index_axi_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal in_idle : std_logic;
signal in_idle_axi_clk : std_logic;
signal idle_and_irq : std_logic;
signal idle_and_irq_d1 : std_logic;
signal ivar_index_sample_en_i : std_logic;
signal ivar_index_sample_en : std_logic;
signal ivar_index_sample_en_mb_clk : std_logic;
signal irq_dis_sample_mb_clk : std_logic;
signal ivar_rd_addr_mb_clk : std_logic_vector(4 downto 0);
signal mer_0_sync : std_logic;
--signal bus2ip_rdce_fast : std_logic_vector(0 to 31);
--signal bus2ip_wrce_fast : std_logic_vector(0 to 31);
signal bus2ip_rdce_fast : std_logic;
signal bus2ip_wrce_fast : std_logic;
signal ivar_rd_data_axi_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivar_rd_data_mb_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_ored_30_0_bits : std_logic;
signal Interrupt_address_in_reg_int : std_logic_vector(31 downto 0);
signal intr_31_deassert_info : std_logic;
signal intr_31_deasserted_d1 : std_logic;
signal intr_31_deasserted : std_logic;
-- --------------------------------------------------------------------------------------
-- -- Function to find logic OR of 32 bit width vector
-- --------------------------------------------------------------------------------------
-- Function OR32_VEC2STDLOGIC (vec_in : std_logic_vector) return std_logic is
-- variable or_out : std_logic := '0';
-- begin
-- for i in 0 to 31 loop
-- or_out := vec_in(i) or or_out;
-- end loop;
-- return or_out;
-- end function Or32_vec2stdlogic;
-- --------------------------------------------------------------------------------------
FUNCTION calc_ivar_ram_addr_bits (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 5;
else
RETURN 4;
end if;
end FUNCTION calc_ivar_ram_addr_bits;
-------------------------------------
FUNCTION calc_ivar_ram_depth (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 32;
else
RETURN 16;
end if;
end FUNCTION calc_ivar_ram_depth;
---------------------------------
CONSTANT IVAR_MEM_ADDR_LINES : INTEGER := calc_ivar_ram_addr_bits (C_NUM_INTR);
CONSTANT IVAR_MEM_DEPTH : INTEGER := calc_ivar_ram_depth (C_NUM_INTR);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
--------------------------------------------------------------------------------------
-- Function to convert std_logic_vector to std_logic
--------------------------------------------------------------------------------------
Function vector_to_scalar (vec_in : std_logic_vector) return std_logic is
variable scalar_out : std_logic := '0';
begin
scalar_out := vec_in(0);
return scalar_out;
end function vector_to_scalar;
-- Begin of architecture
begin
-----
-- active low reset
processor_rst_n <= not Processor_rst;
read <= bus2ip_rdce(0) or -- for ISR
bus2ip_rdce(1) or -- for IPR
bus2ip_rdce(2) or -- for IER
bus2ip_rdce(6) or -- for IVR
bus2ip_rdce(7) or -- for MER
bus2ip_rdce(8) or -- for IMR
bus2ip_rdce(9); -- for ILR
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR - 1 downto 0);
-------------------------------------------------------------------------
-- GENERATING IVAR READ ENABLES
-------------------------------------------------------------------------
bus2ip_rdce_fast <= bus2ip_rdce(16);
bus2ip_wrce_fast <= bus2ip_wrce(16);
write_ivar <= bus2ip_wrce_fast;
read_ivar <= bus2ip_rdce_fast;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------
NO_CASCADE_MASTER_MODE : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------------------------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
-----------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
-----------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
-----------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
-----------------------------------------
end generate NO_CASCADE_MASTER_MODE;
-----------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) & -- to avoide any delay the processor is
(Processor_ack(0) and (not isr_ored_30_0_bits)) ; -- simply passed to below modules
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
--------------------------------------------
end generate ACK_EN_SYNC_EN_GEN;
--------------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
--------------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
--------------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
--------------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
--------------------------------------------
end generate CASCADE_MASTER_MODE_10;
-----------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
------------------------------------
end generate CASCADE_MASTER_MODE_11;
-----------------------------
end generate ACK_EN_SYNC_ON_MB_CLK_GEN;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
NO_CASCADE_MASTER : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate NO_CASCADE_MASTER;
-------------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate CASCADE_MASTER_MODE_10;
-------------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')-- and
--(isr(31) = '0') and
--(ier(31) = '0') -- and
-- (isr_ored_30_0_bits = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
-----------------------------------
end generate CASCADE_MASTER_MODE_11;
-------------------------------
----------------------------------------
end generate ACK_EN_SYNC_ON_AXI_CLK_GEN;
SECOND_ACK_FAST_0_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
second_ack_sync_mb_clk <= ack_or_sync;
end generate SECOND_ACK_FAST_0_GEN;
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (bus2ip_wrce(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((bus2ip_wrce(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
-----------------------------------
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
-----------------------------------
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
-----
begin
-----
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (bus2ip_wrce(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
-----
begin
-----
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
-----
begin
-----
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (bus2ip_wrce(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or bus2ip_wrce(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR - 1) generate
-----
begin
-----
--IAR_NORMAL_MODE_GEN: if ((C_HAS_FAST = 0) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
IAR_NORMAL_MODE_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_NORMAL_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1')) then
iar(i) <= wr_data_int(i);
else
iar(i) <= '0';
end if;
end if;
end process IAR_NORMAL_BIT_P;
-----------------------------------
end generate IAR_NORMAL_MODE_GEN;
---------------------------------
IAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_FAST_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1') and (imr(i) = '0')) then
iar(i) <= wr_data_int(i);
elsif (imr(i) = '1') then
if (((C_KIND_OF_INTR(i) = '1') and (first_ack_sync = '1')) or
((C_KIND_OF_INTR(i) = '0') and (second_ack_sync = '1'))) then
if (i = TO_INTEGER(unsigned(ivar_index_axi_clk))) then -- -- clearing IAR based on Processor_ack in FAST_INTERRUPT mode
iar(i) <= '1';
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
end if;
end process IAR_FAST_BIT_P;
-----------------------------------
end generate IAR_FAST_MODE_GEN;
-------------------------------
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (bus2ip_wrce(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (i < C_NUM_INTR_INPUTS) then
if (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
elsif (i >= C_NUM_INTR_INPUTS) then
if (bus2ip_wrce(0) = '1') then
isr(i) <= Wr_data(i);
end if;
end if;
end if;
end process ISR_P;
----------------------------------------------------------------------
-- Process IMR_P for generating IMR(Interrrupt Mode Register) Register
----------------------------------------------------------------------
IMR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IMR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
imr(i) <= '0';
elsif bus2ip_wrce(8) = '1' then
imr(i) <= wr_data_int(i);
end if;
end if;
end process IMR_P;
end generate IMR_FAST_MODE_GEN;
-----------------------------------
end generate REG_GEN;
---------------------
---------------------------------------------------------------------------
-- Proces IVAR_REG_P for generating IVAR Registers
---------------------------------------------------------------------------
IVAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IVAR_REG_MEM_MB_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 0) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Processor_clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_MB_CLK_GEN;
IVAR_REG_MEM_AXI_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 1) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_AXI_CLK_GEN;
end generate IVAR_FAST_MODE_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR /= C_DWIDTH) generate
-----
begin
-----
ier_out(C_NUM_INTR - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_out(C_NUM_INTR - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
imr_out(C_NUM_INTR - 1 downto 0) <= imr;
imr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-1 downto 0));
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR = C_DWIDTH) generate
-----
begin
-----
ier_out <= ier;
isr_out <= isr;
imr_out <= imr;
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-2 downto 0));
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
ilr_out (INDEX_BIT-1 downto 0) <= ilr(INDEX_BIT - 1 downto 0);
ilr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ilr(INDEX_BIT) = '1' else
(others => '0');
ivr_out (INDEX_BIT-1 downto 0) <= ivr;
ivr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ((ivr = IVR_ALL_ONES)) else
(others => '0');
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
------------------
end generate IPR_GEN;
---------------------
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1 or C_HAS_FAST = 1)
--------------------------------------------------------------------------
IVR_GEN: if ((C_HAS_IVR = 1) or (C_HAS_FAST = 1)) generate
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier) is
variable ivr_in : std_logic_vector(INDEX_BIT - 1 downto 0)
:= (others => '1');
-----
begin
-----
for i in 0 to (C_NUM_INTR - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
--ivr_in := CONV_STD_LOGIC_VECTOR(i, INDEX_BIT);
ivr_in := std_logic_vector(to_unsigned(i, INDEX_BIT));
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ONES if (C_HAS_IVR = 0) and (C_HAS_FAST = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if ((C_HAS_IVR = 0) and (C_HAS_FAST = 0)) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- Generate ILR if (C_HAS_ILR = 1)
--------------------------------------------------------------------------
ILR_GEN: if (C_HAS_ILR = 1) generate
begin
----------------------------------------------------------------------
-- Process ILR_P for generating ILR register
----------------------------------------------------------------------
ILR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ilr <= (others => '1');
elsif (bus2ip_wrce(9) = '1') then
ilr <= Wr_data(INDEX_BIT downto 0);
end if;
end if;
end process ILR_P;
end generate ILR_GEN;
--------------------------------------------------------------------------
-- Assign ILR ALL ONES if (C_HAS_ILR = 0)
--------------------------------------------------------------------------
ILR_NO_GEN: if (C_HAS_ILR = 0) generate
begin
ilr <= (others => '1');
end generate ILR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
signal synced_intr : std_logic := '0';
begin
-----------------------------------------------------------------------
-- Generating the synchronization flip-flops if C_ASYNC_INTR(i) = 1
-----------------------------------------------------------------------
ASYNC_GEN: if C_ASYNC_INTR(i) = '1' and C_NUM_SYNC_FF > 0 generate
signal intr_ff : std_logic_vector(0 to C_NUM_SYNC_FF - 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of intr_ff : signal is "TRUE";
begin
--------------------------------------------
-- Process SYNC_P to synchronize hw_intr
--------------------------------------------
SYNC_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
intr_ff(0) <= Intr(i);
for k in intr_ff'left to intr_ff'right - 1 loop
intr_ff(k + 1) <= intr_ff(k);
end loop;
end if;
end process SYNC_P;
synced_intr <= intr_ff(intr_ff'right);
------------------------------
end generate ASYNC_GEN;
-----------------------------------------------------------------------
-- No synchronization flip-flops if C_ASYNC_INTR(i) = 0
-----------------------------------------------------------------------
SYNC_GEN: if C_ASYNC_INTR(i) = '0' or C_NUM_SYNC_FF = 0 generate
begin
synced_intr <= Intr(i);
end generate SYNC_GEN;
-----------------------------------------------------------------------
-- Generating the edge triggered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if C_KIND_OF_INTR(i) = '1' generate
signal intr_d1 : std_logic;
signal intr_edge : std_logic;
begin
----------------------------------------------------------------
-- Process REG_INTR_EDGE_P to register the interrupt signal edge
----------------------------------------------------------------
REG_INTR_EDGE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if Rst_n = RESET_ACTIVE then
intr_d1 <= not C_KIND_OF_EDGE(i);
else
intr_d1 <= synced_intr;
end if;
end if;
end process REG_INTR_EDGE_P;
-- Creating one-shot edge triggered interrupt
intr_edge <= '1' when (synced_intr = C_KIND_OF_EDGE(i)) and
(intr_d1 = not C_KIND_OF_EDGE(i)) else
'0';
-----------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge triggered interrupt
-----------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if Clk'event and Clk='1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif (intr_edge = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
--------------------------
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if C_KIND_OF_INTR(i) = '0' generate
begin
------------------------------------------------------------------
-- Process LVL_P to generate hw_intr (active high or low)
------------------------------------------------------------------
LVL_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif synced_intr = C_KIND_OF_LVL(i) then
hw_intr(i) <= '1';
end if;
end if;
end process LVL_P;
------------------
end generate LVL_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
-----
begin
-----
irq_gen_i<= isr(0) and ier(0) and ilr(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier, ilr) is
variable ilr_value : integer;
variable irq_gen_int : std_logic;
-----
begin
-----
ilr_value := TO_INTEGER(unsigned( ilr(INDEX_BIT - 1 downto 0) ));
irq_gen_int := '0';
for i in 0 to (isr'length - 1) loop
if (C_HAS_ILR = 1) then
exit when (i = ilr_value) and (ilr(INDEX_BIT) = '0');
end if;
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen_i <= irq_gen_int;
end process IRQ_GEN_P;
----------------------
end generate IRQ_MULTI_INTR_GEN;
--------------------------------
-- Registering irq_gen_i as it will be going through double synchronizer
IRQ_GEN_REG_P : Process(Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_gen <= '0';
else
irq_gen <= irq_gen_i;
end if;
end if;
end process IRQ_GEN_REG_P;
--------------------------
--------------------------------------------------------------
-- Synchronizing irq_gen
--------------------------------------------------------------
IRQ_GEN_SYNC_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
-- Synchronize irq_gen to Processor clock domain
IRQ_GEN_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(irq_gen),
vector_to_scalar(SYNC_DATA_OUT) => irq_gen_sync
);
end generate IRQ_GEN_SYNC_GEN;
IRQ_GEN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
irq_gen_sync <= irq_gen;
end generate IRQ_GEN_SYNC_DISABLE_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
IN_IDLE_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IN_IDLE_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Clk,
RESET_2_n => Rst_n,
DATA_IN => scalar_to_vector(in_idle),
vector_to_scalar(SYNC_DATA_OUT) => in_idle_axi_clk
);
end generate IN_IDLE_SYNC_EN_GEN;
---------------------------------
IN_IDLE_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
in_idle_axi_clk <= in_idle;
end generate IN_IDLE_SYNC_DISABLE_GEN;
--------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen_i and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
------------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
------------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
------------------------------------
IVAR_INDEX_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ivar_index_sample_en,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ivar_index_sample_en_mb_clk
);
end generate IVAR_INDEX_SYNC_EN_GEN;
------------------------------------
IVAR_INDEX_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
end generate IVAR_INDEX_SYNC_DISABLE_GEN;
------------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr_data_in;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
------------------------------------
IVAR_INDEX_MB_REG_P : Process(Processor_clk)
begin
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
ivar_index_mb_clk <= (others => '0');
else
if (ivar_index_sample_en_mb_clk = '1') then
ivar_index_mb_clk <= ivar_index_axi_clk;
else
ivar_index_mb_clk <= ivar_index_mb_clk;
end if;
end if;
end if;
end process IVAR_INDEX_MB_REG_P;
------------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
------------------------------------
end generate IVAR_INDEX_SYNC_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen_i;
IDLE_NOT_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_NOT_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
IRQ_DIS_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => irq_dis_sample,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => irq_dis_sample_mb_clk
);
end generate IRQ_DIS_SYNC_EN_GEN;
IRQ_DIS_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_DISABLE_GEN;
end generate IRQ_DIS_SYNC_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
in_idle_axi_clk <= in_idle;
------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
--------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
--------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
--------------------------------
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
--------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
--------------------------------
ivar_index_mb_clk <= ivar_index_axi_clk;
--------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
end generate IVAR_INDEX_SYNC_ON_AXI_CLK_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen;
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_ON_AXI_CLK_GEN;
NO_IRQ_DIS_SYNC: if (C_HAS_FAST = 0) or (C_HAS_ILR = 0) generate
begin
irq_dis_sample_mb_clk <= '0';
end generate NO_IRQ_DIS_SYNC;
----------------------------------------------------------------------
-- MER_0_DOUBLE_SYNC_I to synchronize MER(0) with Processor_clk
----------------------------------------------------------------------
MER_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize mer(0) to Processor clock domain
MER_0_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(mer(0)),
vector_to_scalar(SYNC_DATA_OUT) => mer_0_sync
);
end generate MER_SYNC_EN_GEN;
------------------------------
MER_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
mer_0_sync <= mer(0);
end generate MER_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
-- Level IRQ generation if C_HAS_FAST is 1
IRQ_LEVEL_FAST_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((ivar_index_sample_en_mb_clk = '1')) then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-----------------------------
GEN_LEVEL_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
-----------------------------
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-- local signal declaration
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
end generate IRQ_LEVEL_FAST_ON_MB_CLK_GEN;
------------------------------------------------------------------
IRQ_LEVEL_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-------------------------------
GEN_LEVEL_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
----------------------------
-- Interrupt_address <= ivar_rd_data_mb_clk;
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
-------------------------------------------
end generate IRQ_LEVEL_FAST_ON_AXI_CLK_GEN;
-- Level IRQ generation if C_HAS_FAST is 0
IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Processor_clk) is
begin
if(Processor_clk'event and Processor_clk = '1') then
if ((processor_rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
-------------------------------------
Interrupt_address <= (others => '0');
-------------------------------------
end generate IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN;
IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_ON_AXI_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_ON_AXI_P;
Interrupt_address <= (others => '0');
end generate IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN;
end generate IRQ_LEVEL_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
ack_or_i <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or_i <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
----------------------------------
ACK_OR_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ack_or <= '0';
else
ack_or <= ack_or_i;
end if;
end if;
end process ACK_OR_REG_P;
-------------------------
ACK_OR_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
ACK_OR_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ack_or,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ack_or_sync
);
end generate ACK_OR_SYNC_EN_GEN;
ACK_OR_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
ack_or_sync <= ack_or;
end generate ACK_OR_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
IRQ_EDGE_FAST_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
GEN_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------
end generate IRQ_EDGE_FAST_GEN;
IRQ_EDGE_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
---------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
---------------------------
GEN_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-----------------------
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------------------
end generate IRQ_EDGE_FAST_ON_AXI_CLK_GEN;
--IRQ_EDGE_NORMAL_GEN: if (C_HAS_FAST = 0) generate
IRQ_EDGE_NO_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_NO_MB_CLK_GEN;
IRQ_EDGE_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK, WAIT_SYNC);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
if (C_DISABLE_SYNCHRONIZERS = 1) then
current_state <= IDLE;
else
current_state <= WAIT_SYNC;
end if;
else
current_state <= WAIT_ACK;
end if;
when WAIT_SYNC => current_state <= IDLE;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_MB_CLK_GEN;
--end generate IRQ_EDGE_NORMAL_GEN;
end generate IRQ_EDGE_GEN;
--Read data in Normal mode (C_HAS_FAST = 0)
OUTPUT_DATA_NORMAL_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out,
ilr_out, ivr_out, mer) is
-----
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate OUTPUT_DATA_NORMAL_GEN;
--Read data in mixed mode (C_HAS_FAST = 1) and C_EN_CASCADE_MODE = 1 and C_CASCADE_MASTER = 1
CASCADE_OP_DATA_FAST_GEN: if ((C_HAS_FAST = 1) and
(C_EN_CASCADE_MODE = 1)
) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk,
Interrupt_address_in_reg_int,
ier ,
isr ,
isr_ored_30_0_bits) is
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then -- read IVAR of 31st bit in case the interrupt is present
if((isr(31) = '1') and -- else to read IVAR of lower modules the processor has to
(ier(31) = '1') and -- initiate the transaction for lower module separately
(isr_ored_30_0_bits = '0')
)then
Rd_data <= Interrupt_address_in_reg_int;
else
Rd_data <= ivar_rd_data_axi_clk;
end if;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
NO_CASCADE_OP_DATA_FAST_GEN: if (C_HAS_FAST = 1) and
(C_CASCADE_MASTER = 0) and
(C_EN_CASCADE_MODE = 0)
generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk) is
begin
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then
Rd_data <= ivar_rd_data_axi_clk;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate NO_CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
end imp;
|
-- NEED RESULT: ARCH00114.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00114: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00114: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00114
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00114)
-- ENT00114_Test_Bench(ARCH00114_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00114 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00114.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00114" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00114" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00114" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
--
end ARCH00114 ;
--
entity ENT00114_Test_Bench is
end ENT00114_Test_Bench ;
--
architecture ARCH00114_Test_Bench of ENT00114_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00114 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00114_Test_Bench ;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-------------------------------------------------------------------------
--
-- 32 bits PROCESSOR TESTBENCH LITTLE ENDIAN 13/october/2004
--
-- It must be observed that the processor is hold in reset
-- (rstCPU <= '1') at the start of simulation, being activated
-- (rstCPU <= '0') just after the end of the object file reading be the
-- testbench.
--
-- This testbench employs two memories, implying a HARVARD organization
--
-- Changes:
-- 16/05/2012 (Ney Calazans)
-- - Corrected bug in memory filling during reset. The instruction
-- memory fill process, makes the processor produce "ce" signals to
-- memory which ended up by filling data memory with rubbish at
-- the same time. To solve this, the first line of the data memory
-- Dce control signal generation was changed from
-- -- ce='1' or go_d='1' to
-- -- (ce='1' and rstCPU/='1') or go_d='1'
-- - Also, there was a problem with the data memory write operation in
-- monocycle MIPS implementations: when multiple SW instructions
-- were issued one after the other, the write operation was executed
-- in two sets of memory positions at once after the first SW. To
-- solve this the data signal was removed from the memory write
-- process sensitivity list.
-- 10/10/2015 (Ney Calazans)
-- - Signal bw from memory set to '1', since the CPU
-- does not generate it anymore.
-- 28/10/2016 (Ney Calazans)
-- - Also, regX defs were changed to wiresX, to improve
-- code readability.
-- 02/06/2017 (Ney Calazans) - bugfix
-- - tmp_address changed to int_address in the memory definition
-- -IN the definition of the memory read/write processes,
-- CONV_INTEGER(low_address+3)<=MEMORY_SIZE was changed to
-- CONV_INTEGER(low_address)<=MEMORY_SIZE-3
-- This avoids an error that freezes the simulation when the
-- ALU contains a large number (>65533) in its output
-- immediately before an LW or SW instruction.
-------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use std.textio.all;
package aux_functions is
subtype wires32 is std_logic_vector(31 downto 0);
subtype wires16 is std_logic_vector(15 downto 0);
subtype wires8 is std_logic_vector( 7 downto 0);
subtype wires4 is std_logic_vector( 3 downto 0);
-- definio do tipo 'memory', que ser utilizado para as memrias de dados/instrues
constant MEMORY_SIZE : integer := 2048;
type memory is array (0 to MEMORY_SIZE) of wires8;
constant TAM_LINHA : integer := 200;
function CONV_VECTOR( letra : string(1 to TAM_LINHA); pos: integer ) return std_logic_vector;
procedure readFileLine(file in_file: TEXT; outStrLine: out string);
end aux_functions;
package body aux_functions is
--
-- converte um caracter de uma dada linha em um std_logic_vector
--
function CONV_VECTOR( letra:string(1 to TAM_LINHA); pos: integer ) return std_logic_vector is
variable bin: wires4;
begin
case (letra(pos)) is
when '0' => bin := "0000";
when '1' => bin := "0001";
when '2' => bin := "0010";
when '3' => bin := "0011";
when '4' => bin := "0100";
when '5' => bin := "0101";
when '6' => bin := "0110";
when '7' => bin := "0111";
when '8' => bin := "1000";
when '9' => bin := "1001";
when 'A' | 'a' => bin := "1010";
when 'B' | 'b' => bin := "1011";
when 'C' | 'c' => bin := "1100";
when 'D' | 'd' => bin := "1101";
when 'E' | 'e' => bin := "1110";
when 'F' | 'f' => bin := "1111";
when others => bin := "0000";
end case;
return bin;
end CONV_VECTOR;
procedure readFileLine(file in_file: TEXT;
outStrLine: out string) is
variable localLine: line;
variable localChar: character;
variable isString: boolean;
begin
readline(in_file, localLine);
for i in outStrLine'range loop
outStrLine(i) := ' ';
end loop;
for i in outStrLine'range loop
read(localLine, localChar, isString);
outStrLine(i) := localChar;
if not isString then -- found end of line
exit;
end if;
end loop;
end readFileLine;
end aux_functions;
--------------------------------------------------------------------------
-- Module implementing a behavioral model of an ASYNCHRONOUS INTERFACE RAM
--------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use std.textio.all;
use work.aux_functions.all;
entity RAM_mem is
generic( START_ADDRESS: wires32 := (others=>'0') );
port( ce_n, we_n, oe_n, bw: in std_logic; address: in wires32; data: inout wires32);
end RAM_mem;
architecture RAM_mem of RAM_mem is
signal RAM : memory;
signal tmp_address: wires32;
alias low_address: wires16 is tmp_address(15 downto 0); -- baixa para 16 bits devido ao CONV_INTEGER --
begin
tmp_address <= address - START_ADDRESS; -- offset do endereamento --
-- writes in memory ASYNCHRONOUSLY -- LITTLE ENDIAN -------------------
process(ce_n, we_n, low_address) -- Modification in 16/05/2012 for monocycle processors only,
begin
if ce_n='0' and we_n='0' then
if CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
if bw='1' then
RAM(CONV_INTEGER(low_address+3)) <= data(31 downto 24);
RAM(CONV_INTEGER(low_address+2)) <= data(23 downto 16);
RAM(CONV_INTEGER(low_address+1)) <= data(15 downto 8);
end if;
RAM(CONV_INTEGER(low_address )) <= data( 7 downto 0);
end if;
end if;
end process;
-- read from memory
process(ce_n, oe_n, low_address)
begin
if ce_n='0' and oe_n='0' and
CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
data(31 downto 24) <= RAM(CONV_INTEGER(low_address+3));
data(23 downto 16) <= RAM(CONV_INTEGER(low_address+2));
data(15 downto 8) <= RAM(CONV_INTEGER(low_address+1));
data( 7 downto 0) <= RAM(CONV_INTEGER(low_address ));
else
data(31 downto 24) <= (others=>'Z');
data(23 downto 16) <= (others=>'Z');
data(15 downto 8) <= (others=>'Z');
data( 7 downto 0) <= (others=>'Z');
end if;
end process;
end RAM_mem;
-------------------------------------------------------------------------
-----------------------------------------
-- Autores: Vinicius Cerutti e Yuri Bittencourt
-- Disciplina: Organização e arquitetura de Computadores II
-- T1 - Comunicação Serial Periférico-Processador
-- Parte do Periferico
-----------------------------------------
-- peripheral module
-- periferico trabalha na velocidade de 115200 bits por segundo
-------------------------------------------------------------------------
Library ieee;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Entity periferico Is
Port (
clock : In std_logic;
reset : In std_logic;
rxd : In std_logic;
txd : Out std_logic
);
End periferico;
Architecture periferico Of periferico Is
Type State_type Is (a, c, d, e,f);
Signal State : State_type;
Signal dadoSync : std_logic_vector(10 Downto 0);
Signal result : std_logic_vector(9 Downto 0);
Type data_memInf Is Array(0 To 1) Of std_logic_vector(7 Downto 0);
Signal memInf : data_memInf := (Others => (Others => '0'));
Signal contBitsReceiver, contBitsSend : std_logic_vector (7 Downto 0);
Signal contVetor : std_logic_vector (7 Downto 0);
signal enviar_dado_sinc : std_logic := '1';
Begin
Process (reset, clock,rxd)
Begin
If (reset = '1') Then
result <= "0000000000";
dadoSync <= "00000000000";
contBitsSend <= "00000000";
contBitsReceiver <= "00000000";
contVetor<=x"00";
Elsif (clock'EVENT And clock = '1') Then
Case State Is
When a =>
-- envia dado 0x55 para sicronizacao com a interface serial
if(enviar_dado_sinc = '1') Then
contBitsSend <= x"0A";
dadoSync <= "10101010101";
State <= f;
-- os dois dados estao recebidos logo devem ser somados e
-- madandos para o periferico
elsif (contVetor = x"02") then
contBitsSend <= x"00";
result(8 Downto 1) <= memInf(0)(7 Downto 0) + memInf(1)(7 Downto 0);
result(9) <= '1';
State <= e;
-- se ainda nao recebeu os dois valores para realizar a soma
elsif (contVetor /= x"02") Then
contBitsReceiver <= x"08";
-- verifica se o primeiro bit é start bit
If (rxd = '0') Then
State <= c;
else State<=a;
End if;
end if;
-- estado que realiza o recebimento dos bits da interface serial
When c =>
If (contBitsReceiver > 1) Then
memInf(CONV_INTEGER(contVetor)) <= rxd & memInf(CONV_INTEGER(contVetor))(7 Downto 1);
contBitsReceiver <= contBitsReceiver - x"01";
State <= c;
Else
memInf(CONV_INTEGER(contVetor)) <= rxd & memInf(CONV_INTEGER(contVetor))(7 Downto 1);
contBitsReceiver <= contBitsReceiver - x"01";
State <= d;
End If;
-- estado que verifica se existe o stop bit
When d =>
If (rxd /= '0') Then
contVetor <= contVetor + x"01";
State <= a;
Else
State <= d;
End If;
-- estado para enviar os dados do periferico para
-- interface serial
When e =>
If (contBitsSend <= x"08") Then
txd <= result(CONV_INTEGER(contBitsSend));
contBitsSend <= contBitsSend + x"01";
State <= e;
Else
txd <= result(CONV_INTEGER(contBitsSend));
contVetor <= x"00";
State <= a;
end if;
-- estado para enviar o dado de sicronizacao(0x55) para
-- a interface serial
When f =>
if(enviar_dado_sinc ='1') Then
enviar_dado_sinc <='0';
End If;
If (contBitsSend >= x"01") Then
txd <= dadoSync(CONV_INTEGER(contBitsSend));
contBitsSend <= contBitsSend - x"01";
State <= f;
Else
txd <= dadoSync(CONV_INTEGER(contBitsSend));
State <= a;
end if;
When Others =>
State <= a;
End Case;
End If;
End Process;
End periferico;
-------------------------------------------------------------------------
-- CPU PROCESSOR SIMULATION TESTBENCH
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use STD.TEXTIO.all;
use work.aux_functions.all;
entity CPU_tb is
end CPU_tb;
architecture cpu_tb of cpu_tb is
signal Dadress, Ddata, Iadress, Idata,
i_cpu_address, d_cpu_address, data_cpu, tb_add, tb_data : wires32 := (others => '0' );
signal Dce_n, Dwe_n, Doe_n, Ice_n, Iwe_n, Ioe_n, ck, rst, rstCPU,
go_i, go_d, ce, rw, bw: std_logic;
signal mem_ce : std_logic;
signal tx_data,rx_data: std_logic_vector (7 downto 0);
signal tx_av,rx_busy, rx_start: std_logic;
signal rxd,txd,clkPeriferico: std_logic;
file ARQ : TEXT open READ_MODE is "textMips2.txt";
begin
Logica_cola: entity work.FsmLogicaCola
port map (ce => Dce_n,address=>Dadress, mem_ce=>mem_ce, rw=>rw, clock=>ck, reset=>rstCPU, tx_data=>tx_data,
rx_data=>rx_data, tx_av=> tx_av, rx_busy=>rx_busy,rx_start=>rx_start, data => Ddata);
Interface_Serial: entity work.serialinterface
port map (clock=>ck,reset=>rstCPU,rxd=>rxd,txd=>txd,rx_data=>rx_data,rx_start=>rx_start,
rx_busy => rx_busy,tx_data=>tx_data,tx_av=>tx_av
);
perifericoMap: entity work.periferico
port map(clock => clkPeriferico,reset=>rstCPU,rxd=>rxd,txd=>txd);
Data_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"10010000" )
port map (ce_n=>mem_ce, we_n=>Dwe_n, oe_n=>Doe_n, bw=>bw, address=>Dadress, data=>Ddata);
Instr_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"00400000" )
port map (ce_n=>Ice_n, we_n=>Iwe_n, oe_n=>Ioe_n, bw=>'1', address=>Iadress, data=>Idata);
-- data memory signals --------------------------------------------------------
Dce_n <= '0' when (ce='1' and rstCPU/='1') or go_d='1' else '1'; -- Bug corrected here in 16/05/2012
Doe_n <= '0' when (ce='1' and rw='1') else '1';
Dwe_n <= '0' when (ce='1' and rw='0') or go_d='1' else '1';
Dadress <= tb_add when rstCPU='1' else d_cpu_address;
Ddata <= tb_data when rstCPU='1' else data_cpu when (ce='1' and rw='0') else (others=>'Z');
data_cpu <= Ddata when (ce='1' and rw='1') else (others=>'Z');
-- instructions memory signals --------------------------------------------------------
Ice_n <= '0';
Ioe_n <= '1' when rstCPU='1' else '0'; -- impede leitura enquanto est escrevendo
Iwe_n <= '0' when go_i='1' else '1'; -- escrita durante a leitura do arquivo
Iadress <= tb_add when rstCPU='1' else i_cpu_address;
Idata <= tb_data when rstCPU='1' else (others => 'Z');
cpu: entity work.MIPS_MCS port map(
clock=>ck, reset=>rstCPU,
i_address => i_cpu_address,
instruction => Idata,
ce=>ce, rw=>rw, bw=>bw,
d_address => d_cpu_address,
data => data_cpu
);
rst <='1', '0' after 15 ns; -- generates the reset signal
process -- generates the clock signal
begin
ck <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process -- generates the clock signal for peripheral
begin
clkPeriferico <= '1', '0' after 4.34 us;
wait for 8.68 us;
end process;
----------------------------------------------------------------------------
-- this process loads the instruction memory and the data memory during reset
--
--
-- O PROCESSO ABAIXO UMA PARSER PARA LER CDIGO GERADO PELO SPIM NO
-- SEGUINTE FORMATO:
--
-- Text Segment
-- [0x00400000] 0x3c011001 lui $1, 4097 [d2] ; 16: la $t0, d2
-- [0x00400004] 0x34280004 ori $8, $1, 4 [d2]
-- [0x00400008] 0x8d080000 lw $8, 0($8) ; 17: lw $t0,0($t0)
-- .....
-- [0x00400048] 0x0810000f j 0x0040003c [loop] ; 30: j loop
-- [0x0040004c] 0x01284821 addu $9, $9, $8 ; 32: addu $t1, $t1, $t0
-- [0x00400050] 0x08100014 j 0x00400050 [x] ; 34: j x
-- Data Segment
-- [0x10010000] 0x0000faaa 0x00000083 0x00000000 0x00000000
--
----------------------------------------------------------------------------
process
variable ARQ_LINE : LINE;
variable line_arq : string(1 to TAM_LINHA);
variable code : boolean;
variable i, address_flag : integer;
begin
go_i <= '0';
go_d <= '0';
rstCPU <= '1'; -- hold the processor during file reading
code:=true; -- default value of code is 1 (CODE)
wait until rst = '1';
while NOT (endfile(ARQ)) loop -- INCIO DA LEITURA DO ARQUIVO CONTENDO INSTRUO E DADOS -----
--readline(ARQ, ARQ_LINE);
--read(ARQ_LINE, line_arq(1 to ARQ_LINE'length) );
readFileLine(ARQ, line_arq);
if line_arq(1 to 12)="Text Segment" then
code:=true; -- code
elsif line_arq(1 to 12)="Data Segment" then
code:=false; -- data
else
i := 1; -- LEITORA DE LINHA - analizar o loop abaixo para compreender
address_flag := 0; -- para INSTRUO um para (end,inst)
-- para DADO aceita (end, dado 0, dado 1, dado 2 ....)
loop
if line_arq(i) = '0' and line_arq(i+1) = 'x' then -- encontrou indicao de nmero hexa: '0x'
i := i + 2;
if address_flag=0 then
for w in 0 to 7 loop
tb_add( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
address_flag := 1;
else
for w in 0 to 7 loop
tb_data( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
wait for 0.1 ns;
if code=true then go_i <= '1'; -- the go_i signal enables instruction memory writing
else go_d <= '1'; -- the go_d signal enables data memory writing
end if;
wait for 0.1 ns;
tb_add <= tb_add + 4; -- *great!* consigo ler mais de uma word por linha!
go_i <= '0';
go_d <= '0';
address_flag := 2; -- sinaliza que j leu o contedo do endereo;
end if;
end if;
i := i + 1;
-- sai da linha quando chegou no seu final OU j leu par(endereo, instruo) no caso de cdigo
exit when i=TAM_LINHA or (code=true and address_flag=2);
end loop;
end if;
end loop; -- FINAL DA LEITURA DO ARQUIVO CONTENDO INSTRUO E DADOS -----
rstCPU <= '0' after 2 ns; -- release the processor to execute
wait for 4 ns; -- To activate the RST CPU signal
wait until rst = '1'; -- to Hold again!
end process;
end cpu_tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity graycode_dist is
generic(width: integer);
port(
inpt0: in std_logic_vector(width-1 downto 0);
inpt1: in std_logic_vector(width-1 downto 0);
outp: out std_logic_vector(width-1 downto 0)
);
end entity;
architecture dist of graycode_dist is
signal aux0: std_logic_vector(width-1 downto 0);
signal aux1: std_logic_vector(width-1 downto 0);
signal zero: std_logic_vector(width-1 downto 0);
signal max: std_logic_vector(width-1 downto 0);
begin
zero <= (others => '0');
max <= (others => '1');
aux0(width-1) <= inpt0(width-1);
gtb0: for i in width-2 downto 0 generate
aux0(i) <= inpt0(i) xor aux0(i+1);
end generate;
aux1(width-1) <= inpt1(width-1);
gbt1: for i in width-2 downto 0 generate
aux1(i) <= inpt1(i) xor aux1(i+1);
end generate;
outp <= std_logic_vector(unsigned(aux0) - unsigned(aux1)) when aux0 > aux1 else
std_logic_vector(unsigned(aux1) - unsigned(aux0)) when aux0 < aux1 else
zero;
end architecture; |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_lane_v6.vhd
-- Description: PIPE per lane module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_lane_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx_data_o : out std_logic_vector(15 downto 0);
pipe_rx_valid_o : out std_logic;
pipe_rx_chanisaligned_o : out std_logic;
pipe_rx_status_o : out std_logic_vector(2 downto 0);
pipe_rx_phy_status_o : out std_logic;
pipe_rx_elec_idle_o : out std_logic;
pipe_rx_polarity_i : in std_logic;
pipe_tx_compliance_i : in std_logic;
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx_data_i : in std_logic_vector(15 downto 0);
pipe_tx_elec_idle_i : in std_logic;
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx_data_i : in std_logic_vector(15 downto 0);
pipe_rx_valid_i : in std_logic;
pipe_rx_chanisaligned_i : in std_logic;
pipe_rx_status_i : in std_logic_vector(2 downto 0);
pipe_rx_phy_status_i : in std_logic;
pipe_rx_elec_idle_i : in std_logic;
pipe_rx_polarity_o : out std_logic;
pipe_tx_compliance_o : out std_logic;
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx_data_o : out std_logic_vector(15 downto 0);
pipe_tx_elec_idle_o : out std_logic;
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_lane_v6;
architecture v6_pcie of pcie_pipe_lane_v6 is
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant TCQ : integer := 1; -- clock to out delay model
signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx_data_q : std_logic_vector(15 downto 0);
signal pipe_rx_valid_q : std_logic;
signal pipe_rx_chanisaligned_q : std_logic;
signal pipe_rx_status_q : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_q : std_logic;
signal pipe_rx_elec_idle_q : std_logic;
signal pipe_rx_polarity_q : std_logic;
signal pipe_tx_compliance_q : std_logic;
signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_tx_data_q : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_q : std_logic;
signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
signal pipe_rx_valid_qq : std_logic;
signal pipe_rx_chanisaligned_qq : std_logic;
signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_qq : std_logic;
signal pipe_rx_elec_idle_qq : std_logic;
signal pipe_rx_polarity_qq : std_logic;
signal pipe_tx_compliance_qq : std_logic;
signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_qq : std_logic;
signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
begin
v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
pipe_rx_data_o <= pipe_rx_data_i;
pipe_rx_valid_o <= pipe_rx_valid_i;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
pipe_rx_status_o <= pipe_rx_status_i;
pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
pipe_rx_polarity_o <= pipe_rx_polarity_i;
pipe_tx_compliance_o <= pipe_tx_compliance_i;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
pipe_tx_data_o <= pipe_tx_data_i;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
end generate;
v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
pipe_rx_data_o <= pipe_rx_data_q;
pipe_rx_valid_o <= pipe_rx_valid_q;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
pipe_rx_status_o <= pipe_rx_status_q;
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
pipe_rx_polarity_o <= pipe_rx_polarity_q;
pipe_tx_compliance_o <= pipe_tx_compliance_q;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
pipe_tx_data_o <= pipe_tx_data_q;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
end generate;
v6pcie3 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_rx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_tx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
pipe_rx_data_o <= pipe_rx_data_qq;
pipe_rx_valid_o <= pipe_rx_valid_qq;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
pipe_rx_status_o <= pipe_rx_status_qq;
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
pipe_tx_data_o <= pipe_tx_data_qq;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
end generate;
end v6_pcie;
|
----------------------------------------------------------------------------------
-- Thibault Bailly
--
-- create date: 07-03-2017
-- design name:
-- module name: generic_counter
-- description: Generic Counter
--
-- dependencies:
--
-- revision: Initial release
--
-- additional comments:
--
--
--
-- parameters :
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------------------
-- Entity --
----------------------------------------------------------------------------------
entity generic_counter is
generic (
number_at_reset_g : natural; -- Number at reset state
number_at_start_g : natural; -- Number at start state
number_at_end_g : natural; -- Last number before to come back at start number
n_bits_g : natural -- Width bits of output number
);
port (
---- Global Inputs
Clk : in std_logic; -- Main clock
Reset_n : in std_logic; -- Reset synchrone on LOW level
---- Inputs
Load : in std_logic; -- Load the counter : Number_to_be_loaded
Number_to_be_loaded : in std_logic_vector ( (n_bits_g-1) downto 0); -- Use by Load counter
Counting : in std_logic; -- Increments the counter
---- outputs
Out_number : out std_logic_vector ( (n_bits_g-1) downto 0); -- Number of counting
Last_number_before_reboot : out std_logic
);
end generic_counter;
----------------------------------------------------------------------------------
-- Architecture --
----------------------------------------------------------------------------------
architecture arch_generic_counter of generic_counter is
signal counter_int : natural range 0 to number_at_end_g;
begin ----------------------------------------------------------------------------
-- Display generic
assert false
report "**** Generic report for generic_Counter : number_at_reset_g = " &natural'image(number_at_reset_g)
severity note;
assert false
report "**** Generic report for generic_Counter : number_at_start_g = " &natural'image(number_at_start_g)
severity note;
assert false
report "**** Generic report for generic_Counter : number_at_end_g = " &natural'image(number_at_end_g)
severity note;
assert false
report "**** Generic report for generic_Counter : n_bits_g = " &natural'image(n_bits_g)
severity note;
--check generic
---- check number_at_reset_g
assert (((number_at_reset_g) >= 0) and ( (number_at_reset_g-1) <= (2**n_bits_g) ))
report "-- generic_counter.vhd : number_at_reset_g parameter is out of range -- "
severity failure;
---- check number_at_start_g
assert (((number_at_start_g) >= 0) and ( (number_at_start_g-1) <= (2**n_bits_g) ))
report "-- generic_counter.vhd : number_at_start_g parameter is out of range -- "
severity failure;
---- check number_at_end_g
assert (((number_at_end_g) >= 0) and ( (number_at_end_g-1) <= (2**n_bits_g) ))
report "-- generic_counter.vhd : number_at_end_g parameter is out of range -- "
severity failure;
---- check cohenrency
assert ( number_at_start_g < number_at_end_g )
report "-- generic_counter.vhd : number_at_end_g is lower than number_at_start_g -- "
severity failure;
assert ( number_at_reset_g < number_at_end_g )
report "-- generic_counter.vhd : number_at_end_g is lower than number_at_reset_g -- "
severity failure;
--=== counter
process (Clk) is
begin
if rising_edge(Clk) then
if (Reset_n = '0') then
counter_int <= number_at_reset_g;
Last_number_before_reboot <= '0';
elsif (Load='1') then
counter_int <= to_integer(unsigned(Number_to_be_loaded)) ;
Last_number_before_reboot <= '0';
elsif (counting = '1') then
if (counter_int = number_at_end_g ) then
counter_int <= number_at_start_g;
Last_number_before_reboot <= '0';
else
counter_int <= counter_int + 1;
end if;
if (counter_int = (number_at_end_g-1) ) then
Last_number_before_reboot <= '1';
end if;
end if;
end if;
end process;
-- Forwarding port
Out_number <= std_logic_vector( to_unsigned(counter_int, Out_number'length) );
end arch_generic_counter;
----------------------------------------------------------------------------------
-- End --
---------------------------------------------------------------------------------- |
package p is
constant a : integer := 2#1101#;
constant b : integer := 3#20#;
constant c : integer := 8#7#;
constant d : integer := 10#1234#;
constant e : integer := 16#beef01#;
constant f : integer := 2#1_0#;
constant g : integer := 2:1_0:;
constant h : integer := 16#abababab#;
end package;
|
package p is
constant a : integer := 2#1101#;
constant b : integer := 3#20#;
constant c : integer := 8#7#;
constant d : integer := 10#1234#;
constant e : integer := 16#beef01#;
constant f : integer := 2#1_0#;
constant g : integer := 2:1_0:;
constant h : integer := 16#abababab#;
end package;
|
package p is
constant a : integer := 2#1101#;
constant b : integer := 3#20#;
constant c : integer := 8#7#;
constant d : integer := 10#1234#;
constant e : integer := 16#beef01#;
constant f : integer := 2#1_0#;
constant g : integer := 2:1_0:;
constant h : integer := 16#abababab#;
end package;
|
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_dualclock is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_dualclock;
architecture syn of generic_dpram_dualclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal clka_int : std_logic;
signal clkb_int : std_logic;
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process (clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
process (clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_b(i) = '1' then
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
:= db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
|
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)
),
element5(
elementE(3 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);
signal sig9 : record_type_3(func1(A, 5, 6) downto func2(4, 6, 8));
signal sig9 : record_type_3(7 downto 0);
signal sig9 : record_type_3(0 to 7);
signal sig9 : record_type_3(7 downto 0, 3 to 4);
signal sig9 : record_type_3(blah'range);
signal sig9 : record_type_3(element1(7 downto 0));
signal sig9 : record_type_3(blah'range);
signal sig9 : record_type_3( blah'range );
signal sig9 : record_type_3( blah'range --Comment
);
signal sig9 : integer range 0 to 31;
signal sig9 : integer range 0 to 31 := 20;
signal sig9 : integer range (0) to (31) := 20;
begin
end architecture rtl;
|
-- $Id: ram32k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $
--===========================================================================--
-- --
-- ram32k_b16.vhd - 32KByte Block RAM Component for Spartan 3/3E --
-- --
--===========================================================================--
--
-- File name : ram32k_b16.vhd
--
-- Entity name : ram_32k
--
-- Purpose : Implements 32K of Synchronous Static RAM
-- using 16 x Spartan 3/3E RAMB16_S9 block rams
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2005 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2006-04-24 Initial release
-- 0.2 John Kent 2005-06-29 Added CS term to CE decodes. (date ???)
-- 0.3 John Kent 2010-09-14 Renamed "rdata" to "data_out"
-- Renamed "wdata" to "data_in"
-- Added header description
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
entity ram_32k is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (14 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end ram_32k;
architecture rtl of ram_32k is
signal we : std_logic;
signal dp : std_logic_vector(15 downto 0);
signal ce : std_logic_vector(15 downto 0);
signal data_out_0 : std_logic_vector(7 downto 0);
signal data_out_1 : std_logic_vector(7 downto 0);
signal data_out_2 : std_logic_vector(7 downto 0);
signal data_out_3 : std_logic_vector(7 downto 0);
signal data_out_4 : std_logic_vector(7 downto 0);
signal data_out_5 : std_logic_vector(7 downto 0);
signal data_out_6 : std_logic_vector(7 downto 0);
signal data_out_7 : std_logic_vector(7 downto 0);
signal data_out_8 : std_logic_vector(7 downto 0);
signal data_out_9 : std_logic_vector(7 downto 0);
signal data_out_a : std_logic_vector(7 downto 0);
signal data_out_b : std_logic_vector(7 downto 0);
signal data_out_c : std_logic_vector(7 downto 0);
signal data_out_d : std_logic_vector(7 downto 0);
signal data_out_e : std_logic_vector(7 downto 0);
signal data_out_f : std_logic_vector(7 downto 0);
begin
RAM0 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_0,
dop(0) => dp(0),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(0),
en => ce(0),
ssr => rst,
we => we
);
RAM1 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_1,
dop(0) => dp(1),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(1),
en => ce(1),
ssr => rst,
we => we
);
RAM2 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_2,
dop(0) => dp(2),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(2),
en => ce(2),
ssr => rst,
we => we
);
RAM3 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_3,
dop(0) => dp(3),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(3),
en => ce(3),
ssr => rst,
we => we
);
RAM4 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_4,
dop(0) => dp(4),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(4),
en => ce(4),
ssr => rst,
we => we
);
RAM5 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_5,
dop(0) => dp(5),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(5),
en => ce(5),
ssr => rst,
we => we
);
RAM6 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_6,
dop(0) => dp(6),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(6),
en => ce(6),
ssr => rst,
we => we
);
RAM7 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_7,
dop(0) => dp(7),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(7),
en => ce(7),
ssr => rst,
we => we
);
RAM8 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_8,
dop(0) => dp(8),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(8),
en => ce(8),
ssr => rst,
we => we
);
RAM9 : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_9,
dop(0) => dp(9),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(9),
en => ce(9),
ssr => rst,
we => we
);
RAMA : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_a,
dop(0) => dp(10),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(10),
en => ce(10),
ssr => rst,
we => we
);
RAMB : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_b,
dop(0) => dp(11),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(11),
en => ce(11),
ssr => rst,
we => we
);
RAMC : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_c,
dop(0) => dp(12),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(12),
en => ce(12),
ssr => rst,
we => we
);
RAMD : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_d,
dop(0) => dp(13),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(13),
en => ce(13),
ssr => rst,
we => we
);
RAME : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
do => data_out_e,
dop(0) => dp(14),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(14),
en => ce(14),
ssr => rst,
we => we
);
RAMF : RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
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port map (
do => data_out_f,
dop(0) => dp(15),
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp(15),
en => ce(15),
ssr => rst,
we => we
);
my_ram_32k : process ( cs, rw, addr,
data_out_0, data_out_1, data_out_2, data_out_3,
data_out_4, data_out_5, data_out_6, data_out_7,
data_out_8, data_out_9, data_out_a, data_out_b,
data_out_c, data_out_d, data_out_e, data_out_f )
begin
we <= not rw;
case addr(14 downto 11) is
when "0000" =>
data_out <= data_out_0;
when "0001" =>
data_out <= data_out_1;
when "0010" =>
data_out <= data_out_2;
when "0011" =>
data_out <= data_out_3;
when "0100" =>
data_out <= data_out_4;
when "0101" =>
data_out <= data_out_5;
when "0110" =>
data_out <= data_out_6;
when "0111" =>
data_out <= data_out_7;
when "1000" =>
data_out <= data_out_8;
when "1001" =>
data_out <= data_out_9;
when "1010" =>
data_out <= data_out_a;
when "1011" =>
data_out <= data_out_b;
when "1100" =>
data_out <= data_out_c;
when "1101" =>
data_out <= data_out_d;
when "1110" =>
data_out <= data_out_e;
when "1111" =>
data_out <= data_out_f;
when others =>
null;
end case;
ce(0) <= cs and not( addr(14) ) and not( addr(13) ) and not( addr(12) ) and not( addr(11) );
ce(1) <= cs and not( addr(14) ) and not( addr(13) ) and not( addr(12) ) and addr(11) ;
ce(2) <= cs and not( addr(14) ) and not( addr(13) ) and addr(12) and not( addr(11) );
ce(3) <= cs and not( addr(14) ) and not( addr(13) ) and addr(12) and addr(11) ;
ce(4) <= cs and not( addr(14) ) and addr(13) and not( addr(12) ) and not( addr(11) );
ce(5) <= cs and not( addr(14) ) and addr(13) and not( addr(12) ) and addr(11) ;
ce(6) <= cs and not( addr(14) ) and addr(13) and addr(12) and not( addr(11) );
ce(7) <= cs and not( addr(14) ) and addr(13) and addr(12) and addr(11) ;
ce(8) <= cs and addr(14) and not( addr(13) ) and not( addr(12) ) and not( addr(11) );
ce(9) <= cs and addr(14) and not( addr(13) ) and not( addr(12) ) and addr(11) ;
ce(10) <= cs and addr(14) and not( addr(13) ) and addr(12) and not( addr(11) );
ce(11) <= cs and addr(14) and not( addr(13) ) and addr(12) and addr(11) ;
ce(12) <= cs and addr(14) and addr(13) and not( addr(12) ) and not( addr(11) );
ce(13) <= cs and addr(14) and addr(13) and not( addr(12) ) and addr(11) ;
ce(14) <= cs and addr(14) and addr(13) and addr(12) and not( addr(11) );
ce(15) <= cs and addr(14) and addr(13) and addr(12) and addr(11) ;
end process;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ddr, inpad_ddrv
-- File: inpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an input pad connected to a DDR_IREG.
-- The generic tech wrappers are not used for nextreme since this
-- technology is not wrapped by ddr_ireg.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity inpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := x33v;
filter : integer := 0;
strength : integer := 0
);
port (
pad : in std_ulogic;
o1, o2 : out std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddr is
signal d : std_ulogic;
begin
def: if (tech /= easic90) and (tech /= easic45) generate
p : inpad generic map (tech, level, voltage, filter, strength)
port map (pad, d);
ddrreg : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
end generate def;
nex : if (tech = easic90) generate
p : nextreme_inpad generic map (level, voltage)
port map(pad, d);
ddrreg : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
end generate;
n2x : if (tech = easic45) generate
p : n2x_inpad_ddr generic map (level, voltage)
port map (pad, o1, o2, c1, c2, ce, r, s);
d <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 0;
width : integer := 1
);
port (
pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddrv is
begin
n2x : if (tech = easic45) generate
p : n2x_inpad_ddrv generic map (level, voltage, width)
port map (pad, o1, o2, c1, c2, ce, r, s);
end generate;
base : if (tech /= easic45) generate
v : for i in width-1 downto 0 generate
x0 : inpad_ddr generic map (tech, level, voltage, filter, strength)
port map (pad(i), o1(i), o2(i), c1, c2, ce, r, s);
end generate;
end generate;
end;
|
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`protect begin_protected
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/sByX+Fru/6hvOj4nEYSpjSXPUUV4mY+YB9hFbQwOy+9or396/x7yv9t5j03o/jhpYTGu2rjgQQT
FVfOXetxp9hSnlJDNqVNIme9obAucuclKNgP
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:51:11 02/28/2017
-- Design Name:
-- Module Name: gal_brancher - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.tinycpu_common.all;
entity gal_brancher is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (7 downto 0);
condition : in STD_LOGIC_VECTOR (7 downto 0);
execute : buffer STD_LOGIC;
branch : buffer STD_LOGIC;
callorreturn: buffer STD_LOGIC);
end gal_brancher;
architecture Behavioral of gal_brancher is
alias current_opcode: std_logic_vector(3 downto 0) is i(7 downto 4);
alias condition_invert: std_logic is i(3);
alias condition_select: std_logic_vector(2 downto 0) is i(2 downto 0);
signal condition_selected: std_logic;
begin
with condition_select select
condition_selected <= condition(0) when "000",
condition(1) when "001",
condition(2) when "010",
condition(3) when "011",
condition(4) when "100",
condition(5) when "101",
condition(6) when "110",
condition(7) when others;
capture: process (reset, clock, condition_selected, condition_invert)
begin
if (reset = '1') then
execute <= '1';
branch <= '0';
callorreturn <= '0';
else
if (rising_edge(clock)) then
if (execute = '1') then
if (current_opcode = std_logic_vector(opcode_BRA)) then
-- next PC will be at offset, so don't interpret as instruction
execute <= '0';
-- capture the branch flag for next cycle
branch <= condition_invert xor condition_selected;
-- determine if next cycle will be call or return
if (condition_select = "111") then
callorreturn <= '1';
else
callorreturn <= '0';
end if;
else
-- this was a regular 1 byte instruction, next PC will point to one too
execute <= '1';
-- these values will be ignored, but set to 0 for consistency
branch <= '0';
callorreturn <= '0';
end if;
else
-- PC is pointing to branch offset, therefore next cycle should be executed
execute <= '1';
-- these values will be ignored, but set to 0 for consistency
branch <= '0';
callorreturn <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1643.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p08n01i01643pkg is
-- function declarations.
function funcI return INTEGER;
function funcI2 return INTEGER;
end c08s12b00x00p08n01i01643pkg;
package body c08s12b00x00p08n01i01643pkg is
function funcI return INTEGER is
begin
return ( 3 );
end;
function funcI2 return INTEGER is
begin
return ( 3 );
end;
end c08s12b00x00p08n01i01643pkg;
use work.c08s12b00x00p08n01i01643pkg.all;
ENTITY c08s12b00x00p08n01i01643ent IS
END c08s12b00x00p08n01i01643ent;
ARCHITECTURE c08s12b00x00p08n01i01643arch OF c08s12b00x00p08n01i01643ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( funcI = 3 and funcI2 = 3)
report "***PASSED TEST: c08s12b00x00p08n01i01643"
severity NOTE;
assert ( funcI = 3 and funcI2 = 3)
report "***FAILED TEST: c08s12b00x00p08n01i01643 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p08n01i01643arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1643.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p08n01i01643pkg is
-- function declarations.
function funcI return INTEGER;
function funcI2 return INTEGER;
end c08s12b00x00p08n01i01643pkg;
package body c08s12b00x00p08n01i01643pkg is
function funcI return INTEGER is
begin
return ( 3 );
end;
function funcI2 return INTEGER is
begin
return ( 3 );
end;
end c08s12b00x00p08n01i01643pkg;
use work.c08s12b00x00p08n01i01643pkg.all;
ENTITY c08s12b00x00p08n01i01643ent IS
END c08s12b00x00p08n01i01643ent;
ARCHITECTURE c08s12b00x00p08n01i01643arch OF c08s12b00x00p08n01i01643ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( funcI = 3 and funcI2 = 3)
report "***PASSED TEST: c08s12b00x00p08n01i01643"
severity NOTE;
assert ( funcI = 3 and funcI2 = 3)
report "***FAILED TEST: c08s12b00x00p08n01i01643 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p08n01i01643arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1643.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p08n01i01643pkg is
-- function declarations.
function funcI return INTEGER;
function funcI2 return INTEGER;
end c08s12b00x00p08n01i01643pkg;
package body c08s12b00x00p08n01i01643pkg is
function funcI return INTEGER is
begin
return ( 3 );
end;
function funcI2 return INTEGER is
begin
return ( 3 );
end;
end c08s12b00x00p08n01i01643pkg;
use work.c08s12b00x00p08n01i01643pkg.all;
ENTITY c08s12b00x00p08n01i01643ent IS
END c08s12b00x00p08n01i01643ent;
ARCHITECTURE c08s12b00x00p08n01i01643arch OF c08s12b00x00p08n01i01643ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( funcI = 3 and funcI2 = 3)
report "***PASSED TEST: c08s12b00x00p08n01i01643"
severity NOTE;
assert ( funcI = 3 and funcI2 = 3)
report "***FAILED TEST: c08s12b00x00p08n01i01643 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p08n01i01643arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p12n02i01747ent IS
function resolve_bit ( inputs : bit_vector) return bit is
VARIABLE val : bit := '0';
begin
if inputs'length = 0 then
return val;
else
for i in inputs'range LOOP
if inputs(i) = '1' then return '1'; end if;
END LOOP;
return '0';
end if;
end resolve_bit;
END c09s05b00x00p12n02i01747ent;
ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
signal a : resolve_bit bit BUS;
signal b : resolve_bit bit BUS;
signal grd : boolean;
BEGIN
grd <= TRUE after 10 ns,
FALSE after 20 ns;
block_label : BLOCK (grd)
begin
b <= guarded '1' after 1 ns;
end block block_label;
block_label_1 : BLOCK (grd)
begin
TESTING: PROCESS
BEGIN
if GUARD then
a <= '1' after 1 ns;
else
a <= NULL;
end if;
wait on GUARD, a;
END PROCESS TESTING;
end block block_label_1;
process(a,b)
variable f1, f2 : integer := 0;
begin
if (now = 11 ns) and (a=b) then
f1 := 1;
end if;
if (now = 20 ns) and (a=b) then
f2 := 1;
end if;
if (now = 20 ns) then
assert NOT((f1=1) and (f2=1))
report "***PASSED TEST: c09s05b00x00p12n02i01747"
severity NOTE;
assert ((f1=1) and (f2=1))
report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
severity ERROR;
end if;
end process;
END c09s05b00x00p12n02i01747arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p12n02i01747ent IS
function resolve_bit ( inputs : bit_vector) return bit is
VARIABLE val : bit := '0';
begin
if inputs'length = 0 then
return val;
else
for i in inputs'range LOOP
if inputs(i) = '1' then return '1'; end if;
END LOOP;
return '0';
end if;
end resolve_bit;
END c09s05b00x00p12n02i01747ent;
ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
signal a : resolve_bit bit BUS;
signal b : resolve_bit bit BUS;
signal grd : boolean;
BEGIN
grd <= TRUE after 10 ns,
FALSE after 20 ns;
block_label : BLOCK (grd)
begin
b <= guarded '1' after 1 ns;
end block block_label;
block_label_1 : BLOCK (grd)
begin
TESTING: PROCESS
BEGIN
if GUARD then
a <= '1' after 1 ns;
else
a <= NULL;
end if;
wait on GUARD, a;
END PROCESS TESTING;
end block block_label_1;
process(a,b)
variable f1, f2 : integer := 0;
begin
if (now = 11 ns) and (a=b) then
f1 := 1;
end if;
if (now = 20 ns) and (a=b) then
f2 := 1;
end if;
if (now = 20 ns) then
assert NOT((f1=1) and (f2=1))
report "***PASSED TEST: c09s05b00x00p12n02i01747"
severity NOTE;
assert ((f1=1) and (f2=1))
report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
severity ERROR;
end if;
end process;
END c09s05b00x00p12n02i01747arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p12n02i01747ent IS
function resolve_bit ( inputs : bit_vector) return bit is
VARIABLE val : bit := '0';
begin
if inputs'length = 0 then
return val;
else
for i in inputs'range LOOP
if inputs(i) = '1' then return '1'; end if;
END LOOP;
return '0';
end if;
end resolve_bit;
END c09s05b00x00p12n02i01747ent;
ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
signal a : resolve_bit bit BUS;
signal b : resolve_bit bit BUS;
signal grd : boolean;
BEGIN
grd <= TRUE after 10 ns,
FALSE after 20 ns;
block_label : BLOCK (grd)
begin
b <= guarded '1' after 1 ns;
end block block_label;
block_label_1 : BLOCK (grd)
begin
TESTING: PROCESS
BEGIN
if GUARD then
a <= '1' after 1 ns;
else
a <= NULL;
end if;
wait on GUARD, a;
END PROCESS TESTING;
end block block_label_1;
process(a,b)
variable f1, f2 : integer := 0;
begin
if (now = 11 ns) and (a=b) then
f1 := 1;
end if;
if (now = 20 ns) and (a=b) then
f2 := 1;
end if;
if (now = 20 ns) then
assert NOT((f1=1) and (f2=1))
report "***PASSED TEST: c09s05b00x00p12n02i01747"
severity NOTE;
assert ((f1=1) and (f2=1))
report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
severity ERROR;
end if;
end process;
END c09s05b00x00p12n02i01747arch;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Fri Mar 04 11:10:30 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.vhdl
-- Design : clk_wiz_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_1 is
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end clk_wiz_1;
architecture stub of clk_wiz_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
use work.mpu_pkg.all;
entity mpu is
generic (
CLK_PROC_FREQ : integer;
ACCELERO_SIZE : integer;
GYROSCOPE_SIZE : integer;
COMPASS_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
ad0 : out std_logic;
sda : inout std_logic;
scl : inout std_logic;
---------------------- accelero flow --------------------
accelero_data : out std_logic_vector(ACCELERO_SIZE-1 downto 0);
accelero_fv : out std_logic;
accelero_dv : out std_logic;
--------------------- gyroscope flow --------------------
gyroscope_data : out std_logic_vector(GYROSCOPE_SIZE-1 downto 0);
gyroscope_fv : out std_logic;
gyroscope_dv : out std_logic;
---------------------- compass flow ---------------------
compass_data : out std_logic_vector(COMPASS_SIZE-1 downto 0);
compass_fv : out std_logic;
compass_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end mpu;
architecture rtl of mpu is
component mpu_acqui
port (
clk_proc : in std_logic;
reset : in std_logic;
sda : inout std_logic;
scl : inout std_logic;
AD0 : out std_logic;
parameters : in param;
accelero : out flow;
gyroscope : out flow;
compass : out flow
);
end component;
component mpu_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
gyro_config_reg : out std_logic_vector(31 downto 0);
accel_config_reg : out std_logic_vector(31 downto 0);
spl_rate_reg : out std_logic_vector(31 downto 0);
gain_compass_reg : out std_logic_vector(31 downto 0);
fz_compass_reg : out std_logic_vector(31 downto 0);
accel_off_x_reg : out std_logic_vector(31 downto 0);
accel_off_y_reg : out std_logic_vector(31 downto 0);
accel_off_z_reg : out std_logic_vector(31 downto 0);
gyro_off_x_reg : out std_logic_vector(31 downto 0);
gyro_off_y_reg : out std_logic_vector(31 downto 0);
gyro_off_z_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal enable_reg : std_logic_vector (31 downto 0);
signal gyro_config_reg : std_logic_vector (31 downto 0);
signal accel_config_reg : std_logic_vector (31 downto 0);
signal spl_rate_reg : std_logic_vector (31 downto 0);
signal gain_compass_reg : std_logic_vector (31 downto 0);
signal fz_compass_reg : std_logic_vector (31 downto 0);
signal accel_off_x_reg : std_logic_vector (31 downto 0);
signal accel_off_y_reg : std_logic_vector (31 downto 0);
signal accel_off_z_reg : std_logic_vector (31 downto 0);
signal gyro_off_x_reg : std_logic_vector (31 downto 0);
signal gyro_off_y_reg : std_logic_vector (31 downto 0);
signal gyro_off_z_reg : std_logic_vector (31 downto 0);
signal parameters : param;
signal accelero, gyroscope, compass : flow;
begin
mpu_acqui_inst : mpu_acqui
port map(
clk_proc => clk_proc,
reset => reset_n,
sda => sda,
scl => scl,
AD0 => AD0,
parameters => parameters,
accelero => accelero,
gyroscope => gyroscope,
compass => compass
);
parameters(0)(31 downto 13) <= enable_reg(0) & spl_rate_reg(7 downto 0) & gyro_config_reg(1 downto 0) & accel_config_reg(1 downto 0)
& gain_compass_reg(2 downto 0) & fz_compass_reg(2 downto 0);
parameters(1) <= gyro_off_x_reg(15 downto 0) & accel_off_x_reg(15 downto 0);
parameters(2) <= gyro_off_y_reg(15 downto 0) & accel_off_y_reg(15 downto 0);
parameters(3) <= gyro_off_z_reg(15 downto 0) & accel_off_z_reg(15 downto 0);
accelero_data <= accelero.data;
accelero_dv <= accelero.dv;
accelero_fv <= accelero.fv;
gyroscope_data <= gyroscope.data;
gyroscope_dv <= gyroscope.dv;
gyroscope_fv <= gyroscope.fv;
compass_data <= compass.data;
compass_dv <= compass.dv;
compass_fv <= compass.fv;
mpu_slave_inst : mpu_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
enable_reg => enable_reg,
gyro_config_reg => gyro_config_reg,
accel_config_reg => accel_config_reg,
spl_rate_reg => spl_rate_reg,
gain_compass_reg => gain_compass_reg,
fz_compass_reg => fz_compass_reg,
accel_off_x_reg => accel_off_x_reg,
accel_off_y_reg => accel_off_y_reg,
accel_off_z_reg => accel_off_z_reg,
gyro_off_x_reg => gyro_off_x_reg,
gyro_off_y_reg => gyro_off_y_reg,
gyro_off_z_reg => gyro_off_z_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:22:13 12/18/2013
-- Design Name:
-- Module Name: calculo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end calculo;
architecture Behavioral of calculo is
component inversor is
port( valor: in std_logic_vector(20 downto 0);
inverso: out std_logic_vector(20 downto 0));
end component inversor;
component logaritmo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
log : out STD_LOGIC_VECTOR (20 downto 0);
xlogmx : out STD_LOGIC_VECTOR (20 downto 0));
end component logaritmo;
component trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end component trigo;
constant b: integer:=11;
constant d: integer:=10;
constant tres: std_logic_vector(20 downto 0):= "000000000000101010101"; -- Un tercio
constant pi: std_logic_vector(20 downto 0):= "000000000000101000101"; -- Inverso de pi
signal inum, sen, cos, log,xlogmx, acc, acc2, accsig, accsig2, mult1, mult2, cumsum, cumsumsig: std_logic_vector(b+d-1 downto 0);
signal rmultaux: std_logic_vector(2*(b+d)-1 downto 0);
signal rmult: std_logic_vector(b+d-1 downto 0);
signal estado, estadosig: std_logic_vector(4 downto 0);
begin
inversa: inversor port map(num, inum);
trigonometrico: trigo port map(num, sen, cos);
loga: logaritmo port map(num, log, xlogmx);
rmultaux <= mult1*mult2;
rmult <= rmultaux(b+2*d-1 downto d);
s <= cumsum;
pestado: process(estado, enable)
begin
if estado = "11111" then
if enable = '1' then
estadosig <= "00000";
else
estadosig <= "11111";
end if;
elsif estado = "01101" then
if enable = '1' then
estadosig <= "11111";
else
estadosig <= "01101";
end if;
elsif estado < "01101" then
estadosig <= estado+1;
else
estadosig <= "11111";
end if;
end process pestado;
asinc: process(estado, cumsum, rmult, acc, enable, num, c, inum, acc2, integral, sen, cos, log, xlogmx)
begin
ready <= '0';
accsig <= acc;
accsig2 <= acc2;
mult1 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
mult2 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
if integral = '0' then
if estado = "11111" then
cumsumsig(b+d-1 downto 5+d) <= (others => c(19));
cumsumsig(4+d downto d) <= c(19 downto 15);
cumsumsig(d-1 downto 0) <= (others => '0');
elsif estado = "00000" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00001" then
mult1 <= num;
mult2 <= num;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00010" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00011" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= inum;
mult2(b+d-1 downto 5+d) <= (others => c(14));
mult2(4+d downto d) <= c(14 downto 10);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00110" then
mult1 <= inum;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00111" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(9));
mult2(4+d downto d) <= c(9 downto 5);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01000" then
mult1 <= acc;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "01001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(4));
mult2(4+d downto d) <= c(4 downto 0);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01010" then
mult1 <= sen;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= cos;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
mult1 <= log;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
else
if estado = "11111" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(19));
mult2(4+d downto d) <= c(19 downto 15);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= rmult(20 downto 0);
elsif estado = "00000" then
mult1 <= num;
mult2 <= num;
if rmult(20) = '0' then
accsig <= '0' & rmult(20 downto 1);
else
accsig <= '1' & rmult(20 downto 1);
end if;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
accsig2 <= acc2;
elsif estado = "00010" then
mult1 <= num;
mult2 <= acc2;
accsig <= rmult;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00011" then
mult1 <= acc;
mult2 <= tres;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00110" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult(20 downto 2);
elsif estado = "00111" then
mult1 <= 0-cos;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01000" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01001" then
mult1 <= sen;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01010" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= xlogmx;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
cumsumsig <= cumsum;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
end if;
end process asinc;
sinc: process(reset, clk)
begin
if reset='1' then
estado <= (others => '1');
cumsum <= (others => '0');
acc <= (others => '0');
acc2 <= (others => '0');
elsif clk'event and clk='1' then
estado <= estadosig;
acc <= accsig;
acc2 <= accsig2;
cumsum <= cumsumsig;
end if;
end process sinc;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:22:13 12/18/2013
-- Design Name:
-- Module Name: calculo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end calculo;
architecture Behavioral of calculo is
component inversor is
port( valor: in std_logic_vector(20 downto 0);
inverso: out std_logic_vector(20 downto 0));
end component inversor;
component logaritmo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
log : out STD_LOGIC_VECTOR (20 downto 0);
xlogmx : out STD_LOGIC_VECTOR (20 downto 0));
end component logaritmo;
component trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end component trigo;
constant b: integer:=11;
constant d: integer:=10;
constant tres: std_logic_vector(20 downto 0):= "000000000000101010101"; -- Un tercio
constant pi: std_logic_vector(20 downto 0):= "000000000000101000101"; -- Inverso de pi
signal inum, sen, cos, log,xlogmx, acc, acc2, accsig, accsig2, mult1, mult2, cumsum, cumsumsig: std_logic_vector(b+d-1 downto 0);
signal rmultaux: std_logic_vector(2*(b+d)-1 downto 0);
signal rmult: std_logic_vector(b+d-1 downto 0);
signal estado, estadosig: std_logic_vector(4 downto 0);
begin
inversa: inversor port map(num, inum);
trigonometrico: trigo port map(num, sen, cos);
loga: logaritmo port map(num, log, xlogmx);
rmultaux <= mult1*mult2;
rmult <= rmultaux(b+2*d-1 downto d);
s <= cumsum;
pestado: process(estado, enable)
begin
if estado = "11111" then
if enable = '1' then
estadosig <= "00000";
else
estadosig <= "11111";
end if;
elsif estado = "01101" then
if enable = '1' then
estadosig <= "11111";
else
estadosig <= "01101";
end if;
elsif estado < "01101" then
estadosig <= estado+1;
else
estadosig <= "11111";
end if;
end process pestado;
asinc: process(estado, cumsum, rmult, acc, enable, num, c, inum, acc2, integral, sen, cos, log, xlogmx)
begin
ready <= '0';
accsig <= acc;
accsig2 <= acc2;
mult1 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
mult2 <= num; --para quitar latches, cuando se usen, aunque sean los mismos,se pondra de forma explicita
if integral = '0' then
if estado = "11111" then
cumsumsig(b+d-1 downto 5+d) <= (others => c(19));
cumsumsig(4+d downto d) <= c(19 downto 15);
cumsumsig(d-1 downto 0) <= (others => '0');
elsif estado = "00000" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00001" then
mult1 <= num;
mult2 <= num;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00010" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00011" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= inum;
mult2(b+d-1 downto 5+d) <= (others => c(14));
mult2(4+d downto d) <= c(14 downto 10);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00110" then
mult1 <= inum;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00111" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(9));
mult2(4+d downto d) <= c(9 downto 5);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01000" then
mult1 <= acc;
mult2 <= inum;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "01001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(4));
mult2(4+d downto d) <= c(4 downto 0);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01010" then
mult1 <= sen;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= cos;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
mult1 <= log;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
else
if estado = "11111" then
mult1 <= num;
mult2(b+d-1 downto 5+d) <= (others => c(19));
mult2(4+d downto d) <= c(19 downto 15);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= rmult(20 downto 0);
elsif estado = "00000" then
mult1 <= num;
mult2 <= num;
if rmult(20) = '0' then
accsig <= '0' & rmult(20 downto 1);
else
accsig <= '1' & rmult(20 downto 1);
end if;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00001" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(24));
mult2(4+d downto d) <= c(24 downto 20);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
accsig2 <= acc2;
elsif estado = "00010" then
mult1 <= num;
mult2 <= acc2;
accsig <= rmult;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00011" then
mult1 <= acc;
mult2 <= tres;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "00100" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(29));
mult2(4+d downto d) <= c(29 downto 25);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "00101" then
mult1 <= num;
mult2 <= acc;
accsig <= rmult;
cumsumsig <= cumsum;
elsif estado = "00110" then
mult1 <= acc;
mult2(b+d-1 downto 5+d) <= (others => c(34));
mult2(4+d downto d) <= c(34 downto 30);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult(20 downto 2);
elsif estado = "00111" then
mult1 <= 0-cos;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01000" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(44));
mult2(4+d downto d) <= c(44 downto 40);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01001" then
mult1 <= sen;
mult2 <= pi;
accsig2 <= rmult;
cumsumsig <= cumsum;
elsif estado = "01010" then
mult1 <= acc2;
mult2(b+d-1 downto 5+d) <= (others => c(39));
mult2(4+d downto d) <= c(39 downto 35);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01011" then
mult1 <= xlogmx;
mult2(b+d-1 downto 5+d) <= (others => c(49));
mult2(4+d downto d) <= c(49 downto 45);
mult2(d-1 downto 0) <= (others => '0');
cumsumsig <= cumsum + rmult;
elsif estado = "01100" then
cumsumsig <= cumsum;
else
ready <= '1';
cumsumsig <= cumsum;
end if;
end if;
end process asinc;
sinc: process(reset, clk)
begin
if reset='1' then
estado <= (others => '1');
cumsum <= (others => '0');
acc <= (others => '0');
acc2 <= (others => '0');
elsif clk'event and clk='1' then
estado <= estadosig;
acc <= accsig;
acc2 <= accsig2;
cumsum <= cumsumsig;
end if;
end process sinc;
end Behavioral;
|
-------------------------------------------------------------------------------
-- dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_bram_if_cntlr_v3_00_b.all;
entity dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_00_b";
end dlmb_cntlr_wrapper;
architecture STRUCTURE of dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
--
-- Design : inst_cache_dpram (Dual Port RAM holding cache data)
-- In summer 2008, it was inst_cache_sprom (Single Port ROM holding the cache data)
-- Project : ee560 Tomosulo -- Instruction Cache Emulator
-- Author : Srinivas Vaduvatha , Gandhi Puvvada
-- Company : University of Southern California
-- Date last revised : 7/23/2008, 7/15/2009
-------------------------------------------------------------------------------
--
-- File : inst_cache_dpram_r2.vhd (produced by modifying Summer 2008 inst_cache_sprom_r1.vhd and data_mem_dp.vhd)
--
-------------------------------------------------------------------------------
--
-- Description : This BRAM is instantiated by the instr_cache module.
-- This holds the instructions.
-- In Summer 2008, it was a ROM (BRAM acting like a ROM) with inital
-- content (instruction stream) defined through a package called
-- instr_stream_pkg.
-- In Summer 2009, it is converted to a dual port RAM. The first port (Port a) is of read/write type
-- and it faciliatates downloading a file containing cache contents from a text file holding instructions
-- in hex notation, 4 instruction per line, with Instruction0 on the right-end of the line:
-- Instruction3_ Instruction2_Instruction1_Instruction0
-- Module features:
-- Data width & Address width - Generics
-- Port b: synchronous Read only (for the processor cache read operation)
-- Port a: synchronous Read/Write (for File I/O through Adept 2.0)
-- Infers BRAM resource in Xilinx FPGAs.
-- If the width / depth specified require more bits than in a single
-- BRAM, multiple BRAMs are automatically cascaded to form a larger
-- memory by the Xilinx XST. Memory has to be of (2**n) depth.
--
-------------------------------------------------------------------------------
-- libraries and use clauses
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
use work.instr_stream_pkg.all; -- instruction stream defining package
entity inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end inst_cache_dpram ;
architecture inferable of inst_cache_dpram is
-- signals declarations.
-- Note: A signal called "mem" of user defined type "mem_type" was declared
-- in a package called "instr_stream_pkg" refered in the use clause above.
-- It has lines similar to the following lines.
-- The initial content defines the stream of instructions.
-- -- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH)-1) of std_logic_vector((DATA_WIDTH-1) downto 0);
--*****************************************************************************************
-- This stream is used to generate the walking led pattern using memory mapped i/0
--*****************************************************************************************
signal mem : mem_type
:= (
X"00000020_AC0200FC_00421020_00000020", -- Loc 0C --nop, 08-- sw $2, 252($0) --[ 252 byte address = 64 word address], 04-- add $2, $2, $2 , 00- nop
X"00000020_00000020_00000020_08000000", -- Loc 1C, 18, 14, 10 --jump Loc 00 --rest all are NOP's
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
begin
porta_oper : process (clka)
begin
if (clka = '1' and clka'event) then
if (wea = '1' and ena='1') then
mem(CONV_INTEGER(unsigned(addr_a))) <= data_in_a;
end if;
if( ena='1')then
data_out_a <= mem(CONV_INTEGER(unsigned(addr_a)));
end if;
end if;
end process;
portb_oper : process (clkb)
begin
if (clkb = '1' and clkb'event) then
-- if (web = '1') then
-- mem(CONV_INTEGER(addr_b)) := data_in_b;
-- end if;
data_out_b <= mem(CONV_INTEGER(unsigned(addr_b)));
end if;
end process;
end inferable ;
--- ===========================================================
|
--
-- Copyright 2016 Ognjen Glamocanin
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4_to_1 is
port(
x1: in std_logic_vector (31 downto 0);
x2: in std_logic_vector (31 downto 0);
x3: in std_logic_vector (31 downto 0);
x4: in std_logic_vector (31 downto 0);
sel: in std_logic_vector (1 downto 0);
y: out std_logic_vector (31 downto 0)
);
end entity mux_4_to_1;
architecture behavioral of mux_4_to_1 is
begin
mux: process (x1, x2, x3, x4, sel) is
begin
case sel is
when "00" => y <= x1;
when "01" => y <= x2;
when "10" => y <= x3;
when others => y <= x4;
end case;
end process;
end architecture behavioral; |
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: WaveAddrMux.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY WaveAddrMux IS
PORT
(
clock : IN STD_LOGIC ;
data0x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data15x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END WaveAddrMux;
ARCHITECTURE SYN OF waveaddrmux IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_2D (15 DOWNTO 0, 11 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire14 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire15 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire16 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire17 : STD_LOGIC_VECTOR (11 DOWNTO 0);
BEGIN
sub_wire16 <= data0x(11 DOWNTO 0);
sub_wire15 <= data1x(11 DOWNTO 0);
sub_wire14 <= data2x(11 DOWNTO 0);
sub_wire13 <= data3x(11 DOWNTO 0);
sub_wire12 <= data4x(11 DOWNTO 0);
sub_wire11 <= data5x(11 DOWNTO 0);
sub_wire10 <= data6x(11 DOWNTO 0);
sub_wire9 <= data7x(11 DOWNTO 0);
sub_wire8 <= data8x(11 DOWNTO 0);
sub_wire7 <= data9x(11 DOWNTO 0);
sub_wire6 <= data10x(11 DOWNTO 0);
sub_wire5 <= data11x(11 DOWNTO 0);
sub_wire4 <= data12x(11 DOWNTO 0);
sub_wire3 <= data13x(11 DOWNTO 0);
sub_wire2 <= data14x(11 DOWNTO 0);
sub_wire0 <= data15x(11 DOWNTO 0);
sub_wire1(15, 0) <= sub_wire0(0);
sub_wire1(15, 1) <= sub_wire0(1);
sub_wire1(15, 2) <= sub_wire0(2);
sub_wire1(15, 3) <= sub_wire0(3);
sub_wire1(15, 4) <= sub_wire0(4);
sub_wire1(15, 5) <= sub_wire0(5);
sub_wire1(15, 6) <= sub_wire0(6);
sub_wire1(15, 7) <= sub_wire0(7);
sub_wire1(15, 8) <= sub_wire0(8);
sub_wire1(15, 9) <= sub_wire0(9);
sub_wire1(15, 10) <= sub_wire0(10);
sub_wire1(15, 11) <= sub_wire0(11);
sub_wire1(14, 0) <= sub_wire2(0);
sub_wire1(14, 1) <= sub_wire2(1);
sub_wire1(14, 2) <= sub_wire2(2);
sub_wire1(14, 3) <= sub_wire2(3);
sub_wire1(14, 4) <= sub_wire2(4);
sub_wire1(14, 5) <= sub_wire2(5);
sub_wire1(14, 6) <= sub_wire2(6);
sub_wire1(14, 7) <= sub_wire2(7);
sub_wire1(14, 8) <= sub_wire2(8);
sub_wire1(14, 9) <= sub_wire2(9);
sub_wire1(14, 10) <= sub_wire2(10);
sub_wire1(14, 11) <= sub_wire2(11);
sub_wire1(13, 0) <= sub_wire3(0);
sub_wire1(13, 1) <= sub_wire3(1);
sub_wire1(13, 2) <= sub_wire3(2);
sub_wire1(13, 3) <= sub_wire3(3);
sub_wire1(13, 4) <= sub_wire3(4);
sub_wire1(13, 5) <= sub_wire3(5);
sub_wire1(13, 6) <= sub_wire3(6);
sub_wire1(13, 7) <= sub_wire3(7);
sub_wire1(13, 8) <= sub_wire3(8);
sub_wire1(13, 9) <= sub_wire3(9);
sub_wire1(13, 10) <= sub_wire3(10);
sub_wire1(13, 11) <= sub_wire3(11);
sub_wire1(12, 0) <= sub_wire4(0);
sub_wire1(12, 1) <= sub_wire4(1);
sub_wire1(12, 2) <= sub_wire4(2);
sub_wire1(12, 3) <= sub_wire4(3);
sub_wire1(12, 4) <= sub_wire4(4);
sub_wire1(12, 5) <= sub_wire4(5);
sub_wire1(12, 6) <= sub_wire4(6);
sub_wire1(12, 7) <= sub_wire4(7);
sub_wire1(12, 8) <= sub_wire4(8);
sub_wire1(12, 9) <= sub_wire4(9);
sub_wire1(12, 10) <= sub_wire4(10);
sub_wire1(12, 11) <= sub_wire4(11);
sub_wire1(11, 0) <= sub_wire5(0);
sub_wire1(11, 1) <= sub_wire5(1);
sub_wire1(11, 2) <= sub_wire5(2);
sub_wire1(11, 3) <= sub_wire5(3);
sub_wire1(11, 4) <= sub_wire5(4);
sub_wire1(11, 5) <= sub_wire5(5);
sub_wire1(11, 6) <= sub_wire5(6);
sub_wire1(11, 7) <= sub_wire5(7);
sub_wire1(11, 8) <= sub_wire5(8);
sub_wire1(11, 9) <= sub_wire5(9);
sub_wire1(11, 10) <= sub_wire5(10);
sub_wire1(11, 11) <= sub_wire5(11);
sub_wire1(10, 0) <= sub_wire6(0);
sub_wire1(10, 1) <= sub_wire6(1);
sub_wire1(10, 2) <= sub_wire6(2);
sub_wire1(10, 3) <= sub_wire6(3);
sub_wire1(10, 4) <= sub_wire6(4);
sub_wire1(10, 5) <= sub_wire6(5);
sub_wire1(10, 6) <= sub_wire6(6);
sub_wire1(10, 7) <= sub_wire6(7);
sub_wire1(10, 8) <= sub_wire6(8);
sub_wire1(10, 9) <= sub_wire6(9);
sub_wire1(10, 10) <= sub_wire6(10);
sub_wire1(10, 11) <= sub_wire6(11);
sub_wire1(9, 0) <= sub_wire7(0);
sub_wire1(9, 1) <= sub_wire7(1);
sub_wire1(9, 2) <= sub_wire7(2);
sub_wire1(9, 3) <= sub_wire7(3);
sub_wire1(9, 4) <= sub_wire7(4);
sub_wire1(9, 5) <= sub_wire7(5);
sub_wire1(9, 6) <= sub_wire7(6);
sub_wire1(9, 7) <= sub_wire7(7);
sub_wire1(9, 8) <= sub_wire7(8);
sub_wire1(9, 9) <= sub_wire7(9);
sub_wire1(9, 10) <= sub_wire7(10);
sub_wire1(9, 11) <= sub_wire7(11);
sub_wire1(8, 0) <= sub_wire8(0);
sub_wire1(8, 1) <= sub_wire8(1);
sub_wire1(8, 2) <= sub_wire8(2);
sub_wire1(8, 3) <= sub_wire8(3);
sub_wire1(8, 4) <= sub_wire8(4);
sub_wire1(8, 5) <= sub_wire8(5);
sub_wire1(8, 6) <= sub_wire8(6);
sub_wire1(8, 7) <= sub_wire8(7);
sub_wire1(8, 8) <= sub_wire8(8);
sub_wire1(8, 9) <= sub_wire8(9);
sub_wire1(8, 10) <= sub_wire8(10);
sub_wire1(8, 11) <= sub_wire8(11);
sub_wire1(7, 0) <= sub_wire9(0);
sub_wire1(7, 1) <= sub_wire9(1);
sub_wire1(7, 2) <= sub_wire9(2);
sub_wire1(7, 3) <= sub_wire9(3);
sub_wire1(7, 4) <= sub_wire9(4);
sub_wire1(7, 5) <= sub_wire9(5);
sub_wire1(7, 6) <= sub_wire9(6);
sub_wire1(7, 7) <= sub_wire9(7);
sub_wire1(7, 8) <= sub_wire9(8);
sub_wire1(7, 9) <= sub_wire9(9);
sub_wire1(7, 10) <= sub_wire9(10);
sub_wire1(7, 11) <= sub_wire9(11);
sub_wire1(6, 0) <= sub_wire10(0);
sub_wire1(6, 1) <= sub_wire10(1);
sub_wire1(6, 2) <= sub_wire10(2);
sub_wire1(6, 3) <= sub_wire10(3);
sub_wire1(6, 4) <= sub_wire10(4);
sub_wire1(6, 5) <= sub_wire10(5);
sub_wire1(6, 6) <= sub_wire10(6);
sub_wire1(6, 7) <= sub_wire10(7);
sub_wire1(6, 8) <= sub_wire10(8);
sub_wire1(6, 9) <= sub_wire10(9);
sub_wire1(6, 10) <= sub_wire10(10);
sub_wire1(6, 11) <= sub_wire10(11);
sub_wire1(5, 0) <= sub_wire11(0);
sub_wire1(5, 1) <= sub_wire11(1);
sub_wire1(5, 2) <= sub_wire11(2);
sub_wire1(5, 3) <= sub_wire11(3);
sub_wire1(5, 4) <= sub_wire11(4);
sub_wire1(5, 5) <= sub_wire11(5);
sub_wire1(5, 6) <= sub_wire11(6);
sub_wire1(5, 7) <= sub_wire11(7);
sub_wire1(5, 8) <= sub_wire11(8);
sub_wire1(5, 9) <= sub_wire11(9);
sub_wire1(5, 10) <= sub_wire11(10);
sub_wire1(5, 11) <= sub_wire11(11);
sub_wire1(4, 0) <= sub_wire12(0);
sub_wire1(4, 1) <= sub_wire12(1);
sub_wire1(4, 2) <= sub_wire12(2);
sub_wire1(4, 3) <= sub_wire12(3);
sub_wire1(4, 4) <= sub_wire12(4);
sub_wire1(4, 5) <= sub_wire12(5);
sub_wire1(4, 6) <= sub_wire12(6);
sub_wire1(4, 7) <= sub_wire12(7);
sub_wire1(4, 8) <= sub_wire12(8);
sub_wire1(4, 9) <= sub_wire12(9);
sub_wire1(4, 10) <= sub_wire12(10);
sub_wire1(4, 11) <= sub_wire12(11);
sub_wire1(3, 0) <= sub_wire13(0);
sub_wire1(3, 1) <= sub_wire13(1);
sub_wire1(3, 2) <= sub_wire13(2);
sub_wire1(3, 3) <= sub_wire13(3);
sub_wire1(3, 4) <= sub_wire13(4);
sub_wire1(3, 5) <= sub_wire13(5);
sub_wire1(3, 6) <= sub_wire13(6);
sub_wire1(3, 7) <= sub_wire13(7);
sub_wire1(3, 8) <= sub_wire13(8);
sub_wire1(3, 9) <= sub_wire13(9);
sub_wire1(3, 10) <= sub_wire13(10);
sub_wire1(3, 11) <= sub_wire13(11);
sub_wire1(2, 0) <= sub_wire14(0);
sub_wire1(2, 1) <= sub_wire14(1);
sub_wire1(2, 2) <= sub_wire14(2);
sub_wire1(2, 3) <= sub_wire14(3);
sub_wire1(2, 4) <= sub_wire14(4);
sub_wire1(2, 5) <= sub_wire14(5);
sub_wire1(2, 6) <= sub_wire14(6);
sub_wire1(2, 7) <= sub_wire14(7);
sub_wire1(2, 8) <= sub_wire14(8);
sub_wire1(2, 9) <= sub_wire14(9);
sub_wire1(2, 10) <= sub_wire14(10);
sub_wire1(2, 11) <= sub_wire14(11);
sub_wire1(1, 0) <= sub_wire15(0);
sub_wire1(1, 1) <= sub_wire15(1);
sub_wire1(1, 2) <= sub_wire15(2);
sub_wire1(1, 3) <= sub_wire15(3);
sub_wire1(1, 4) <= sub_wire15(4);
sub_wire1(1, 5) <= sub_wire15(5);
sub_wire1(1, 6) <= sub_wire15(6);
sub_wire1(1, 7) <= sub_wire15(7);
sub_wire1(1, 8) <= sub_wire15(8);
sub_wire1(1, 9) <= sub_wire15(9);
sub_wire1(1, 10) <= sub_wire15(10);
sub_wire1(1, 11) <= sub_wire15(11);
sub_wire1(0, 0) <= sub_wire16(0);
sub_wire1(0, 1) <= sub_wire16(1);
sub_wire1(0, 2) <= sub_wire16(2);
sub_wire1(0, 3) <= sub_wire16(3);
sub_wire1(0, 4) <= sub_wire16(4);
sub_wire1(0, 5) <= sub_wire16(5);
sub_wire1(0, 6) <= sub_wire16(6);
sub_wire1(0, 7) <= sub_wire16(7);
sub_wire1(0, 8) <= sub_wire16(8);
sub_wire1(0, 9) <= sub_wire16(9);
sub_wire1(0, 10) <= sub_wire16(10);
sub_wire1(0, 11) <= sub_wire16(11);
result <= sub_wire17(11 DOWNTO 0);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 2,
lpm_size => 16,
lpm_type => "LPM_MUX",
lpm_width => 12,
lpm_widths => 4
)
PORT MAP (
clock => clock,
data => sub_wire1,
sel => sel,
result => sub_wire17
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
-- Retrieval info: USED_PORT: data10x 0 0 12 0 INPUT NODEFVAL "data10x[11..0]"
-- Retrieval info: USED_PORT: data11x 0 0 12 0 INPUT NODEFVAL "data11x[11..0]"
-- Retrieval info: USED_PORT: data12x 0 0 12 0 INPUT NODEFVAL "data12x[11..0]"
-- Retrieval info: USED_PORT: data13x 0 0 12 0 INPUT NODEFVAL "data13x[11..0]"
-- Retrieval info: USED_PORT: data14x 0 0 12 0 INPUT NODEFVAL "data14x[11..0]"
-- Retrieval info: USED_PORT: data15x 0 0 12 0 INPUT NODEFVAL "data15x[11..0]"
-- Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
-- Retrieval info: USED_PORT: data2x 0 0 12 0 INPUT NODEFVAL "data2x[11..0]"
-- Retrieval info: USED_PORT: data3x 0 0 12 0 INPUT NODEFVAL "data3x[11..0]"
-- Retrieval info: USED_PORT: data4x 0 0 12 0 INPUT NODEFVAL "data4x[11..0]"
-- Retrieval info: USED_PORT: data5x 0 0 12 0 INPUT NODEFVAL "data5x[11..0]"
-- Retrieval info: USED_PORT: data6x 0 0 12 0 INPUT NODEFVAL "data6x[11..0]"
-- Retrieval info: USED_PORT: data7x 0 0 12 0 INPUT NODEFVAL "data7x[11..0]"
-- Retrieval info: USED_PORT: data8x 0 0 12 0 INPUT NODEFVAL "data8x[11..0]"
-- Retrieval info: USED_PORT: data9x 0 0 12 0 INPUT NODEFVAL "data9x[11..0]"
-- Retrieval info: USED_PORT: result 0 0 12 0 OUTPUT NODEFVAL "result[11..0]"
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 12 0 data0x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 10 12 0 data10x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 11 12 0 data11x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 12 12 0 data12x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 13 12 0 data13x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 14 12 0 data14x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 15 12 0 data15x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 1 12 0 data1x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 2 12 0 data2x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 3 12 0 data3x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 4 12 0 data4x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 5 12 0 data5x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 6 12 0 data6x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 7 12 0 data7x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 8 12 0 data8x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 9 12 0 data9x 0 0 12 0
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 12 0 @result 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
-- Title : 5-stage RISCV integer pipeline
-- Project : Freezing Spice
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : Tim Wawrzynczak
-- Created : 2015-07-07
-- Last update: 2015-07-28
-- Platform : FPGA
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: RV32I 5-stage ("classic MIPS") pipeline:
-- Instruction Fetch
-- Instruction Decode
-- Instruction Execute
-- Memory Access
-- Register File Writeback
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.if_pkg.all;
use work.id_pkg.all;
use work.ex_pkg.all;
entity pipeline is
generic (g_initial_pc : unsigned(31 downto 0) := (others => '0');
g_for_sim : boolean := false);
port (clk : in std_logic;
rst_n : in std_logic;
-- Instruction interface
insn_in : in word;
insn_valid : in std_logic;
insn_addr : out word;
-- Data interface
data_in : in word;
data_out : out word;
data_addr : out word;
data_write_en : out std_logic;
data_read_en : out std_logic;
data_in_valid : in std_logic);
end entity pipeline;
architecture Behavioral of pipeline is
-------------------------------------------------
-- IF signals
-------------------------------------------------
signal if_d : if_in;
signal if_q : if_out;
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
signal if_id_ir : word := (others => '0');
signal if_id_pc : word := (others => '0');
-------------------------------------------------
-- ID signals
-------------------------------------------------
signal id_d : id_in;
signal id_q : id_out;
signal rs1_data : word;
signal rs2_data : word;
-------------------------------------------------
-- ID/EX pipeline registers
-------------------------------------------------
signal id_ex_pc : word := (others => '0');
signal id_ex_rs1_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_rs2_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_op1 : word := (others => '0');
signal id_ex_op2 : word := (others => '0');
signal id_ex_ir : word := NOP;
signal id_ex_imm : word := (others => '0');
signal id_ex_insn_type : insn_type_t := OP_ILLEGAL;
signal id_ex_use_imm : std_logic := '0';
signal id_ex_alu_func : alu_func_t := ALU_NONE;
signal id_ex_branch_type : branch_type_t := BRANCH_NONE;
signal id_ex_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_load_type : load_type_t := LOAD_NONE;
signal id_ex_store_type : store_type_t := STORE_NONE;
signal id_ex_rf_we : std_logic := '0';
-------------------------------------------------
-- EX signals
-------------------------------------------------
signal ex_d : ex_in;
signal ex_q : ex_out;
signal ex_rf_data : word;
signal ex_load_pc : std_logic;
signal ex_data_addr : word;
-------------------------------------------------
-- EX/MEM pipeline registers
-------------------------------------------------
signal ex_mem_load_pc : std_logic := '0';
signal ex_mem_next_pc : word := (others => '0');
signal ex_mem_rf_data : word := (others => '0');
signal ex_mem_return_addr : word := (others => '0');
signal ex_mem_load_type : load_type_t := LOAD_NONE;
signal ex_mem_store_type : store_type_t := STORE_NONE;
signal ex_mem_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_insn_type : insn_type_t := OP_ILLEGAL;
signal ex_mem_rf_we : std_logic := '0';
signal ex_mem_data_addr : word := (others => '0');
signal ex_mem_data_out : word := (others => '0');
-------------------------------------------------
-- MEM signals
-------------------------------------------------
signal mem_we : std_logic;
signal mem_re : std_logic;
signal mem_data_addr : word;
signal mem_data_out : word;
signal mem_lmd_lh : word;
signal mem_lmd_lb : word;
signal mem_lmd : word;
-------------------------------------------------
-- MEM/WB pipeline registers
-------------------------------------------------
signal mem_wb_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal mem_wb_rf_we : std_logic := '0';
signal mem_wb_rf_data : word := (others => '0');
signal mem_wb_insn_type : insn_type_t := OP_ILLEGAL;
signal mem_wb_lmd : word := (others => '0');
-------------------------------------------------
-- WB signals
-------------------------------------------------
signal wb_rf_wr_addr : std_logic_vector(4 downto 0);
signal wb_rf_wr_en : std_logic;
signal wb_rf_wr_data : word;
-------------------------------------------------
-- Stalling
-------------------------------------------------
signal branch_stall : std_logic;
signal hazard_stall : std_logic;
signal if_kill : std_logic;
signal id_kill : std_logic;
signal id_stall : std_logic;
signal full_stall : std_logic;
begin -- architecture Behavioral
-------------------------------------------------
-- Drive module outputs
-------------------------------------------------
-- instruction interface
insn_addr <= if_q.fetch_addr;
-- memory interface
data_read_en <= mem_re;
data_write_en <= mem_we;
data_addr <= mem_data_addr;
data_out <= mem_data_out;
-------------------------------------------------
-- Detect when stalling is necessary
-------------------------------------------------
branch_stall <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
id_stall <= hazard_stall or branch_stall;
if_kill <= ex_mem_load_pc or (not insn_valid);
id_kill <= ex_mem_load_pc;
full_stall <= '1' when (ex_mem_insn_type = OP_LOAD and data_in_valid = '0') else '0';
-- Determine when to stall the pipeline because of structural hazards
hazard_stall <= '1' when (((id_ex_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((id_ex_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs1) and (id_ex_rd_addr /= "00000") and (id_q.rs1_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs2) and (id_ex_rd_addr /= "00000") and (id_q.rs2_rd = '1')))
else '0';
---------------------------------------------------
-- Instruction fetch
---------------------------------------------------
-- inputs
if_d.stall <= ex_mem_load_pc or hazard_stall or branch_stall;
if_d.load_pc <= ex_mem_load_pc;
if_d.next_pc <= ex_mem_next_pc;
-- instantiation
if_stage : entity work.instruction_fetch(Behavioral)
port map (clk, rst_n, if_d, if_q);
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
if_id_reg_proc : process (clk, rst_n) is
begin -- process if_id_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
if_id_ir <= NOP;
if_id_pc <= (others => '0');
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
if (if_kill = '1') then
if_id_ir <= NOP;
else
if_id_ir <= insn_in;
end if;
if_id_pc <= if_q.pc;
end if;
end if;
end process if_id_reg_proc;
---------------------------------------------------
-- Instruction decode
---------------------------------------------------
-- register file
register_file : entity work.regfile(rtl)
port map (clk => clk,
addra => id_q.rs1,
addrb => id_q.rs2,
rega => rs1_data,
regb => rs2_data,
addrw => wb_rf_wr_addr,
dataw => wb_rf_wr_data,
we => wb_rf_wr_en);
-- inputs
id_d.instruction <= if_id_ir;
-- instantiation
id_stage : entity work.instruction_decoder(Behavioral)
port map (id_d, id_q);
---------------------------------------------------
-- ID/EX pipeline registers
---------------------------------------------------
-- this is where instructions get issued,
-- controlled by id_stall, full_stall, and id_kill
id_ex_reg_proc : process (clk, rst_n) is
begin -- process id_ex_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
id_ex_pc <= (others => '0');
id_ex_rs1_addr <= (others => '0');
id_ex_rs2_addr <= (others => '0');
id_ex_op1 <= (others => '0');
id_ex_op2 <= (others => '0');
id_ex_ir <= NOP;
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
id_ex_rs1_addr <= id_q.rs1;
id_ex_rs2_addr <= id_q.rs2;
id_ex_op1 <= rs1_data;
id_ex_op2 <= rs2_data;
id_ex_use_imm <= id_q.use_imm;
if (id_kill = '1') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
else
-- instruction issue
id_ex_pc <= if_id_pc;
id_ex_ir <= if_id_ir;
id_ex_rd_addr <= id_q.rd;
id_ex_insn_type <= id_q.insn_type;
id_ex_rf_we <= id_q.rf_we;
id_ex_use_imm <= id_q.use_imm;
id_ex_imm <= id_q.imm;
id_ex_alu_func <= id_q.alu_func;
id_ex_branch_type <= id_q.branch_type;
id_ex_load_type <= id_q.load_type;
id_ex_store_type <= id_q.store_type;
end if;
elsif (id_stall = '1' and full_stall = '0') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
end if;
end if;
end process id_ex_reg_proc;
---------------------------------------------------
-- print instructions as they are issued
---------------------------------------------------
print_decode : if (g_for_sim = true) generate
print_decode_proc : process (id_ex_ir, id_ex_pc) is
variable l : line;
begin -- process print_decode_proc
write(l, to_integer(unsigned(id_ex_pc)));
write(l, string'(" : "));
write(l, hstr(id_ex_ir));
writeline(output, l);
end process print_decode_proc;
end generate print_decode;
---------------------------------------------------
-- Instruction execution stage
---------------------------------------------------
-- inputs
ex_d.insn_type <= id_ex_insn_type;
ex_d.npc <= id_ex_pc;
ex_d.rs1 <= id_ex_op1;
ex_d.rs2 <= id_ex_op2;
ex_d.use_imm <= id_ex_use_imm;
ex_d.alu_func <= id_ex_alu_func;
ex_d.branch_type <= id_ex_branch_type;
ex_d.imm <= id_ex_imm;
-- instantiation
ex_stage : entity work.instruction_executor(Behavioral)
port map (ex_d, ex_q);
-- multiplexer for Register File write data
ex_rf_data <= ex_q.return_addr when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR) else
id_ex_imm when (id_ex_insn_type = OP_LUI) else
ex_q.alu_result;
-- selecter for loading the PC with a new value
ex_load_pc <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
-- multiplexer for data memory address
ex_data_addr <= ex_q.alu_result when (id_ex_insn_type = OP_LOAD or id_ex_insn_type = OP_STORE) else ex_mem_data_addr;
---------------------------------------------------
-- EX/MEM pipeline registers
---------------------------------------------------
-- purpose: Pipeline data between EX and MEM stages
ex_mem_regs_proc : process (clk, rst_n) is
begin -- process ex_mem_regs_proc
if (rst_n = '0') then -- asynchronous reset (active low)
ex_mem_load_pc <= '0';
ex_mem_next_pc <= (others => '0');
ex_mem_rf_data <= (others => '0');
ex_mem_return_addr <= (others => '0');
ex_mem_load_type <= LOAD_NONE;
ex_mem_store_type <= STORE_NONE;
ex_mem_rd_addr <= (others => '0');
ex_mem_insn_type <= OP_ILLEGAL;
ex_mem_rf_we <= '0';
elsif (rising_edge(clk)) then
if (full_stall = '0') then
ex_mem_next_pc <= ex_q.alu_result;
ex_mem_load_pc <= ex_load_pc;
ex_mem_rf_data <= ex_rf_data;
ex_mem_data_addr <= ex_data_addr;
ex_mem_data_out <= id_ex_op2;
ex_mem_load_type <= id_ex_load_type;
ex_mem_store_type <= id_ex_store_type;
ex_mem_rd_addr <= id_ex_rd_addr;
ex_mem_insn_type <= id_ex_insn_type;
ex_mem_rf_we <= id_ex_rf_we;
end if;
end if;
end process ex_mem_regs_proc;
---------------------------------------------------
-- Memory stage
---------------------------------------------------
-- memory access logic
mem_we <= '1' when ex_mem_insn_type = OP_STORE else '0';
mem_re <= '1' when ex_mem_insn_type = OP_LOAD else '0';
-- data memory interface multiplexers
mem_data_addr <= ex_mem_data_addr;
mem_data_out <= X"0000" & ex_mem_data_out(15 downto 0) when ex_mem_store_type = SH else
X"000000" & ex_mem_data_out(7 downto 0) when ex_mem_store_type = SB else
ex_mem_data_out;
-- if the load is a signed halfword
mem_lmd_lh <= data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) &
data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15 downto 0);
-- if the load is a signed byte
mem_lmd_lb <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7 downto 0);
-- Load Memory Data register input
with ex_mem_load_type select
mem_lmd <=
X"0000" & data_in(15 downto 0) when LHU,
X"000000" & data_in(7 downto 0) when LBU,
mem_lmd_lh when LH,
mem_lmd_lb when LB,
data_in when others;
---------------------------------------------------
-- MEM/WB pipeline registers
---------------------------------------------------
-- purpose: Create the MEM/WB pipeline registers
mem_wb_regs : process (clk, rst_n) is
begin -- process mem_wb_regs
if (rst_n = '0') then -- asynchronous reset (active low)
mem_wb_rd_addr <= (others => '0');
mem_wb_rf_we <= '0';
mem_wb_rf_data <= (others => '0');
mem_wb_insn_type <= OP_ILLEGAL;
elsif (rising_edge(clk)) then
if (full_stall = '0') then
mem_wb_rd_addr <= ex_mem_rd_addr;
mem_wb_rf_we <= ex_mem_rf_we;
mem_wb_insn_type <= ex_mem_insn_type;
mem_wb_rf_data <= ex_mem_rf_data;
if (data_in_valid = '1') then
mem_wb_lmd <= mem_lmd;
end if;
else
mem_wb_rf_we <= '0';
end if;
end if;
end process mem_wb_regs;
---------------------------------------------------
-- Writeback stage
---------------------------------------------------
wb_rf_wr_addr <= mem_wb_rd_addr;
wb_rf_wr_en <= mem_wb_rf_we;
wb_rf_wr_data <= mem_wb_lmd when (mem_wb_insn_type = OP_LOAD) else mem_wb_rf_data;
end architecture Behavioral;
|
-------------------------------------------------------------------------------
-- Title : 5-stage RISCV integer pipeline
-- Project : Freezing Spice
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : Tim Wawrzynczak
-- Created : 2015-07-07
-- Last update: 2015-07-28
-- Platform : FPGA
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: RV32I 5-stage ("classic MIPS") pipeline:
-- Instruction Fetch
-- Instruction Decode
-- Instruction Execute
-- Memory Access
-- Register File Writeback
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.if_pkg.all;
use work.id_pkg.all;
use work.ex_pkg.all;
entity pipeline is
generic (g_initial_pc : unsigned(31 downto 0) := (others => '0');
g_for_sim : boolean := false);
port (clk : in std_logic;
rst_n : in std_logic;
-- Instruction interface
insn_in : in word;
insn_valid : in std_logic;
insn_addr : out word;
-- Data interface
data_in : in word;
data_out : out word;
data_addr : out word;
data_write_en : out std_logic;
data_read_en : out std_logic;
data_in_valid : in std_logic);
end entity pipeline;
architecture Behavioral of pipeline is
-------------------------------------------------
-- IF signals
-------------------------------------------------
signal if_d : if_in;
signal if_q : if_out;
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
signal if_id_ir : word := (others => '0');
signal if_id_pc : word := (others => '0');
-------------------------------------------------
-- ID signals
-------------------------------------------------
signal id_d : id_in;
signal id_q : id_out;
signal rs1_data : word;
signal rs2_data : word;
-------------------------------------------------
-- ID/EX pipeline registers
-------------------------------------------------
signal id_ex_pc : word := (others => '0');
signal id_ex_rs1_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_rs2_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_op1 : word := (others => '0');
signal id_ex_op2 : word := (others => '0');
signal id_ex_ir : word := NOP;
signal id_ex_imm : word := (others => '0');
signal id_ex_insn_type : insn_type_t := OP_ILLEGAL;
signal id_ex_use_imm : std_logic := '0';
signal id_ex_alu_func : alu_func_t := ALU_NONE;
signal id_ex_branch_type : branch_type_t := BRANCH_NONE;
signal id_ex_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_load_type : load_type_t := LOAD_NONE;
signal id_ex_store_type : store_type_t := STORE_NONE;
signal id_ex_rf_we : std_logic := '0';
-------------------------------------------------
-- EX signals
-------------------------------------------------
signal ex_d : ex_in;
signal ex_q : ex_out;
signal ex_rf_data : word;
signal ex_load_pc : std_logic;
signal ex_data_addr : word;
-------------------------------------------------
-- EX/MEM pipeline registers
-------------------------------------------------
signal ex_mem_load_pc : std_logic := '0';
signal ex_mem_next_pc : word := (others => '0');
signal ex_mem_rf_data : word := (others => '0');
signal ex_mem_return_addr : word := (others => '0');
signal ex_mem_load_type : load_type_t := LOAD_NONE;
signal ex_mem_store_type : store_type_t := STORE_NONE;
signal ex_mem_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_insn_type : insn_type_t := OP_ILLEGAL;
signal ex_mem_rf_we : std_logic := '0';
signal ex_mem_data_addr : word := (others => '0');
signal ex_mem_data_out : word := (others => '0');
-------------------------------------------------
-- MEM signals
-------------------------------------------------
signal mem_we : std_logic;
signal mem_re : std_logic;
signal mem_data_addr : word;
signal mem_data_out : word;
signal mem_lmd_lh : word;
signal mem_lmd_lb : word;
signal mem_lmd : word;
-------------------------------------------------
-- MEM/WB pipeline registers
-------------------------------------------------
signal mem_wb_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal mem_wb_rf_we : std_logic := '0';
signal mem_wb_rf_data : word := (others => '0');
signal mem_wb_insn_type : insn_type_t := OP_ILLEGAL;
signal mem_wb_lmd : word := (others => '0');
-------------------------------------------------
-- WB signals
-------------------------------------------------
signal wb_rf_wr_addr : std_logic_vector(4 downto 0);
signal wb_rf_wr_en : std_logic;
signal wb_rf_wr_data : word;
-------------------------------------------------
-- Stalling
-------------------------------------------------
signal branch_stall : std_logic;
signal hazard_stall : std_logic;
signal if_kill : std_logic;
signal id_kill : std_logic;
signal id_stall : std_logic;
signal full_stall : std_logic;
begin -- architecture Behavioral
-------------------------------------------------
-- Drive module outputs
-------------------------------------------------
-- instruction interface
insn_addr <= if_q.fetch_addr;
-- memory interface
data_read_en <= mem_re;
data_write_en <= mem_we;
data_addr <= mem_data_addr;
data_out <= mem_data_out;
-------------------------------------------------
-- Detect when stalling is necessary
-------------------------------------------------
branch_stall <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
id_stall <= hazard_stall or branch_stall;
if_kill <= ex_mem_load_pc or (not insn_valid);
id_kill <= ex_mem_load_pc;
full_stall <= '1' when (ex_mem_insn_type = OP_LOAD and data_in_valid = '0') else '0';
-- Determine when to stall the pipeline because of structural hazards
hazard_stall <= '1' when (((id_ex_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((id_ex_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs1) and (id_ex_rd_addr /= "00000") and (id_q.rs1_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs2) and (id_ex_rd_addr /= "00000") and (id_q.rs2_rd = '1')))
else '0';
---------------------------------------------------
-- Instruction fetch
---------------------------------------------------
-- inputs
if_d.stall <= ex_mem_load_pc or hazard_stall or branch_stall;
if_d.load_pc <= ex_mem_load_pc;
if_d.next_pc <= ex_mem_next_pc;
-- instantiation
if_stage : entity work.instruction_fetch(Behavioral)
port map (clk, rst_n, if_d, if_q);
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
if_id_reg_proc : process (clk, rst_n) is
begin -- process if_id_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
if_id_ir <= NOP;
if_id_pc <= (others => '0');
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
if (if_kill = '1') then
if_id_ir <= NOP;
else
if_id_ir <= insn_in;
end if;
if_id_pc <= if_q.pc;
end if;
end if;
end process if_id_reg_proc;
---------------------------------------------------
-- Instruction decode
---------------------------------------------------
-- register file
register_file : entity work.regfile(rtl)
port map (clk => clk,
addra => id_q.rs1,
addrb => id_q.rs2,
rega => rs1_data,
regb => rs2_data,
addrw => wb_rf_wr_addr,
dataw => wb_rf_wr_data,
we => wb_rf_wr_en);
-- inputs
id_d.instruction <= if_id_ir;
-- instantiation
id_stage : entity work.instruction_decoder(Behavioral)
port map (id_d, id_q);
---------------------------------------------------
-- ID/EX pipeline registers
---------------------------------------------------
-- this is where instructions get issued,
-- controlled by id_stall, full_stall, and id_kill
id_ex_reg_proc : process (clk, rst_n) is
begin -- process id_ex_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
id_ex_pc <= (others => '0');
id_ex_rs1_addr <= (others => '0');
id_ex_rs2_addr <= (others => '0');
id_ex_op1 <= (others => '0');
id_ex_op2 <= (others => '0');
id_ex_ir <= NOP;
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
id_ex_rs1_addr <= id_q.rs1;
id_ex_rs2_addr <= id_q.rs2;
id_ex_op1 <= rs1_data;
id_ex_op2 <= rs2_data;
id_ex_use_imm <= id_q.use_imm;
if (id_kill = '1') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
else
-- instruction issue
id_ex_pc <= if_id_pc;
id_ex_ir <= if_id_ir;
id_ex_rd_addr <= id_q.rd;
id_ex_insn_type <= id_q.insn_type;
id_ex_rf_we <= id_q.rf_we;
id_ex_use_imm <= id_q.use_imm;
id_ex_imm <= id_q.imm;
id_ex_alu_func <= id_q.alu_func;
id_ex_branch_type <= id_q.branch_type;
id_ex_load_type <= id_q.load_type;
id_ex_store_type <= id_q.store_type;
end if;
elsif (id_stall = '1' and full_stall = '0') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
end if;
end if;
end process id_ex_reg_proc;
---------------------------------------------------
-- print instructions as they are issued
---------------------------------------------------
print_decode : if (g_for_sim = true) generate
print_decode_proc : process (id_ex_ir, id_ex_pc) is
variable l : line;
begin -- process print_decode_proc
write(l, to_integer(unsigned(id_ex_pc)));
write(l, string'(" : "));
write(l, hstr(id_ex_ir));
writeline(output, l);
end process print_decode_proc;
end generate print_decode;
---------------------------------------------------
-- Instruction execution stage
---------------------------------------------------
-- inputs
ex_d.insn_type <= id_ex_insn_type;
ex_d.npc <= id_ex_pc;
ex_d.rs1 <= id_ex_op1;
ex_d.rs2 <= id_ex_op2;
ex_d.use_imm <= id_ex_use_imm;
ex_d.alu_func <= id_ex_alu_func;
ex_d.branch_type <= id_ex_branch_type;
ex_d.imm <= id_ex_imm;
-- instantiation
ex_stage : entity work.instruction_executor(Behavioral)
port map (ex_d, ex_q);
-- multiplexer for Register File write data
ex_rf_data <= ex_q.return_addr when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR) else
id_ex_imm when (id_ex_insn_type = OP_LUI) else
ex_q.alu_result;
-- selecter for loading the PC with a new value
ex_load_pc <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
-- multiplexer for data memory address
ex_data_addr <= ex_q.alu_result when (id_ex_insn_type = OP_LOAD or id_ex_insn_type = OP_STORE) else ex_mem_data_addr;
---------------------------------------------------
-- EX/MEM pipeline registers
---------------------------------------------------
-- purpose: Pipeline data between EX and MEM stages
ex_mem_regs_proc : process (clk, rst_n) is
begin -- process ex_mem_regs_proc
if (rst_n = '0') then -- asynchronous reset (active low)
ex_mem_load_pc <= '0';
ex_mem_next_pc <= (others => '0');
ex_mem_rf_data <= (others => '0');
ex_mem_return_addr <= (others => '0');
ex_mem_load_type <= LOAD_NONE;
ex_mem_store_type <= STORE_NONE;
ex_mem_rd_addr <= (others => '0');
ex_mem_insn_type <= OP_ILLEGAL;
ex_mem_rf_we <= '0';
elsif (rising_edge(clk)) then
if (full_stall = '0') then
ex_mem_next_pc <= ex_q.alu_result;
ex_mem_load_pc <= ex_load_pc;
ex_mem_rf_data <= ex_rf_data;
ex_mem_data_addr <= ex_data_addr;
ex_mem_data_out <= id_ex_op2;
ex_mem_load_type <= id_ex_load_type;
ex_mem_store_type <= id_ex_store_type;
ex_mem_rd_addr <= id_ex_rd_addr;
ex_mem_insn_type <= id_ex_insn_type;
ex_mem_rf_we <= id_ex_rf_we;
end if;
end if;
end process ex_mem_regs_proc;
---------------------------------------------------
-- Memory stage
---------------------------------------------------
-- memory access logic
mem_we <= '1' when ex_mem_insn_type = OP_STORE else '0';
mem_re <= '1' when ex_mem_insn_type = OP_LOAD else '0';
-- data memory interface multiplexers
mem_data_addr <= ex_mem_data_addr;
mem_data_out <= X"0000" & ex_mem_data_out(15 downto 0) when ex_mem_store_type = SH else
X"000000" & ex_mem_data_out(7 downto 0) when ex_mem_store_type = SB else
ex_mem_data_out;
-- if the load is a signed halfword
mem_lmd_lh <= data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) &
data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15 downto 0);
-- if the load is a signed byte
mem_lmd_lb <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7 downto 0);
-- Load Memory Data register input
with ex_mem_load_type select
mem_lmd <=
X"0000" & data_in(15 downto 0) when LHU,
X"000000" & data_in(7 downto 0) when LBU,
mem_lmd_lh when LH,
mem_lmd_lb when LB,
data_in when others;
---------------------------------------------------
-- MEM/WB pipeline registers
---------------------------------------------------
-- purpose: Create the MEM/WB pipeline registers
mem_wb_regs : process (clk, rst_n) is
begin -- process mem_wb_regs
if (rst_n = '0') then -- asynchronous reset (active low)
mem_wb_rd_addr <= (others => '0');
mem_wb_rf_we <= '0';
mem_wb_rf_data <= (others => '0');
mem_wb_insn_type <= OP_ILLEGAL;
elsif (rising_edge(clk)) then
if (full_stall = '0') then
mem_wb_rd_addr <= ex_mem_rd_addr;
mem_wb_rf_we <= ex_mem_rf_we;
mem_wb_insn_type <= ex_mem_insn_type;
mem_wb_rf_data <= ex_mem_rf_data;
if (data_in_valid = '1') then
mem_wb_lmd <= mem_lmd;
end if;
else
mem_wb_rf_we <= '0';
end if;
end if;
end process mem_wb_regs;
---------------------------------------------------
-- Writeback stage
---------------------------------------------------
wb_rf_wr_addr <= mem_wb_rd_addr;
wb_rf_wr_en <= mem_wb_rf_we;
wb_rf_wr_data <= mem_wb_lmd when (mem_wb_insn_type = OP_LOAD) else mem_wb_rf_data;
end architecture Behavioral;
|
entity tb_fsm_3s is
end tb_fsm_3s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_3s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_3s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"101_101_1100";
constant res : std_logic_vector := b"001_001_0000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
|
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ui_rd_data.v
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
-- User interface read buffer. Re orders read data returned from the
-- memory controller back to the request order.
--
-- Consists of a large buffer for the data, a status RAM and two counters.
--
-- The large buffer is implemented with distributed RAM in 6 bit wide,
-- 1 read, 1 write mode. The status RAM is implemented with a distributed
-- RAM configured as 2 bits wide 1 read/write, 1 read mode.
--
-- As read requests are received from the application, the data_buf_addr
-- counter supplies the data_buf_addr sent into the memory controller.
-- With each read request, the counter is incremented, eventually rolling
-- over. This mechanism labels each read request with an incrementing number.
--
-- When the memory controller returns read data, it echos the original
-- data_buf_addr with the read data.
--
-- The status RAM is indexed with the same address as the data buffer
-- RAM. Each word of the data buffer RAM has an associated status bit
-- and "end" bit. Requests of size 1 return a data burst on two consecutive
-- states. Requests of size zero return with a single assertion of rd_data_en.
--
-- Upon returning data, the status and end bits are updated for each
-- corresponding location in the status RAM indexed by the data_buf_addr
-- echoed on the rd_data_addr field.
--
-- The other side of the status and data RAMs is indexed by the rd_buf_indx.
-- The rd_buf_indx constantly monitors the status bit it is currently
-- pointing to. When the status becomes set to the proper state (more on
-- this later) read data is returned to the application, and the rd_buf_indx
-- is incremented.
--
-- At rst the rd_buf_indx is initialized to zero. Data will not have been
-- returned from the memory controller yet, so there is nothing to return
-- to the application. Evenutally, read requests will be made, and the
-- memory controller will return the corresponding data. The memory
-- controller may not return this data in the request order. In which
-- case, the status bit at location zero, will not indicate
-- the data for request zero is ready. Eventually, the memory controller
-- will return data for request zero. The data is forwarded on to the
-- application, and rd_buf_indx is incremented to point to the next status
-- bits and data in the buffers. The status bit will be examined, and if
-- data is valid, this data will be returned as well. This process
-- continues until the status bit indexed by rd_buf_indx indicates data
-- is not ready. This may be because the rd_data_buf
-- is empty, or that some data was returned out of order. Since rd_buf_indx
-- always increments sequentially, data is always returned to the application
-- in request order.
--
-- Some further discussion of the status bit is in order. The rd_data_buf
-- is a circular buffer. The status bit is a single bit. Distributed RAM
-- supports only a single write port. The write port is consumed by
-- memory controller read data updates. If a simple '1' were used to
-- indicate the status, when rd_data_indx rolled over it would immediately
-- encounter a one for a request that may not be ready.
--
-- This problem is solved by causing read data returns to flip the
-- status bit, and adding hi order bit beyond the size required to
-- index the rd_data_buf. Data is considered ready when the status bit
-- and this hi order bit are equal.
--
-- The status RAM needs to be initialized to zero after reset. This is
-- accomplished by cycling through all rd_buf_indx valus and writing a
-- zero to the status bits directly following deassertion of reset. This
-- mechanism is used for similar purposes
-- for the wr_data_buf.
--
-- When ORDERING == "STRICT", read data reordering is unnecessary. For thi
-- case, most of the logic in the block is not generated.
-- User interface read data.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
LIBRARY unisim;
USE unisim.VCOMPONENTS.all;
ENTITY ui_rd_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
ECC : STRING := "OFF";
ORDERING : STRING := "NORM"
);
PORT (
ram_init_done_r : OUT STD_LOGIC;
ram_init_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_buf_full : OUT STD_LOGIC;
rd_data_buf_addr_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_accepted : IN STD_LOGIC
);
END ENTITY ui_rd_data;
ARCHITECTURE trans OF ui_rd_data IS
SIGNAL rd_buf_indx_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL ram_init_done_r_lcl : STD_LOGIC;
SIGNAL app_rd_data_valid_ns : STD_LOGIC;
SIGNAL app_rd_data_valid_copy : STD_LOGIC;
SIGNAL single_data : STD_LOGIC;
SIGNAL app_ecc_multiple_err_r : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
FUNCTION CALC_RD_BUF_WIDTH ( APP_DATA_WIDTH : integer; ECC : string) RETURN integer is
BEGIN
IF ( ECC = "OFF" ) THEN
RETURN APP_DATA_WIDTH;
ELSE
RETURN APP_DATA_WIDTH + 4;
END IF;
END FUNCTION CALC_RD_BUF_WIDTH;
FUNCTION CALC_RAM_CNT ( FULL_RAM_CNT,REMAINDER: integer) RETURN integer is
BEGIN
IF ( REMAINDER = 0 ) THEN
RETURN FULL_RAM_CNT;
ELSE
RETURN FULL_RAM_CNT + 1;
END IF;
END FUNCTION CALC_RAM_CNT;
-- Compute dimensions of read data buffer. Depending on width of
-- DQ bus and DRAM CK
-- to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
-- single write, single read, 6 bit wide mode.
CONSTANT RD_BUF_WIDTH : INTEGER := CALC_RD_BUF_WIDTH(APP_DATA_WIDTH,ECC);
CONSTANT FULL_RAM_CNT : INTEGER := (RD_BUF_WIDTH/6);
CONSTANT REMAINDER : INTEGER := (RD_BUF_WIDTH mod 6);
CONSTANT RAM_CNT : INTEGER := CALC_RAM_CNT(FULL_RAM_CNT,REMAINDER);
CONSTANT RAM_WIDTH : INTEGER := (RAM_CNT * 6);
-- X-HDL generated signals
SIGNAL xhdl11 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL upd_rd_buf_indx : STD_LOGIC;
SIGNAL ram_init_done_ns : STD_LOGIC;
SIGNAL rd_buf_indx_ns : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL rd_data_buf_addr_ns : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rd_data_buf_addr_r_lcl : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
SIGNAL rd_buf_wr_addr : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rd_status : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL status_ram_wr_addr_ns : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL status_ram_wr_addr_r : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wr_status : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wr_status_r1 : STD_LOGIC;
SIGNAL status_ram_wr_data_ns : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL status_ram_wr_data_r : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rd_buf_we_r1 : STD_LOGIC;
SIGNAL rd_buf_out_data : STD_LOGIC_VECTOR (RAM_WIDTH-1 DOWNTO 0);
SIGNAL rd_buf_indx_copy_r : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
SIGNAL rd_buf_in_data : STD_LOGIC_VECTOR (RAM_WIDTH-1 DOWNTO 0);
SIGNAL rd_data_rdy : STD_LOGIC;
SIGNAL bypass : STD_LOGIC;
SIGNAL app_rd_data_end_ns : STD_LOGIC;
SIGNAL app_rd_data_ns : STD_LOGIC_VECTOR (APP_DATA_WIDTH-1 DOWNTO 0);
SIGNAL app_ecc_multiple_err_ns : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL free_rd_buf : STD_LOGIC;
SIGNAL occ_cnt_r : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_minus_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_plus_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_cnt_ns : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rd_buf_we : STD_LOGIC;
SIGNAL app_rd_data_end_int : STD_LOGIC;
ATTRIBUTE equivalent_register_removal : string;
ATTRIBUTE equivalent_register_removal of rd_buf_indx_copy_r : signal is "no";
ATTRIBUTE equivalent_register_removal of app_rd_data_valid_copy : SIGNAL IS "no";
BEGIN
--This signal is added have the internal usage of the port
--app_rd_data_end
app_rd_data_end <= app_rd_data_end_int;
-- rd_buf_indx points to the status and data storage rams for
-- reading data out to the app.
ram_init_done_r <= ram_init_done_r_lcl;
upd_rd_buf_indx <= NOT(ram_init_done_r_lcl) OR app_rd_data_valid_ns;
-- Loop through all status write addresses once after rst. Initializes
-- the status and pointer RAMs.
ram_init_done_ns <= NOT(rst) when (rd_buf_indx_r(4 DOWNTO 0) = "11111") else NOT(rst) AND ram_init_done_r_lcl ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
ram_init_done_r_lcl <= ram_init_done_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (rd_buf_indx_r, rst, single_data, upd_rd_buf_indx)
BEGIN
rd_buf_indx_ns <= rd_buf_indx_r;
IF (rst = '1') THEN
rd_buf_indx_ns <= "000000";
ELSIF (upd_rd_buf_indx = '1') THEN
rd_buf_indx_ns <= rd_buf_indx_r + "000001" + ("00000" & single_data);
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_indx_r <= rd_buf_indx_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
ram_init_addr <= rd_buf_indx_r(3 DOWNTO 0);
app_ecc_multiple_err <= app_ecc_multiple_err_r;
xhdl0 : IF (ORDERING = "STRICT") GENERATE
app_rd_data_valid_ns <= '0';
single_data <= '0';
rd_buf_full <= '0';
rd_data_buf_addr_ns <= "0000" WHEN (rst = '1') ELSE
rd_data_buf_addr_r_lcl + ("000" & rd_accepted);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_data_buf_addr_r_lcl <= rd_data_buf_addr_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
rd_data_buf_addr_r <= rd_data_buf_addr_ns;
-- app_* signals required to be registered.
xhdl1 : IF (ECC = "OFF") GENERATE
PROCESS (rd_data)
BEGIN
app_rd_data <= rd_data;
END PROCESS;
PROCESS (rd_data_en)
BEGIN
app_rd_data_valid <= rd_data_en;
END PROCESS;
PROCESS (rd_data_end)
BEGIN
app_rd_data_end_int <= rd_data_end;
END PROCESS;
END GENERATE;
xhdl2 : IF (NOT(ECC = "OFF")) GENERATE
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data <= rd_data AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid <= rd_data_en AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_end_int <= rd_data_end AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_ecc_multiple_err_r <= ecc_multiple AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
END GENERATE;
END GENERATE;
xhdl3 : IF (NOT(ORDERING = "STRICT")) GENERATE
rd_buf_we <= NOT(ram_init_done_r_lcl) OR rd_data_en;
rd_buf_wr_addr <= (rd_data_addr & rd_data_offset);
-- Instantiate status RAM. One bit for status and one for "end".
-- Turns out read to write back status is a timing path. Update
-- the status in the ram on the state following the read. Bypass
-- the write data into the status read path.
status_ram_wr_addr_ns <= rd_buf_wr_addr WHEN (ram_init_done_r_lcl = '1') ELSE
rd_buf_indx_r(4 DOWNTO 0);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
status_ram_wr_addr_r <= status_ram_wr_addr_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
-- Not guaranteed to write second status bit. If it is written, always
-- copy in the first status bit.
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
wr_status_r1 <= wr_status(0) AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
status_ram_wr_data_ns <= "00" WHEN ( ram_init_done_r_lcl = '0') ELSE
(rd_data_end & NOT( wr_status_r1 )) WHEN (rd_data_offset = '1') ELSE
(rd_data_end & NOT( wr_status(0) ));
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
status_ram_wr_data_r <= status_ram_wr_data_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_we_r1 <= rd_buf_we AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
RAM32M0 : RAM32M
GENERIC MAP (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
PORT MAP (
doa => rd_status,
dob => open,
doc => wr_status,
dod => open,
dia => status_ram_wr_data_r,
dib => "00",
dic => status_ram_wr_data_r,
did => status_ram_wr_data_r,
addra => rd_buf_indx_r(4 DOWNTO 0),
addrb => "00000",
addrc => status_ram_wr_addr_ns,
addrd => status_ram_wr_addr_r,
we => rd_buf_we_r1,
wclk => clk
);
-- block: status_ram
xhdl4 : IF (REMAINDER = 0) GENERATE
xhdl5 : IF (ECC = "OFF") GENERATE
rd_buf_in_data <= rd_data;
END GENERATE;
xhdl6 : IF (NOT(ECC = "OFF")) GENERATE
SIGNAL ecc_multiple_rd_data : STD_LOGIC_VECTOR ( APP_DATA_WIDTH + 3 DOWNTO 0 );
BEGIN
ecc_multiple_rd_data <= (ecc_multiple & rd_data);
rd_buf_in_data <= ecc_multiple_rd_data(RAM_WIDTH - 1 DOWNTO 0);
END GENERATE;
END GENERATE;
xhdl7 : IF (NOT(REMAINDER = 0)) GENERATE
xhdl8 : IF (ECC = "OFF") GENERATE
SIGNAL zero_rd_data : STD_LOGIC_VECTOR ( 6-REMAINDER+APP_DATA_WIDTH-1 DOWNTO 0);
BEGIN
zero_rd_data <= (std_logic_vector(to_unsigned(0,6-REMAINDER)) & rd_data);
rd_buf_in_data <= zero_rd_data (RAM_WIDTH-1 DOWNTO 0);
END GENERATE;
xhdl9 : IF (NOT(ECC = "OFF")) GENERATE
SIGNAL zero_ecc_multiple_rd_data : STD_LOGIC_VECTOR ( 6-REMAINDER+APP_DATA_WIDTH+3 DOWNTO 0);
BEGIN
zero_ecc_multiple_rd_data <= (std_logic_vector(to_unsigned(0,6-REMAINDER)) & ecc_multiple & rd_data);
rd_buf_in_data <= zero_ecc_multiple_rd_data(RAM_WIDTH - 1 DOWNTO 0);
END GENERATE;
END GENERATE;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_indx_copy_r <= rd_buf_indx_ns (4 DOWNTO 0);
END IF;
END PROCESS;
rd_buffer_ram : FOR i IN 0 TO RAM_CNT - 1 GENERATE
RAM32M0 : RAM32M
GENERIC MAP (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
PORT MAP (
doa => rd_buf_out_data(((i * 6) + 4) + 1 DOWNTO ((i * 6) + 4)),
dob => rd_buf_out_data(((i * 6) + 2) + 1 DOWNTO ((i * 6) + 2)),
doc => rd_buf_out_data(((i * 6) + 0) + 1 DOWNTO ((i * 6) + 0)),
dod => open,
dia => rd_buf_in_data(((i * 6) + 4) + 1 DOWNTO ((i * 6) + 4)),
dib => rd_buf_in_data(((i * 6) + 2) + 1 DOWNTO ((i * 6) + 2)),
dic => rd_buf_in_data(((i * 6) + 0) + 1 DOWNTO ((i * 6) + 0)),
did => "00",
addra => rd_buf_indx_copy_r(4 DOWNTO 0),
addrb => rd_buf_indx_copy_r(4 DOWNTO 0),
addrc => rd_buf_indx_copy_r(4 DOWNTO 0),
addrd => rd_buf_wr_addr,
we => rd_buf_we,
wclk => clk
);
-- block: rd_buffer_ram
END GENERATE;
rd_data_rdy <= '1' when (rd_status(0) = rd_buf_indx_r(5)) else '0';
bypass <= rd_data_en when (rd_buf_wr_addr(4 DOWNTO 0) = rd_buf_indx_r(4 DOWNTO 0)) else '0';
app_rd_data_valid_ns <= ram_init_done_r_lcl AND (bypass OR rd_data_rdy);
app_rd_data_end_ns <= rd_data_end WHEN (bypass = '1') ELSE
rd_status(1);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid <= app_rd_data_valid_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_end_int <= app_rd_data_end_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
single_data <= app_rd_data_valid_ns AND app_rd_data_end_ns AND NOT(rd_buf_indx_r(0));
app_rd_data_ns <= rd_data WHEN (bypass = '1') ELSE
rd_buf_out_data(APP_DATA_WIDTH - 1 DOWNTO 0);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data <= app_rd_data_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
xhdl10 : IF ( NOT(ECC = "OFF")) GENERATE
app_ecc_multiple_err_ns <= ecc_multiple WHEN (bypass = '1') ELSE
rd_buf_out_data(APP_DATA_WIDTH + 3 DOWNTO APP_DATA_WIDTH);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_ecc_multiple_err_r <= app_ecc_multiple_err_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
-- Keep track of how many entries in the queue hold data.
END GENERATE;
--Added to fix timing. The signal app_rd_data_valid has
--a very high fanout. So making a dedicated copy for usage
--with the occ_cnt counter.
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid_copy <= app_rd_data_valid_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
free_rd_buf <= app_rd_data_valid_copy AND app_rd_data_end_int; --changed to use registered version
--of the signals in ordered to fix timing
occ_minus_one <= occ_cnt_r - "00001";
occ_plus_one <= occ_cnt_r + "00001";
xhdl11 <= rd_accepted & free_rd_buf;
PROCESS (free_rd_buf, occ_cnt_r, rd_accepted, rst, occ_minus_one, occ_plus_one,xhdl11)
BEGIN
occ_cnt_ns <= occ_cnt_r;
IF (rst = '1') THEN
occ_cnt_ns <= "00000";
ELSE
CASE xhdl11 IS
WHEN "01" =>
occ_cnt_ns <= occ_minus_one;
WHEN "10" => -- case ({wr_data_end, new_rd_data})
occ_cnt_ns <= occ_plus_one;
WHEN OTHERS =>
occ_cnt_ns <= occ_cnt_r;
END CASE;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
occ_cnt_r <= occ_cnt_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
rd_buf_full <= occ_cnt_ns(4);
-- block: occupied_counter
-- Generate the data_buf_address written into the memory controller
-- for reads. Increment with each accepted read, and rollover at 0xf.
rd_data_buf_addr_r <= rd_data_buf_addr_r_lcl;
PROCESS (rd_accepted, rd_data_buf_addr_r_lcl, rst)
BEGIN
rd_data_buf_addr_ns <= rd_data_buf_addr_r_lcl;
IF (rst = '1') THEN
rd_data_buf_addr_ns <= "0000";
ELSIF (rd_accepted = '1') THEN
rd_data_buf_addr_ns <= rd_data_buf_addr_r_lcl + "0001";
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_data_buf_addr_r_lcl <= rd_data_buf_addr_ns AFTER (TCQ)*1 ps; -- block: data_buf_addr
END IF;
END PROCESS;
-- block: not_strict_mode
END GENERATE;
-- ui_rd_data
END ARCHITECTURE trans;
|
entity tb_memmux05 is
end tb_memmux05;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux05 is
signal ad : std_logic;
signal val : std_logic_vector (1 downto 0);
signal dat, res : std_logic_vector (2 downto 0);
begin
dut : entity work.memmux05
port map (
ad => ad,
val => val,
dat => dat,
res => res);
process
begin
dat <= "110";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = "100" report "1) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = "000" report "2) res=" & to_bstring (res) severity failure;
ad <= '0';
val <= "01";
wait for 1 ns;
assert res = "101" report "3) res=" & to_bstring (res) severity failure;
ad <= '0';
val <= "10";
wait for 1 ns;
assert res = "110" report "4) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = "100" report "5) res=" & to_bstring (res) severity failure;
dat <= "010";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = "000" report "6) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = "000" report "7) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = "100" report "8) res=" & to_bstring (res) severity failure;
wait;
end process;
end behav;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY base_zynq_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END base_zynq_design_axi_gpio_0_0;
ARCHITECTURE base_zynq_design_axi_gpio_0_0_arch OF base_zynq_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 5,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END base_zynq_design_axi_gpio_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1798.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01798ent IS
END c07s01b00x00p02n01i01798ent;
ARCHITECTURE c07s01b00x00p02n01i01798arch OF c07s01b00x00p02n01i01798ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if -x + z < y + x and x * z > y - x then -- No_failure_here
x := x - z;
end if;
assert NOT(x=-6)
report "***PASSED TEST: c07s01b00x00p02n01i01798"
severity NOTE;
assert (x=-6)
report "***FAILED TEST: c07s01b00x00p02n01i01798 - The expression is a valid expression according to the rules of the syntactic diagram."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p02n01i01798arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1798.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01798ent IS
END c07s01b00x00p02n01i01798ent;
ARCHITECTURE c07s01b00x00p02n01i01798arch OF c07s01b00x00p02n01i01798ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if -x + z < y + x and x * z > y - x then -- No_failure_here
x := x - z;
end if;
assert NOT(x=-6)
report "***PASSED TEST: c07s01b00x00p02n01i01798"
severity NOTE;
assert (x=-6)
report "***FAILED TEST: c07s01b00x00p02n01i01798 - The expression is a valid expression according to the rules of the syntactic diagram."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p02n01i01798arch;
|
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