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--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:18:41 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_pb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end logi_virtual_pb;
architecture Behavioral of logi_virtual_pb is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
pb <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:18:41 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_pb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end logi_virtual_pb;
architecture Behavioral of logi_virtual_pb is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
pb <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity graphics is
port(
clk, not_reset: in std_logic;
nes1_up, nes1_down: in std_logic;
nes2_up, nes2_down: in std_logic;
nes_start: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
video_on: in std_logic;
rgb_stream: out std_logic_vector(2 downto 0);
ball_bounced: out std_logic;
ball_missed: out std_logic
);
end graphics;
architecture dispatcher of graphics is
constant SCREEN_WIDTH: integer := 640;
constant SCREEN_HEIGHT: integer := 480;
type game_states is (start, waiting, playing, game_over);
signal state, state_next: game_states;
type counter_storage is array(0 to 3) of std_logic_vector(17 downto 0);
constant COUNTER_VALUES: counter_storage :=
(
"110010110111001101", -- 208333
"101000101100001011", -- 166667
"100001111010001001", -- 138889
"011101000100001000" -- 119048
);
-- counters to determine ball control frequency
signal ball_control_counter,
ball_control_counter_next: std_logic_vector(17 downto 0);
signal ball_control_value: integer;
-- counts how many times the ball hits the bar
-- used to determine ball speed
signal bounce_counter, bounce_counter_next: std_logic_vector(7 downto 0);
constant MIDDLE_LINE_POS: integer := SCREEN_WIDTH / 2;
signal middle_line_on: std_logic;
signal middle_line_rgb: std_logic_vector(2 downto 0);
signal score_1, score_1_next: std_logic_vector(5 downto 0);
signal score_2, score_2_next: std_logic_vector(5 downto 0);
signal score_on: std_logic;
signal current_score: std_logic_vector(5 downto 0);
signal score_font_addr: std_logic_vector(8 downto 0);
-- message format is "PLAYER p WINS!"
-- where p is replaced by player_id
signal message_on, player_id_on: std_logic;
signal message_font_addr, player_id_font_addr: std_logic_vector(8 downto 0);
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal font_rgb: std_logic_vector(2 downto 0);
constant BALL_SIZE: integer := 16; -- ball is square
signal ball_enable: std_logic;
signal ball_addr: std_logic_vector(3 downto 0);
signal ball_px_addr: std_logic_vector(3 downto 0);
signal ball_data: std_logic_vector(0 to BALL_SIZE - 1);
signal ball_pixel: std_logic;
signal ball_rgb: std_logic_vector(2 downto 0);
signal ball_x, ball_x_next: std_logic_vector(9 downto 0);
signal ball_y, ball_y_next: std_logic_vector(9 downto 0);
signal ball_h_dir, ball_h_dir_next, ball_v_dir, ball_v_dir_next: std_logic;
signal ball_bounce, ball_miss: std_logic;
constant BAR_1_POS: integer := 20;
constant BAR_2_POS: integer := 600;
constant BAR_WIDTH: integer := 20;
constant BAR_HEIGHT: integer := 64;
signal bar_pos: integer;
signal bar_addr: std_logic_vector(5 downto 0);
signal bar_data: std_logic_vector(0 to BAR_WIDTH - 1);
signal bar_pixel: std_logic;
signal bar_rgb: std_logic_vector(2 downto 0);
signal bar_1_y, bar_1_y_next,
bar_2_y, bar_2_y_next: std_logic_vector(9 downto 0);
signal ball_on, bar_on: std_logic;
begin
process(state, ball_x, nes_start, score_1, score_2)
begin
state_next <= state;
ball_enable <= '0';
ball_miss <= '0';
score_1_next <= score_1;
score_2_next <= score_2;
case state is
when start =>
score_1_next <= (others => '0');
score_2_next <= (others => '0');
state_next <= waiting;
when waiting =>
ball_enable <= '0';
if score_1 = 7 or score_2 = 7 then
state_next <= game_over;
elsif nes_start = '1' then
state_next <= playing;
end if;
when playing =>
ball_enable <= '1';
if ball_x = 0 then
-- player 2 wins
score_2_next <= score_2 + 1;
state_next <= waiting;
ball_miss <= '1';
elsif ball_x = SCREEN_WIDTH - BALL_SIZE then
-- player 1 wins
score_1_next <= score_1 + 1;
state_next <= waiting;
ball_miss <= '1';
end if;
when game_over =>
if nes_start = '1' then
state_next <= start;
end if;
end case;
end process;
process(clk, not_reset)
begin
if not_reset = '0' then
state <= start;
ball_x <= (others => '0');
ball_y <= (others => '0');
bar_1_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
bar_2_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
ball_h_dir <= '0';
ball_v_dir <= '0';
bounce_counter <= (others => '0');
ball_control_counter <= (others => '0');
score_1 <= (others => '0');
score_2 <= (others => '0');
elsif clk'event and clk = '0' then
state <= state_next;
ball_x <= ball_x_next;
ball_y <= ball_y_next;
bar_1_y <= bar_1_y_next;
bar_2_y <= bar_2_y_next;
ball_h_dir <= ball_h_dir_next;
ball_v_dir <= ball_v_dir_next;
bounce_counter <= bounce_counter_next;
ball_control_counter <= ball_control_counter_next;
score_1 <= score_1_next;
score_2 <= score_2_next;
end if;
end process;
score_on <= '1' when px_y(9 downto 3) = 1 and
(px_x(9 downto 3) = 42 or px_x(9 downto 3) = 37) else
'0';
current_score <= score_1 when px_x < 320 else score_2;
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
score_font_addr <= conv_std_logic_vector(128, 9) +
(current_score(2 downto 0) & current_score(5 downto 3));
player_id_on <= '1' when state = game_over and px_y(9 downto 3) = 29 and
(px_x(9 downto 3) = 19 or px_x(9 downto 3) = 59) else
'0';
-- player_id will display either 1 or 2
player_id_font_addr <= "010001000" when px_x < 320 else "010010000";
message_on <= '1' when state = game_over and
-- message on player_1's side
((score_1 > score_2 and
px_x(9 downto 3) >= 12 and
px_x(9 downto 3) < 26 and
px_y(9 downto 3) = 29) or
-- message on player_2's side
(score_2 > score_1 and
px_x(9 downto 3) >= 52 and
px_x(9 downto 3) < 66 and
px_y(9 downto 3) = 29)) else
'0';
with px_x(9 downto 3) select
message_font_addr <= "110000000" when "0110100"|"0001100", -- P
"101100000" when "0110101"|"0001101", -- L
"100001000" when "0110110"|"0001110", -- A
"111001000" when "0110111"|"0001111", -- Y
"100101000" when "0111000"|"0010000", -- E
"110010000" when "0111001"|"0010001", -- R
"111100000" when "0111011"|"0010011", -- not visible
"110111000" when "0111101"|"0010101", -- W
"101111000" when "0111110"|"0010110", -- O
"101110000" when "0111111"|"0010111", -- N
"000001000" when "1000000"|"0011000", -- !
"000000000" when others;
-- font address mutltiplexer
font_addr <= px_y(2 downto 0) + score_font_addr when score_on = '1' else
px_y(2 downto 0) + player_id_font_addr when player_id_on = '1' else
px_y(2 downto 0) + message_font_addr when message_on = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
font_rgb <= "000" when font_pixel = '1' else "111";
direction_control: process(
ball_control_counter,
ball_x, ball_y,
ball_h_dir, ball_v_dir,
ball_h_dir_next, ball_v_dir_next,
bar_1_y, bar_2_y
)
begin
ball_h_dir_next <= ball_h_dir;
ball_v_dir_next <= ball_v_dir;
ball_bounce <= '0';
--
-- BEWARE! Looks like ball_bounce signal is generated twice
-- due to slower clock! Too lazy to fix now :D
--
if ball_control_counter = 0 then
if ball_x = bar_1_pos + BAR_WIDTH and
ball_y + BALL_SIZE > bar_1_y and
ball_y < bar_1_y + BAR_HEIGHT then
ball_h_dir_next <= '1';
ball_bounce <= '1';
elsif ball_x + BALL_SIZE = bar_2_pos and
ball_y + BALL_SIZE > bar_2_y and
ball_y < bar_2_y + BAR_HEIGHT then
ball_h_dir_next <= '0';
ball_bounce <= '1';
elsif ball_x < bar_1_pos + BAR_WIDTH and
ball_x + BALL_SIZE > bar_1_pos then
if ball_y + BALL_SIZE = bar_1_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_1_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
elsif ball_x + BALL_SIZE > bar_2_pos and
ball_x < bar_2_pos + BAR_WIDTH then
if ball_y + BALL_SIZE = bar_2_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_2_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
end if;
if ball_y = 0 then
ball_v_dir_next <= '1';
elsif ball_y = SCREEN_HEIGHT - BALL_SIZE then
ball_v_dir_next <= '0';
end if;
end if;
end process;
bounce_counter_next <= bounce_counter + 1 when ball_bounce = '1' else
(others => '0') when ball_miss = '1' else
bounce_counter;
ball_control_value <= 0 when bounce_counter < 4 else
1 when bounce_counter < 15 else
2 when bounce_counter < 25 else
3;
ball_control_counter_next <= ball_control_counter + 1 when ball_control_counter < COUNTER_VALUES(ball_control_value) else
(others => '0');
ball_control: process(
ball_control_counter,
ball_x, ball_y,
ball_x_next, ball_y_next,
ball_h_dir, ball_v_dir,
ball_enable
)
begin
ball_x_next <= ball_x;
ball_y_next <= ball_y;
if ball_enable = '1' then
if ball_control_counter = 0 then
if ball_h_dir = '1' then
ball_x_next <= ball_x + 1;
else
ball_x_next <= ball_x - 1;
end if;
if ball_v_dir = '1' then
ball_y_next <= ball_y + 1;
else
ball_y_next <= ball_y - 1;
end if;
end if;
else
ball_x_next <= conv_std_logic_vector(SCREEN_WIDTH / 2 - BALL_SIZE / 2, 10);
ball_y_next <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BALL_SIZE / 2, 10);
end if;
end process;
bar_control: process(
bar_1_y, bar_2_y,
nes1_up, nes1_down,
nes2_up, nes2_down
)
begin
bar_1_y_next <= bar_1_y;
bar_2_y_next <= bar_2_y;
if nes1_up = '1' then
if bar_1_y > 0 then
bar_1_y_next <= bar_1_y - 1;
end if;
elsif nes1_down = '1' then
if bar_1_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_1_y_next <= bar_1_y + 1;
end if;
end if;
if nes2_up = '1' then
if bar_2_y > 0 then
bar_2_y_next <= bar_2_y - 1;
end if;
elsif nes2_down = '1' then
if bar_2_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_2_y_next <= bar_2_y + 1;
end if;
end if;
end process;
middle_line_on <= '1' when px_x = MIDDLE_LINE_POS else '0';
middle_line_rgb <= "000" when px_y(0) = '1' else "111";
ball_on <= '1' when px_x >= ball_x and
px_x < (ball_x + BALL_SIZE) and
px_y >= ball_y and
px_y < (ball_y + BALL_SIZE) else
'0';
-- whether bar_1 or bar_2 is on
bar_on <= '1' when (px_x >= BAR_1_POS and
px_x < BAR_1_POS + BAR_WIDTH and
px_y >= bar_1_y and
px_y < bar_1_y + BAR_HEIGHT) or
(px_x >= BAR_2_POS and
px_x < BAR_2_POS + BAR_WIDTH and
px_y >= bar_2_y and
px_y < bar_2_y + BAR_HEIGHT) else
'0';
ball_addr <= px_y(3 downto 0) - ball_y(3 downto 0);
ball_px_addr <= px_x(3 downto 0) - ball_x(3 downto 0);
ball_pixel <= ball_data(conv_integer(ball_px_addr));
ball_rgb <= "000" when ball_pixel = '1' else "111";
bar_addr <= (px_y(5 downto 0) - bar_1_y(5 downto 0)) when px_x < 320 else
(px_y(5 downto 0) - bar_2_y(5 downto 0));
bar_pos <= BAR_1_POS when px_x < 320 else BAR_2_POS;
bar_pixel <= bar_data(conv_integer(px_x - bar_pos));
bar_rgb <= "000" when bar_pixel = '1' else "111";
process(
ball_on, bar_on,
ball_rgb, bar_rgb,
score_on, message_on, font_rgb,
middle_line_on, middle_line_rgb,
video_on
)
begin
if video_on = '1' then
if bar_on = '1' then
rgb_stream <= bar_rgb;
elsif ball_on = '1' then
rgb_stream <= ball_rgb;
elsif middle_line_on = '1' then
rgb_stream <= middle_line_rgb;
-- scores and messages share rgb stream
elsif score_on = '1' or message_on = '1' then
rgb_stream <= font_rgb;
else
-- background is white
rgb_stream <= "111";
end if;
else
-- blank screen
rgb_stream <= "000";
end if;
end process;
ball_unit:
entity work.ball_rom(content)
port map(addr => ball_addr, data => ball_data);
bar_unit:
entity work.bar_rom(content)
port map(clk => clk, addr => bar_addr, data => bar_data);
font_unit:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
ball_bounced <= ball_bounce;
ball_missed <= ball_miss;
end dispatcher; |
----------------------------------------------------------------------------------
-- Company: UOM
-- Engineer: Gihan Karunarathne
--
-- Create Date: 12:48:34 08/21/2013
-- Design Name:
-- Module Name: BIDIR - Behavioral
-- Project Name: Tutorial I
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BIDIR is
Port ( DATA : inout STD_LOGIC;
IOCTR : in STD_LOGIC;
INPUT : out STD_LOGIC;
OUTPUT : in STD_LOGIC);
end BIDIR;
architecture Behavioral of BIDIR is
begin
INPUT <= DATA when IOCTR = '1';
DATA <= OUTPUT when IOCTR = '0';
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1737.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p09n01i01737ent IS
END c09s04b00x00p09n01i01737ent;
ARCHITECTURE c09s04b00x00p09n01i01737arch OF c09s04b00x00p09n01i01737ent IS
signal s1 : bit;
signal s2 : bit;
BEGIN
s1 <= not s1 after 70 ns;
s2 <= not s2 after 30 ns;
block_label1 : BLOCK (s1 = '1')
begin
assert (s2 = s2'last_value)
report "PASSED TEST"
severity NOTE;
TESTING: PROCESS(s2)
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p09n01i01737 - This test needs manual check, depend on the simulation time, the assertion 'PASSED TEST' should fire every time s2 is changed regardless of the value of the signal GUARD."
severity NOTE;
END PROCESS TESTING;
end block block_label1;
END c09s04b00x00p09n01i01737arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1737.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p09n01i01737ent IS
END c09s04b00x00p09n01i01737ent;
ARCHITECTURE c09s04b00x00p09n01i01737arch OF c09s04b00x00p09n01i01737ent IS
signal s1 : bit;
signal s2 : bit;
BEGIN
s1 <= not s1 after 70 ns;
s2 <= not s2 after 30 ns;
block_label1 : BLOCK (s1 = '1')
begin
assert (s2 = s2'last_value)
report "PASSED TEST"
severity NOTE;
TESTING: PROCESS(s2)
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p09n01i01737 - This test needs manual check, depend on the simulation time, the assertion 'PASSED TEST' should fire every time s2 is changed regardless of the value of the signal GUARD."
severity NOTE;
END PROCESS TESTING;
end block block_label1;
END c09s04b00x00p09n01i01737arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1737.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p09n01i01737ent IS
END c09s04b00x00p09n01i01737ent;
ARCHITECTURE c09s04b00x00p09n01i01737arch OF c09s04b00x00p09n01i01737ent IS
signal s1 : bit;
signal s2 : bit;
BEGIN
s1 <= not s1 after 70 ns;
s2 <= not s2 after 30 ns;
block_label1 : BLOCK (s1 = '1')
begin
assert (s2 = s2'last_value)
report "PASSED TEST"
severity NOTE;
TESTING: PROCESS(s2)
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p09n01i01737 - This test needs manual check, depend on the simulation time, the assertion 'PASSED TEST' should fire every time s2 is changed regardless of the value of the signal GUARD."
severity NOTE;
END PROCESS TESTING;
end block block_label1;
END c09s04b00x00p09n01i01737arch;
|
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Ny4AK3CuIpQ1mJJ0zvMzGg==
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string);
end c09s00b00x00p05n01i01655pkg;
package body c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string) is -- concurrent procedure
begin
assert false
report "Concurrent procedure called from " & loc
severity note ;
end cpc;
end c09s00b00x00p05n01i01655pkg;
use work.c09s00b00x00p05n01i01655pkg.all;
entity c09s00b00x00p05n01i01655ent_a is
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from component."
severity note ;
cpcc : cpc("component entity");
ppsc : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in component."
severity note ;
end process;
end c09s00b00x00p05n01i01655ent_a;
architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
begin
cpc("component architecture");
end;
use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
ENTITY c09s00b00x00p05n01i01655ent IS
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from entity."
severity note ;
cpce : cpc("entity.");
ppse : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in entity."
severity note ;
end process;
END c09s00b00x00p05n01i01655ent;
ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
signal lab_sig : boolean := true;
component comp
port (signal pi : in bit;
signal po : out bit
);
end component; -- comp
for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
port map (pi, po);
BEGIN
casa : assert false
report "Labeled concurrent assert called from architecture."
severity note ;
cpca : cpc("architecture.");
ppsa : process (pi)
begin
assert false
report "Passive process can be labeled in architecture."
severity note ;
end process;
lba: block
begin
cpcb : cpc("block.");
casb : assert false
report "Labeled concurrent assert called from labeled block."
severity note ;
end block lba;
csa : lab_sig <= false;
assert lab_sig
report "Labeled concurrent signal assignment executed in architecture."
severity note ;
lcia : comp
port map (pi => pi, po => po);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p05n01i01655arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string);
end c09s00b00x00p05n01i01655pkg;
package body c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string) is -- concurrent procedure
begin
assert false
report "Concurrent procedure called from " & loc
severity note ;
end cpc;
end c09s00b00x00p05n01i01655pkg;
use work.c09s00b00x00p05n01i01655pkg.all;
entity c09s00b00x00p05n01i01655ent_a is
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from component."
severity note ;
cpcc : cpc("component entity");
ppsc : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in component."
severity note ;
end process;
end c09s00b00x00p05n01i01655ent_a;
architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
begin
cpc("component architecture");
end;
use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
ENTITY c09s00b00x00p05n01i01655ent IS
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from entity."
severity note ;
cpce : cpc("entity.");
ppse : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in entity."
severity note ;
end process;
END c09s00b00x00p05n01i01655ent;
ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
signal lab_sig : boolean := true;
component comp
port (signal pi : in bit;
signal po : out bit
);
end component; -- comp
for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
port map (pi, po);
BEGIN
casa : assert false
report "Labeled concurrent assert called from architecture."
severity note ;
cpca : cpc("architecture.");
ppsa : process (pi)
begin
assert false
report "Passive process can be labeled in architecture."
severity note ;
end process;
lba: block
begin
cpcb : cpc("block.");
casb : assert false
report "Labeled concurrent assert called from labeled block."
severity note ;
end block lba;
csa : lab_sig <= false;
assert lab_sig
report "Labeled concurrent signal assignment executed in architecture."
severity note ;
lcia : comp
port map (pi => pi, po => po);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p05n01i01655arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string);
end c09s00b00x00p05n01i01655pkg;
package body c09s00b00x00p05n01i01655pkg is
procedure cpc (constant loc : string) is -- concurrent procedure
begin
assert false
report "Concurrent procedure called from " & loc
severity note ;
end cpc;
end c09s00b00x00p05n01i01655pkg;
use work.c09s00b00x00p05n01i01655pkg.all;
entity c09s00b00x00p05n01i01655ent_a is
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from component."
severity note ;
cpcc : cpc("component entity");
ppsc : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in component."
severity note ;
end process;
end c09s00b00x00p05n01i01655ent_a;
architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
begin
cpc("component architecture");
end;
use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
ENTITY c09s00b00x00p05n01i01655ent IS
port (signal pi : in bit;
signal po : out bit
);
begin
cas : assert false
report "Labeled concurrent assert called from entity."
severity note ;
cpce : cpc("entity.");
ppse : -- passive process stmt
process (pi)
begin
assert false
report "Passive process can be labeled in entity."
severity note ;
end process;
END c09s00b00x00p05n01i01655ent;
ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
signal lab_sig : boolean := true;
component comp
port (signal pi : in bit;
signal po : out bit
);
end component; -- comp
for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
port map (pi, po);
BEGIN
casa : assert false
report "Labeled concurrent assert called from architecture."
severity note ;
cpca : cpc("architecture.");
ppsa : process (pi)
begin
assert false
report "Passive process can be labeled in architecture."
severity note ;
end process;
lba: block
begin
cpcb : cpc("block.");
casb : assert false
report "Labeled concurrent assert called from labeled block."
severity note ;
end block lba;
csa : lab_sig <= false;
assert lab_sig
report "Labeled concurrent signal assignment executed in architecture."
severity note ;
lcia : comp
port map (pi => pi, po => po);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p05n01i01655arch;
|
----------------------------------------------------------------------------------
--this merges the data from different streams onto the serdes interface
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity data_merge is
port(
pclk : in std_logic;
reset : in std_logic;
data_rdy_pcie : in std_logic; --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o : out std_logic;
stream1 : in std_logic_vector(15 downto 0);
stream2 : in std_logic_vector(15 downto 0);
stream3 : in std_logic_vector(15 downto 0);
stream4 : in std_logic_vector(15 downto 0);
dout_o : out std_logic_vector(7 downto 0)
);
end data_merge;
architecture Behavioral of data_merge is
signal pclk_data_rdy_pcie : std_logic; --pclk synced data_rdy_pcie signal
signal dout, dout_next : std_logic_vector(7 downto 0); --digital output
signal vsync, vsync_next : std_logic;
type merge_state_type is (IDLE, S1MSB, S1LSB, S2MSB, S2LSB, S3MSB, S3LSB, S4MSB, S4LSB, WAITLOW); --state machine definition:
signal merge_state, merge_state_next : merge_state_type;
signal sm_cnt, sm_cnt_next : unsigned(3 downto 0);
begin
--signal assignment
vsync_o <= vsync;
dout_o <= dout;
--vsync triggers the data spliting process
process(reset, merge_state, pclk)
begin
if (reset='1') then
merge_state <= IDLE;
dout <= (others=>'0');
vsync <= '0';
sm_cnt <= (others=>'0');
elsif (rising_edge(pclk)) then
merge_state <= merge_state_next;
dout <= dout_next;
vsync <= vsync_next;
sm_cnt <= sm_cnt_next;
end if;
end process;
--next states
process(reset, merge_state, data_rdy_pcie, sm_cnt, dout, stream1, stream2, stream3, stream4)
begin
case merge_state is
when IDLE =>
if data_rdy_pcie = '1' then
merge_state_next <= S1MSB;
else
merge_state_next <= IDLE;
end if;
dout_next <= dout;
vsync_next <= '0';
sm_cnt_next <= (others=>'0');
when S1MSB =>
merge_state_next <= S1LSB;
dout_next <= stream1(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S1LSB =>
merge_state_next <= S2MSB;
dout_next <= stream1(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S2MSB =>
merge_state_next <= S2LSB;
dout_next <= stream2(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S2LSB =>
merge_state_next <= S3MSB;
dout_next <= stream2(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S3MSB =>
merge_state_next <= S3LSB;
dout_next <= stream3(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S3LSB =>
merge_state_next <= S4MSB;
dout_next <= stream3(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S4MSB =>
merge_state_next <= S4LSB;
dout_next <= stream4(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S4LSB =>
merge_state_next <= WAITLOW;
dout_next <= stream4(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when WAITLOW =>
if data_rdy_pcie = '0' then
if sm_cnt >= 10 then
merge_state_next <= IDLE;
vsync_next <= '0';
sm_cnt_next <= (others=>'0');
else
sm_cnt_next <= sm_cnt + 1;
vsync_next <= '1';
merge_state_next <= WAITLOW;
end if;
else
merge_state_next <= WAITLOW;
vsync_next <= '1';
sm_cnt_next <= sm_cnt;
end if;
dout_next <= (others=>'0');
--sm_cnt_next <= (others=>'0');
end case;
end process;
end Behavioral;
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all; --tost
use grlib.amba.all;
use grlib.devices.all; -- vendor gaisler etc
--library gaisler;
--use gaisler.misc.all; --vår typ
use work.mypackage.all; --contains type
entity apblcd is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer range 0 to 1 := 0;
tas : integer range 0 to 15 := 1;
epw : integer range 0 to 127 := 12
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdo : out lcd_out_type;
lcdi : in lcd_in_type
);
end;
architecture rtl of apblcd is
--FSM states
type statetype is (idle,as,pwh,pwl); --idle, adress hold time, pulse width high, pulse width low
type lcd_cfg_type is record
tas : std_logic_vector(3 downto 0); --****
epw : std_logic_vector(6 downto 0); --****
end record;
type lcd_regs is record
rs : std_ulogic;
rw : std_ulogic;
e : std_ulogic;
db : std_logic_vector(7 downto 0);
cmstate : statetype;
clkcnt : std_logic_vector(6 downto 0);
cfg : lcd_cfg_type;
----new regs----
busy : std_ulogic;
prdata : std_logic_vector(7 downto 0);
db_oe : std_ulogic;
----------------
end record;
constant TAS_RESET : std_logic_vector(3 downto 0) := conv_std_logic_vector(tas, 4);
constant EPW_RESET : std_logic_vector(6 downto 0) := conv_std_logic_vector(epw, 7);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LCDCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask)); --OBS ändra till GAISLER_APBLCD
signal r, rin : lcd_regs;
begin
ctrl : process(r, rst, apbi, lcdi)
variable v : lcd_regs;
begin
v := r;
if r.clkcnt /= "0000000" then v.clkcnt := r.clkcnt - 1; end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "11" =>
if r.cmstate = idle then
v.cfg.tas := apbi.pwdata(3 downto 0); --****
v.cfg.epw := apbi.pwdata(10 downto 4); --****
end if;
when others =>
if r.cmstate = idle then
v.rs := apbi.pwdata(9);
v.rw := apbi.pwdata(8);
v.busy := '1'; --new
if(apbi.pwdata(8) = '0') then --write command => drive bus
v.db := apbi.pwdata(7 downto 0);
v.db_oe := OUTPUT; --set drive signal for write
else
v.db_oe := INPUT;
end if;
v.cmstate := as;
v.clkcnt := "000" & r.cfg.tas; --(generic value should be 2. And decreased to 2-1 =1 so that value is used here. tas will be the value
end if; --assigned here +1, hence (2-1)+1 = 2.
end case;
end if;
case r.cmstate is
when as =>
if (r.clkcnt = "0000000") then
v.cmstate := pwh;
v.e := '1';
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable high
end if;
when pwh => --when entering here tas is fulfilled and enable goes high
if (r.clkcnt = "0000000") then
v.cmstate := pwl;
v.e := '0';
if(r.rw = '1') then --sample read data
v.prdata := lcdi.db;
end if;
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable low
end if;
when pwl =>
if (r.clkcnt = "0000000") then
v.cmstate := idle;
v.busy := '0';
end if;
when others => null; --idle
end case;
if rst = '0' then
v.busy := '0'; --new
v.e := '0';
v.cmstate := idle;
v.clkcnt := (others => '0');
v.cfg.tas := TAS_RESET; --"0001"; --default 2 cyles w8 time
v.cfg.epw := EPW_RESET; --"0001100";--default 13 cycles w8 time
end if;
--update registers
rin <= v;
--drive outputs
apbo.prdata <= (others => '0');
apbo.prdata(19 downto 0) <= r.cfg.epw & r.cfg.tas & r.busy & r.prdata; --***** 11 + 1 + 8
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
lcdo.rs <= r.rs;
lcdo.rw <= r.rw;
lcdo.e <= r.e;
lcdo.db <= r.db;
lcdo.db_oe <= r.db_oe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apblcd" & tost(pindex) & ": APB LCD module rev " & tost(REVISION));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all; --tost
use grlib.amba.all;
use grlib.devices.all; -- vendor gaisler etc
--library gaisler;
--use gaisler.misc.all; --vår typ
use work.mypackage.all; --contains type
entity apblcd is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer range 0 to 1 := 0;
tas : integer range 0 to 15 := 1;
epw : integer range 0 to 127 := 12
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdo : out lcd_out_type;
lcdi : in lcd_in_type
);
end;
architecture rtl of apblcd is
--FSM states
type statetype is (idle,as,pwh,pwl); --idle, adress hold time, pulse width high, pulse width low
type lcd_cfg_type is record
tas : std_logic_vector(3 downto 0); --****
epw : std_logic_vector(6 downto 0); --****
end record;
type lcd_regs is record
rs : std_ulogic;
rw : std_ulogic;
e : std_ulogic;
db : std_logic_vector(7 downto 0);
cmstate : statetype;
clkcnt : std_logic_vector(6 downto 0);
cfg : lcd_cfg_type;
----new regs----
busy : std_ulogic;
prdata : std_logic_vector(7 downto 0);
db_oe : std_ulogic;
----------------
end record;
constant TAS_RESET : std_logic_vector(3 downto 0) := conv_std_logic_vector(tas, 4);
constant EPW_RESET : std_logic_vector(6 downto 0) := conv_std_logic_vector(epw, 7);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LCDCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask)); --OBS ändra till GAISLER_APBLCD
signal r, rin : lcd_regs;
begin
ctrl : process(r, rst, apbi, lcdi)
variable v : lcd_regs;
begin
v := r;
if r.clkcnt /= "0000000" then v.clkcnt := r.clkcnt - 1; end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "11" =>
if r.cmstate = idle then
v.cfg.tas := apbi.pwdata(3 downto 0); --****
v.cfg.epw := apbi.pwdata(10 downto 4); --****
end if;
when others =>
if r.cmstate = idle then
v.rs := apbi.pwdata(9);
v.rw := apbi.pwdata(8);
v.busy := '1'; --new
if(apbi.pwdata(8) = '0') then --write command => drive bus
v.db := apbi.pwdata(7 downto 0);
v.db_oe := OUTPUT; --set drive signal for write
else
v.db_oe := INPUT;
end if;
v.cmstate := as;
v.clkcnt := "000" & r.cfg.tas; --(generic value should be 2. And decreased to 2-1 =1 so that value is used here. tas will be the value
end if; --assigned here +1, hence (2-1)+1 = 2.
end case;
end if;
case r.cmstate is
when as =>
if (r.clkcnt = "0000000") then
v.cmstate := pwh;
v.e := '1';
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable high
end if;
when pwh => --when entering here tas is fulfilled and enable goes high
if (r.clkcnt = "0000000") then
v.cmstate := pwl;
v.e := '0';
if(r.rw = '1') then --sample read data
v.prdata := lcdi.db;
end if;
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable low
end if;
when pwl =>
if (r.clkcnt = "0000000") then
v.cmstate := idle;
v.busy := '0';
end if;
when others => null; --idle
end case;
if rst = '0' then
v.busy := '0'; --new
v.e := '0';
v.cmstate := idle;
v.clkcnt := (others => '0');
v.cfg.tas := TAS_RESET; --"0001"; --default 2 cyles w8 time
v.cfg.epw := EPW_RESET; --"0001100";--default 13 cycles w8 time
end if;
--update registers
rin <= v;
--drive outputs
apbo.prdata <= (others => '0');
apbo.prdata(19 downto 0) <= r.cfg.epw & r.cfg.tas & r.busy & r.prdata; --***** 11 + 1 + 8
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
lcdo.rs <= r.rs;
lcdo.rw <= r.rw;
lcdo.e <= r.e;
lcdo.db <= r.db;
lcdo.db_oe <= r.db_oe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apblcd" & tost(pindex) & ": APB LCD module rev " & tost(REVISION));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all; --tost
use grlib.amba.all;
use grlib.devices.all; -- vendor gaisler etc
--library gaisler;
--use gaisler.misc.all; --vår typ
use work.mypackage.all; --contains type
entity apblcd is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer range 0 to 1 := 0;
tas : integer range 0 to 15 := 1;
epw : integer range 0 to 127 := 12
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
lcdo : out lcd_out_type;
lcdi : in lcd_in_type
);
end;
architecture rtl of apblcd is
--FSM states
type statetype is (idle,as,pwh,pwl); --idle, adress hold time, pulse width high, pulse width low
type lcd_cfg_type is record
tas : std_logic_vector(3 downto 0); --****
epw : std_logic_vector(6 downto 0); --****
end record;
type lcd_regs is record
rs : std_ulogic;
rw : std_ulogic;
e : std_ulogic;
db : std_logic_vector(7 downto 0);
cmstate : statetype;
clkcnt : std_logic_vector(6 downto 0);
cfg : lcd_cfg_type;
----new regs----
busy : std_ulogic;
prdata : std_logic_vector(7 downto 0);
db_oe : std_ulogic;
----------------
end record;
constant TAS_RESET : std_logic_vector(3 downto 0) := conv_std_logic_vector(tas, 4);
constant EPW_RESET : std_logic_vector(6 downto 0) := conv_std_logic_vector(epw, 7);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LCDCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask)); --OBS ändra till GAISLER_APBLCD
signal r, rin : lcd_regs;
begin
ctrl : process(r, rst, apbi, lcdi)
variable v : lcd_regs;
begin
v := r;
if r.clkcnt /= "0000000" then v.clkcnt := r.clkcnt - 1; end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "11" =>
if r.cmstate = idle then
v.cfg.tas := apbi.pwdata(3 downto 0); --****
v.cfg.epw := apbi.pwdata(10 downto 4); --****
end if;
when others =>
if r.cmstate = idle then
v.rs := apbi.pwdata(9);
v.rw := apbi.pwdata(8);
v.busy := '1'; --new
if(apbi.pwdata(8) = '0') then --write command => drive bus
v.db := apbi.pwdata(7 downto 0);
v.db_oe := OUTPUT; --set drive signal for write
else
v.db_oe := INPUT;
end if;
v.cmstate := as;
v.clkcnt := "000" & r.cfg.tas; --(generic value should be 2. And decreased to 2-1 =1 so that value is used here. tas will be the value
end if; --assigned here +1, hence (2-1)+1 = 2.
end case;
end if;
case r.cmstate is
when as =>
if (r.clkcnt = "0000000") then
v.cmstate := pwh;
v.e := '1';
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable high
end if;
when pwh => --when entering here tas is fulfilled and enable goes high
if (r.clkcnt = "0000000") then
v.cmstate := pwl;
v.e := '0';
if(r.rw = '1') then --sample read data
v.prdata := lcdi.db;
end if;
v.clkcnt := r.cfg.epw; --spend epw -1 cycles with enable low
end if;
when pwl =>
if (r.clkcnt = "0000000") then
v.cmstate := idle;
v.busy := '0';
end if;
when others => null; --idle
end case;
if rst = '0' then
v.busy := '0'; --new
v.e := '0';
v.cmstate := idle;
v.clkcnt := (others => '0');
v.cfg.tas := TAS_RESET; --"0001"; --default 2 cyles w8 time
v.cfg.epw := EPW_RESET; --"0001100";--default 13 cycles w8 time
end if;
--update registers
rin <= v;
--drive outputs
apbo.prdata <= (others => '0');
apbo.prdata(19 downto 0) <= r.cfg.epw & r.cfg.tas & r.busy & r.prdata; --***** 11 + 1 + 8
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
lcdo.rs <= r.rs;
lcdo.rw <= r.rw;
lcdo.e <= r.e;
lcdo.db <= r.db;
lcdo.db_oe <= r.db_oe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apblcd" & tost(pindex) & ": APB LCD module rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- $Id: sys_w11a_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/fx2rlink/rlink_sp1c_fx2
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2019-05-19 1150 14.7 131013 xc3s1200e-4 3219 8981 638 5796 ok: +dz11 66%
-- 2019-04-27 1140 14.7 131013 xc3s1200e-4 3087 ???? 588 5515 ok: +*buf 63%
-- 2019-03-02 1116 14.7 131013 xc3s1200e-4 3024 8246 526 5322 ok: +ibtst 61%
-- 2019-01-27 1108 14.7 131013 xc3s1200e-4 2976 8101 510 5201 ok: -iist
-- 2018-10-13 1055 14.7 131013 xc3s1200e-4 3097 8484 510 5471 ok: +dmpcnt
-- 2018-09-15 1045 14.7 131013 xc3s1200e-4 2860 7983 446 5098 ok: +KW11P
-- 2017-04-30 888 14.7 131013 xc3s1200e-4 2806 7865 446 5043 ok: +fx2dbg
-- 2017-03-04 858 14.7 131013 xc3s1200e-4 2740 7713 446 4912 ok: +DEUNA
-- 2017-01-29 846 14.7 131013 xc3s1200e-4 2696 7620 446 4857 ok: +int24
-- 2015-06-21 692 14.7 131013 xc3s1200e-4 2312 6716 414 4192 ok: rhrp fixes
-- 2015-06-04 686 14.7 131013 xc3s1200e-4 2311 6725 414 4198 ok: +TM11
-- 2015-05-14 680 14.7 131013 xc3s1200e-4 2232 6547 414 4083 ok: +RHRP
-- 2015-02-21 649 14.7 131013 xc3s1200e-4 1903 5512 382 3483 ok: +RL11
-- 2014-12-22 619 14.7 131013 xc3s1200e-4 1828 5131 366 3263 ok: +rbmon
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 1714 4896 366 3125 ok: -RL11,rlv4
-- 2014-06-08 561 14.7 131013 xc3s1200e-4 1626 4821 360 3052 ok: +RL11
-- 2014-06-01 558 14.7 131013 xc3s1200e-4 1561 4597 334 2901 ok:
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-11 666 1.7.2 rearrange XON handling
-- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-15 647 1.7 drop bram and minisys options
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
-- 2014-08-28 588 1.6 use new rlink v4 iface generics and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
-- 2011-11-19 427 1.2.4 now numeric_std clean
-- 2011-11-17 426 1.2.3 use dcm_sfs now
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
-- BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
-- use s3_humanio_rri
-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
-- w11a + rlink + serport + cuff
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:6): select LED display mode
-- 0x w11 sys70 LED display (further controlled by SWI(3))
-- 10 FX2 debug: fx2 fifo states
-- 11 FX2 debug: fx2 fsm states
-- (5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LEDs if SWI(7) = 0 and SWI(3) = 1
-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
--
-- LEDs if SWI(7) = 0 and SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- LEDs if SWI(7) = 1
-- (7) fifo_ep4
-- (6) fifo_ep6
-- (5) fsm_rx
-- (4) fsm_tx
-- LEDs if SWI(7) = 1 and SWI(6) = 0
-- (3) flag_ep4_empty
-- (2) flag_ep4_almost
-- (1) flag_ep6_full
-- (0) flag_ep6_almost
-- LEDs if SWI(7) = 1 and SWI(6) = 1
-- (3) fsm_idle
-- (2) fsm_prep
-- (1) fsm_disp
-- (0) fsm_pipe
--
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back pressure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back pressure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back pressure)
-- (2): RLB_TXBUSY (shows tx back pressure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n2;
architecture syn of sys_w11a_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal LED70 : slv8 := (others=>'0');
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"02"; -- nexys2
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs -- clock generator -------------------
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce -- usec/msec clock divider -----------
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => GRESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
if SWI(7) = '0' then
iled := LED70;
else
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fsm_rx;
iled(4) := FX2_MONI.fsm_tx;
if SWI(6) = '0' then
iled(3) := FX2_MONI.flag_ep4_empty;
iled(2) := FX2_MONI.flag_ep4_almost;
iled(1) := FX2_MONI.flag_ep6_full;
iled(0) := FX2_MONI.flag_ep6_almost;
else
iled(3) := FX2_MONI.fsm_idle;
iled(2) := FX2_MONI.fsm_prep;
iled(1) := FX2_MONI.fsm_disp;
iled(0) := FX2_MONI.fsm_pipe;
end if;
end if;
LED <= iled;
end process proc_fx2leds;
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity timing is
generic (
F : natural;
min_baud: natural
);
port (
clk : in std_logic;
rst : in std_logic;
divisor : in std_logic_vector;
ClrDiv : in std_logic;
Top16 : buffer std_logic;
TopTx : out std_logic;
TopRx : out std_logic
);
end timing;
architecture timing_arq of timing is
-- signal baud_value : natural;
constant max_div : natural := ((F*1000)/(16*min_baud));
subtype div16_type is natural range 0 to max_div-1;
signal Div16 : div16_type;
signal ClkDiv : integer;
signal RxDiv : integer;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
--
-- process (clk) -- baud_value setting.
-- begin
-- if rising_edge(clk) then
-- case Baud is
-- when "000" => baud_value <= 115200;
-- when "001" => baud_value <= 57600;
-- when "010" => baud_value <= 38400;
-- when "011" => baud_value <= 19200;
-- when "100" => baud_value <= 9600;
-- when "101" => baud_value <= 4800;
-- when "110" => baud_value <= 2400;
-- when "111" => baud_value <= 1200;
-- when others => baud_value <= 1200; -- n.u.
-- end case;
-- end if;
-- end process;
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (rst, clk)
begin
if rst = '1' then
Top16 <= '0';
Div16 <= 0;
elsif rising_edge(clk) then
Top16 <= '0';
if Div16 = conv_integer(divisor) then
Div16 <= 0;
Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (rst, clk)
begin
if rst = '1' then
TopTx <= '0';
ClkDiv <= 0; --(others=>'0');
elsif rising_edge(clk) then
TopTx <= '0';
if Top16 = '1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (rst, clk)
begin
if rst = '1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(clk) then
TopRx <= '0';
if ClrDiv = '1' then
RxDiv <= 0;
elsif Top16 = '1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
end;
|
architecture rtl of fifo is begin
process is begin
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= ( item1 => 12,
item2 => f(a, b ,c),
item3 => 36
);
s_foo <= (a and
b and
c);
end process;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libcache
-- File: libcache.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Cache-related types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libcache is
constant TAG_HIGH : integer := 31;
constant CTAG_LRRPOS : integer := 9;
constant CTAG_LOCKPOS : integer := 8;
constant MAXSETS : integer := 4;
-- 3-way set permutations
-- s012 => set 0 - least recently used
-- set 2 - most recently used
constant s012 : std_logic_vector(2 downto 0) := "000";
constant s021 : std_logic_vector(2 downto 0) := "001";
constant s102 : std_logic_vector(2 downto 0) := "010";
constant s120 : std_logic_vector(2 downto 0) := "011";
constant s201 : std_logic_vector(2 downto 0) := "100";
constant s210 : std_logic_vector(2 downto 0) := "101";
-- 4-way set permutations
-- s0123 => set 0 - least recently used
-- set 3 - most recently used
-- bits assigned so bits 4:3 is LRU and 1:0 is MRU
-- middle bit is 0 for 01 02 03 12 13 23, 1 for 10 20 30 21 31 32
constant s0123 : std_logic_vector(4 downto 0) := "00011";
constant s0132 : std_logic_vector(4 downto 0) := "00010";
constant s0213 : std_logic_vector(4 downto 0) := "00111";
constant s0231 : std_logic_vector(4 downto 0) := "00001";
constant s0312 : std_logic_vector(4 downto 0) := "00110";
constant s0321 : std_logic_vector(4 downto 0) := "00101";
constant s1023 : std_logic_vector(4 downto 0) := "01011";
constant s1032 : std_logic_vector(4 downto 0) := "01010";
constant s1203 : std_logic_vector(4 downto 0) := "01111";
constant s1230 : std_logic_vector(4 downto 0) := "01000";
constant s1302 : std_logic_vector(4 downto 0) := "01110";
constant s1320 : std_logic_vector(4 downto 0) := "01100";
constant s2013 : std_logic_vector(4 downto 0) := "10011";
constant s2031 : std_logic_vector(4 downto 0) := "10001";
constant s2103 : std_logic_vector(4 downto 0) := "10111";
constant s2130 : std_logic_vector(4 downto 0) := "10000";
constant s2301 : std_logic_vector(4 downto 0) := "10101";
constant s2310 : std_logic_vector(4 downto 0) := "10100";
constant s3012 : std_logic_vector(4 downto 0) := "11010";
constant s3021 : std_logic_vector(4 downto 0) := "11001";
constant s3102 : std_logic_vector(4 downto 0) := "11110";
constant s3120 : std_logic_vector(4 downto 0) := "11000";
constant s3201 : std_logic_vector(4 downto 0) := "11101";
constant s3210 : std_logic_vector(4 downto 0) := "11100";
type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0);
type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type;
constant lru_3set_table : lru_3set_table_type :=
( (s120, s021, s012), -- s012
(s210, s021, s012), -- s021
(s120, s021, s102), -- s102
(s120, s201, s102), -- s120
(s210, s201, s012), -- s201
(s210, s201, s102), -- s210
(s210, s201, s102), -- dummy
(s210, s201, s102) -- dummy
);
type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type;
constant lru_4set_table : lru_4set_table_type :=
( (s2310, s0231, s0312, s0213), -- "00000" (s0231/reset)
(s2310, s0231, s0312, s0213), -- "00001" s0231
(s1320, s0321, s0132, s0123), -- "00010" s0132
(s1230, s0231, s0132, s0123), -- "00011" s0123
(s3210, s0321, s0312, s0213), -- "00100" (s0321)
(s3210, s0321, s0312, s0213), -- "00101" s0321
(s3120, s0321, s0312, s0123), -- "00110" s0312
(s2130, s0231, s0132, s0213), -- "00111" s0213
(s1230, s2301, s1302, s1203), -- "01000" s1230
(s1230, s2301, s1302, s1203), -- "01001" (s1230)
(s1320, s0321, s1032, s1023), -- "01010" s1032
(s1230, s0231, s1032, s1023), -- "01011" s1023
(s1320, s3201, s1302, s1203), -- "01100" s1320
(s1320, s3201, s1302, s1203), -- "01101" (s1320)
(s1320, s3021, s1302, s1023), -- "01110" s1302
(s1230, s2031, s1032, s1203), -- "01111" s1203
(s2130, s2301, s1302, s2103), -- "10000" s2130
(s2310, s2031, s0312, s2013), -- "10001" s2031
(s2130, s2031, s0132, s2013), -- "10010" (s2013)
(s2130, s2031, s0132, s2013), -- "10011" s2013
(s2310, s2301, s3102, s2103), -- "10100" s2310
(s2310, s2301, s3012, s2013), -- "10101" s2301
(s2130, s2031, s1032, s2103), -- "10110" (s2103)
(s2130, s2031, s1032, s2103), -- "10111" s2103
(s3120, s3201, s3102, s1203), -- "11000" s3120
(s3210, s3021, s3012, s0213), -- "11001" s3021
(s3120, s3021, s3012, s0123), -- "11010" s3012
(s3120, s3021, s3012, s0123), -- "11011" (s3012)
(s3210, s3201, s3102, s2103), -- "11100" s3210
(s3210, s3201, s3012, s2013), -- "11101" s3201
(s3120, s3021, s3102, s1023), -- "11110" s3102
(s3120, s3021, s3102, s1023) -- "11111" (s3102)
);
type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2;
type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type;
constant lru3_repl_table : lru3_repl_table_type :=
( (0, 1, 2), -- s012
(0, 2, 2), -- s021
(1, 1, 2), -- s102
(1, 1, 2), -- s120
(2, 2, 2), -- s201
(2, 2, 2), -- s210
(2, 2, 2), -- dummy
(2, 2, 2) -- dummy
);
type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3;
type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type;
constant lru4_repl_table : lru4_repl_table_type :=
( (0, 2, 2, 3), -- (s0231/reset)
(0, 2, 2, 3), -- s0231
(0, 1, 3, 3), -- s0132
(0, 1, 2, 3), -- s0123
(0, 3, 3, 3), -- (s0321)
(0, 3, 3, 3), -- s0321
(0, 3, 3, 3), -- s0312
(0, 2, 2, 3), -- s0213
(1, 1, 2, 3), -- s1230
(1, 1, 2, 3), -- (s1230)
(1, 1, 3, 3), -- s1032
(1, 1, 2, 3), -- s1023
(1, 1, 3, 3), -- s1320
(1, 1, 3, 3), -- (s1320)
(1, 1, 3, 3), -- s1302
(1, 1, 2, 3), -- s1203
(2, 2, 2, 3), -- s2130
(2, 2, 2, 3), -- s2031
(2, 2, 2, 3), -- (s2013)
(2, 2, 2, 3), -- s2013
(2, 2, 2, 3), -- s2310
(2, 2, 2, 3), -- s2301
(2, 2, 2, 3), -- (s2103)
(2, 2, 2, 3), -- s2103
(3, 3, 3, 3), -- s3120
(3, 3, 3, 3), -- s3021
(3, 3, 3, 3), -- s3012
(3, 3, 3, 3), -- (s3012)
(3, 3, 3, 3), -- s3210
(3, 3, 3, 3), -- s3201
(3, 3, 3, 3), -- s3102
(3, 3, 3, 3) -- (s3102)
);
type ildram_in_type is record
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
end record;
subtype ctxword is std_logic_vector(M_CTX_SZ-1 downto 0);
type ctxdatatype is array (0 to 3) of ctxword;
type icram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype;
twrite : std_logic_vector(0 to 3);
tenable : std_ulogic;
flush : std_ulogic;
data : std_logic_vector(31 downto 0);
denable : std_ulogic;
dwrite : std_logic_vector(0 to 3);
ldramin : ildram_in_type;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
end record;
type icram_out_type is record
tag : cdatatype;
data : cdatatype;
ctx : ctxdatatype;
end record;
type ldram_in_type is record
address : std_logic_vector(23 downto 2);
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
end record;
type dcram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype; --std_logic_vector(31 downto 0);
ptag : cdatatype; --std_logic_vector(31 downto 0);
twrite : std_logic_vector(0 to 3);
tpwrite : std_logic_vector(0 to 3);
tenable : std_logic_vector(0 to 3);
flush : std_ulogic;
data : cdatatype;
denable : std_logic_vector(0 to 3);
dwrite : std_logic_vector(0 to 3);
senable : std_logic_vector(0 to 3);
swrite : std_logic_vector(0 to 3);
saddress : std_logic_vector(19 downto 0);
faddress : std_logic_vector(19 downto 0);
ldramin : ldram_in_type;
ctx : ctxdatatype;
tdiag : std_logic_vector(3 downto 0);
ddiag : std_logic_vector(3 downto 0);
sdiag : std_logic_vector(3 downto 0);
end record;
type dcram_out_type is record
tag : cdatatype;
data : cdatatype;
stag : cdatatype;
ctx : ctxdatatype;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramo : icram_out_type;
dcramo : dcram_out_type;
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_ulogic; -- burst request
req : std_ulogic; -- memory cycle request
su : std_ulogic; -- supervisor address space
flush : std_ulogic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic; --
retry : std_ulogic; --
mexc : std_ulogic; -- memory exception
cache : std_ulogic; -- cacheable data
scanen : std_ulogic;
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_ulogic;
read : std_ulogic;
req : std_ulogic;
lock : std_ulogic;
cache : std_ulogic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic; -- memory exception
werr : std_ulogic; -- memory write error
cache : std_ulogic; -- cacheable data
ba : std_ulogic; -- bus active (used for snooping)
bg : std_ulogic; -- bus grant (used for snooping)
scanen : std_ulogic;
testen : std_ulogic;
end record;
constant dir : integer := 3;
constant rnd : integer := 2;
constant lrr : integer := 1;
constant lru : integer := 0;
type cache_replalgbits_type is array (0 to 3) of integer;
constant creplalg_tbl : cache_replalgbits_type := (0, 1, 0, 0);
type lru_bits_type is array(1 to 4) of integer;
constant lru_table : lru_bits_type := (1,1,3,5);
component cachemem
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end component;
-- mmu versions
component mmu_acache
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end component;
component mmu_icache
generic (
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_logic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end component;
component mmu_dcache
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end component;
component mmu_cache
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component clk2xqual
port (
rst : in std_ulogic;
clk : in std_ulogic;
clk2 : in std_ulogic;
clken : out std_ulogic);
end component;
component clk2xsync
generic (
hindex : integer := 0;
clk2x : integer := 1);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbi2 : out ahb_mst_in_type;
ahbo : in ahb_mst_out_type;
ahbo2 : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbsi2 : out ahb_slv_in_type;
mcii : in memory_ic_in_type;
mcdi : in memory_dc_in_type;
mcdo : in memory_dc_out_type;
mmreq : in std_ulogic;
mmgrant : in std_ulogic;
hclken : in std_ulogic
);
end component;
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer) return std_logic_vector;
end;
package body libcache is
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
cfg(31 downto 31) := conv_std_logic_vector(lock, 1);
if sets /= 1 then
cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3);
end if;
if snoop /= 0 then cfg(27) := '1'; end if;
cfg(26 downto 24) := conv_std_logic_vector(sets-1, 3);
cfg(23 downto 20) := conv_std_logic_vector(log2(setsize), 4);
cfg(19 downto 19) := conv_std_logic_vector(lram, 1);
cfg(18 downto 16) := conv_std_logic_vector(log2(linesize), 3);
cfg(15 downto 12) := conv_std_logic_vector(log2(lramsize), 4);
cfg(11 downto 4) := conv_std_logic_vector(lramstart, 8);
cfg(3 downto 3) := conv_std_logic_vector(mmuen, 1);
return(cfg);
end;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity big_register is
generic
(
C_REGISTER_LENGTH : integer := 10000
);
port
(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic; -- clock enable
xor_sig : out std_logic -- xor of all register bits
);
end entity big_register;
architecture behavioral of big_register is
signal vector : std_logic_vector(0 to C_REGISTER_LENGTH-1);
begin
-- for active heater: invert vector and write number of 1s vector into output signal
change_vector : process (rst, clk) is
variable bit_temp : std_logic;
begin
if rst = '1' then
vector(1 to C_REGISTER_LENGTH-1) <= (others=>'0');
vector(0) <= '1';
xor_sig <= '0';
elsif rising_edge(clk) then
if ce = '1' then
vector <= not vector;
bit_temp := '0';
for i in 0 to C_REGISTER_LENGTH-1 loop
bit_temp := bit_temp xor vector(i);
end loop;
xor_sig <= bit_temp;
end if;
end if;
end process;
end behavioral;
|
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc949.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00949ent IS
END c06s01b00x00p10n01i00949ent;
ARCHITECTURE c06s01b00x00p10n01i00949arch OF c06s01b00x00p10n01i00949ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of BOOLEAN;
type R3 is record
RE3: A1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE3=>(1=>TRUE,2=>TRUE)).RE3(1);
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00949 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00949arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc949.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00949ent IS
END c06s01b00x00p10n01i00949ent;
ARCHITECTURE c06s01b00x00p10n01i00949arch OF c06s01b00x00p10n01i00949ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of BOOLEAN;
type R3 is record
RE3: A1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE3=>(1=>TRUE,2=>TRUE)).RE3(1);
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00949 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00949arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc949.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00949ent IS
END c06s01b00x00p10n01i00949ent;
ARCHITECTURE c06s01b00x00p10n01i00949arch OF c06s01b00x00p10n01i00949ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of BOOLEAN;
type R3 is record
RE3: A1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE3=>(1=>TRUE,2=>TRUE)).RE3(1);
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00949 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00949arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_1_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_cpu_1_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_cpu_1_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
entity test is
package a is new b generic map(c => foo'subtype range bar'baz);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grdmac_1p
-- File: grdmac_1p.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: AMBA DMA controller with single master interface
-- Supports scatter gather on unaligned data through internal
-- re-alignment buffer and conditional descriptors
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.grdmac_pkg.all;
use grlib.devices.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity grdmac_1p is
generic (
hmindex : integer := 0; -- AHB master index
hirq : integer := 0;
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FFF#;
ndmach : integer range 1 to 16 := 1; -- number of DMA channels --TODO: implement ndmach = 0
bufsize : integer range 4*AHBDW/8 to 64*1024:= 256; -- number of bytes in buffer (must be a multiple of 4*WORD_SIZE)
burstbound : integer range 4 to 1024 := 512;
memtech : integer := 0;
testen : integer := 0;
ft : integer range 0 to 2 := 0;
wbmask : integer := 0;
busw : integer := 64
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irq_trig : in std_logic_vector(63 downto 0)
);
end;
architecture rtl of grdmac_1p is
begin
dma: grdmac
generic map(
hmindex => hmindex,
hirq => hirq,
pindex => pindex,
paddr => paddr,
pmask => pmask,
en_ahbm1 => 0,
hmindex1 => 0,
ndmach => ndmach,
bufsize => bufsize,
burstbound => burstbound,
memtech => memtech,
testen => testen,
ft => ft,
wbmask => wbmask,
busw => busw
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi1 => ahbm_in_none,
ahbmo1 => open,
apbi => apbi,
apbo => apbo,
irq_trig => irq_trig
);
end architecture;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_out_8b_sync is
generic (
FIFO_DEPTH : natural range 8 to 64 := 16;
BUS_WIDTH : natural range 16 to 64 := 32
);
port (
rst : in std_logic;
clk : in std_logic;
irq : out std_logic;
-- Avalon-MM 32-bits slave
addr : in std_logic_vector(1 downto 0);
byte_en : in std_logic_vector(3 downto 0) := (others => '1');
in_data : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(31 downto 0);
wait_req : out std_logic;
-- output stream
st_data : out std_logic_vector(7 downto 0);
st_valid : out std_logic;
st_ready : in std_logic
);
end entity;
architecture RTL of fifo_out_8b_sync is
function log2ceil (arg: natural) return natural is
begin
if arg < 2 then
return 1;
else
return log2ceil(arg / 2) + 1;
end if;
end function;
constant FIFO_ADDR_WIDTH : natural := log2ceil(FIFO_DEPTH - 1);
constant REG_DATA : std_logic_vector(1 downto 0) := "00";
constant REG_CTRL_STAT : std_logic_vector(1 downto 0) := "10";
signal read_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal write_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal not_empty : std_logic;
signal data_wren : std_logic;
signal ctrl_wren : std_logic;
signal write_phase : unsigned(1 downto 0);
signal end_phase : std_logic_vector(2 downto 0);
signal write_not_compl : std_logic;
signal fifo_reset : std_logic;
signal imask : std_logic;
signal ipend : std_logic;
signal fill : unsigned(FIFO_ADDR_WIDTH downto 0);
signal threshold : unsigned(FIFO_ADDR_WIDTH - 1 downto 0);
signal st_valid_i : std_logic;
type mem_t is array(0 to FIFO_DEPTH - 1) of std_logic_vector(7 downto 0);
signal fifo_ram : mem_t;
signal fifo_ram_we : std_logic;
signal fifo_ram_re : std_logic;
signal fifo_ram_d : std_logic_vector(7 downto 0);
signal fifo_ram_q : std_logic_vector(7 downto 0);
attribute ramstyle : string;
attribute ramstyle of fifo_ram : signal is "logic";
begin
-- RAM block logic
process (clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
fifo_ram(to_integer(write_ptr(FIFO_ADDR_WIDTH - 1 downto 0))) <= fifo_ram_d;
end if;
if fifo_ram_re = '1' then
fifo_ram_q <= fifo_ram(to_integer(read_ptr(FIFO_ADDR_WIDTH - 1 downto 0)));
end if;
end if;
end process;
-- FIFO pointers logic
process (rst, clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
write_ptr <= write_ptr + 1;
end if;
if fifo_ram_re = '1' then
read_ptr <= read_ptr + 1;
end if;
st_valid_i <= not_empty or (st_valid_i and not st_ready);
if fifo_reset = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
st_valid_i <= '0';
end if;
end if;
if rst = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
st_valid_i <= '0';
end if;
end process;
not_empty <= '0' when read_ptr = write_ptr else '1';
fill <= write_ptr - read_ptr;
-- bus interface logic
ipend <= '0' when fill > unsigned('0' & threshold) else '1';
with addr select
out_data <= (BUS_WIDTH - 1 downto 16 => '0') & imask & (14 downto FIFO_ADDR_WIDTH + 8 => '0') & std_logic_vector(threshold) & ipend & (6 downto FIFO_ADDR_WIDTH + 1 => '0') & std_logic_vector(fill) when REG_CTRL_STAT,
(others => '0') when others;
data_wren <= wr_en and not fill(FIFO_ADDR_WIDTH) when addr = REG_DATA else '0';
ctrl_wren <= (byte_en(1) and wr_en) when addr = REG_CTRL_STAT else '0';
fifo_reset <= ctrl_wren and in_data(14);
with byte_en select
end_phase <= data_wren & "00" when "0001",
data_wren & "01" when "0011",
data_wren & "11" when "1111",
"000" when others;
write_not_compl <= end_phase(2) when write_phase /= unsigned(end_phase(1 downto 0)) else '0';
process (rst, clk)
begin
if rising_edge(clk) then
if ctrl_wren = '1' then
imask <= in_data(15);
threshold <= unsigned(in_data(FIFO_ADDR_WIDTH + 7 downto 8));
end if;
if write_not_compl = '0' then
write_phase <= (others => '0');
else
write_phase <= write_phase + 1;
end if;
end if;
if rst = '1' then
imask <= '0';
threshold <= (others => '0');
write_phase <= (others => '0');
end if;
end process;
wait_req <= write_not_compl;
fifo_ram_we <= end_phase(2);
fifo_ram_re <= not_empty and (st_ready or not st_valid_i);
with write_phase select
fifo_ram_d <= in_data(31 downto 24) when "11",
in_data(23 downto 16) when "10",
in_data(15 downto 8) when "01",
in_data(7 downto 0) when others;
st_data <= fifo_ram_q;
st_valid <= st_valid_i;
irq <= ipend and imask;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1235.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01235ent IS
END c08s02b00x00p03n01i01235ent;
ARCHITECTURE c08s02b00x00p03n01i01235arch OF c08s02b00x00p03n01i01235ent IS
BEGIN
TESTING: PROCESS
BEGIN
erlab : assert FALSE;
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01235 - Labels are not permitted on sequential assertion statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01235arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1235.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01235ent IS
END c08s02b00x00p03n01i01235ent;
ARCHITECTURE c08s02b00x00p03n01i01235arch OF c08s02b00x00p03n01i01235ent IS
BEGIN
TESTING: PROCESS
BEGIN
erlab : assert FALSE;
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01235 - Labels are not permitted on sequential assertion statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01235arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1235.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01235ent IS
END c08s02b00x00p03n01i01235ent;
ARCHITECTURE c08s02b00x00p03n01i01235arch OF c08s02b00x00p03n01i01235ent IS
BEGIN
TESTING: PROCESS
BEGIN
erlab : assert FALSE;
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01235 - Labels are not permitted on sequential assertion statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01235arch;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe_v3_Slave
-- Module Name: Syndrome_Calculator_N_Pipe_v3_Slave
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is circuit version with a variable number of computation units, pipeline and
-- a variable number of pipelines. This is the slave pipeline circuit controlled by the
-- master circuit, where it is repeated on the master circuit.
--
-- The circuits parameters
--
-- initial_address :
--
-- The initial address for this circuit to begin computing the syndrome.
-- This is necessary so different syndrome calculator, do not compute the same ciphertext.
--
-- increment_address :
--
-- How much is incremented in the initial_addres, in each step.
-- This is necessary so different syndrome calculator, do not compute the same ciphertext.
--
-- syndrome_calculator_size :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be bigger than 1.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3_slave Rev 1.0
-- controller_syndrome_calculator_2_pipe_v3_master Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
-- and_reduce Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n_pipe_v3_slave is
Generic(
initial_address : integer;
increment_address : integer;
syndrome_calculator_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0)
);
end syndrome_calculator_n_pipe_v3_slave;
architecture Behavioral of syndrome_calculator_n_pipe_v3_slave is
component controller_syndrome_calculator_2_pipe_v3_slave
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal square_h : STD_LOGIC;
signal reg_load_L_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_L_ce : STD_LOGIC;
signal reg_load_L_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_ce : STD_LOGIC;
signal reg_load_h_rst : STD_LOGIC;
constant reg_load_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_ce : STD_LOGIC;
signal reg_new_value_syndrome_rst : STD_LOGIC;
constant reg_new_value_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_address_codeword_ce : STD_LOGIC;
signal ctr_load_address_codeword_rst : STD_LOGIC;
constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(initial_address, size_codeword));
signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal reg_load_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_load_limit_codeword_ce : STD_LOGIC;
signal reg_load_limit_codeword_rst : STD_LOGIC;
constant reg_load_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_load_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_ce : STD_LOGIC;
signal reg_calc_limit_codeword_rst : STD_LOGIC;
signal reg_calc_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_calc_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((syndrome_calculator_size) downto (syndrome_calculator_size)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst: STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_2_pipe_v3_slave
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => reg_calc_limit_codeword_q(0),
reg_codeword_q => reg_codeword_q,
start_calculation => start_calculation,
last_syndrome => last_syndrome,
ready_calculation => ready_calculation,
finished_calculation => finished_calculation,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
square_h => square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_load_L_ce => reg_load_L_ce,
reg_load_h_ce => reg_load_h_ce,
reg_load_h_rst => reg_load_h_rst,
reg_new_value_syndrome_ce => reg_new_value_syndrome_ce,
reg_new_value_syndrome_rst => reg_new_value_syndrome_rst,
reg_codeword_ce => reg_codeword_ce,
ctr_load_address_codeword_ce => ctr_load_address_codeword_ce,
ctr_load_address_codeword_rst => ctr_load_address_codeword_rst,
reg_load_limit_codeword_ce => reg_load_limit_codeword_ce,
reg_load_limit_codeword_rst => reg_load_limit_codeword_rst,
reg_calc_limit_codeword_ce => reg_calc_limit_codeword_ce,
reg_calc_limit_codeword_rst => reg_calc_limit_codeword_rst
);
calculator_units : for I in 0 to (syndrome_calculator_size - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_load_L_q;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
reg_load_h_q;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or int_sel_reg_h);
reg_h_rst(I) <= int_reg_h_rst and control_units_q(I);
sel_reg_h(I) <= int_sel_reg_h;
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => syndrome_calculator_size+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
reg_load_L : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_L_d,
clk => clk,
ce => reg_load_L_ce,
q => reg_load_L_q
);
reg_load_h : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_h_d,
clk => clk,
ce => reg_load_h_ce,
rst => reg_load_h_rst,
rst_value => reg_load_h_rst_value,
q => reg_load_h_q
);
reg_new_value_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_syndrome_d,
clk => clk,
ce => reg_new_value_syndrome_ce,
rst => reg_new_value_syndrome_rst,
rst_value => reg_new_value_syndrome_rst_value,
q => reg_new_value_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
ctr_load_address_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => increment_address
)
Port Map(
clk => clk,
ce => ctr_load_address_codeword_ce,
rst => ctr_load_address_codeword_rst,
rst_value => ctr_load_address_codeword_rst_value,
q => ctr_load_address_codeword_q
);
reg_load_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_load_limit_codeword_d,
clk => clk,
ce => reg_load_limit_codeword_ce,
rst => reg_load_limit_codeword_rst,
rst_value => reg_load_limit_codeword_rst_value,
q => reg_load_limit_codeword_q
);
reg_calc_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_calc_limit_codeword_d,
clk => clk,
ce => reg_calc_limit_codeword_ce,
rst => reg_calc_limit_codeword_rst,
rst_value => reg_calc_limit_codeword_rst_value,
q => reg_calc_limit_codeword_q
);
calculator_size_1 : if (syndrome_calculator_size = 1) generate
reg_new_value_syndrome_d <= reg_h_q;
end generate;
calculator_size_more_than_1 : if (syndrome_calculator_size > 1) generate
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => syndrome_calculator_size
)
Port Map(
a => adder_a,
o => adder_o
);
adder_a <= reg_h_q;
reg_new_value_syndrome_d <= adder_o;
end generate;
reg_load_limit_codeword_d(0) <= limit_ctr_codeword_q;
reg_calc_limit_codeword_d <= reg_load_limit_codeword_q;
reg_load_L_d <= value_L;
reg_load_h_d <= value_h;
reg_codeword_d <= value_codeword;
new_value_syndrome <= reg_new_value_syndrome_q;
address_h <= ctr_load_address_codeword_q;
address_L <= ctr_load_address_codeword_q;
address_codeword <= ctr_load_address_codeword_q;
almost_units_ready <= control_units_q(syndrome_calculator_size - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (unsigned(ctr_load_address_codeword_q) >= (to_unsigned(length_codeword - increment_address, ctr_load_address_codeword_q'length))) else '0';
end Behavioral; |
use std.textio.all;
entity ISSUE351 is
end ISSUE351;
architecture RTL of ISSUE351 is
type WORD_TYPE is record
KEY : integer;
VALUE : integer;
end record;
constant WORD_NULL : WORD_TYPE := (KEY => 0, VALUE => 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
procedure dump_words(WORDS: in WORD_VECTOR)
is
variable text_line : LINE;
begin
for i in WORDS'range loop
WRITE(text_line, string'(" | "));
WRITE(text_line, i, LEFT, 5);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).KEY , LEFT, 10);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).VALUE, LEFT, 10);
WRITELINE(OUTPUT, text_line);
end loop;
end procedure;
begin
process
variable curr_queue : WORD_VECTOR(0 to 3);
variable text_line : LINE;
begin
for i in curr_queue'range loop
curr_queue(i).KEY := i;
curr_queue(i).VALUE := i;
end loop;
for i in curr_queue'range loop
WRITE(text_line, i);
WRITE(text_line, string'(" to "));
WRITE(text_line, curr_queue'length-1);
WRITELINE(OUTPUT, text_line);
dump_words(curr_queue(i to curr_queue'length-1)); -- Bug?
end loop;
wait;
end process;
end RTL;
|
use std.textio.all;
entity ISSUE351 is
end ISSUE351;
architecture RTL of ISSUE351 is
type WORD_TYPE is record
KEY : integer;
VALUE : integer;
end record;
constant WORD_NULL : WORD_TYPE := (KEY => 0, VALUE => 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
procedure dump_words(WORDS: in WORD_VECTOR)
is
variable text_line : LINE;
begin
for i in WORDS'range loop
WRITE(text_line, string'(" | "));
WRITE(text_line, i, LEFT, 5);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).KEY , LEFT, 10);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).VALUE, LEFT, 10);
WRITELINE(OUTPUT, text_line);
end loop;
end procedure;
begin
process
variable curr_queue : WORD_VECTOR(0 to 3);
variable text_line : LINE;
begin
for i in curr_queue'range loop
curr_queue(i).KEY := i;
curr_queue(i).VALUE := i;
end loop;
for i in curr_queue'range loop
WRITE(text_line, i);
WRITE(text_line, string'(" to "));
WRITE(text_line, curr_queue'length-1);
WRITELINE(OUTPUT, text_line);
dump_words(curr_queue(i to curr_queue'length-1)); -- Bug?
end loop;
wait;
end process;
end RTL;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE dacad5668_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 16;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END COMPONENT dacad5668;
END PACKAGE dacad5668_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.dacad5668_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END ENTITY dacad5668;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF dacad5668 IS
CONSTANT SS_HOLD_CYCLES : INTEGER := 40; -- minimum 15ns see datasheet
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := 4;
CONSTANT TRANSFER_WIDTH : INTEGER := 32;
--COMMAND CODES
CONSTANT WRITE_AND_UPDATE_CHANNEL_N : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT SETUP_INTERNAL_REF : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
TYPE t_states IS (idle,wait_for_transfer_to_finish,wait_for_next_transfer,set_internal_reference,keep_clear_low,wait_after_reset);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
cycle_count : UNSIGNED(6 DOWNTO 0);
LDAC_n : STD_LOGIC;
CLR_n : STD_LOGIC;
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => TRANSFER_WIDTH, -- 32 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '0', -- sckl inactive high
CPHA => '1', -- data is captured on the tailing edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_Ss(0) => oslv_Ss,
osl_mosi => osl_mosi,
isl_miso => '0'
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data,it_set_values)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
vi.LDAC_n := '0';
vi.CLR_n := '1';
CASE vi.state IS
WHEN keep_clear_low =>
vi.CLR_n := '0';
IF vi.cycle_count = 10 THEN
vi.state := wait_after_reset;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN wait_after_reset =>
IF vi.cycle_count = 100 THEN
vi.state := set_internal_reference;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN set_internal_reference =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := SETUP_INTERNAL_REF;
vi.tx_data(0) := INTERNAL_REFERENCE;
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := WRITE_AND_UPDATE_CHANNEL_N;
vi.tx_data(TRANSFER_WIDTH -9 DOWNTO TRANSFER_WIDTH-12) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_data(TRANSFER_WIDTH -13 DOWNTO TRANSFER_WIDTH-28) := it_set_values(to_integer(vi.channel_count));
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN wait_for_transfer_to_finish =>
IF sl_rx_done = '1' THEN
vi.state := wait_for_next_transfer;
vi.cycle_count := (OTHERS => '0');
END IF;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 100 THEN
vi.cycle_count := to_unsigned(0,7);
IF vi.channel_count = NUMBER_OF_CHANNELS -1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := keep_clear_low;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
vi.cycle_count := (OTHERS => '0');
vi.CLR_n := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_LDAC_n <= ri.LDAC_n;
osl_CLR_N <= ri.CLR_n;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE dacad5668_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 16;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END COMPONENT dacad5668;
END PACKAGE dacad5668_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.dacad5668_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END ENTITY dacad5668;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF dacad5668 IS
CONSTANT SS_HOLD_CYCLES : INTEGER := 40; -- minimum 15ns see datasheet
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := 4;
CONSTANT TRANSFER_WIDTH : INTEGER := 32;
--COMMAND CODES
CONSTANT WRITE_AND_UPDATE_CHANNEL_N : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT SETUP_INTERNAL_REF : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
TYPE t_states IS (idle,wait_for_transfer_to_finish,wait_for_next_transfer,set_internal_reference,keep_clear_low,wait_after_reset);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
cycle_count : UNSIGNED(6 DOWNTO 0);
LDAC_n : STD_LOGIC;
CLR_n : STD_LOGIC;
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => TRANSFER_WIDTH, -- 32 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '0', -- sckl inactive high
CPHA => '1', -- data is captured on the tailing edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_Ss(0) => oslv_Ss,
osl_mosi => osl_mosi,
isl_miso => '0'
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data,it_set_values)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
vi.LDAC_n := '0';
vi.CLR_n := '1';
CASE vi.state IS
WHEN keep_clear_low =>
vi.CLR_n := '0';
IF vi.cycle_count = 10 THEN
vi.state := wait_after_reset;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN wait_after_reset =>
IF vi.cycle_count = 100 THEN
vi.state := set_internal_reference;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN set_internal_reference =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := SETUP_INTERNAL_REF;
vi.tx_data(0) := INTERNAL_REFERENCE;
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := WRITE_AND_UPDATE_CHANNEL_N;
vi.tx_data(TRANSFER_WIDTH -9 DOWNTO TRANSFER_WIDTH-12) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_data(TRANSFER_WIDTH -13 DOWNTO TRANSFER_WIDTH-28) := it_set_values(to_integer(vi.channel_count));
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN wait_for_transfer_to_finish =>
IF sl_rx_done = '1' THEN
vi.state := wait_for_next_transfer;
vi.cycle_count := (OTHERS => '0');
END IF;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 100 THEN
vi.cycle_count := to_unsigned(0,7);
IF vi.channel_count = NUMBER_OF_CHANNELS -1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := keep_clear_low;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
vi.cycle_count := (OTHERS => '0');
vi.CLR_n := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_LDAC_n <= ri.LDAC_n;
osl_CLR_N <= ri.CLR_n;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE dacad5668_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 16;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END COMPONENT dacad5668;
END PACKAGE dacad5668_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.dacad5668_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END ENTITY dacad5668;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF dacad5668 IS
CONSTANT SS_HOLD_CYCLES : INTEGER := 40; -- minimum 15ns see datasheet
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := 4;
CONSTANT TRANSFER_WIDTH : INTEGER := 32;
--COMMAND CODES
CONSTANT WRITE_AND_UPDATE_CHANNEL_N : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT SETUP_INTERNAL_REF : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
TYPE t_states IS (idle,wait_for_transfer_to_finish,wait_for_next_transfer,set_internal_reference,keep_clear_low,wait_after_reset);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
cycle_count : UNSIGNED(6 DOWNTO 0);
LDAC_n : STD_LOGIC;
CLR_n : STD_LOGIC;
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => TRANSFER_WIDTH, -- 32 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '0', -- sckl inactive high
CPHA => '1', -- data is captured on the tailing edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_Ss(0) => oslv_Ss,
osl_mosi => osl_mosi,
isl_miso => '0'
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data,it_set_values)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
vi.LDAC_n := '0';
vi.CLR_n := '1';
CASE vi.state IS
WHEN keep_clear_low =>
vi.CLR_n := '0';
IF vi.cycle_count = 10 THEN
vi.state := wait_after_reset;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN wait_after_reset =>
IF vi.cycle_count = 100 THEN
vi.state := set_internal_reference;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN set_internal_reference =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := SETUP_INTERNAL_REF;
vi.tx_data(0) := INTERNAL_REFERENCE;
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := WRITE_AND_UPDATE_CHANNEL_N;
vi.tx_data(TRANSFER_WIDTH -9 DOWNTO TRANSFER_WIDTH-12) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_data(TRANSFER_WIDTH -13 DOWNTO TRANSFER_WIDTH-28) := it_set_values(to_integer(vi.channel_count));
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN wait_for_transfer_to_finish =>
IF sl_rx_done = '1' THEN
vi.state := wait_for_next_transfer;
vi.cycle_count := (OTHERS => '0');
END IF;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 100 THEN
vi.cycle_count := to_unsigned(0,7);
IF vi.channel_count = NUMBER_OF_CHANNELS -1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := keep_clear_low;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
vi.cycle_count := (OTHERS => '0');
vi.CLR_n := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_LDAC_n <= ri.LDAC_n;
osl_CLR_N <= ri.CLR_n;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE dacad5668_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 16;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END COMPONENT dacad5668;
END PACKAGE dacad5668_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.dacad5668_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END ENTITY dacad5668;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF dacad5668 IS
CONSTANT SS_HOLD_CYCLES : INTEGER := 40; -- minimum 15ns see datasheet
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := 4;
CONSTANT TRANSFER_WIDTH : INTEGER := 32;
--COMMAND CODES
CONSTANT WRITE_AND_UPDATE_CHANNEL_N : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT SETUP_INTERNAL_REF : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
TYPE t_states IS (idle,wait_for_transfer_to_finish,wait_for_next_transfer,set_internal_reference,keep_clear_low,wait_after_reset);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
cycle_count : UNSIGNED(6 DOWNTO 0);
LDAC_n : STD_LOGIC;
CLR_n : STD_LOGIC;
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => TRANSFER_WIDTH, -- 32 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '0', -- sckl inactive high
CPHA => '1', -- data is captured on the tailing edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_Ss(0) => oslv_Ss,
osl_mosi => osl_mosi,
isl_miso => '0'
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data,it_set_values)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
vi.LDAC_n := '0';
vi.CLR_n := '1';
CASE vi.state IS
WHEN keep_clear_low =>
vi.CLR_n := '0';
IF vi.cycle_count = 10 THEN
vi.state := wait_after_reset;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN wait_after_reset =>
IF vi.cycle_count = 100 THEN
vi.state := set_internal_reference;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN set_internal_reference =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := SETUP_INTERNAL_REF;
vi.tx_data(0) := INTERNAL_REFERENCE;
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := WRITE_AND_UPDATE_CHANNEL_N;
vi.tx_data(TRANSFER_WIDTH -9 DOWNTO TRANSFER_WIDTH-12) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_data(TRANSFER_WIDTH -13 DOWNTO TRANSFER_WIDTH-28) := it_set_values(to_integer(vi.channel_count));
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN wait_for_transfer_to_finish =>
IF sl_rx_done = '1' THEN
vi.state := wait_for_next_transfer;
vi.cycle_count := (OTHERS => '0');
END IF;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 100 THEN
vi.cycle_count := to_unsigned(0,7);
IF vi.channel_count = NUMBER_OF_CHANNELS -1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := keep_clear_low;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
vi.cycle_count := (OTHERS => '0');
vi.CLR_n := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_LDAC_n <= ri.LDAC_n;
osl_CLR_N <= ri.CLR_n;
END ARCHITECTURE rtl;
|
-- SIMON 64/128
-- Simon core component (encryption and decryption presume pre-expansion of key to RAM)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic_vector(1 downto 0); -- state indicator (11 = init, 01 = pre-expand, 00 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (v_in_s, ram_data_out, v_out_s);
-- round index is used as ram address, round key is ram input
RAM_0 : ram port map (subkey_out_s, ram_rw, clk, r_s, ram_data_out);
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = "11" then
r_s <= (others => '0');
-- pre-expansion clock
elsif rst = "01" then
if (r_s = X"2B") then
if (enc = '0') then
r_s <= (others => '0');
else
r_s <= X"2A";
end if;
else
r_s <= std_logic_vector(unsigned(r_s) + 1);
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON Core
-- Take 2 clock cycle for initialization (since we route key through RAM) + 1 clock cycle per round for encryption/decryption
pr_smn : process(clk, rst, enc, r_s, key, key_s, subkey_out_s, block_in, v_in_s, v_out_s, ram_rw, ram_data_out)
begin
if rising_edge(clk) then
-- initalize
if rst = "11" then
if enc = '0' then
v_in_s <= block_in;
else
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
end if;
-- initialize intermediate key from master key
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
-- write pre-expansion to RAM
ram_rw <= '1';
-- pre-expansion (run 0x2C times, 0x2B to expand + 1 to put correct value on ram_data_out)
elsif rst = "01" then
-- intermediate key rotates for initial 4 key words, beyond that gets gradually filled in by expansion
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
if r_s = X"2B" then
ram_rw <= '0';
end if;
-- run
else
v_in_s <= v_out_s;
end if;
end if;
end process;
block_out <= v_out_s when (enc = '0') else v_out_s(31 downto 0) & v_out_s(63 downto 32);
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model_tb is
end entity;
architecture test of mb_model_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(31 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal io_byte_en : std_logic_vector(3 downto 0);
signal io_wdata : std_logic_vector(31 downto 0);
signal io_rdata : std_logic_vector(31 downto 0) := (others => 'Z');
signal io_ack : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
model: entity work.mb_model
port map (
clock => clock,
reset => reset,
io_addr => io_addr,
io_byte_en=> io_byte_en,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
io_ack => io_ack );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
io_ack <= '0';
if io_write = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := io_wdata(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(io_addr) & " dropped";
end case;
elsif io_read = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"0000C" => -- Capabilities
io_rdata <= X"00000002";
when X"00012" => -- UART_FLAGS
io_rdata <= X"40404040";
when X"2000A" => -- 1541_A memmap
io_rdata <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
io_rdata <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(io_addr) & " dropped";
io_rdata <= X"00000000";
end case;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model_tb is
end entity;
architecture test of mb_model_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(31 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal io_byte_en : std_logic_vector(3 downto 0);
signal io_wdata : std_logic_vector(31 downto 0);
signal io_rdata : std_logic_vector(31 downto 0) := (others => 'Z');
signal io_ack : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
model: entity work.mb_model
port map (
clock => clock,
reset => reset,
io_addr => io_addr,
io_byte_en=> io_byte_en,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
io_ack => io_ack );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
io_ack <= '0';
if io_write = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := io_wdata(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(io_addr) & " dropped";
end case;
elsif io_read = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"0000C" => -- Capabilities
io_rdata <= X"00000002";
when X"00012" => -- UART_FLAGS
io_rdata <= X"40404040";
when X"2000A" => -- 1541_A memmap
io_rdata <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
io_rdata <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(io_addr) & " dropped";
io_rdata <= X"00000000";
end case;
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_6_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_6_e-rtl-conf-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_6_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_6_e_rtl_conf / inst_6_e
--
configuration inst_6_e_rtl_conf of inst_6_e is
for rtl
-- Generated Configuration
end for;
end inst_6_e_rtl_conf;
--
-- End of Generated Configuration inst_6_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
port ( clk_i: in std_logic;
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
sw_i: in std_logic_vector(7 downto 0);
btn_i: in std_logic_vector(3 downto 0);
led_o: out std_logic_vector(7 downto 0)
);
end top;
architecture Behavioral of top is
component fx2async is
Port(
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
usb_data_i : in std_logic_vector(7 downto 0);
usb_data_o : out std_logic_vector(7 downto 0);
usb_wr_en_i : in std_logic;
usb_rd_en_i : in std_logic;
usb_wr_strobe_o : out std_logic;
usb_rd_strobe_o : out std_logic;
usb_pktend_i : in std_logic;
usb_pktstart_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end component;
signal usb_txd : std_logic_vector(7 downto 0);
signal usb_rxd : std_logic_vector(7 downto 0);
signal usb_wr : std_logic;
signal usb_rd : std_logic;
signal usb_wr_strobe : std_logic;
signal usb_rd_strobe : std_logic;
signal usb_pktend : std_logic;
signal usb_pktstart: std_logic;
signal rst : std_logic := '1';
signal delay_cnt : std_logic_vector(15 downto 0) := (others => '0');
signal sw_r1 : std_logic_vector(7 downto 0);
signal sw_r2 : std_logic_vector(7 downto 0);
begin
fx2async_inst : fx2async
port map (
-- einfach durchreichen...
fx2_wr_full_i => fx2_wr_full_i,
fx2_rd_empty_i => fx2_rd_empty_i,
fx2_data_io => fx2_data_io,
fx2_fifo_addr_o => fx2_fifo_addr_o,
fx2_slwr_o => fx2_slwr_o,
fx2_slrd_o => fx2_slrd_o,
fx2_sloe_o => fx2_sloe_o,
fx2_slcs_o => fx2_slcs_o,
fx2_pktend_o => fx2_pktend_o,
-- user interface zum USB interface
usb_data_i => usb_txd,
usb_data_o => usb_rxd,
usb_wr_en_i => usb_wr,
usb_rd_en_i => usb_rd,
usb_wr_strobe_o => usb_wr_strobe,
usb_rd_strobe_o => usb_rd_strobe,
usb_pktend_i => usb_pktend,
usb_pktstart_o => usb_pktstart,
clk_i => clk_i,
rst_i => rst
);
process
begin
wait until rising_edge(clk_i);
-- reset generator for usb if
if delay_cnt /= x"ffff" then
delay_cnt <= delay_cnt + 1;
rst <= '1';
else
rst <= '0';
end if;
-- we like well defined init states!
if rst = '1' then
usb_wr <= '0';
usb_rd <= '0';
usb_pktend <= '0';
else
-- always receive
usb_rd <= '1';
-- got a byte
if usb_rd_strobe = '1' then
-- output 1st byte on LEDs
if usb_pktstart = '1' then
led_o <= usb_rxd;
end if;
end if;
-- always send
usb_wr <= '1';
-- sync switches
sw_r1 <= sw_i;
sw_r2 <= sw_r1;
-- send switches
usb_txd <= sw_r2;
end if;
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index at the end and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3a IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_23downto16 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto24 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto24 & r_next_23downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "00" =>
r_next_7downto0 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "10" =>
r_next_23downto16 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_23downto16 <= X"00";
r_next_31downto24 <= X"00";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Title : Data unit of DMA controller
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_du.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of the data switching for the dma.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_du
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_dma_du.vhd,v $
-- Revision 1.2 2013/09/12 08:45:25 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.1 2012/03/29 10:14:44 MMiehling
-- Initial Revision
--
-- Revision 1.4 2006/05/18 14:02:22 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:24 mmiehling
-- Initial Revision
--
-- Revision 1.3 2004/08/13 15:41:12 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:22 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:50 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma_du IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
dma_sta : IN std_logic_vector(9 DOWNTO 0);
irq_o : OUT std_logic; -- irq for cpu; asserted when done or error (if enabled)
arbit_slv : IN std_logic; -- if set, dma_slv has access and vica verse
slv_ack : IN std_logic; -- if set, write from slave side will be done
mstr_ack : IN std_logic; -- if set, write from master side will be done
-- slave signals
adr_i : IN std_logic_vector(6 DOWNTO 2);
sel_i : IN std_logic_vector(3 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
we_i : IN std_logic;
ack_o : IN std_logic;
-- wb_master singals
adr_o : IN std_logic_vector(6 DOWNTO 2);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vme_dma_au
dma_act_bd : IN std_logic_vector(7 DOWNTO 4); -- active bd number
dma_dest_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : OUT std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : OUT std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : OUT std_logic; -- indicates if source adress should be incremented
inc_dest : OUT std_logic; -- indicates if destination adress should be incremented
dma_size : OUT std_logic_vector(15 DOWNTO 0); -- size of data package
clr_dma_act_bd : OUT std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- dma_mstr
set_dma_err : IN std_logic; -- sets dma error bit if vme error
clr_dma_en : IN std_logic; -- clears dma en bit if dma_mstr has done
dma_en : OUT std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : OUT std_logic; -- indicates the last bd
en_mstr_dat_i_reg : IN std_logic -- enable for data in
);
END vme_dma_du;
ARCHITECTURE vme_dma_du_arch OF vme_dma_du IS
SIGNAL dma_sta_int : std_logic_vector(7 DOWNTO 0);
SIGNAL act_bd_conf_int : std_logic_vector(31 DOWNTO 0);
SIGNAL int_data : std_logic_vector(31 DOWNTO 0);
SIGNAL int_adr : std_logic_vector(6 DOWNTO 2);
SIGNAL dma_err : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL dma_ien : std_logic;
SIGNAL dma_en_int : std_logic;
SIGNAL write_flag_mstr : std_logic;
SIGNAL mstr_dat_i_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_dest_adr_int : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_sour_adr_int : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_size_reg : std_logic_vector(15 DOWNTO 0);
BEGIN
clr_dma_act_bd <= '1' WHEN (clr_dma_en = '1' AND set_dma_err = '0') OR dma_sta(9) = '1' ELSE '0';
dma_en <= dma_sta(0);
irq_o <= dma_sta(2);
dma_dest_adr <= dma_dest_adr_int(31 DOWNTO 2);
dma_sour_adr <= dma_sour_adr_int(31 DOWNTO 2);
dma_size <= dma_size_reg;
dma_sour_device <= act_bd_conf_int(18 DOWNTO 16);
dma_dest_device <= act_bd_conf_int(14 DOWNTO 12);
dma_vme_am <= act_bd_conf_int(8 DOWNTO 4);
blk_sgl <= '1' WHEN act_bd_conf_int(7 DOWNTO 4) = "0001" or act_bd_conf_int(7 DOWNTO 4) = "0101" ELSE -- A16 does not provide block mode => always single will be selected
'0' WHEN act_bd_conf_int(7 DOWNTO 4) = "1100" ELSE -- A24D64 does not provide single mode => always block will be selected
'0' WHEN act_bd_conf_int(7 DOWNTO 4) = "1110" ELSE -- A32D64 does not provide single mode => always block will be selected
act_bd_conf_int(3);
inc_sour <= act_bd_conf_int(2);
inc_dest <= act_bd_conf_int(1);
dma_null <= act_bd_conf_int(0);
int_data <= mstr_dat_i_reg;
int_adr <= adr_o;
write_flag_mstr <= '1' WHEN mstr_ack = '1' ELSE '0';
slv_dat_o <= (OTHERS => '0');
outdec : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mstr_dat_i_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF en_mstr_dat_i_reg = '1' THEN
mstr_dat_i_reg <= mstr_dat_i;
END IF;
END IF;
END PROCESS outdec;
-- dma_dest_adr_int 0x48
dest : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_dest_adr_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "00") THEN
dma_dest_adr_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS dest;
-- dma_sour_adr_int 0x4c
sour: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_sour_adr_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "01") THEN
dma_sour_adr_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS sour;
-- dma_size 0x50
siz : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_size_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "10") THEN
dma_size_reg(15 DOWNTO 0) <= int_data(15 DOWNTO 0);
END IF;
END IF;
END PROCESS siz;
-- act_bd_conf_int 0x54
conf: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
act_bd_conf_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "11") THEN
act_bd_conf_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS conf;
END vme_dma_du_arch;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
--
-- Clocks on ml605
--
-- There are four clock sources on ml605 board:
-- * On-board differential 200 MHz oscillator.
-- * On-board single-ended Oscillator Socket populated with 66 MHz.
-- * User differential through SMA.
-- * MGT differential through SMA.
-- This example is about on-board clock sources. They are used to blink user leds.
-- The clock of 200 MHz is used to blink the 8 GPIO LEDs.
-- The clock of 66 MHz is used to blink the 5 direction LEDs.
-- CPU Reset push-button (SW10) is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(12 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk200, led66, led200 : std_logic;
begin
IBUFGDS_inst: IBUFGDS
port map (I => clk_p_i, IB => clk_n_i, O => clk200);
blink66_inst: Blink
generic map (FREQUENCY => 66e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led66);
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => rst_i, blink_o => led200);
leds_o(4 downto 0) <= led66 & led66 & led66 & led66 & not(led66);
leds_o(12 downto 5) <= led200 & not(led200) & led200 & not(led200) &
led200 & not(led200) & led200 & not(led200);
end architecture RTL;
|
--------------------------------------------------------------------------------
-- File Name: conversions_p.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was written by SEVA Technologies, Inc. and donated to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
--------------------------------------------------------------------------------
PACKAGE conversions IS
----------------------------------------------------------------------------
-- the conversions in this package are not guaranteed to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
-- <these packages are mutually exclusive>
-- conv_integer(std_logic_vector)
-- <except for this conversion, these packages are unnecessary)
-- to minimize compile problems write:
-- use std_logic_unsigned.conv_integer;
-- use std_logic_signed.conv_integer;
--
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
END conversions;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversions IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
function min(x,y: integer) return integer is
begin
if x < y then return x; else return y; end if;
end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
case slv4'(int(i to i+3)) is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
when "LLLL" => r(ptr) := 'L';
when "HHHH" => r(ptr) := 'H';
when "UUUU" => r(ptr) := 'U';
when "XXXX" => r(ptr) := 'X';
when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
END conversions;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity ZeroCounter is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end ZeroCounter;
architecture Beh of ZeroCounter is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out std_logic_vector(8 downto 0)
);
end component;
component MRAM is
port (
RW: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DIN: in std_logic_vector (7 downto 0);
DOUT: out std_logic_vector (7 downto 0)
);
end component;
component DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF: out std_logic;
-- significant bit set flag
SBF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ÏÇÓ
ROM_re: out std_logic;
ROM_adr: out std_logic_vector(5 downto 0);
ROM_dout: in std_logic_vector(8 downto 0);
-- ÎÇÓ
RAM_rw: out std_logic;
RAM_adr: out std_logic_vector(5 downto 0);
RAM_din: out std_logic_vector(7 downto 0);
RAM_dout: in std_logic_vector(7 downto 0);
--datapath
DP_op1: out std_logic_vector(7 downto 0);
DP_ot: out std_logic_vector(2 downto 0);
DP_en: out std_logic;
DP_res: in std_logic_vector(7 downto 0);
DP_zf: in std_logic;
DP_sbf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_adr: std_logic_vector(5 downto 0);
signal rom_dout: std_logic_vector(8 downto 0);
signal ram_rw: std_logic;
signal ram_adr: std_logic_vector(5 downto 0);
signal ram_din: std_logic_vector(7 downto 0);
signal ram_dout: std_logic_vector(7 downto 0);
signal dp_op1: std_logic_vector(7 downto 0);
signal dp_ot: std_logic_vector(2 downto 0);
signal dp_en: std_logic;
signal dp_res: std_logic_vector(7 downto 0);
signal dp_zf: std_logic;
signal dp_sbf: std_logic;
begin
UMRAM: entity MRAM (Beh_Zer) port map(
RW => ram_rw,
ADR => ram_adr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Zer) port map (
RE => rom_re,
ADR => rom_adr,
DOUT => rom_dout
);
UDPATH: DPATH port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
RES => dp_res,
ZF => dp_zf,
SBF => dp_sbf
);
UCTRL1: CTRL1 port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADR => rom_adr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADR => ram_adr,
RAM_DIN => ram_din,
RAM_DOUT => ram_dout,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_RES => dp_res,
DP_ZF => dp_zf,
DP_SBF => dp_sbf
);
end Beh;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean;
end c02s02b00x00p07n05i02945pkg;
package body c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean is
begin
return TRUE;
end F1;
end c02s02b00x00p07n05i02945pkg;
use work.c02s02b00x00p07n05i02945pkg.all;
ENTITY c02s02b00x00p07n05i02945ent IS
END c02s02b00x00p07n05i02945ent;
ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
BEGIN
k := F1(2);
assert NOT( k=TRUE )
report "***PASSED TEST: c02s02b00x00p07n05i02945"
severity NOTE;
assert ( k=TRUE )
report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n05i02945arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean;
end c02s02b00x00p07n05i02945pkg;
package body c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean is
begin
return TRUE;
end F1;
end c02s02b00x00p07n05i02945pkg;
use work.c02s02b00x00p07n05i02945pkg.all;
ENTITY c02s02b00x00p07n05i02945ent IS
END c02s02b00x00p07n05i02945ent;
ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
BEGIN
k := F1(2);
assert NOT( k=TRUE )
report "***PASSED TEST: c02s02b00x00p07n05i02945"
severity NOTE;
assert ( k=TRUE )
report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n05i02945arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean;
end c02s02b00x00p07n05i02945pkg;
package body c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean is
begin
return TRUE;
end F1;
end c02s02b00x00p07n05i02945pkg;
use work.c02s02b00x00p07n05i02945pkg.all;
ENTITY c02s02b00x00p07n05i02945ent IS
END c02s02b00x00p07n05i02945ent;
ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
BEGIN
k := F1(2);
assert NOT( k=TRUE )
report "***PASSED TEST: c02s02b00x00p07n05i02945"
severity NOTE;
assert ( k=TRUE )
report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n05i02945arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block4
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_2_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_11_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_re_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_im_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block4 IS
-- Signals
SIGNAL dout_10_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_10_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_12_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_12_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_11_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_11_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_12_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_12_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
BEGIN
dout_10_re_signed <= signed(dout_10_re);
din1_re <= resize(dout_10_re_signed, 18);
dout_10_im_signed <= signed(dout_10_im);
din1_im <= resize(dout_10_im_signed, 18);
dout_12_re_signed <= signed(dout_12_re);
din2_re <= resize(dout_12_re_signed, 18);
dout_12_im_signed <= signed(dout_12_im);
din2_im <= resize(dout_12_im_signed, 18);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_11)
VARIABLE add_cast : signed(18 DOWNTO 0);
VARIABLE add_cast_0 : signed(18 DOWNTO 0);
VARIABLE add_cast_1 : signed(18 DOWNTO 0);
VARIABLE add_cast_2 : signed(18 DOWNTO 0);
VARIABLE sub_cast : signed(18 DOWNTO 0);
VARIABLE sub_cast_0 : signed(18 DOWNTO 0);
VARIABLE sub_cast_1 : signed(18 DOWNTO 0);
VARIABLE sub_cast_2 : signed(18 DOWNTO 0);
VARIABLE add_cast_3 : signed(18 DOWNTO 0);
VARIABLE add_cast_4 : signed(18 DOWNTO 0);
VARIABLE add_cast_5 : signed(18 DOWNTO 0);
VARIABLE add_cast_6 : signed(18 DOWNTO 0);
VARIABLE sub_cast_3 : signed(18 DOWNTO 0);
VARIABLE sub_cast_4 : signed(18 DOWNTO 0);
VARIABLE sub_cast_5 : signed(18 DOWNTO 0);
VARIABLE sub_cast_6 : signed(18 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_11 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 19);
add_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 19);
sub_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 19);
add_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 19);
sub_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 19);
add_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 19);
sub_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 19);
add_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 19);
sub_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_11_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(17 DOWNTO 0);
dout_11_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(17 DOWNTO 0);
dout_12_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(17 DOWNTO 0);
dout_12_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(17 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re_1 <= std_logic_vector(dout_12_re_tmp);
dout_12_im_1 <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02968ent IS
END c02s03b01x00p02n02i02968ent;
ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
assert NOT( c1=10 )
report "***PASSED TEST: c02s03b01x00p02n02i02968"
severity NOTE;
assert ( c1=10 )
report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= abs 10;
assert (n1=three)
report "Error in call to operloaded operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02968arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02968ent IS
END c02s03b01x00p02n02i02968ent;
ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
assert NOT( c1=10 )
report "***PASSED TEST: c02s03b01x00p02n02i02968"
severity NOTE;
assert ( c1=10 )
report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= abs 10;
assert (n1=three)
report "Error in call to operloaded operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02968arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02968ent IS
END c02s03b01x00p02n02i02968ent;
ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
assert NOT( c1=10 )
report "***PASSED TEST: c02s03b01x00p02n02i02968"
severity NOTE;
assert ( c1=10 )
report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= abs 10;
assert (n1=three)
report "Error in call to operloaded operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02968arch;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system_wa is
port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs
end entity motor_system_wa;
----------------------------------------------------------------
architecture simple of motor_system_wa is
quantity v_in across vp to vm; -- Inout voltage/Current
quantity x1 across ix1 through px1 to electrical_ref;
quantity x2 across ix2 through px2 to electrical_ref;
quantity x3 across ix3 through px3 to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
constant c11 : real := -1.0/Tfb;
constant c12 : real := 0.0;
constant c13 : real := Kfb/Tfb;
constant c21 : real := -Ke/Te;
constant c22 : real := -1.0/Te;
constant c23 : real := 0.0;
constant c31 : real := 0.0;
constant c32 : real := Km/Tm;
constant c33 : real := -1.0/Tm;
begin -- architecture simple
x1'dot == c11*x1 + c12*x2 + c13*x3;
x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in;
x3'dot == c31*x1 + c32*x2 + c33*x3;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system_wa is
port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs
end entity motor_system_wa;
----------------------------------------------------------------
architecture simple of motor_system_wa is
quantity v_in across vp to vm; -- Inout voltage/Current
quantity x1 across ix1 through px1 to electrical_ref;
quantity x2 across ix2 through px2 to electrical_ref;
quantity x3 across ix3 through px3 to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
constant c11 : real := -1.0/Tfb;
constant c12 : real := 0.0;
constant c13 : real := Kfb/Tfb;
constant c21 : real := -Ke/Te;
constant c22 : real := -1.0/Te;
constant c23 : real := 0.0;
constant c31 : real := 0.0;
constant c32 : real := Km/Tm;
constant c33 : real := -1.0/Tm;
begin -- architecture simple
x1'dot == c11*x1 + c12*x2 + c13*x3;
x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in;
x3'dot == c31*x1 + c32*x2 + c33*x3;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system_wa is
port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs
end entity motor_system_wa;
----------------------------------------------------------------
architecture simple of motor_system_wa is
quantity v_in across vp to vm; -- Inout voltage/Current
quantity x1 across ix1 through px1 to electrical_ref;
quantity x2 across ix2 through px2 to electrical_ref;
quantity x3 across ix3 through px3 to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
constant c11 : real := -1.0/Tfb;
constant c12 : real := 0.0;
constant c13 : real := Kfb/Tfb;
constant c21 : real := -Ke/Te;
constant c22 : real := -1.0/Te;
constant c23 : real := 0.0;
constant c31 : real := 0.0;
constant c32 : real := Km/Tm;
constant c33 : real := -1.0/Tm;
begin -- architecture simple
x1'dot == c11*x1 + c12*x2 + c13*x3;
x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in;
x3'dot == c31*x1 + c32*x2 + c33*x3;
end architecture simple;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:34 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : gcd_block_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2018.2";
begin
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrlx
-- File: spictrlx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Auto mode: J. Andersson, J. Ekergarn - Aeroflex Gaisler AB
-- Contact: [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrlx is
generic (
rev : integer := 0; -- Core revision
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length;
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer range 0 to NTECH := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
attribute sync_set_reset of rstn : signal is "true";
end entity spictrlx;
architecture rtl of spictrlx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant ASEL_EN : integer := aslvsel * slvselen;
constant AM_EN : integer := automode;
constant AM_CNT_BITS : integer := acntbits;
constant OD_EN : integer := odmode;
constant TW_EN : integer := twen;
constant MAX_WLEN : integer := maxwlen;
constant AM_MSK1_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 32;
constant AM_MSK2_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 64;
constant AM_MSK3_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 96;
constant FIFO_BITS : integer := fdepth;
constant APBBITS : integer := 6+3*AM_EN;
constant APBH : integer := 2+APBBITS-1;
constant CAP_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(0, APBBITS);
constant MODE_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(8, APBBITS);
constant EVENT_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(9, APBBITS);
constant MASK_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(10, APBBITS);
constant COM_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(11, APBBITS);
constant TD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(12, APBBITS);
constant RD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(13, APBBITS);
constant SLVSEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(14, APBBITS);
constant ASEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(15, APBBITS);
constant AMCFG_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(16, APBBITS);
constant AMPER_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(17, APBBITS);
constant AMMSK0_ADDR : std_logic_vector(10 downto 2) := "000010100"; -- 0x050
constant AMMSK1_ADDR : std_logic_vector(10 downto 2) := "000010101"; -- 0x054
constant AMMSK2_ADDR : std_logic_vector(10 downto 2) := "000010110"; -- 0x058
constant AMMSK3_ADDR : std_logic_vector(10 downto 2) := "000010111"; -- 0x05C
constant AMTX_ADDR : std_logic_vector(10 downto 2) := "010000000"; -- 0x200
constant AMRX_ADDR : std_logic_vector(10 downto 2) := "100000000"; -- 0x40
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ, 8) & conv_std_logic_vector(MAX_WLEN, 4) &
conv_std_logic_vector(TW_EN, 1) & conv_std_logic_vector(AM_EN, 1) &
conv_std_logic_vector(ASEL_EN, 1) & conv_std_logic_vector(SLVSEL_EN, 1) &
conv_std_logic_vector(FIFO_DEPTH, 8) & conv_std_logic(syncram = 1) &
conv_std_logic_vector(ft, 2) & conv_std_logic_vector(rev, 5);
-- Returns an integer containing the maximum characted length - 1 as
-- restricted by the maxwlen VHDL generic.
function wlen return integer is
begin -- maxwlen
if MAX_WLEN = 0 then return 31; end if;
return MAX_WLEN;
end wlen;
constant PROG_AM_MASK : boolean :=
AM_EN = 1 and automask0 = 0 and (automask1 = 0 or FIFO_DEPTH <= 32) and
(automask2 = 0 or FIFO_DEPTH <= 64) and (automask3 = 0 or FIFO_DEPTH <= 96);
constant AM_MASK : std_logic_vector(127 downto 0) :=
conv_std_logic_vector_signed(automask3,32) &
conv_std_logic_vector_signed(automask2,32) &
conv_std_logic_vector_signed(automask1,32) &
conv_std_logic_vector_signed(automask0,32);
function check_discont_am_mask return boolean is
variable foundzero : boolean;
begin
if AM_EN = 0 then
return false;
elsif PROG_AM_MASK then
return true;
else
foundzero := false;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '0' then
foundzero := true;
else
if foundzero then
return true;
end if;
end if;
end loop;
return false;
end if;
end function;
constant DISCONT_AM_MASK : boolean := check_discont_am_mask;
function check_am_mask_end return integer is
variable ret : integer;
begin
ret := 0;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '1' then
ret := i;
end if;
end loop;
return ret;
end function;
constant AM_MASK_END : integer := check_am_mask_end;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
amen : std_ulogic;
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
tw : std_ulogic; -- 3-wire mode
asel : std_ulogic; -- Automatic slave select
fact : std_ulogic; -- PM multiplication factor
od : std_ulogic; -- Open drain mode
cg : std_logic_vector(4 downto 0); -- Clock gap
aseldel : std_logic_vector(1 downto 0); -- Asel delay
tac : std_ulogic;
tto : std_ulogic; -- Three-wire mode word order
igsel : std_ulogic; -- Ignore spisel input
cite : std_ulogic; -- Require SCK = CPOL for TIP end
end record;
type spi_em_rec is record -- SPI Event and Mask registers
tip : std_ulogic; -- Transfer in progress/Clock generated
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
at : std_ulogic; -- Automated transfer
end record;
type spi_fifo is array (0 to (1-syncram)*(FIFO_DEPTH-1)) of std_logic_vector(wlen downto 0);
type spi_amcfg_rec is record -- AM config register
seq : std_ulogic; -- Data must always be read out of receive queue
strict : std_ulogic; -- Strict period
ovtb : std_ulogic; -- Perform transfer on OV
ovdb : std_ulogic; -- Skip data on OV
act : std_ulogic; -- Start immediately
eact : std_ulogic; -- Activate on external event
erpt : std_ulogic; -- Repeat on external event, not on period done
lock : std_ulogic; -- Lock receive registers when reading data
ecgc : std_ulogic; -- External clock gap control
end record;
type spi_am_rec is record -- Automode state
-- Register interface
cfg : spi_amcfg_rec; -- AM config register
per : std_logic_vector((AM_CNT_BITS-1)*AM_EN downto 0); -- AM period
--
active : std_ulogic; -- Auto mode active
lock : std_ulogic;
cnt : unsigned((AM_CNT_BITS-1)*AM_EN downto 0);
--
skipdata : std_ulogic;
rxfull : std_ulogic; -- AM RX FIFO is filled
rxfifo : spi_fifo; -- Receive data FIFO
txfifo : spi_fifo; -- Transmit data FIFO
rfreecnt : integer range 0 to FIFO_DEPTH; -- free rx fifo slots
mask : std_logic_vector(FIFO_DEPTH-1 downto 0);
mask_shdw : std_logic_vector(FIFO_DEPTH-1 downto 0);
unread : std_logic_vector(FIFO_DEPTH-1 downto 0);
at : std_ulogic;
--
rxread : std_ulogic;
txwrite : std_ulogic;
txread : std_ulogic;
apbaddr : std_logic_vector(FIFO_BITS-1 downto 0);
rxsel : std_ulogic;
end record;
-- Two stage synchronizers on each input coming from off-chip
type spi_in_local_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_in_array is array (1 downto 0) of spi_in_local_type;
-- Local spi out type without ssn
type spi_out_local_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
-- Yet another subset of out type to make it easier for certain tools to
-- place registers near pads.
type spi_out_local_lb_type is record
mosi : std_ulogic;
sck : std_ulogic;
end record;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
aslvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Automatic slave select
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
rxd : std_logic_vector(wlen downto 0); -- Receive shift register
txd : std_logic_vector(wlen downto 0); -- Transmit shift register
txdupd : std_ulogic; -- Update txd
txdbyp : std_ulogic; -- txd update bypass
toggle : std_ulogic; -- SCK has toggled
samp : std_ulogic; -- Sample
chng : std_ulogic; -- Change
psck : std_ulogic; -- Previous value of SC
twdir : std_ulogic; -- Direction in 3-wire mode
syncsamp : std_logic_vector(1 downto 0); -- Sample synchronized input
incrdli : std_ulogic;
rxdone : std_ulogic;
rxdone2 : std_ulogic;
running : std_ulogic;
ov2 : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : std_logic_vector(fdepth-1 downto 0); -- First tx queue element
rdfi : std_logic_vector(fdepth-1 downto 0); -- First rx queue element
tdli : std_logic_vector(fdepth-1 downto 0); -- Last tx queue element
rdli : std_logic_vector(fdepth-1 downto 0); -- Last rx queue element
rbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current receive bit
tbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current transmit bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
cgcntblock: std_ulogic;
aselcnt : unsigned(1 downto 0); -- ASEL delay
cgasel : std_ulogic; -- ASEL when entering CG
--
irq : std_ulogic;
--
-- Automode
am : spi_am_rec;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_local_type;
spiolb : spi_out_local_lb_type;
--
astart : std_ulogic;
cstart : std_ulogic;
txdupd2 : std_ulogic;
twdir2 : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns a vector containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(wlen downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
variable sdata : std_logic_vector(31 downto 0) := (others => '0');
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
sdata := (others => '0'); sdata(wlen downto 0) := data;
case length is
when 15 => rdata(15 downto 0) := sdata(15 downto 0);
when 14 => rdata(14 downto 0) := sdata(14 downto 0);
when 13 => rdata(13 downto 0) := sdata(13 downto 0);
when 12 => rdata(12 downto 0) := sdata(12 downto 0);
when 11 => rdata(11 downto 0) := sdata(11 downto 0);
when 10 => rdata(10 downto 0) := sdata(10 downto 0);
when 9 => rdata(9 downto 0) := sdata(9 downto 0);
when 8 => rdata(8 downto 0) := sdata(8 downto 0);
when 7 => rdata(7 downto 0) := sdata(7 downto 0);
when 6 => rdata(6 downto 0) := sdata(6 downto 0);
when 5 => rdata(5 downto 0) := sdata(5 downto 0);
when 4 => rdata(4 downto 0) := sdata(4 downto 0);
when 3 => rdata(3 downto 0) := sdata(3 downto 0);
when others => rdata := sdata;
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
spisel : std_ulogic;
cpol : std_ulogic;
sck : std_ulogic;
fsck_chg : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if fsck_chg = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function spictrl_resval return spi_reg_type is
variable v : spi_reg_type;
begin
v.mode := ('0','0','0','0','0','0','0','0',"0000","0000",
'0','0','0','0',"00000","00", '0', '0', '0', '0');
v.event := ('0', '0', '0', '0', '0', '0', '0', '0');
v.mask := ('0', '0', '0', '0', '0', '0', '0', '0');
v.lst := '0';
v.td := (others => '0');
v.rd := (others => '0');
v.slvsel := (others => '1');
v.aslvsel := (others => '0');
v.uf := '0';
v.ov := '0';
v.td_occ := '0';
v.rd_free := '1';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.txfifo(i) := (others => '0');
v.rxfifo(i) := (others => '0');
end loop;
v.rxd := (others => '0');
v.txd := (others => '0'); v.txd(0) := '1';
v.txdupd := '0';
v.txdbyp := '0';
v.toggle := '0';
v.samp := '1';
v.chng := '0';
v.psck := '0';
v.twdir := INPUT;
v.syncsamp := (others => '0');
v.incrdli := '0';
v.rxdone := '0';
v.rxdone2 := '0';
v.running := '0';
v.ov2 := '0';
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := (others => '0');
v.rdfi := (others => '0');
v.tdli := (others => '0');
v.rdli := (others => '0');
v.rbitcnt := (others => '0');
v.tbitcnt := (others => '0');
v.divcnt := (others => '0');
v.cgcnt := (others => '0');
v.cgcntblock := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
v.irq := '0';
v.am.cfg := ('0', '0', '0', '0', '0', '0', '0', '0', '0');
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.cnt := (others => '0');
v.am.skipdata := '0';
v.am.rxfull := '0';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.am.rxfifo := (others => (others => '0'));
v.am.txfifo := (others => (others => '0'));
end loop;
v.am.rfreecnt := 0;
v.am.mask := (others => '0');
v.am.mask_shdw := (others => '1');
v.am.unread := (others => '0');
v.am.at := '0';
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
for i in 1 downto 0 loop
v.spii(i).miso := '1';
v.spii(i).mosi := '1';
v.spii(i).sck := '0';
v.spii(i).spisel := '1';
end loop;
v.spio.miso := '1';
v.spio.misooen := INPUT;
v.spio.mosi := '1';
v.spio.mosioen := INPUT;
v.spio.sck := '0';
v.spio.sckoen := INPUT;
v.spio.enable := '0';
v.spio.astart := '0';
v.spio.aready := '0';
v.spiolb.mosi := '1';
v.spiolb.sck := '1';
v.astart := '0';
v.cstart := '0';
v.txdupd2 := '0';
v.twdir2 := '0';
return v;
end spictrl_resval;
constant RES : spi_reg_type := spictrl_resval;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
type fifo_data_vector_array is array (automode downto 0) of std_logic_vector(wlen downto 0);
type fifo_addr_vector_array is array (automode downto 0) of std_logic_vector(fdepth-1 downto 0);
signal rx_di, rx_do, tx_di, tx_do : fifo_data_vector_array;
signal rx_ra, rx_wa, tx_ra, tx_wa : fifo_addr_vector_array;
signal rx_read, tx_read, rx_write, tx_write : std_logic_vector(automode downto 0);
signal arstn : std_ulogic;
begin
arstn <= apbi_testrst when (scantest = 1) and (apbi_testen = '1') else rstn;
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi_psel, apbi_penable, apbi_paddr, apbi_pwrite,
apbi_pwdata, apbi_testen, apbi_testrst, apbi_scanen,
apbi_testoen, spii_miso, spii_mosi, spii_sck, spii_spisel,
spii_astart, rx_do, tx_do, spii_cstart, spii_ignore)
variable v : spi_reg_type;
variable apbaddr : std_logic_vector(APBH downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable change : std_ulogic;
variable update : std_ulogic;
variable sample : std_ulogic;
variable reload : std_ulogic;
variable cgasel : std_ulogic;
variable txshift : std_ulogic;
-- automode
variable rstop1 : std_ulogic;
variable rstop2 : std_ulogic;
variable rstop3 : std_ulogic;
variable tstop1 : std_ulogic;
variable tstop2 : std_ulogic;
variable tstop3 : std_ulogic;
variable astart : std_ulogic;
-- fifos
variable rx_rd : std_ulogic;
variable tx_rd : std_ulogic;
variable rx_wr : std_ulogic;
variable tx_wr : std_ulogic;
--
variable fsck : std_ulogic;
variable fsck_chg : std_ulogic;
--
variable spisel : std_ulogic;
--
variable rntxd : std_logic_vector(0 to 31);
variable ntxd : std_logic_vector(wlen downto 0);
variable amask : std_logic_vector(FIFO_DEPTH-1 downto 0);
variable aloop : integer;
begin -- process comb
v := r; v.irq := '0';
apbaddr := apbi_paddr(APBH downto 2); apbout := (others => '0');
len := spilen(r.mode.len); v.toggle := '0'; v.txdupd := '0';
v.syncsamp := r.syncsamp(0) & '0'; update := '0'; v.rxdone := '0';
indata := '0'; sample := '0'; change := '0'; reload := '0';
v.spio.astart := '0'; cgasel := '0'; v.ov2 := r.ov; txshift := '0';
fsck := '0'; fsck_chg := '0'; v.txdbyp := '0';
spisel := r.spii(1).spisel or r.mode.igsel;
ntxd := r.td(wlen downto 0); rntxd := reverse(r.td);
if r.mode.rev = '1' then ntxd := rntxd(31-wlen to 31); end if;
v.spio.aready := '0';
if AM_EN = 1 then
v.txdupd2 := '0';
v.cstart := '0';
if TW_EN = 1 then
v.twdir2 := r.twdir;
end if;
end if;
if PROG_AM_MASK then
amask := r.am.mask;
aloop := FIFO_DEPTH-1;
else
amask := AM_MASK(FIFO_DEPTH-1 downto 0);
aloop := AM_MASK_END;
end if;
rx_rd := '0'; tx_rd := '0'; rx_wr := '0'; tx_wr := '0';
rstop1 := '0'; rstop2 := '0'; rstop3 := '0';
tstop1 := '0'; tstop2 := '0'; tstop3 := '0';
astart := '0'; v.am.txwrite := '0'; v.am.txwrite := '0'; v.am.rxread := '0';
if AM_EN = 1 then
v.am.at := r.event.at;
v.astart := spii_astart;
if r.event.at = '0' then
astart := spii_astart and (not r.astart);
if PROG_AM_MASK then
v.am.mask := r.am.mask_shdw;
end if;
end if;
if spii_cstart = '1' then v.cstart := '1'; end if;
end if;
if (apbi_psel and apbi_penable and (not apbi_pwrite)) = '1' then
if apbaddr = CAP_ADDR then
apbout := SPICTRLCAPREG;
elsif apbaddr = MODE_ADDR then
apbout := r.mode.amen & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & r.mode.tw & r.mode.asel &
r.mode.fact & r.mode.od & r.mode.cg & r.mode.aseldel &
r.mode.tac & r.mode.tto & r.mode.igsel & r.mode.cite &
zero32(0);
elsif apbaddr = EVENT_ADDR then
apbout := r.event.tip & zero32(30 downto 16) & r.event.at &
r.event.lt & zero32(13) & r.event.ov & r.event.un &
r.event.mme & r.event.ne & r.event.nf & zero32(7 downto 0);
elsif apbaddr = MASK_ADDR then
apbout := r.mask.tip & zero32(30 downto 16) & r.mask.at &
r.mask.lt & zero32(13) & r.mask.ov & r.mask.un &
r.mask.mme & r.mask.ne & r.mask.nf & zero32(7 downto 0);
elsif apbaddr = RD_ADDR then
apbout := condhwordswap(r.rd, len);
if AM_EN = 0 or r.mode.amen = '0' then
v.rd_free := '1';
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
apbout((SLVSEL_SZ-1) downto 0) := r.aslvsel;
else null; end if;
end if;
end if;
-- write registers
if (apbi_psel and apbi_penable and apbi_pwrite) = '1' then
if apbaddr = MODE_ADDR then
if AM_EN = 1 then v.mode.amen := apbi_pwdata(31); end if;
v.mode.loopb := apbi_pwdata(30);
v.mode.cpol := apbi_pwdata(29);
v.mode.cpha := apbi_pwdata(28);
v.mode.div16 := apbi_pwdata(27);
v.mode.rev := apbi_pwdata(26);
v.mode.ms := apbi_pwdata(25);
v.mode.en := apbi_pwdata(24);
v.mode.len := apbi_pwdata(23 downto 20);
v.mode.pm := apbi_pwdata(19 downto 16);
if TW_EN = 1 then v.mode.tw := apbi_pwdata(15); end if;
if ASEL_EN = 1 then v.mode.asel := apbi_pwdata(14); end if;
v.mode.fact := apbi_pwdata(13);
if OD_EN = 1 then v.mode.od := apbi_pwdata(12); end if;
v.mode.cg := apbi_pwdata(11 downto 7);
if ASEL_EN = 1 then
v.mode.aseldel := apbi_pwdata(6 downto 5);
v.mode.tac := apbi_pwdata(4);
end if;
if TW_EN = 1 then v.mode.tto := apbi_pwdata(3); end if;
v.mode.igsel := apbi_pwdata(2);
v.mode.cite := apbi_pwdata(1);
elsif apbaddr = EVENT_ADDR then
wc(v.event.lt, r.event.lt, apbi_pwdata(14));
wc(v.event.ov, r.event.ov, apbi_pwdata(12));
wc(v.event.un, r.event.un, apbi_pwdata(11));
wc(v.event.mme, r.event.mme, apbi_pwdata(10));
elsif apbaddr = MASK_ADDR then
v.mask.tip := apbi_pwdata(31);
if AM_EN = 1 then
v.mask.at := apbi_pwdata(15);
end if;
v.mask.lt := apbi_pwdata(14);
v.mask.ov := apbi_pwdata(12);
v.mask.un := apbi_pwdata(11);
v.mask.mme := apbi_pwdata(10);
v.mask.ne := apbi_pwdata(9);
v.mask.nf := apbi_pwdata(8);
elsif apbaddr = COM_ADDR then
v.lst := apbi_pwdata(22);
elsif apbaddr = TD_ADDR then
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi_pwdata;
if AM_EN = 0 or r.mode.amen = '0' then
v.td_occ := '1';
end if;
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then v.slvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
v.aslvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
end if;
end if;
-- Automode register interface
if AM_EN /= 0 then
if apbi_psel = '1' then
v.am.apbaddr := apbaddr(FIFO_BITS+1 downto 2);
if syncram /= 0 then
-- Check if tx queue will be read
if apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
v.am.txread := apbi_pwrite and not r.am.txread;
end if;
if apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
v.am.rxread := not r.am.rxread;
end if;
end if;
end if;
if (apbi_psel and apbi_penable) = '1' then
if apbaddr = AMCFG_ADDR then
apbout := zero32(31 downto 9) & r.am.cfg.ecgc & r.am.cfg.lock &
r.am.cfg.erpt & r.am.cfg.seq & r.am.cfg.strict &
r.am.cfg.ovtb & r.am.cfg.ovdb & r.am.active &
r.am.cfg.eact;
if apbi_pwrite = '1' then
v.am.cfg.ecgc := apbi_pwdata(8);
v.am.cfg.lock := apbi_pwdata(7);
v.am.cfg.erpt := apbi_pwdata(6);
v.am.cfg.seq := apbi_pwdata(5);
v.am.cfg.strict := apbi_pwdata(4);
v.am.cfg.ovtb := apbi_pwdata(3);
v.am.cfg.ovdb := apbi_pwdata(2);
v.am.cfg.act := apbi_pwdata(1);
v.spio.astart := apbi_pwdata(1);
v.am.cfg.eact := apbi_pwdata(0);
end if;
elsif apbaddr = AMPER_ADDR then
apbout((AM_CNT_BITS-1)*AM_EN downto 0) := r.am.per;
if apbi_pwrite = '1' then
v.am.per := apbi_pwdata((AM_CNT_BITS-1)*AM_EN downto 0);
end if;
elsif apbaddr = AMMSK0_ADDR then
if FIFO_DEPTH > 32 then
apbout := amask(31 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(31 downto 0) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-1 downto 0) := amask(FIFO_DEPTH-1 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 0) := apbi_pwdata(FIFO_DEPTH-1 downto 0);
end if;
end if;
end if;
elsif apbaddr = AMMSK1_ADDR then
if AM_MSK1_EN then
if FIFO_DEPTH > 64 then
apbout := amask(63 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(63 downto 32) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-33 downto 0) := amask(FIFO_DEPTH-1 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 32) := apbi_pwdata(FIFO_DEPTH-33 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK2_ADDR then
if AM_MSK2_EN then
if FIFO_DEPTH > 96 then
apbout := amask(95 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(95 downto 64) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-65 downto 0) := amask(FIFO_DEPTH-1 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 64) := apbi_pwdata(FIFO_DEPTH-65 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK3_ADDR then
if AM_MSK3_EN then
apbout(FIFO_DEPTH-97 downto 0) := amask(FIFO_DEPTH-1 downto 96);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 96) := apbi_pwdata(FIFO_DEPTH-97 downto 0);
end if;
end if;
else
null;
end if;
elsif apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
apbout(wlen downto 0) :=
r.am.txfifo(conv_integer(apbaddr(FIFO_BITS+1 downto 2)));
else
apbout(wlen downto 0) := tx_do(automode);
end if;
if apbi_pwrite = '1' then
v.am.txwrite := '1';
v.td := apbi_pwdata;
end if;
end if;
elsif apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len)), len);
else
apbout := condhwordswap(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len), len);
end if;
else
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(rx_do(conv_integer(not r.am.rxsel)), len)), len);
else
apbout := condhwordswap(select_data(rx_do(conv_integer(not r.am.rxsel)), len), len);
end if;
end if;
if r.am.unread(conv_integer(r.am.apbaddr)) = '1' then
v.rd_free := '1';
v.am.unread(conv_integer(r.am.apbaddr)) := '0';
v.am.lock := r.am.cfg.lock;
end if;
end if;
end if;
end if;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if syncram = 0 then
v.txfifo(conv_integer(r.tdli)) := ntxd;
else
tx_wr := '1';
end if;
v.tdli := r.tdli + 1;
v.tfreecnt := r.tfreecnt - 1;
v.td_occ := '0';
if r.tfreecnt = FIFO_DEPTH then
v.txdbyp := r.running and r.mode.ms and r.txdupd;
v.txdupd := not r.uf;
tx_rd := '1';
end if;
end if;
-- AM transmit FIFO handling when core is not implemented with SYNCRAM
if syncram = 0 and AM_EN /= 0 and r.am.txwrite = '1' then
if r.mode.rev = '0' then
v.am.txfifo(conv_integer(r.am.apbaddr)) := r.td(wlen downto 0);
else
v.am.txfifo(conv_integer(r.am.apbaddr)) := reverse(r.td)(31-wlen to 31);
end if;
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(conv_integer(r.rdfi)), len));
else
v.rd := select_data(r.rxfifo(conv_integer(r.rdfi)), len);
end if;
else
if r.mode.rev = '0' then
v.rd := reverse(select_data(rx_do(0), len));
else
v.rd := select_data(rx_do(0), len);
end if;
end if;
if not ((ignore > 0) and (spii_ignore = '1')) then
v.rdfi := r.rdfi + 1;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
end if;
if v.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then rx_rd := '1'; end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if ((AM_EN = 0 or r.mode.amen = '0') and (r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.unread /= zero128(FIFO_DEPTH-1 downto 0)) then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
if AM_EN = 1 then v.am.lock := '0'; end if;
end if;
end if;
---------------------------------------------------------------------------
-- Automated periodic transfer control
---------------------------------------------------------------------------
if AM_EN = 1 and r.mode.amen = '1' then
if r.am.active = '0' then
-- Activation either from register write or external event.
v.am.active := r.spio.astart or (astart and r.am.cfg.eact);
v.am.cfg.act := v.am.active;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
end if;
end loop;
v.am.skipdata := '0'; v.am.rxfull := '0';
v.am.cnt := unsigned(r.am.per);
v.event.at := v.am.active;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop1 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop1 := '1';
end if;
end loop;
if v.am.active = '1' then
v.txdupd2 := '1'; tx_rd := '1';
v.tfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '1' then
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
end if;
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop1 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop1 := '1';
end if;
end if;
end loop;
v.cstart := v.am.active;
else
-- Receive fifo handling
if r.am.rxfull = '1' then -- AM RX fifo is filled
-- Move to receive queue if the queue is empty or if there is no
-- requirement on sequential transfers and the queue is not locked.
if (r.event.ne and (v.am.lock or r.am.cfg.seq)) = '0' then
-- Queue is empty
if syncram = 0 then
v.rxfifo := r.am.rxfifo;
else
v.am.rxsel := not r.am.rxsel;
end if;
v.rdfi := (others => '0');
v.rfreecnt := r.am.rfreecnt;
v.rd_free := '0';
v.am.rxfull := '0';
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.unread(i) := '1';
end if;
end loop;
end if;
if r.event.tip = '0' and r.am.at = '1' then
v.event.at := '0';
end if;
if (r.mask.at and r.event.at) = '1' then
v.irq := '1';
end if;
end if;
if r.am.cfg.act = '0' then v.am.active := r.running; end if;
v.am.cfg.eact := '0';
if (r.am.cnt = 0 and r.am.cfg.erpt = '0') or (astart = '1' and r.am.cfg.erpt = '1') then
-- Only allowed to start new transfer if previous transfer(s) is finished
if r.event.tip = '0' then
if (not v.am.rxfull or r.am.cfg.strict) = '1' then
v.am.cnt := unsigned(r.am.per);
end if;
if (not v.am.rxfull or (r.am.cfg.strict and not r.am.cfg.ovtb)) = '1' then
-- Start transfer. Initialize indexes and fifo counter
v.txdupd2 := '1'; tx_rd := '1';
v.am.cnt := unsigned(r.am.per);
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop2 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop2 := '1';
end if;
end if;
end loop;
v.tfreecnt := FIFO_DEPTH;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop2 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop2 := '1';
end if;
end loop;
-- Skip incoming data if receive FIFO is full and OVDB is '1'.
v.am.skipdata := v.am.rxfull and r.am.cfg.ovdb;
if v.am.skipdata = '0' then
-- Clear AM receive fifo if we will overwrite it.
v.am.rfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '0' then
v.am.rfreecnt := v.am.rfreecnt-1;
end if;
end loop;
v.am.rxfull := '0';
end if;
v.event.at := '1';
v.cstart := astart and r.am.cfg.erpt;
end if;
end if;
else
v.am.cnt := r.am.cnt - 1;
end if;
end if;
end if;
---------------------------------------------------------------------------
-- SCK filtering, only used in slave mode
---------------------------------------------------------------------------
fsck := r.psck;
if (r.mode.en and not r.mode.ms) = '1' then
if (r.spii(1).sck xor r.psck) = '0' then
reload := '1';
else
-- Detected SCK change
if r.divcnt = 0 then
v.psck := r.spii(1).sck;
fsck := r.spii(1).sck;
fsck_chg := '1';
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
end if;
elsif r.mode.en = '1' then
v.psck := r.spii(1).sck;
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' and (r.mode.ms = '0' or r.divcnt = 0) then
if r.mode.ms = '1' then
if r.divcnt = 0 then
v.spio.sck := r.mode.cpol;
end if;
v.spio.misooen := INPUT;
if TW_EN = 0 or r.mode.tw = '0' then
if OD_EN = 0 or r.mode.od = '0' then
v.spio.mosioen := OUTPUT;
end if;
else
v.spio.mosioen := INPUT;
end if;
v.spio.sckoen := OUTPUT;
if TW_EN = 1 then v.twdir := OUTPUT xor r.mode.tto; end if;
else
if (spisel or r.mode.tw) = '0' then
v.spio.misooen := OUTPUT;
else
v.spio.misooen := INPUT;
end if;
if (not spisel and r.mode.tw and r.mode.tto) = '0' then
v.spio.mosioen := INPUT;
else
v.spio.mosioen := OUTPUT;
end if;
v.spio.sckoen := INPUT;
if TW_EN = 1 then v.twdir := INPUT xor r.mode.tto; end if;
end if;
if ((((AM_EN = 0 or r.mode.amen = '0') or
(AM_EN = 1 and r.mode.amen = '1' and r.am.active = '1')) and
r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH and r.txdupd = '0' and (AM_EN = 0 or r.txdupd2 = '0')) or
slv_start(spisel, r.mode.cpol, fsck, fsck_chg)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
if r.mode.ms = '1' then
if TW_EN = 0 or r.mode.tw = '0' then
v.spio.mosioen := OUTPUT;
else
v.spio.mosioen := OUTPUT xor r.mode.tto;
end if;
change := not r.mode.cpha;
-- Insert cycles when cpha = '0' to ensure proper setup
-- time for first MOSI value in master mode.
reload := not r.mode.cpha;
end if;
end if;
v.cgcnt := (others => '0');
v.rbitcnt := (others => '0'); v.tbitcnt := (others => '0');
if r.mode.ms = '0' then
update := not (r.mode.cpha or (fsck xor r.mode.cpol));
if r.mode.cpha = '0' then
-- Prepare first bit
v.tbitcnt := (others => '0'); v.tbitcnt(0) := '1';
if v.running = '1' and (TW_EN = 0 or r.mode.tw = '0' or r.twdir = OUTPUT) then
txshift := '1';
end if;
end if;
end if;
-- samp and chng should not be changed on b2b
if spisel /= '0' then
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
if AM_EN = 0 or r.mode.amen = '0' or r.am.cfg.ecgc = '0' then
v.cgcntblock := '0';
else
if r.cstart = '1' then
v.cgcntblock := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if r.mode.ms = '1' and (r.running = '1' or r.divcnt /= 0) then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the fact, div16 and pm register fields.
--
-- With fact = 0 the fields have the same meaning as in the MPC83xx
-- register interface. The clock is divided by 4*([PM]+1) and if div16
-- is set the clock is divided by 16*(4*([PM]+1)).
--
-- With fact = 1 the core's register i/f is no longer compatible with
-- the MPC83xx register interface. The clock is divided by 2*([PM]+1) and
-- if div16 is set the clock is divided by 16*(2*([PM]+1)).
--
-- The generated clock's duty cycle is always 50%.
if r.divcnt = 0 then
if ASEL_EN = 0 or r.aselcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if (r.cgcnt = 0 and (AM_EN = 0 or r.cgcntblock = '0')) or
r.spiolb.sck /= r.mode.cpol then
v.spio.sck := not r.spiolb.sck;
v.toggle := r.running;
end if;
if r.cgcnt /= 0 and (AM_EN = 0 or r.cgcntblock = '0') then
v.cgcnt := r.cgcnt - 1;
if ASEL_EN /= 0 and r.cgcnt = 1 then
cgasel := r.mode.tac;
end if;
end if;
elsif ASEL_EN = 1 then
v.aselcnt := r.aselcnt - 1;
end if;
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
elsif r.mode.ms = '1' then
v.divcnt := (others => '0');
end if;
if reload = '1' then
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if (not r.mode.fact and r.mode.ms) = '1' then
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
if (r.mode.div16 and r.mode.ms) = '1' then
v.divcnt := shift_left(v.divcnt, 4) - 1;
else
v.divcnt(9 downto 4) := (others => '0');
v.divcnt(3 downto 0) := unsigned(r.mode.pm);
end if;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- Sample data
if r.toggle = '1' then
v.samp := not r.samp;
sample := r.samp;
end if;
-- Change data on the clock flank...
if v.toggle = '1' then
v.chng := not r.chng;
change := r.chng;
end if;
-- Detect multiple-master errors (mode-fault)
if spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
v.event.tip := '0';
if AM_EN = 1 then
v.event.at := '0';
end if;
end if;
-- Select input data
if r.mode.loopb = '1' then
indata := r.spiolb.mosi;
elsif TW_EN = 1 and r.mode.tw = '1' then
indata := r.spii(1).mosi;
else
indata := r.spii(1).miso;
end if;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if spisel = '0' then
if fsck_chg = '1' then
sample := r.samp; v.samp := not r.samp;
change := r.chng; v.chng := not r.chng;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if ((AM_EN = 0 or r.mode.amen = '0' ) and (r.rfreecnt = 0 and r.rd_free = '0')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.rfreecnt = 0) or
r.ov = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.twdir = INPUT then
-- Overflow event and IRQ
v.ov := '1';
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
end if;
sample := '0'; -- Prevent sample below
else
sample := not r.mode.ms or r.mode.loopb;
v.syncsamp(0) := not sample;
end if;
if r.rbitcnt = len(log2(wlen+1)-1 downto 0) then
v.rbitcnt := (others => '0');
if TW_EN = 1 then
v.twdir := r.twdir xor not r.mode.loopb;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(r.mode.tw = '1' and r.twdir = INPUT)) then
v.incrdli := not r.ov;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '0' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
v.ov := '0';
if r.tfreecnt = FIFO_DEPTH then
v.running := '0';
-- When running with with SCK freq. at half the system freq. we are
-- past the last edge here and SCK has transitioned from CPOL.
-- Force controller into idle state, only applies to master mode.
if (r.toggle and v.toggle) = '1' then
v.toggle := '0';
v.spio.sck := r.mode.cpol;
v.chng := r.chng;
end if;
end if;
v.uf := '0';
end if;
else
v.rbitcnt := r.rbitcnt + 1;
end if;
end if;
-- Sample data line and put into shift register.
if (r.syncsamp(1) or sample) = '1' then
v.rxd := r.rxd(wlen-1 downto 0) & indata;
if ((r.syncsamp(1) and r.incrdli) or (sample and v.incrdli)) = '1' then
v.rxdone := '1'; v.rxdone2 := '1'; v.incrdli := '0';
end if;
end if;
-- Put data into receive queue
if ((AM_EN = 0 or (r.mode.amen and r.am.skipdata) = '0') and
r.rxdone = '1') then
if AM_EN = 1 and r.am.active = '1'then
if not ((ignore > 0) and (spii_ignore = '1')) then
-- Check mask, maybe we need to skip next word in fifo
v.rdli := r.rdli + 1;
v.am.rfreecnt := v.am.rfreecnt - 1;
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if i > conv_integer(r.rdli) and rstop3 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop3 := '1';
end if;
end if;
end loop;
end if;
end if;
else
v.rdli := r.rdli + 1;
v.rfreecnt := v.rfreecnt - 1;
rx_rd := v.rd_free;
end if;
if syncram = 0 then
if AM_EN = 1 and r.am.active = '1' then
v.am.rxfifo(conv_integer(r.rdli)) := r.rxd;
else
v.rxfifo(conv_integer(r.rdli)) := r.rxd;
end if;
else
rx_wr := '1';
end if;
if r.running = '0' then
if AM_EN = 1 then v.am.rxfull := r.am.active; end if;
end if;
end if;
if AM_EN = 1 and r.mode.amen = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.mode.tto = '0' then
if r.rxdone = '1' then
v.spio.aready := '1';
end if;
else
if r.twdir = '1' and r.twdir2 = '0' then
v.spio.aready := '1';
end if;
end if;
end if;
-- Special case to put data in receive queue for automatic
-- transfer while in three wire mode with tto = 1
if AM_EN = 1 and TW_EN = 1 and r.mode.amen = '1' and
r.mode.tw = '1' and r.running = '0' and r.rxdone2 = '1' and
r.mode.tto = '1' and r.twdir = INPUT and r.mode.ms = '1' then
v.am.rxfull := r.am.active;
end if;
-- Advance transmit queue
if change = '1' then
if TW_EN = 1 and r.mode.tw = '1' then
v.spio.mosioen := r.twdir;
end if;
if r.tbitcnt = len(log2(wlen+1)-1 downto 0) then
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '1' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
if r.uf = '0' then
if not ((ignore > 0) and (spii_ignore = '1')) then
v.tfreecnt := v.tfreecnt + 1;
end if;
end if;
v.txdupd := '1'; tx_rd := '1';
end if;
v.tbitcnt := (others => '0');
else
v.tbitcnt := r.tbitcnt + 1;
end if;
if v.uf = '0' and (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
txshift := v.running;
end if;
end if;
if txshift = '1' then
v.txd := '1' & r.txd(wlen downto 1);
end if;
if AM_EN = 1 then
if r.txdupd2 = '1' then
tx_rd := '1';
v.txdupd := '1';
end if;
end if;
if r.txdupd = '1' then
tx_rd := '1';
if r.txdbyp = '0' then
if syncram = 0 then
if AM_EN = 1 and r.mode.amen = '1' then
v.txd := r.am.txfifo(conv_integer(r.tdfi));
else
v.txd := r.txfifo(conv_integer(r.tdfi));
end if;
else
-- The first FIFO is always used when using syncrams, even in AM mode
v.txd := tx_do(0);
end if;
end if;
-- Data written to TD, bypass
if v.txdbyp = '1' then
v.txd := ntxd;
end if;
if r.tfreecnt /= FIFO_DEPTH then
if AM_EN = 0 or r.mode.amen = '0' then
v.tdfi := v.tdfi + 1;
else
-- Check mask, might need to skip next word
if not (((ignore > 0) and (spii_ignore = '1'))) then
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if tstop3 = '0' and i > conv_integer(v.tdfi) then
if amask(i) = '0' then
v.tdfi := v.tdfi + 1;
else
tstop3 := '1';
end if;
end if;
end loop;
end if;
v.tdfi := v.tdfi + 1;
end if;
end if;
elsif v.txdbyp = '0' then
-- Bus idle value
v.txd(0) := '1';
end if;
end if;
-- Transmit bit
if (change or update) = '1' then
if v.uf = '0' then
v.spio.miso := r.txd(0);
v.spio.mosi := r.txd(0);
if OD_EN = 1 and r.mode.od = '1' then
if (r.mode.ms or r.mode.tw) = '1' then
v.spio.mosioen := r.txd(0) xor OUTPUT;
else
v.spio.misooen := r.txd(0) xor OUTPUT;
end if;
end if;
else
v.spio.miso := '1';
v.spio.mosi := '1';
if OD_EN = 1 and r.mode.od = '1' then
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
end if;
end if;
end if;
-- Transfer in progress interrupt generation
if (not r.running and (r.ov2 or (r.rxdone2 or (not r.mode.ms and r.mode.tw)))) = '1' then
if r.mode.ms = '0' or r.mode.cite = '0' or r.divcnt = 0 then
v.event.tip := '0'; v.rxdone2 := '0';
end if;
end if;
if v.running = '1' then v.event.tip := '1'; end if;
if (v.running and not r.event.tip and r.mask.tip and r.mode.en) = '1' then
v.irq := '1';
end if;
-- LST detection and interrupt generation
if v.running = '0' and v.tfreecnt = FIFO_DEPTH and r.lst = '1' then
v.event.lt := '1'; v.lst := '0';
if (r.mask.lt and not r.event.lt) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- Automatic slave select, only in master mode
---------------------------------------------------------------------------
if ASEL_EN /= 0 then
if (r.mode.ms and r.mode.asel) = '1' then
if ((not r.running and v.running) or -- Transfer start or
(r.event.tip and not v.event.tip) or -- transfer end or
(v.running and (cgasel or -- End or start of CG
(r.cgasel and not (r.spiolb.sck xor r.mode.cpol))))) = '1'
then
v.slvsel := r.aslvsel;
v.aslvsel := r.slvsel;
v.cgasel := '0';
end if;
-- May need to delay start of transfer
if ((not r.running and v.running) or cgasel) = '1' then -- Transfer start
v.aselcnt := unsigned(r.mode.aseldel);
end if;
else
v.cgasel := '0';
v.aselcnt := (others => '0');
end if;
end if;
-- Do not toggle outputs in loopback mode
if (r.mode.loopb = '1' or
(r.mode.tw = '1' and TW_EN = 1 and r.twdir = INPUT)) then
v.spio.mosioen := INPUT; v.spio.misooen := INPUT;
end if;
if r.mode.loopb = '1' then v.spio.sckoen := INPUT; end if;
-- When driving in OD mode, always drive low.
if OD_EN = 1 and (r.mode.od and not r.mode.loopb) = '1' then
v.spio.miso := v.spio.miso and not r.mode.od;
v.spio.mosi := v.spio.mosi and not r.mode.od;
end if;
-- Core is disabled
if ((not RESET_ALL) and rstn = '0') or (r.mode.en = '0') then
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := RES.tdfi; v.rdfi := RES.rdfi;
v.tdli := RES.tdli; v.rdli := RES.rdli;
v.rd_free := RES.rd_free;
v.td_occ := RES.td_occ;
v.lst := RES.lst;
v.uf := RES.uf;
v.ov := RES.ov;
v.running := RES.running;
v.event.tip := RES.event.tip;
v.incrdli := RES.incrdli;
if TW_EN = 1 then
v.twdir := RES.twdir;
end if;
v.spio.miso := RES.spio.miso;
v.spio.mosi := RES.spio.mosi;
if syncrst = 1 or (r.mode.en = '0') then
v.spio.misooen := RES.spio.misooen;
v.spio.mosioen := RES.spio.mosioen;
v.spio.sckoen := RES.spio.sckoen;
end if;
if AM_EN = 1 then
v.event.at := RES.event.at;
end if;
-- Need to assign samp, chng and psck here if spisel is low when the
-- core is enabled
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
if AM_EN = 1 then
v.am.active := RES.am.active;
v.am.cfg.act := RES.am.cfg.act;
v.am.cfg.eact := RES.am.cfg.eact;
v.am.unread := RES.am.unread;
v.am.rxsel := RES.am.rxsel;
end if;
v.rxdone2 := '0';
v.divcnt := (others => '0');
end if;
-- Chip reset
if (not RESET_ALL) and (rstn = '0') then
v.mode := RES.mode;
v.event.tip := RES.event.tip;
v.event.lt := RES.event.lt;
v.event.ov := RES.event.ov;
v.event.un := RES.event.un;
v.event.mme := RES.event.mme;
v.event.ne := RES.event.ne;
v.event.nf := RES.event.nf;
v.mask := RES.mask;
if AM_EN = 1 then
v.event.at := RES.event.at;
if PROG_AM_MASK then
v.am.mask_shdw := RES.am.mask_shdw;
end if;
v.am.per := RES.am.per;
v.am.cfg := RES.am.cfg;
v.am.rxread := RES.am.rxread;
v.am.txwrite := RES.am.txwrite;
v.am.txread := RES.am.txread;
v.am.apbaddr := RES.am.apbaddr;
v.am.rxsel := RES.am.rxsel;
v.cgcntblock := RES.cgcntblock;
end if;
v.lst := RES.lst;
if syncrst = 1 then
v.slvsel := RES.slvsel;
end if;
v.cgcnt := RES.cgcnt;
v.rbitcnt := RES.rbitcnt; v.tbitcnt := RES.tbitcnt;
v.txd := RES.txd;
end if;
-- Drive unused bit if open drain mode is not supported
if OD_EN = 0 then v.mode.od := '0'; end if;
-- Drive unused bits if automode is not supported
if AM_EN = 0 then
v.mode.amen := '0';
--
v.am.cfg.seq := '0';
v.am.cfg.strict := '0';
v.am.cfg.ovtb := '0';
v.am.cfg.ovdb := '0';
v.am.cfg.act := '0';
v.am.cfg.eact := '0';
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.skipdata := '0';
v.am.rxfull := '0';
v.am.rfreecnt := 0;
v.event.at := '0';
v.am.unread := (others=>'0');
v.am.cfg.erpt := '0';
v.am.cfg.lock := '0';
v.am.cfg.ecgc := '0';
v.am.cnt := (others=>'0');
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
v.mask.at := '0';
v.cstart := '0';
end if;
if AM_EN = 0 or not PROG_AM_MASK then
v.am.mask := (others=>'0');
v.am.mask_shdw := (others=>'0');
end if;
-- Drive unused bits if automatic slave select is not enabled
if ASEL_EN = 0 then
v.mode.asel := '0';
v.aslvsel := (others => '0');
v.mode.aseldel := (others => '0');
v.mode.tac := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
end if;
-- Drive unused bits if three-wire mode is not enabled
if TW_EN = 0 then
v.mode.tw := '0';
v.mode.tto := '0';
v.twdir := INPUT;
end if;
if TW_EN = 0 or AM_EN = 0 then
v.twdir2 := INPUT;
end if;
if SLVSEL_EN = 0 then
v.slvsel := (others => '1');
end if;
-- Propagate core enable bit
v.spio.enable := r.mode.en;
-- Synchronize inputs coming from off-chip
v.spii(0) := (spii_miso, spii_mosi, spii_sck, spii_spisel);
v.spii(1) := r.spii(0);
-- Outputs to RAMs
if syncram = 0 then
rx_di <= (others => (others => '0'));
tx_di <= (others => (others => '0'));
rx_ra <= (others => (others => '0'));
rx_wa <= (others => (others => '0'));
tx_ra <= (others => (others => '0'));
tx_wa <= (others => (others => '0'));
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
else
-- TX RAM(s) write
-- TX RAM(s) are either written from TX register or AM TX area
for i in 0 to automode loop
tx_di(i) <= ntxd;
end loop;
for i in 0 to automode loop
tx_wa(i) <= r.tdli;
end loop;
tx_write(0) <= tx_wr;
if AM_EN /= 0 then
-- Auto mode present
-- Write from AM register interface writes both RAMs
-- Write from TXD register writes RAM 0
tx_write(automode) <= r.am.txwrite;
tx_write(0) <= tx_wr or r.am.txwrite;
if r.am.txwrite = '1' then
for i in 0 to automode loop
tx_wa(i) <= r.am.apbaddr;
end loop;
end if;
end if;
-- TX RAM(s) read
-- First RAM is read by bit shift logic
tx_read(0) <= tx_rd;
tx_ra(0) <= r.tdfi;
if AM_EN /= 0 then
-- Second RAM is read from register interface
tx_read(automode) <= v.am.txread or r.am.txread;
tx_ra(automode) <= v.am.apbaddr;
end if;
-- RX RAM(s) write
-- RX RAM(s) is always written from receive shift register
for i in 0 to automode loop
rx_di(i) <= r.rxd;
rx_wa(i) <= r.rdli;
end loop;
rx_write(0) <= rx_wr;
if AM_EN /= 0 then
rx_write(automode) <= '0';
end if;
if AM_EN /= 0 and r.mode.amen = '1' then
-- AM active
-- Handle writes from bit shift logic
if r.am.rxsel = '0' then
rx_write(0) <= rx_wr;
rx_write(automode) <= '0';
else
rx_write(0) <= '0';
rx_write(automode) <= rx_wr;
end if;
end if;
-- RX RAM(s) are read via register interface
for i in 0 to automode loop
rx_ra(i) <= r.rdfi;
rx_read(i) <= rx_rd;
end loop;
if AM_EN /= 0 and r.mode.amen = '1' then
if r.am.rxsel = '0' then
rx_read(0) <= '0';
rx_read(automode) <= v.am.rxread;
if v.am.rxread = '1' then
rx_ra(automode) <= v.am.apbaddr;
end if;
else
rx_read(0) <= v.am.rxread;
rx_read(automode) <= '0';
if v.am.rxread = '1' then
rx_ra(0) <= v.am.apbaddr;
end if;
end if;
end if;
if scantest = 1 and (apbi_scanen and apbi_testen) = '1' then
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
end if;
end if;
v.spiolb.mosi := v.spio.mosi;
v.spiolb.sck := v.spio.sck;
-- Update registers
rin <= v;
-- Update outputs
apbo_prdata <= apbout;
apbo_pirq <= r.irq;
slvsel <= r.slvsel;
spio_miso <= r.spio.miso;
spio_misooen <= r.spio.misooen;
spio_mosi <= r.spio.mosi;
spio_mosioen <= r.spio.mosioen;
spio_sck <= r.spio.sck;
spio_sckoen <= r.spio.sckoen;
spio_enable <= r.spio.enable;
spio_astart <= r.spio.astart;
spio_aready <= r.spio.aready;
if scantest = 1 and apbi_testen = '1' then
spio_misooen <= apbi_testoen;
spio_mosioen <= apbi_testoen;
spio_sckoen <= apbi_testoen;
end if;
end process comb;
-- FIFOs
fiforams : if syncram /= 0 generate
fifoloop : for i in 0 to automode generate
noft : if ft = 0 generate
rxfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i));
-- testin => testin);
txfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i));
-- testin => testin);
end generate noft;
ftfifos : if ft /= 0 generate
ftrxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i),
error => open);
-- testin => testin);
fttxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i),
error => open);
-- testin => testin);
end generate ftfifos;
end generate fifoloop;
end generate fiforams;
nofiforams : if syncram = 0 generate
rx_do <= (others => (others => '0'));
tx_do <= (others => (others => '0'));
end generate;
-- Registers
reg: process (clk, arstn)
begin -- process reg
if rising_edge(clk) then
r <= rin;
if rstn = '0' then
r.spio.sck <= RES.spio.sck;
r.rbitcnt <= RES.rbitcnt; r.tbitcnt <= RES.tbitcnt;
if RESET_ALL then
r <= RES;
-- Do not use synchronous reset for sync. registers
r.spii <= rin.spii;
end if;
end if;
end if;
if syncrst = 0 and arstn = '0' then
r.spio.misooen <= RES.spio.misooen;
r.spio.mosioen <= RES.spio.mosioen;
r.spio.sckoen <= RES.spio.sckoen;
if SLVSEL_EN /= 0 then
r.slvsel <= RES.slvsel;
end if;
end if;
end process reg;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
break: out std_logic;
intack: out std_logic;
rstreq: out std_logic;
edbg: in memory_debug_type
);
end xtc;
architecture behave of xtc is
signal fuo: fetch_output_type;
signal duo: decode_output_type;
signal fduo: fetchdata_output_type;
signal euo: execute_output_type;
signal muo: memory_output_type;
signal rbw1_addr: regaddress_type;
signal rbw1_wr: std_logic_vector(31 downto 0);
signal rbw1_we: std_logic;
signal rbw1_en: std_logic;
signal rbw2_addr: regaddress_type;
signal rbw2_wr: std_logic_vector(31 downto 0);
signal rbw2_we: std_logic := '0';
signal rbw2_en: std_logic := '0';
signal rb1_addr: regaddress_type;
signal rb1_en: std_logic;
signal rb1_rd: std_logic_vector(31 downto 0);
signal rb2_addr: regaddress_type;
signal rb2_en: std_logic;
signal rb2_rd: std_logic_vector(31 downto 0);
signal jumpaddr: word_type;
signal cache_valid: std_logic;
signal dcache_flush: std_logic;
signal dcache_inflush: std_logic;
signal icache_flush: std_logic;
signal icache_abort: std_logic;
signal cache_data: std_logic_vector(31 downto 0);
signal cache_address: std_logic_vector(31 downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal cache_seq: std_logic;
signal cache_nseq: std_logic;
signal decode_freeze: std_logic;
signal w_en: std_logic;
signal w_addr: regaddress_type;
signal memory_busy: std_logic;
signal execute_busy: std_logic;
signal wb_busy: std_logic;
signal refetch: std_logic;
signal dual: std_logic;
signal allvalid: std_logic;
signal notallvalid: std_logic;
signal e_busy: std_logic;
--signal refetch_registers: std_logic;
signal freeze_decoder: std_logic;
signal executed: boolean;
component tracer is
port (
clk: in std_logic;
dbgi: in execute_debug_type
);
end component tracer;
signal dbg: execute_debug_type;
signal mdbg: memory_debug_type;
signal cifo: copifo;
signal cifi: copifi;
signal co: copo_a;
signal ci: copi_a;
signal mwbi: wb_miso_type;
signal mwbo: wb_mosi_type;
signal immu_tlbw: std_logic:='0';
signal immu_tlbv: tlb_entry_type;
signal immu_tlba: std_logic_vector(2 downto 0):="000";
signal immu_context: std_logic_vector(5 downto 0):=(others => '0');
signal immu_paddr: std_logic_vector(31 downto 0);
signal immu_valid: std_logic;
signal immu_enabled: std_logic:='1';
signal cache_tag: std_logic_vector(31 downto 0);
signal dcache_accesstype: std_logic_vector(1 downto 0);
signal flushfd: std_logic;
signal clrhold: std_logic;
signal internalfault: std_logic;
signal pipeline_internalfault: std_logic;
signal busycnt: unsigned (31 downto 0);
signal proten: std_logic;
signal protw: std_logic_vector(31 downto 0);
signal rstreq_i: std_logic;
signal fflags: std_logic_vector(31 downto 0);
signal intin: std_logic_vector(31 downto 0);
signal trappc: std_logic_vector(31 downto 0);
signal trapaddr: std_logic_vector(31 downto 0);
signal trapbase: std_logic_vector(31 downto 0);
signal istrap: std_logic;
begin
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if pipeline_internalfault='1' then
fflags(0) <= execute_busy;
fflags(1) <= notallvalid;
fflags(2) <= freeze_decoder;
fflags(3) <= wb_busy;
fflags(4) <= memory_busy;
fflags(5) <= dbg.hold;
fflags(6) <= dbg.multvalid;
fflags(7) <= dbg.trap;
end if;
end if;
end process;
rstreq_i<= pipeline_internalfault ;
rstreq <= rstreq_i;
-- synthesis translate_off
trc: tracer
port map (
clk => wb_syscon.clk,
dbgi => dbg
);
-- synthesis translate_on
-- Register bank.
rbe: entity work.regbank_3p
generic map (
ADDRESS_BITS => 5,
ZEROSIZE => 4
)
port map (
clk => wb_syscon.clk,
rb1_en => rb1_en,
rb1_addr=> rb1_addr,
rb1_rd => rb1_rd,
rb2_en => rb2_en,
rb2_addr=> rb2_addr,
rb2_rd => rb2_rd,
rb3_en => rbw1_en,
rb3_we => rbw1_we,
rb3_addr=> rbw1_addr,
rb3_wr => rbw1_wr
);
cache: if INSTRUCTION_CACHE generate
cache: entity work.icache
generic map (
ADDRESS_HIGH => 31
)
port map (
syscon => wb_syscon,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => icache_flush,
abort => icache_abort,
seq => cache_seq,
tag => cache_tag,
tagen => immu_enabled,
mwbi => romwbi,
mwbo => romwbo
);
mmub: if MMU_ENABLED generate
cache_tag <= immu_paddr;
immuinst: entity work.mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
addr => cache_address,
ctx => immu_context,
en => cache_strobe,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
paddr => immu_paddr,
valid => immu_valid,
pw => open,
pr => open,
px => open,
ps => open
);
end generate;
end generate;
--romwbo.we<='0';
nocache: if not INSTRUCTION_CACHE generate
-- Hack... we need to provide a solution for ACK being held low
-- when no pipelined transaction exists
-- For now, the romram is hacked to do it.
--nopipe: if not EXTRA_PIPELINE generate
cache_valid <= romwbi.ack;
cache_data <= romwbi.dat;
romwbo.adr <= cache_address;
romwbo.stb <= cache_strobe;
romwbo.cyc <= cache_enable;
cache_stall <= romwbi.stall;
--end generate;
end generate;
fetch_unit: entity work.fetch
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Connection to ROM
stall => cache_stall,
valid => cache_valid,
address => cache_address,
read => cache_data,
enable => cache_enable,
strobe => cache_strobe,
abort => icache_abort,
seq => cache_seq,
nseq => cache_nseq,
freeze => decode_freeze,
jump => euo.jump,
jumppriv => euo.jumppriv,
jumpaddr => euo.r.jumpaddr,
dual => dual,
-- Outputs for next stages
fuo => fuo
);
decode_unit: entity work.decode
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Input from fetch unit
fui => fuo,
-- Outputs for next stages
duo => duo,
busy => decode_freeze,
freeze => freeze_decoder,
dual => dual,
flush => euo.jump, -- DELAY SLOT when fetchdata is passthrough
jump => euo.jump,
jumpmsb => euo.r.jumpaddr(1)
);
freeze_decoder <= execute_busy or notallvalid;
flushfd <= euo.jump or euo.trap;
fetchdata_unit: entity work.fetchdata
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
r1_en => rb1_en,
r1_addr => rb1_addr,
r1_read => rb1_rd,
r2_en => rb2_en,
r2_addr => rb2_addr,
r2_read => rb2_rd,
freeze => execute_busy,
flush => flushfd,-- euo.jump, -- DELAY SLOT
refetch => notallvalid, --refetch_registers,--execute_busy,-- TEST TEST: was refetch,
w_addr => w_addr,
w_en => w_en,
executed => executed,
clrhold => euo.clrhold,
-- Input from decode unit
dui => duo,
-- Outputs for next stages
fduo => fduo
);
busycheck: block
signal dirtyReg: regaddress_type;
signal dirty: std_logic;
signal v1,v2,v3: std_logic;
signal isBlocking: std_logic;
signal canProceed: std_logic;
begin
v1 <= '0' when dirty='1' and rb1_en='1' and rb1_addr=dirtyReg else '1';
v2 <= '0' when dirty='1' and rb2_en='1' and rb2_addr=dirtyReg else '1';
v3 <= '0' when dirty='1' and w_en='1' and w_addr=dirtyReg else '1';
isBlocking <= '1' when duo.r.valid='1' and ( duo.r.blocks='1' )
and execute_busy='0' and euo.jump='0'
and allvalid='1' and euo.trap='0'
else '0';
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
dirty <= '0';
dirtyReg <= (others => '0'); -- X
else
if isBlocking='1' and dirty='0' then -- and duo.r.sra2/="0000"
dirty <= '1';
dirtyReg <= duo.r.sra2;
end if;
-- Memory reads clear flags.
if muo.mregwe='1' and dirty='1' then
-- TODO here: why not use only the memory wb, rather than all wb ?
if (dirtyReg=muo.mreg) then
dirty <= '0';
dirtyReg <= (others => 'X');
--if (dirtyReg /= muo.mreg) then
-- report "Omg.. clearing reg " &hstr(muo.mreg) & ", but dirty register is "&hstr(dirtyReg) severity failure;
end if;
end if;
if muo.fault='1' then
dirty <= '0';
end if;
end if;
end if;
end process;
canProceed <= '0' when (dirty='1' and duo.r.valid='1' and duo.r.blocks='1') else '1';
allvalid <= v1 and v2 and v3 and canProceed;
notallvalid <= not allvalid;
end block;
execute_busy <= e_busy;
executed <= euo.executed;
execute_unit: entity work.execute
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => e_busy,
mem_busy => memory_busy,
wb_busy => wb_busy,
refetch => refetch,
int => wbi.int,
nmi => nmi,
nmiack => nmiack,
intline => x"00",
-- Input from fetchdata unit
fdui => fduo,
-- Outputs for next stages
euo => euo,
-- Input from memory unit (spr update)
mui => muo,
-- COP
co => cifo,
ci => cifi,
-- Trap
trappc => trappc,
istrap => istrap,
trapbase => trapbase,
-- Debug
dbgo => dbg
);
-- MMU cop
copmmuinst: entity work.cop_mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
mmuen => immu_enabled,
proten => proten,
protw => protw,
dbgi => dbg,
mdbgi => mdbg,--edbg,
fflags => fflags,
ci => ci(1),
co => co(1)
);
coparbinst: entity work.cop_arb
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
cfi => cifo,
cfo => cifi,
ci => co,
co => ci
);
-- MMU cop
copsysinst: entity work.cop_sys
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
icache_flush => icache_flush,
dcache_flush => dcache_flush,
dcache_inflush => dcache_inflush,
int_in => x"00000000",
trappc => trappc,
trapaddr => trapaddr,
istrap => istrap,
trapbase => trapbase,
--intacken => '0',
ci => ci(0),
co => co(0)
);
dcachegen: if DATA_CACHE generate
dcache_accesstype <= ACCESS_NOCACHE when mwbo.adr(31)='1' else
ACCESS_WT;
dcacheinst: entity work.dcache
generic map (
ADDRESS_HIGH => 31,
CACHE_MAX_BITS => 13, -- 8 Kb
CACHE_LINE_SIZE_BITS => 6 -- 64 bytes
)
port map (
syscon => wb_syscon,
ci.data => mwbo.dat,
ci.address => mwbo.adr,
ci.strobe => mwbo.stb,
ci.we => mwbo.we,
ci.wmask => mwbo.sel,
ci.enable => mwbo.cyc,
ci.tag => mwbo.tag,
ci.flush => dcache_flush,
ci.accesstype => dcache_accesstype,
co.in_flush => dcache_inflush,
co.data => mwbi.dat,
co.stall => mwbi.stall,
co.valid => mwbi.ack,
co.tag => mwbi.tag,
co.err => mwbi.err,
mwbi => wbi,
mwbo => wbo
);
end generate;
nodcache: if not DATA_CACHE generate
wbo<=mwbo;
mwbi<=wbi;
end generate;
memory_unit: entity work.memory
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Memory interface
wb_ack_i => mwbi.ack,
wb_err_i => mwbi.err,
wb_dat_i => mwbi.dat,
wb_dat_o => mwbo.dat,
wb_adr_o => mwbo.adr,
wb_cyc_o => mwbo.cyc,
wb_stb_o => mwbo.stb,
wb_sel_o => mwbo.sel,
wb_tag_o => mwbo.tag,
wb_tag_i => mwbi.tag,
wb_we_o => mwbo.we,
wb_stall_i => mwbi.stall,
dbgo => mdbg,
refetch => refetch,
busy => memory_busy,
proten => proten,
protw => protw,
-- Input for previous stages
eui => euo,
-- Output for next stages
muo => muo
);
writeback_unit: entity work.writeback
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => wb_busy,
r0_en => rbw1_en,
r0_we => rbw1_we,
r0_addr => rbw1_addr,
r0_write => rbw1_wr,
r1_en => rbw2_en,
r1_we => rbw2_we,
r1_addr => rbw2_addr,
r1_write => rbw2_wr,
--r_read => rbw_rd,
-- Input from previous stage
mui => muo,
eui => euo -- for fast register write
);
faultcheck: if FAULTCHECKS generate
-- Internal pipeline fault...
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
busycnt<=(others =>'0');
else
if execute_busy='1' or notallvalid='1' or freeze_decoder='1' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
pipeline_internalfault<='1' when busycnt > 65535 else '0';
end generate;
nofaultchecks: if not FAULTCHECKS generate
pipeline_internalfault<='0';
end generate;
-- synthesis translate_off
process
begin
wait on muo.internalfault;
if muo.internalfault'event and muo.internalfault='1' then
wait until rising_edge(wb_syscon.clk);
wait until rising_edge(wb_syscon.clk);
report "Internal memory fault" severity failure;
end if;
end process;
-- synthesis translate_on
end behave;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:40:17 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block;
ARCHITECTURE rtl OF Complex3Multiply_block IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_sum : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdl_3_3_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_3_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfIm : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfSum : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg1 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_re_reg2 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_im_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_tmpResult_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL multResFP_re : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL multResFP_im : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL twdlXdin_3_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_3_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 18) + resize(din_im_reg, 18);
twdl_3_3_re_signed <= signed(twdl_3_3_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_3_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_3_im_signed <= signed(twdl_3_3_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_3_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 36);
Complex3Add_tmpResult_reg <= to_signed(0, 36);
Complex3Add_multRes_re_reg1 <= to_signed(0, 35);
Complex3Add_multRes_re_reg2 <= to_signed(0, 35);
Complex3Add_multRes_im_reg <= to_signed(0, 37);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(34 DOWNTO 0);
VARIABLE sub_cast_0 : signed(34 DOWNTO 0);
VARIABLE sub_cast_1 : signed(36 DOWNTO 0);
VARIABLE sub_cast_2 : signed(36 DOWNTO 0);
VARIABLE add_cast : signed(34 DOWNTO 0);
VARIABLE add_cast_0 : signed(34 DOWNTO 0);
VARIABLE add_temp : signed(34 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 35);
sub_cast_0 := resize(prodOfIm, 35);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 37);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 37);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 35);
add_cast_0 := resize(prodOfIm, 35);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 36);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_3_re_tmp <= multResFP_re(31 DOWNTO 15);
twdlXdin_3_re <= std_logic_vector(twdlXdin_3_re_tmp);
twdlXdin_3_im_tmp <= multResFP_im(31 DOWNTO 15);
twdlXdin_3_im <= std_logic_vector(twdlXdin_3_im_tmp);
END rtl;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library work;
use work.transaction_pkg.all;
use work.axi_bfm_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
aid : std_logic_vector(C_VVC_CMD_ID_MAX_LENGTH-1 downto 0);
id : std_logic_vector(C_VVC_CMD_ID_MAX_LENGTH-1 downto 0);
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
len : unsigned(7 downto 0);
size : integer range 1 to 128;
burst : t_axburst;
lock : t_axlock;
cache : std_logic_vector(3 downto 0);
prot : t_axprot;
qos : std_logic_vector(3 downto 0);
region : std_logic_vector(3 downto 0);
resp : t_xresp;
auser : std_logic_vector(C_VVC_CMD_USER_MAX_LENGTH-1 downto 0);
user : std_logic_vector(C_VVC_CMD_USER_MAX_LENGTH-1 downto 0);
user_array : t_slv_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1)(C_VVC_CMD_USER_MAX_LENGTH-1 downto 0);
data_array : t_slv_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
resp_array : t_xresp_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1);
strb_array : t_slv_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1)(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => NO_OPERATION, -- Default unless overwritten by a common operation
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL,
-- VVC dedicated fields
aid => (others => '0'),
id => (others => '0'),
addr => (others => '0'),
len => (others => '0'),
size => 1,
burst => INCR,
lock => NORMAL,
cache => (others => '0'),
prot => UNPRIVILEGED_NONSECURE_DATA,
qos => (others => '0'),
region => (others => '0'),
resp => OKAY,
auser => (others => '0'),
user => (others => '0'),
user_array => (others=>(others=>'0')),
data_array => (others=>(others=>'0')),
resp_array => (others=>OKAY),
strb_array => (others=>(others=>'1'))
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
type t_vvc_result is record
len : natural range 0 to 255; -- Actual length = len+1 (Same interpretation as axlen)
rid : std_logic_vector(C_VVC_CMD_ID_MAX_LENGTH-1 downto 0);
rdata : t_slv_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
rresp : t_xresp_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1);
ruser : t_slv_array(0 to C_VVC_CMD_MAX_BURST_WORDS-1)(C_VVC_CMD_USER_MAX_LENGTH-1 downto 0);
end record;
constant C_EMPTY_VVC_RESULT : t_vvc_result := (
len => 0,
rid => (others=>'0'),
rdata => (others=>(others=>'0')),
rresp => (others=>OKAY),
ruser => (others=>(others=>'0')));
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
--==========================================================================================
-- Procedures
--==========================================================================================
function to_string(
result : t_vvc_result
) return string;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a record type
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.rdata'length) & " Symbols";
end;
end package body vvc_cmd_pkg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_zed_vga_0_0 -prefix
-- system_zed_vga_0_0_ system_zed_vga_0_0_sim_netlist.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_vga_0_0 is
port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_vga_0_0 : entity is "system_zed_vga_0_0,zed_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_vga_0_0 : entity is "zed_vga,Vivado 2016.4";
end system_zed_vga_0_0;
architecture STRUCTURE of system_zed_vga_0_0 is
signal \^rgb565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb565\(15 downto 12) <= rgb565(15 downto 12);
\^rgb565\(10 downto 7) <= rgb565(10 downto 7);
\^rgb565\(4 downto 1) <= rgb565(4 downto 1);
vga_b(3 downto 0) <= \^rgb565\(4 downto 1);
vga_g(3 downto 0) <= \^rgb565\(10 downto 7);
vga_r(3 downto 0) <= \^rgb565\(15 downto 12);
end STRUCTURE;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML605"; -- ML605 - Xilinx Virtex 6 reference design board: XC6VLX240T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
package body my_config is
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML605"; -- ML605 - Xilinx Virtex 6 reference design board: XC6VLX240T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
package body my_config is
end package body;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:44 03/25/2016
-- Design Name:
-- Module Name: REG_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity REG_CTL is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OPC4 : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end REG_CTL;
architecture Dataflow of REG_CTL is
begin
with OPC select RD_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
'1' when OTHERS; -- always enable reading
with OPC4 select WR_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1011",
'0' when OTHERS;
end Dataflow;
--architecture Behavioral of REG_CTL is
--
--begin
-- process(CLK)
-- begin
-- if (rising_edge(CLK)) then
-- case OPC is
-- when "0000" => RD_EN <= '1';
-- when "0001" => RD_EN <= '1';
-- when "0010" => RD_EN <= '1';
-- when "0011" => RD_EN <= '1';
-- when "0100" => RD_EN <= '1';
-- when "0101" => RD_EN <= '1';
-- when "0110" => RD_EN <= '1';
-- when "0111" => RD_EN <= '1';
-- when "1000" => RD_EN <= '1';
-- when "1001" => RD_EN <= '1';
-- when others => RD_EN <= '0';
-- end case;
-- end if;
--
---- if (OPC = "1001") then
---- RD_EN <= '0';
---- else
---- RD_EN <= '1';
---- end if;
-- if (falling_edge(CLK)) then
-- case OPC4 is
-- when "0000" => WR_EN <= '1';
-- when "0001" => WR_EN <= '1';
-- when "0010" => WR_EN <= '1';
-- when "0011" => WR_EN <= '1';
-- when "0100" => WR_EN <= '1';
-- when "0101" => WR_EN <= '1';
-- when "0110" => WR_EN <= '1';
-- when "0111" => WR_EN <= '1';
-- when "1000" => WR_EN <= '1';
-- when "1010" => WR_EN <= '1';
-- when others => WR_EN <= '0';
-- end case;
--
---- if (OPC4 = "1010") then
---- WR_EN <= '0';
---- else
---- WR_EN <= '1';
---- end if;
-- end if;
-- end process;
--
--end Behavioral;
--
|
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers. If
-- the signal is a strobe, the edge can be specified.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end entity;
architecture RTL of synchronizer is
component edge_detect
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic;
reset : in std_logic;
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
signal async_meta1 : std_logic;
signal async_meta2 : std_logic;
begin
proc_synchronize : process(clk,reset)
begin
if (reset = '1') then
async_meta1 <= RESET_OUTPUT;
async_meta2 <= RESET_OUTPUT;
else
if rising_edge(clk) then
async_meta1 <= async;
async_meta2 <= async_meta1;
end if;
end if;
end process;
gen_if_use_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) /= 'N') generate
inst_edge_detect : edge_detect
generic map (
EDGE => STROBE_EDGE)
port map (
clk => clk,
reset => reset,
input_detect => async_meta2,
edge_detect_stb => sync);
end generate;
gen_if_no_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) = 'N') generate
sync <= async_meta2;
end generate;
end RTL; |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers. If
-- the signal is a strobe, the edge can be specified.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end entity;
architecture RTL of synchronizer is
component edge_detect
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic;
reset : in std_logic;
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
signal async_meta1 : std_logic;
signal async_meta2 : std_logic;
begin
proc_synchronize : process(clk,reset)
begin
if (reset = '1') then
async_meta1 <= RESET_OUTPUT;
async_meta2 <= RESET_OUTPUT;
else
if rising_edge(clk) then
async_meta1 <= async;
async_meta2 <= async_meta1;
end if;
end if;
end process;
gen_if_use_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) /= 'N') generate
inst_edge_detect : edge_detect
generic map (
EDGE => STROBE_EDGE)
port map (
clk => clk,
reset => reset,
input_detect => async_meta2,
edge_detect_stb => sync);
end generate;
gen_if_no_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) = 'N') generate
sync <= async_meta2;
end generate;
end RTL; |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lightAverager is
port (
CLK : in std_logic;
CE : in std_logic;
START : in std_logic;
YPOS : in std_logic_vector(5 downto 0);
LINE_BUF_ADDR : out std_logic_vector(6 downto 0);
LINE_BUF_DATA : in std_logic_vector(23 downto 0);
CONFIG_ADDR : out std_logic_vector(8 downto 0);
CONFIG_DATA : in std_logic_vector(31 downto 0);
RESULT_CLK : in std_logic;
RESULT_ADDR : in std_logic_vector(8 downto 0);
RESULT_DATA : out std_logic_vector(31 downto 0)
);
end lightAverager;
architecture Behavioral of lightAverager is
COMPONENT resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- count is overflow (1), xpos (6), light (8), read/write (1) = 16 bits
signal COUNT : std_logic_vector(15 downto 0);
signal FRAME : std_logic := '0';
signal RUNNING : std_logic;
signal WRITE_CYCLE : std_logic;
signal XPOS : std_logic_vector(5 downto 0);
signal LIGHT_ADDR : std_logic_vector(7 downto 0);
signal WRITE_ENABLE : std_logic;
signal WRITE_ADDR : std_logic_vector(7 downto 0);
signal WRITE_DATA : std_logic_vector(71 downto 0);
signal RESULT_RAM_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_WE : std_logic_vector(0 downto 0);
signal RESULT_RAM_D : std_logic_vector(71 downto 0);
signal RESULT_RAM_Q : std_logic_vector(71 downto 0);
signal RESULT_RAM_B_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_B_Q : std_logic_vector(71 downto 0);
signal XMIN_p0 : std_logic_vector(5 downto 0);
signal XMAX_p0 : std_logic_vector(5 downto 0);
signal YMIN_p0 : std_logic_vector(5 downto 0);
signal YMAX_p0 : std_logic_vector(5 downto 0);
signal SHIFT_p0 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p0 : std_logic_vector(2 downto 0);
signal R_TOTAL_p0 : std_logic_vector(20 downto 0);
signal G_TOTAL_p0 : std_logic_vector(20 downto 0);
signal B_TOTAL_p0 : std_logic_vector(20 downto 0);
signal R_p0 : std_logic_vector(7 downto 0);
signal G_p0 : std_logic_vector(7 downto 0);
signal B_p0 : std_logic_vector(7 downto 0);
signal WRITE_ADDR_p0 : std_logic_vector(7 downto 0);
signal XPOS_p0 : std_logic_vector(5 downto 0);
signal YPOS_p0 : std_logic_vector(5 downto 0);
signal RUNNING_p0 : std_logic;
signal SHIFT_p1 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p1 : std_logic_vector(2 downto 0);
signal R_TOTAL_p1 : std_logic_vector(20 downto 0);
signal G_TOTAL_p1 : std_logic_vector(20 downto 0);
signal B_TOTAL_p1 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p1 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p1 : std_logic;
signal OUT_ADDR_p2 : std_logic_vector(2 downto 0);
signal R_TOTAL_p2 : std_logic_vector(20 downto 0);
signal G_TOTAL_p2 : std_logic_vector(20 downto 0);
signal B_TOTAL_p2 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p2 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p2 : std_logic;
begin
resultBuffer : resultRam
PORT MAP (
clka => CLK,
ena => CE,
wea => RESULT_RAM_WE,
addra => RESULT_RAM_ADDR,
dina => RESULT_RAM_D,
douta => RESULT_RAM_Q,
clkb => RESULT_CLK,
web => "0",
addrb => RESULT_RAM_B_ADDR,
dinb => (others=> '0'),
doutb => RESULT_RAM_B_Q
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(START = '1') then
COUNT <= (others => '0');
RUNNING <= '1';
if(YPOS = "000000") then
FRAME <= not FRAME;
end if;
elsif(COUNT(15) = '1') then
RUNNING <= '0';
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
-- read address is set when write_cycle = '0'
-- so read data is available when write_cycle = '1'
if(WRITE_CYCLE = '1') then
XMIN_p0 <= CONFIG_DATA(5 downto 0);
XMAX_p0 <= CONFIG_DATA(11 downto 6);
YMIN_p0 <= CONFIG_DATA(17 downto 12);
YMAX_p0 <= CONFIG_DATA(23 downto 18);
SHIFT_p0 <= CONFIG_DATA(27 downto 24);
OUT_ADDR_p0 <= CONFIG_DATA(30 downto 28);
R_TOTAL_p0 <= RESULT_RAM_Q(20 downto 0);
G_TOTAL_p0 <= RESULT_RAM_Q(41 downto 21);
B_TOTAL_p0 <= RESULT_RAM_Q(62 downto 42);
R_p0 <= LINE_BUF_DATA(23 downto 16);
G_p0 <= LINE_BUF_DATA(15 downto 8);
B_p0 <= LINE_BUF_DATA( 7 downto 0);
WRITE_ADDR_p0 <= LIGHT_ADDR;
XPOS_p0 <= XPOS;
YPOS_p0 <= YPOS;
RUNNING_p0 <= RUNNING;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(RUNNING_p0 = '1' and
unsigned(XPOS_p0) >= unsigned(XMIN_p0) and unsigned(XPOS_p0) <= unsigned(XMAX_p0) and
unsigned(YPOS_p0) >= unsigned(YMIN_p0) and unsigned(YPOS_p0) <= unsigned(YMAX_p0)) then
WRITE_ENABLE_p1 <= '1';
else
WRITE_ENABLE_p1 <= '0';
end if;
if(XPOS_p0 = XMIN_p0 and YPOS_p0 = YMIN_p0) then
R_TOTAL_p1 <= "0000000000000" & R_p0;
G_TOTAL_p1 <= "0000000000000" & G_p0;
B_TOTAL_p1 <= "0000000000000" & B_p0;
else
R_TOTAL_p1 <= std_logic_vector(unsigned(R_TOTAL_p0) + unsigned(R_p0));
G_TOTAL_p1 <= std_logic_vector(unsigned(G_TOTAL_p0) + unsigned(G_p0));
B_TOTAL_p1 <= std_logic_vector(unsigned(B_TOTAL_p0) + unsigned(B_p0));
end if;
if(XPOS_p0 = XMAX_p0 and YPOS_p0 = YMAX_p0) then
SHIFT_p1 <= SHIFT_p0;
else
SHIFT_p1 <= (others => '0');
end if;
WRITE_ADDR_p1 <= WRITE_ADDR_p0;
OUT_ADDR_p1 <= OUT_ADDR_p0;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
R_TOTAL_p2 <= std_logic_vector(unsigned(R_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
G_TOTAL_p2 <= std_logic_vector(unsigned(G_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
B_TOTAL_p2 <= std_logic_vector(unsigned(B_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
WRITE_ENABLE_p2 <= WRITE_ENABLE_p1;
WRITE_ADDR_p2 <= WRITE_ADDR_p1;
OUT_ADDR_p2 <= OUT_ADDR_p1;
end if;
end if;
end process;
WRITE_ENABLE <= '1' when WRITE_ENABLE_p2 = '1' and WRITE_CYCLE = '1' else '0';
WRITE_ADDR <= WRITE_ADDR_p2;
WRITE_DATA(20 downto 0) <= R_TOTAL_p2;
WRITE_DATA(41 downto 21) <= G_TOTAL_p2;
WRITE_DATA(62 downto 42) <= B_TOTAL_p2;
WRITE_DATA(65 downto 63) <= OUT_ADDR_p2;
WRITE_DATA(71 downto 66) <= (others => '0');
WRITE_CYCLE <= COUNT(0);
LIGHT_ADDR <= COUNT(8 downto 1);
XPOS <= COUNT(14 downto 9);
CONFIG_ADDR <= "0" & LIGHT_ADDR;
LINE_BUF_ADDR <= YPOS(0) & XPOS;
RESULT_RAM_ADDR <= (not FRAME) & LIGHT_ADDR when WRITE_CYCLE = '0' else (not FRAME) & WRITE_ADDR;
RESULT_RAM_WE(0) <= '0' when WRITE_CYCLE = '0' else WRITE_ENABLE;
RESULT_RAM_D <= WRITE_DATA;
RESULT_RAM_B_ADDR <= FRAME & RESULT_ADDR(7 downto 0);
RESULT_DATA( 7 downto 0) <= RESULT_RAM_B_Q( 7 downto 0);
RESULT_DATA(15 downto 8) <= RESULT_RAM_B_Q(28 downto 21);
RESULT_DATA(23 downto 16) <= RESULT_RAM_B_Q(49 downto 42);
RESULT_DATA(26 downto 24) <= RESULT_RAM_B_Q(65 downto 63);
RESULT_DATA(31 downto 27) <= (others => '0');
end Behavioral;
|
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lightAverager is
port (
CLK : in std_logic;
CE : in std_logic;
START : in std_logic;
YPOS : in std_logic_vector(5 downto 0);
LINE_BUF_ADDR : out std_logic_vector(6 downto 0);
LINE_BUF_DATA : in std_logic_vector(23 downto 0);
CONFIG_ADDR : out std_logic_vector(8 downto 0);
CONFIG_DATA : in std_logic_vector(31 downto 0);
RESULT_CLK : in std_logic;
RESULT_ADDR : in std_logic_vector(8 downto 0);
RESULT_DATA : out std_logic_vector(31 downto 0)
);
end lightAverager;
architecture Behavioral of lightAverager is
COMPONENT resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- count is overflow (1), xpos (6), light (8), read/write (1) = 16 bits
signal COUNT : std_logic_vector(15 downto 0);
signal FRAME : std_logic := '0';
signal RUNNING : std_logic;
signal WRITE_CYCLE : std_logic;
signal XPOS : std_logic_vector(5 downto 0);
signal LIGHT_ADDR : std_logic_vector(7 downto 0);
signal WRITE_ENABLE : std_logic;
signal WRITE_ADDR : std_logic_vector(7 downto 0);
signal WRITE_DATA : std_logic_vector(71 downto 0);
signal RESULT_RAM_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_WE : std_logic_vector(0 downto 0);
signal RESULT_RAM_D : std_logic_vector(71 downto 0);
signal RESULT_RAM_Q : std_logic_vector(71 downto 0);
signal RESULT_RAM_B_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_B_Q : std_logic_vector(71 downto 0);
signal XMIN_p0 : std_logic_vector(5 downto 0);
signal XMAX_p0 : std_logic_vector(5 downto 0);
signal YMIN_p0 : std_logic_vector(5 downto 0);
signal YMAX_p0 : std_logic_vector(5 downto 0);
signal SHIFT_p0 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p0 : std_logic_vector(2 downto 0);
signal R_TOTAL_p0 : std_logic_vector(20 downto 0);
signal G_TOTAL_p0 : std_logic_vector(20 downto 0);
signal B_TOTAL_p0 : std_logic_vector(20 downto 0);
signal R_p0 : std_logic_vector(7 downto 0);
signal G_p0 : std_logic_vector(7 downto 0);
signal B_p0 : std_logic_vector(7 downto 0);
signal WRITE_ADDR_p0 : std_logic_vector(7 downto 0);
signal XPOS_p0 : std_logic_vector(5 downto 0);
signal YPOS_p0 : std_logic_vector(5 downto 0);
signal RUNNING_p0 : std_logic;
signal SHIFT_p1 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p1 : std_logic_vector(2 downto 0);
signal R_TOTAL_p1 : std_logic_vector(20 downto 0);
signal G_TOTAL_p1 : std_logic_vector(20 downto 0);
signal B_TOTAL_p1 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p1 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p1 : std_logic;
signal OUT_ADDR_p2 : std_logic_vector(2 downto 0);
signal R_TOTAL_p2 : std_logic_vector(20 downto 0);
signal G_TOTAL_p2 : std_logic_vector(20 downto 0);
signal B_TOTAL_p2 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p2 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p2 : std_logic;
begin
resultBuffer : resultRam
PORT MAP (
clka => CLK,
ena => CE,
wea => RESULT_RAM_WE,
addra => RESULT_RAM_ADDR,
dina => RESULT_RAM_D,
douta => RESULT_RAM_Q,
clkb => RESULT_CLK,
web => "0",
addrb => RESULT_RAM_B_ADDR,
dinb => (others=> '0'),
doutb => RESULT_RAM_B_Q
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(START = '1') then
COUNT <= (others => '0');
RUNNING <= '1';
if(YPOS = "000000") then
FRAME <= not FRAME;
end if;
elsif(COUNT(15) = '1') then
RUNNING <= '0';
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
-- read address is set when write_cycle = '0'
-- so read data is available when write_cycle = '1'
if(WRITE_CYCLE = '1') then
XMIN_p0 <= CONFIG_DATA(5 downto 0);
XMAX_p0 <= CONFIG_DATA(11 downto 6);
YMIN_p0 <= CONFIG_DATA(17 downto 12);
YMAX_p0 <= CONFIG_DATA(23 downto 18);
SHIFT_p0 <= CONFIG_DATA(27 downto 24);
OUT_ADDR_p0 <= CONFIG_DATA(30 downto 28);
R_TOTAL_p0 <= RESULT_RAM_Q(20 downto 0);
G_TOTAL_p0 <= RESULT_RAM_Q(41 downto 21);
B_TOTAL_p0 <= RESULT_RAM_Q(62 downto 42);
R_p0 <= LINE_BUF_DATA(23 downto 16);
G_p0 <= LINE_BUF_DATA(15 downto 8);
B_p0 <= LINE_BUF_DATA( 7 downto 0);
WRITE_ADDR_p0 <= LIGHT_ADDR;
XPOS_p0 <= XPOS;
YPOS_p0 <= YPOS;
RUNNING_p0 <= RUNNING;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(RUNNING_p0 = '1' and
unsigned(XPOS_p0) >= unsigned(XMIN_p0) and unsigned(XPOS_p0) <= unsigned(XMAX_p0) and
unsigned(YPOS_p0) >= unsigned(YMIN_p0) and unsigned(YPOS_p0) <= unsigned(YMAX_p0)) then
WRITE_ENABLE_p1 <= '1';
else
WRITE_ENABLE_p1 <= '0';
end if;
if(XPOS_p0 = XMIN_p0 and YPOS_p0 = YMIN_p0) then
R_TOTAL_p1 <= "0000000000000" & R_p0;
G_TOTAL_p1 <= "0000000000000" & G_p0;
B_TOTAL_p1 <= "0000000000000" & B_p0;
else
R_TOTAL_p1 <= std_logic_vector(unsigned(R_TOTAL_p0) + unsigned(R_p0));
G_TOTAL_p1 <= std_logic_vector(unsigned(G_TOTAL_p0) + unsigned(G_p0));
B_TOTAL_p1 <= std_logic_vector(unsigned(B_TOTAL_p0) + unsigned(B_p0));
end if;
if(XPOS_p0 = XMAX_p0 and YPOS_p0 = YMAX_p0) then
SHIFT_p1 <= SHIFT_p0;
else
SHIFT_p1 <= (others => '0');
end if;
WRITE_ADDR_p1 <= WRITE_ADDR_p0;
OUT_ADDR_p1 <= OUT_ADDR_p0;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
R_TOTAL_p2 <= std_logic_vector(unsigned(R_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
G_TOTAL_p2 <= std_logic_vector(unsigned(G_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
B_TOTAL_p2 <= std_logic_vector(unsigned(B_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
WRITE_ENABLE_p2 <= WRITE_ENABLE_p1;
WRITE_ADDR_p2 <= WRITE_ADDR_p1;
OUT_ADDR_p2 <= OUT_ADDR_p1;
end if;
end if;
end process;
WRITE_ENABLE <= '1' when WRITE_ENABLE_p2 = '1' and WRITE_CYCLE = '1' else '0';
WRITE_ADDR <= WRITE_ADDR_p2;
WRITE_DATA(20 downto 0) <= R_TOTAL_p2;
WRITE_DATA(41 downto 21) <= G_TOTAL_p2;
WRITE_DATA(62 downto 42) <= B_TOTAL_p2;
WRITE_DATA(65 downto 63) <= OUT_ADDR_p2;
WRITE_DATA(71 downto 66) <= (others => '0');
WRITE_CYCLE <= COUNT(0);
LIGHT_ADDR <= COUNT(8 downto 1);
XPOS <= COUNT(14 downto 9);
CONFIG_ADDR <= "0" & LIGHT_ADDR;
LINE_BUF_ADDR <= YPOS(0) & XPOS;
RESULT_RAM_ADDR <= (not FRAME) & LIGHT_ADDR when WRITE_CYCLE = '0' else (not FRAME) & WRITE_ADDR;
RESULT_RAM_WE(0) <= '0' when WRITE_CYCLE = '0' else WRITE_ENABLE;
RESULT_RAM_D <= WRITE_DATA;
RESULT_RAM_B_ADDR <= FRAME & RESULT_ADDR(7 downto 0);
RESULT_DATA( 7 downto 0) <= RESULT_RAM_B_Q( 7 downto 0);
RESULT_DATA(15 downto 8) <= RESULT_RAM_B_Q(28 downto 21);
RESULT_DATA(23 downto 16) <= RESULT_RAM_B_Q(49 downto 42);
RESULT_DATA(26 downto 24) <= RESULT_RAM_B_Q(65 downto 63);
RESULT_DATA(31 downto 27) <= (others => '0');
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File Name: MT58L512L18F.VHD
-- Revision: 2.0
-- Date: April 3rd, 2002
-- Model: Bus Functional
-- Simulator: Aldec, ModemSim, NCDesktop
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part #: MT58L512L18F
--
-- Description: Micron 8 Meg SyncBurst SRAM (Flow-through)
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1997 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- --- -------------- ------------ ---------- -----------------------------
-- 2.0 Son P. Huynh 208-368-3825 04/03/2002 - Fix Burst counter
-- Micron Technology, Inc.
--
-------------------------------------------------------------------------------
LIBRARY ieee, std, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.standard.ALL;
USE std.textio.all;
ENTITY MT58L512L18F IS
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 16
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END MT58L512L18F;
ARCHITECTURE behave OF MT58L512L18F IS
TYPE memory IS ARRAY (2 ** addr_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits / 2 - 1 DOWNTO 0);
SIGNAL doe : STD_LOGIC;
SIGNAL dout : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
SIGNAL bwan, bwbn, ce, clr : STD_LOGIC;
--FILE outfile: TEXT IS OUT "sram_outfile.txt";
BEGIN
bwan <= ((Bwa_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
bwbn <= ((Bwb_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
ce <= NOT(Ce_n) AND Ce2 AND NOT(Ce2_n);
clr <= NOT(Adsc_n) OR (NOT(Adsp_n) AND NOT(Ce_n));
main : PROCESS
-- Memory Array
VARIABLE bank0, bank1 : memory;
-- Address Registers
VARIABLE addr_reg_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE addr_reg_out : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Burst Counter
VARIABLE bcount : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE baddr0 : STD_LOGIC;
VARIABLE baddr1 : STD_LOGIC;
-- Other Registers
VARIABLE din : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
VARIABLE ce_reg : STD_LOGIC;
VARIABLE bwa_reg : STD_LOGIC;
VARIABLE bwb_reg : STD_LOGIC;
VARIABLE write_line : line;
VARIABLE i,j : integer;
VARIABLE dat : STD_LOGIC_VECTOR (data_bits*2 - 1 DOWNTO 0);
BEGIN
i := 0;
j := 0;
LOOP
dat := conv_std_logic_vector(j,data_bits*2);
bank0(i) := dat(data_bits/2 -1 DOWNTO 0);
bank1(i) := dat(data_bits-1 DOWNTO data_bits/2);
bank0(i+1) := dat(3*data_bits/2 -1 DOWNTO data_bits);
bank1(i+1) := dat(2*data_bits-1 DOWNTO 3*data_bits/2);
i := i + 2;
j := j + 1;
IF i = 2 ** addr_bits THEN
exit;
END IF;
END LOOP;
LOOP
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' AND Zz = '0' THEN
-- Address Register
IF clr = '1' THEN
addr_reg_in := Addr;
END IF;
-- Binary Counter and Logic
IF Mode = '1' AND clr = '1' THEN
bcount := "00";
ELSIF Mode = '0' AND clr = '1' THEN
bcount := Addr(1 DOWNTO 0);
ELSIF Adv_n = '0' AND clr = '0' THEN
bcount(1) := bcount(0) XOR bcount(1);
bcount(0) := NOT(bcount(0));
END IF;
-- Burst Address Decode
IF Mode = '1' THEN
baddr0 := bcount(0) XOR addr_reg_in(0);
baddr1 := bcount(1) XOR addr_reg_in(1);
ELSE
baddr0 := bcount(0);
baddr1 := bcount(1);
END IF;
-- Output Address
addr_reg_out (addr_bits - 1 DOWNTO 2) := addr_reg_in (addr_bits - 1 DOWNTO 2);
addr_reg_out (1) := baddr1;
addr_reg_out (0) := baddr0;
-- Byte Write Register
bwa_reg := NOT(bwan);
bwb_reg := NOT(bwbn);
-- Enable Register
IF clr = '1' THEN
ce_reg := ce;
END IF;
-- Input Register
IF (ce_reg = '1' AND (bwa_reg = '1' OR bwb_reg = '1')) THEN
din := Dq;
ELSE
din := (OTHERS => 'Z');
END IF;
-- Byte Write Driver
IF ce_reg = '1' AND bwa_reg = '1' THEN
bank0 (CONV_INTEGER(addr_reg_out)) := din ( 7 DOWNTO 0);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'L');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(7 DOWNTO 0)));
-- WRITELINE(outfile, write_line);
END IF;
IF ce_reg = '1' AND bwb_reg = '1' THEN
bank1 (CONV_INTEGER(addr_reg_out)) := din (15 DOWNTO 8);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'H');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(15 DOWNTO 8)));
-- WRITELINE(outfile, write_line);
END IF;
-- Output Register
IF (NOT(bwa_reg = '1' OR bwb_reg = '1')) THEN
dout ( 7 DOWNTO 0) <= bank0 (CONV_INTEGER(addr_reg_out));
dout (15 DOWNTO 8) <= bank1 (CONV_INTEGER(addr_reg_out));
-- WRITE(write_line, 'R');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(bank1 (CONV_INTEGER(addr_reg_out))));
-- WRITE(write_line, TO_HEX_STRING(bank0 (CONV_INTEGER(addr_reg_out))));
-- WRITELINE(outfile, write_line);
END IF;
-- Data Out Enable
doe <= ce_reg AND (NOT(bwa_reg OR bwb_reg));
END IF;
END LOOP;
END PROCESS main;
-- Output buffer
WITH (NOT(Oe_n) AND NOT(Zz) AND doe) SELECT
Dq <= TRANSPORT dout AFTER tKQHZ WHEN '1',
(OTHERS => 'Z') AFTER tKQHZ WHEN '0',
(OTHERS => 'Z') AFTER tKQHZ WHEN OTHERS;
-- Checking for setup time violation
Setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' THEN
ASSERT(Addr'LAST_EVENT >= tAS)
REPORT "Addr Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Adsc_n'LAST_EVENT >= tADSS)
REPORT "Adsc_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT >= tADSS)
REPORT "Adsp_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adv_n'LAST_EVENT >= tAAS)
REPORT "Adv_n Setup time violation -- tAAS"
SEVERITY WARNING;
ASSERT(Bwa_n'LAST_EVENT >= tWS)
REPORT "Bwa_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT >= tWS)
REPORT "Bwb_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT >= tWS)
REPORT "Bwe_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT >= tWS)
REPORT "Gw_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Ce_n'LAST_EVENT >= tCES)
REPORT "Ce_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT >= tCES)
REPORT "Ce2_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT >= tCES)
REPORT "Ce2 Setup time violation -- tCES"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Checking for hold time violation
Hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tADSH), Clk'DELAYED(tAAH), Clk'DELAYED(tWH), Clk'DELAYED(tCEH);
IF Clk'DELAYED(tAH)'EVENT AND Clk'DELAYED(tAH) = '1' THEN
ASSERT(Addr'LAST_EVENT > tAH)
REPORT "Addr Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tADSH)'EVENT AND Clk'DELAYED(tADSH) = '1' THEN
ASSERT(Adsc_n'LAST_EVENT > tADSH)
REPORT "Adsc_n Hold time violation -- tADSH"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT > tADSH)
REPORT "Adsp_n Hold time violation -- tADSH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tAAH)'EVENT AND Clk'DELAYED(tAAH) = '1' THEN
ASSERT(Adv_n'LAST_EVENT > tAAH)
REPORT "Adv_n Hold time violation -- tAAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tWH)'EVENT AND Clk'DELAYED(tWH) = '1' THEN
ASSERT(Bwa_n'LAST_EVENT > tWH)
REPORT "Bwa_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT > tWH)
REPORT "Bwb_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT > tWH)
REPORT "Bwe_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT > tWH)
REPORT "Gw_n Hold time violation -- tWH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tCEH)'EVENT AND Clk'DELAYED(tCEH) = '1' THEN
ASSERT(Ce_n'LAST_EVENT > tCEH)
REPORT "Ce_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT > tCEH)
REPORT "Ce2_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT > tCEH)
REPORT "Ce2 Hold time violation -- tCEH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
|
library ieee;
use ieee.std_logic_1164.all;
library machxo2;
use machxo2.components;
entity vether_xo2 is
port (
tx_po,
tx_no : out std_ulogic;
led_no : out std_ulogic_vector(7 downto 0));
end;
architecture tbd of vether_xo2 is
attribute frequency_pin_clkos : string;
attribute frequency_pin_clkos of pll : label is "19.950000";
attribute frequency_pin_clki : string;
attribute frequency_pin_clki of pll : label is "133.000000";
attribute icp_current : string;
attribute icp_current of pll : label is "9";
attribute lpf_resistor : string;
attribute lpf_resistor of pll : label is "72";
constant clk_freq : natural := 19_950e3;
signal clk133, clk, lock, rst, stb, run, tx_p, tx_n, run_pulse : std_ulogic;
begin
osc : component machxo2.components.osch
generic map (
nom_freq => "133.0")
port map (
stdby => '0',
osc => clk133);
pll : component machxo2.components.ehxpllj
generic map (
clki_div => 16,
clkfb_div => 3,
clkop_div => 20,
clkos_div => 25,
clkop_cphase => 19,
clkos_cphase => 24,
clkos2_enable => "DISABLED",
clkos3_enable => "DISABLED",
feedbk_path => "INT_DIVA")
port map (
clki => clk133,
clkos => clk,
lock => lock);
rst <= not lock;
stb_gen : entity work.stb_gen
generic map (
period_g => clk_freq) -- 1 sec
port map (
rst_i => rst,
clk_i => clk,
stb_o => stb);
vether_tx : entity work.vether_tx
generic map (
clk_freq_g => clk_freq)
port map (
rst_i => rst,
clk_i => clk,
stb_i => stb,
tx_po => tx_p,
tx_no => tx_n,
run_o => run);
run_pulse_gen : entity work.pulse_gen
generic map (
duration_g => clk_freq/10) -- 100 ms
port map (
rst_i => rst,
clk_i => clk,
stb_i => run,
pulse_o => run_pulse);
led_no <= not ("00000" & tx_p & tx_n & run_pulse);
tx_po <= tx_p;
tx_no <= tx_n;
end; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity draw is
generic (
CLK_PROC_FREQ : integer;
IMG_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end draw;
architecture rtl of draw is
component draw_process
generic (
CLK_PROC_FREQ : integer;
IMG_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end component;
component draw_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
inImg_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal inImg_size_reg_in_w_reg : std_logic_vector (11 downto 0);
signal inImg_size_reg_in_h_reg : std_logic_vector (11 downto 0);
begin
draw_process_inst : draw_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IMG_SIZE => IMG_SIZE,
COORD_SIZE => COORD_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
Img_data => Img_data,
Img_fv => Img_fv,
Img_dv => Img_dv,
coord_data => coord_data,
coord_fv => coord_fv,
coord_dv => coord_dv
);
draw_slave_inst : draw_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
inImg_size_reg_in_w_reg => inImg_size_reg_in_w_reg,
inImg_size_reg_in_h_reg => inImg_size_reg_in_h_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
-------------------------------------------------------------------------------
-- Title : Look-up table sweeper
-- Project :
-------------------------------------------------------------------------------
-- File : lut_sweep.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tool for sweeping through look-up table addresses
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity lut_sweep is
generic (
g_bus_size : natural := 8;
g_first_address : natural := 0;
g_last_address : natural := 147;
g_sweep_mode : string := "sawtooth"
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0));
end entity lut_sweep;
-------------------------------------------------------------------------------
architecture str of lut_sweep is
begin -- architecture str
counting : process(clk_i)
variable count : natural := 0;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count := 0;
elsif ce_i = '1' then
if count = g_last_address then
count := g_first_address;
else
count := count + 1;
end if; --count = last_address
address_o <= std_logic_vector(to_unsigned(count, g_bus_size));
end if; -- reset
end if; -- rising_edge
end process counting;
end architecture str;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Look-up table sweeper
-- Project :
-------------------------------------------------------------------------------
-- File : lut_sweep.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tool for sweeping through look-up table addresses
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity lut_sweep is
generic (
g_bus_size : natural := 8;
g_first_address : natural := 0;
g_last_address : natural := 147;
g_sweep_mode : string := "sawtooth"
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0));
end entity lut_sweep;
-------------------------------------------------------------------------------
architecture str of lut_sweep is
begin -- architecture str
counting : process(clk_i)
variable count : natural := 0;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count := 0;
elsif ce_i = '1' then
if count = g_last_address then
count := g_first_address;
else
count := count + 1;
end if; --count = last_address
address_o <= std_logic_vector(to_unsigned(count, g_bus_size));
end if; -- reset
end if; -- rising_edge
end process counting;
end architecture str;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- test routine for the post synthesis 32 bit multiply
-------------------------------------------------------------------------------
entity test_float_synth is
generic (
quiet : BOOLEAN := false);
end entity test_float_synth;
use std.textio.all;
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
--library modelsim_lib;
--use modelsim_lib.util.all;
architecture testbench of test_float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
function reverse (
inpvec : STD_LOGIC_VECTOR (0 to 31))
return float32 is
variable result : float32;
begin
for i in 0 to 31 loop
result (i-23) := inpvec(i);
end loop; -- i
return result;
end function reverse;
-- purpose: converts an float32 into a std_logic_vector
-- function to_slv (
-- input : float32) -- float32 input
-- return std_logic_vector is
-- variable result : std_logic_vector (31 downto 0); -- result
-- begin -- function to_slv
-- floop: for i in float32'range loop
-- result (i + fp_fraction_width) := input (i);
-- end loop floop;
-- return result;
-- end function to_slv;
-- purpose: converts a std_logic_vector to an float32
function to_float32x (
signal input : STD_LOGIC_VECTOR (31 downto 0))
return float32 is
variable result : float32;
begin -- function to_float32x
return to_float (input, float32'high, -float32'low);
end function to_float32x;
procedure report_error (
constant errmes : STRING; -- error message
actual : in float32; -- data from algorithm
constant expected : float32) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error;
procedure report_error16 (
constant errmes : STRING; -- error message
actual : in fp16; -- data from algorithm
constant expected : fp16) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error16;
component float_synth is
port (
in1, in2 : in STD_LOGIC_VECTOR(31 downto 0); -- inputs
out1 : out STD_LOGIC_VECTOR(31 downto 0); -- output
cmd : in STD_LOGIC_VECTOR (3 downto 0);
clk, rst_n : in STD_ULOGIC); -- clk and reset
end component float_synth;
for all : float_synth
use entity work.float_synth(rtl);
constant clock_period : TIME := 500 ns; -- clock period
signal stop_clock : BOOLEAN := false; -- stop the clock
signal out1real : REAL; -- real version
signal in1, in2 : float32; -- inputs
signal out1 : float32; -- output
constant zero0 : float32 := (others => '0'); -- zero
signal cmd : STD_LOGIC_VECTOR (3 downto 0); -- command
signal clk, rst_n : STD_ULOGIC; -- clk and reset
signal in1slv, in2slv, out1slv : STD_LOGIC_VECTOR(31 downto 0);
signal indelay : float32; -- spied signal
begin -- architecture testbench
out1real <= to_real (out1);
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
out1 <= to_float32x(out1slv);
DUT : float_synth
port map (
in1 => in1slv, -- [in float32] inputs
in2 => in2slv, -- [in float32] inputs
out1 => out1slv, -- [out float32] output
cmd => cmd,
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- spy_process : process
-- begin
-- signal_force ("/DUT/in2reg3", "00000000000000000000000000000000",
-- 500 ns, freeze, 5000 ns, 1);
-- wait;
-- end process spy_process;
-- purpose: clock driver
-- type : combinational
-- inputs :
-- outputs:
clkprc : process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
-- type : combinational
-- inputs :
-- outputs:
reset_proc : process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
-- type : combinational
-- inputs :
-- outputs:
tester : process is
begin -- process tester
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101111"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop1: for i in 1 to 100 loop
wait for clock_period;
end loop floop1;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop2: for i in 1 to 100 loop
wait for clock_period;
end loop floop2;
cmd <= "0010";
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000001010001000010"); -- 42
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000011"); -- -6.5
wait for clock_period;
in1 <= reverse("10000000000000000000000000000000"); -- 2**-149
in2 <= "11000000000000000000000000000000"; -- -2.0
wait for clock_period;
in1 <= reverse("00000000000000000000001000000000"); -- 2**-127
in2 <= "00111110100000000000000000000000"; -- 0.25
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
cmd <= "0001"; -- subtract mode
in2 <= "01001011111001110011000110011011"; -- 30303030
in1 <= "01001011111001110011000110011100"; -- 30303033
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
in1 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00111110101010101010101010101011"; -- 1/3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in2 <= "00111110101010101010101010101011"; -- 1/3
in1 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00000000100000000000000000000001"; -- 2**-126
in2 <= "01000000100000000000000000000001"; -- 4+
wait for clock_period;
cmd <= "0011"; -- divide mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000010000000000000000000000"; -- 3.0
wait for clock_period;
in1 <= "01001100000011001011110001001111"; -- 36892987
in2 <= "00000000010000000000000000000000"; -- 2**-127
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
cmd <= "0100"; -- 32 to 16 conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= (others => '0');
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3, no round
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
cmd <= "0101"; -- conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000000000000000000000000000"; -- opcode zero
wait for clock_period;
in1 <= "01000010001010000000000000000000"; -- 42.0
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
in1 <= "10111111100000000000000000000000"; -- -1.0
in2 <= "00000000000000000000000000000010"; -- 2
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000011"; -- 3
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "00000000000000000000000000000110"; -- 6 to_sfixed
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000111"; -- 7 to_sfixed
wait for clock_period;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "00000000000000000000000000000011"; -- 3
in2 <= "01000000000000000000000000000000"; -- mode 0
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000001"; -- 1
wait for clock_period;
in1 <= "00000000000000001111111111111110"; -- -2
in2 <= "01000000000000000000000000000010"; -- 2 to_float(signed)
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000011"; -- mode 3
wait for clock_period;
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 ufixed
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000000000001111110111010101"; -- -4.333 sfixed
in2 <= "00000000000000000000000000000110"; -- 6
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 sfixed
in2 <= "00000000000000000000000000000111"; -- 7
wait for clock_period;
cmd <= "0111"; -- Mod
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1000"; -- rem
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1001"; -- constants conversion
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in2 <= "11000000000000000000000000000010"; -- command 2
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- command 4
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- command 5
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- command 6
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- command 7
wait for clock_period;
cmd <= "1010"; -- conversions
in1 <= to_float (1, in1);
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in1 <= to_float (-2, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "00010000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11110000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (0.25, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- 4 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- 5 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- 6 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- 7 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
cmd <= "1011"; -- copy sign
in1 <= to_float (2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= to_float (-3, in1);
in2 <= to_float (3, in1);
wait for clock_period;
in1 <= to_float (4, in1);
in2 <= to_float (-4, in1);
wait for clock_period;
in1 <= to_float (-5, in1);
in2 <= to_float (-5, in1);
wait for clock_period;
cmd <= "1100"; -- compare test
in1 <= to_float (15, in1);
in2 <= to_float (15, in1);
wait for clock_period;
in1 <= to_float (15.5, in1);
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= to_float (-2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000001"; -- NAN
in2 <= to_float (-2, in1);
wait for clock_period;
cmd <= "1101"; -- boolean test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0 , not
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and
wait for clock_period;
in1 <= "01111111000000000000000000000000"; -- + inf
in2 <= "00111111000000000000000000000010"; -- command 2, or
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000011"; -- command 3, nand
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000100"; -- command 4, nor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000101"; -- command 5, xor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000110"; -- command 6, xnor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000111"; -- command 7, xor '1'
wait for clock_period;
cmd <= "1110"; -- reduce and vector test test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0,
wait for clock_period;
in1 <= "11111111111111111111111111111111"; -- all 1
wait for clock_period;
in1 <= "10000000000000000000000000000000"; -- -0
wait for clock_period;
in1 <= "00000000000000000000000000000000"; -- 0
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, and '1'
wait for clock_period;
in2 <= "00111111100000000000000000000010"; -- command 2, or '0'
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, or '1'
wait for clock_period;
in2 <= "00111111100000000000000000000011"; -- command 3, nand '0'
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, nand '1'
wait for clock_period;
in2 <= "00111111100000000000000000000100"; -- command 4, nor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, nor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000101"; -- command 5, xor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, xor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000110"; -- command 6, xnor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, xnor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000111"; -- command 7, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, and '1'
wait for clock_period;
cmd <= "1111"; -- add and mult by constant
in2 <= "10111111100000000000000000000000"; -- command 0, + 1
in1 <= to_float (2, in1);
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, 1 +
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, + 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, 1.0 +
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, * 1
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, 1 *
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, * 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, 1.0 *
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest : process is
variable out16, out16t : fp16; -- 16 bit fp variables
variable out1t, out2t : float32; -- 32 bit float
variable s16, s16t : SIGNED(7 downto 0); -- 7 bit SIGNED
variable latency : INTEGER := 0;
begin -- process checktest
wait for clock_period/2.0;
floop3: for i in 1 to 100 loop
wait for clock_period;
end loop floop3;
latency := 0;
out2t := "01000000100010101100000000000000";
wl1: while out1 /= out2t loop
wait for clock_period;
latency := latency + 1;
assert latency /= 100 report "After 100 loops, pattern never found"
severity failure;
end loop wl1;
report "Latency was " & INTEGER'image(latency) severity note;
floop4: for i in 1 to 100 loop
wait for clock_period;
end loop floop4;
report_error ("42 * 6.5 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1'high, -out1'low));
wait for clock_period;
report_error ("Multiply 42.25 miscompare",
out1,
"01000010001010010000000000000000"); -- 42.25
wait for clock_period;
report_error ("Multiply 84 miscompare",
out1,
"01000010101010000000000000000000"); -- 84
wait for clock_period;
report_error ("Multiply 2/3 miscompare",
out1,
"00111111001010101010101010101011"); -- 2/3
wait for clock_period;
report_error ("Multiply -273 miscompare",
out1,
"11000011100010001000000000000000"); -- -273
wait for clock_period;
report_error ("mult 2**-148 test miscompare",
out1,
reverse("01000000000000000000000000000001")); -- -2*-148
wait for clock_period;
report_error ("Multiply 2**-129 miscompare",
out1,
reverse("00000000000000000000100000000000")); -- 2**-129
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("Subtract 30303033 - 30303030 miscompare",
out1,
"01000000000000000000000000000000"); -- 2 (not 3, rounding)
wait for clock_period;
report_error ("Subtract 6.5 - 4 miscompare",
out1,
"01000000001000000000000000000000"); -- 2.5
wait for clock_period;
report_error ("Subtract 4 - 6.5 miscompare",
out1,
"11000000001000000000000000000000"); -- -2.5
wait for clock_period;
report_error ("Subtract 4.333 - 1/3 miscompare",
out1,
"01000000100000000000000000000000"); -- 4
wait for clock_period;
report_error ("Add 2.333 miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 2.333 rev miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 4 + miscompare",
out1,
"01000000100000000000000000000001"); -- 4
wait for clock_period;
report_error ("div 1/3 test miscompare",
out1,
"00111110101010101010101010101011"); -- 1/3
wait for clock_period;
report_error ("div 369297/2**-126 test miscompare",
out1,
"01111111100000000000000000000000");
wait for clock_period;
report_error ("-1/6 test miscompare",
out1, "10111110001010101010101010101011"); -- -1/6
wait for clock_period;
-- resize function
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (1, out16t);
report_error16 ("1.0 fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (arg => -1.0/3.0, size_res => out16t,
round_style => round_zero);
report_error16 ("-1/3 not rounded fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (-1.0/3.0, out16t);
report_error16 ("-1/3 fp16 converserion",
out16, out16t);
-- conversion test
wait for clock_period;
report_error ("1.0 to unsigned miscompare",
out1, "00000000000000000000000000000001");
wait for clock_period;
report_error ("42 to unsigned miscompare",
out1, "00100000000000000000000000101010");
wait for clock_period;
report_error ("-1.0 to signed miscompare",
out1, "01000000000000001111111111111111");
wait for clock_period;
report_error ("1.0 to signed miscompare",
out1, "01100000000000000000000000000001");
wait for clock_period;
report_error ("4.33 to ufixed miscompare",
out1, "10000000000000000000001000101011");
wait for clock_period;
report_error ("1.0 to ufixed miscompare",
out1, "10100000000000000000000010000000");
wait for clock_period;
report_error ("4.333 to sfixed miscompare",
out1, "11000000000000001111110111010101");
wait for clock_period;
report_error ("1.0 to sfixed miscompare",
out1, "11100000000000000000000010000000");
wait for clock_period;
report_error ("unsigned 3 to float miscompare",
out1, to_float(3, out1));
wait for clock_period;
report_error ("unsigned 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("signed -2 to float miscompare",
out1, to_float(-2, out1));
wait for clock_period;
report_error ("signed 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("ufixed 4.333 to float miscompare",
out1, "01000000100010101100000000000000"); -- 4.333333
wait for clock_period;
report_error ("ufixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("sfixed -4.333 to float miscompare",
out1, "11000000100010101100000000000000"); -- -4.333333
wait for clock_period;
report_error ("sfixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("denormal mod denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large mod large miscompare",
out1, zero0);
wait for clock_period;
report_error ("-4.333 mod 4 miscompare",
out1,
from_string ("01000000011010101010101010101010", out1));
wait for clock_period;
report_error ("denormal rem denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large rem large miscompare",
out1, zero0);
wait for clock_period;
out1t := "10111110101010101010101010110000";
report_error ("-4.333 rem 4 miscompare",
out1, out1t);
wait for clock_period;
report_error ("to_float(0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(0.0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(8) miscompare",
out1, to_float(8.0, out1));
wait for clock_period;
report_error ("to_float(8.0) miscompare",
out1, to_float(8, out1));
wait for clock_period;
report_error ("to_float(-8) miscompare",
out1, to_float(-8.0, out1));
wait for clock_period;
report_error ("to_float(-8.0) miscompare",
out1, to_float(-8, out1));
wait for clock_period;
report_error ("to_float(27000) miscompare",
out1, to_float(27000.0, out1));
wait for clock_period;
report_error ("to_float(PI) miscompare",
out1, to_float(3.141592653589, out1));
-- Conversion test
wait for clock_period;
report_error ("-1 miscompare",
out1, to_float(-1, out1));
wait for clock_period;
report_error ("-(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(1) miscompare",
out1, to_float(1, out1));
wait for clock_period;
report_error ("scalb (1, 1) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("scalb (1, -1) miscompare",
out1, to_float(0.5, out1));
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = 0) report "logb (1) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = -2) report "logb (0.25) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, 1.5)", out1, out1t);
wait for clock_period;
out1t := "01000000011111111111111111111111";
report_error ("nextafter (4, 1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, -1.5)", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111";
report_error ("nextafter (-4, -1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, inf)", out1, out1t);
wait for clock_period;
out1t := "01000000100000000000000000000001";
report_error ("nextafter (4, inf)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, neginf)", out1, out1t);
wait for clock_period;
out1t := "11000000100000000000000000000001";
report_error ("nextafter (-4, neginf)", out1, out1t);
wait for clock_period;
report_error ("Copysign (2,2)", out1, to_float(2, out1));
wait for clock_period;
report_error ("Copysign (-3,3)", out1, to_float(3, out1));
wait for clock_period;
report_error ("Copysign (4,-4)", out1, to_float(-4, out1));
wait for clock_period;
report_error ("Copysign (-5,-5)", out1, to_float(-5, out1));
wait for clock_period;
out1t := "10001110000000000000000000000000";
report_error ("compare test 15, 15", out1, out1t);
wait for clock_period;
out1t := "01101001000000000000000000000000";
report_error ("compare test 15.5, -2", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000";
report_error ("compare test -2, 2", out1, out1t);
wait for clock_period;
out1t := "01101000010000000000000000000000";
report_error ("compare test inf, -2", out1, out1t);
wait for clock_period;
out1t := "01000000101000000000000000000000";
report_error ("compare test NAN, -2", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- not + inf
report_error ("not +inf", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000000"; -- and
report_error ("and +inf", out1, out1t);
wait for clock_period;
out1t := "01111111000000000000000000000010"; -- or
report_error ("or +inf", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111"; -- nand
report_error ("nand +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111011"; -- nor
report_error ("nor +inf", out1, out1t);
wait for clock_period;
out1t := "01000000000000000000000000000101"; -- xor
report_error ("xor +inf", out1, out1t);
wait for clock_period;
out1t := "10111111111111111111111111111001"; -- xnor
report_error ("xnor +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- xnor '1'
report_error ("+inf xor '1'", out1, out1t);
wait for clock_period;
out1t := "01100100000000000000000000000000"; -- reduce test
report_error ("_reduce test", out1, out1t);
wait for clock_period;
out1t := "10100100000000000000000000000000"; -- reduce test
report_error ("_reduce all 1 test", out1, out1t);
wait for clock_period;
out1t := "01101000000000000000000000000000"; -- reduce test
report_error ("_reduce -0 test", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000"; -- reduce test
report_error ("_reduce 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("or 0 test", out1, out1t);
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "or 1 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "nand 0 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nand 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nor 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("nor 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xor 0 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xor 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xnor 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xnor 1 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := to_float(3, out1t);
report_error ("2 + 1 test", out1, out1t);
wait for clock_period;
report_error ("1 + 2 test", out1, out1t);
wait for clock_period;
report_error ("2 + 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 + 2 test", out1, out1t);
wait for clock_period;
out1t := to_float(2, out1t);
report_error ("2 * 1 test", out1, out1t);
wait for clock_period;
report_error ("1 * 2 test", out1, out1t);
wait for clock_period;
report_error ("2 * 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 * 2 test", out1, out1t);
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
|
-------------------------------------------------------------------------------
-- test routine for the post synthesis 32 bit multiply
-------------------------------------------------------------------------------
entity test_float_synth is
generic (
quiet : BOOLEAN := false);
end entity test_float_synth;
use std.textio.all;
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
--library modelsim_lib;
--use modelsim_lib.util.all;
architecture testbench of test_float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
function reverse (
inpvec : STD_LOGIC_VECTOR (0 to 31))
return float32 is
variable result : float32;
begin
for i in 0 to 31 loop
result (i-23) := inpvec(i);
end loop; -- i
return result;
end function reverse;
-- purpose: converts an float32 into a std_logic_vector
-- function to_slv (
-- input : float32) -- float32 input
-- return std_logic_vector is
-- variable result : std_logic_vector (31 downto 0); -- result
-- begin -- function to_slv
-- floop: for i in float32'range loop
-- result (i + fp_fraction_width) := input (i);
-- end loop floop;
-- return result;
-- end function to_slv;
-- purpose: converts a std_logic_vector to an float32
function to_float32x (
signal input : STD_LOGIC_VECTOR (31 downto 0))
return float32 is
variable result : float32;
begin -- function to_float32x
return to_float (input, float32'high, -float32'low);
end function to_float32x;
procedure report_error (
constant errmes : STRING; -- error message
actual : in float32; -- data from algorithm
constant expected : float32) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error;
procedure report_error16 (
constant errmes : STRING; -- error message
actual : in fp16; -- data from algorithm
constant expected : fp16) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error16;
component float_synth is
port (
in1, in2 : in STD_LOGIC_VECTOR(31 downto 0); -- inputs
out1 : out STD_LOGIC_VECTOR(31 downto 0); -- output
cmd : in STD_LOGIC_VECTOR (3 downto 0);
clk, rst_n : in STD_ULOGIC); -- clk and reset
end component float_synth;
for all : float_synth
use entity work.float_synth(rtl);
constant clock_period : TIME := 500 ns; -- clock period
signal stop_clock : BOOLEAN := false; -- stop the clock
signal out1real : REAL; -- real version
signal in1, in2 : float32; -- inputs
signal out1 : float32; -- output
constant zero0 : float32 := (others => '0'); -- zero
signal cmd : STD_LOGIC_VECTOR (3 downto 0); -- command
signal clk, rst_n : STD_ULOGIC; -- clk and reset
signal in1slv, in2slv, out1slv : STD_LOGIC_VECTOR(31 downto 0);
signal indelay : float32; -- spied signal
begin -- architecture testbench
out1real <= to_real (out1);
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
out1 <= to_float32x(out1slv);
DUT : float_synth
port map (
in1 => in1slv, -- [in float32] inputs
in2 => in2slv, -- [in float32] inputs
out1 => out1slv, -- [out float32] output
cmd => cmd,
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- spy_process : process
-- begin
-- signal_force ("/DUT/in2reg3", "00000000000000000000000000000000",
-- 500 ns, freeze, 5000 ns, 1);
-- wait;
-- end process spy_process;
-- purpose: clock driver
-- type : combinational
-- inputs :
-- outputs:
clkprc : process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
-- type : combinational
-- inputs :
-- outputs:
reset_proc : process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
-- type : combinational
-- inputs :
-- outputs:
tester : process is
begin -- process tester
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101111"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop1: for i in 1 to 100 loop
wait for clock_period;
end loop floop1;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop2: for i in 1 to 100 loop
wait for clock_period;
end loop floop2;
cmd <= "0010";
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000001010001000010"); -- 42
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000011"); -- -6.5
wait for clock_period;
in1 <= reverse("10000000000000000000000000000000"); -- 2**-149
in2 <= "11000000000000000000000000000000"; -- -2.0
wait for clock_period;
in1 <= reverse("00000000000000000000001000000000"); -- 2**-127
in2 <= "00111110100000000000000000000000"; -- 0.25
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
cmd <= "0001"; -- subtract mode
in2 <= "01001011111001110011000110011011"; -- 30303030
in1 <= "01001011111001110011000110011100"; -- 30303033
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
in1 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00111110101010101010101010101011"; -- 1/3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in2 <= "00111110101010101010101010101011"; -- 1/3
in1 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00000000100000000000000000000001"; -- 2**-126
in2 <= "01000000100000000000000000000001"; -- 4+
wait for clock_period;
cmd <= "0011"; -- divide mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000010000000000000000000000"; -- 3.0
wait for clock_period;
in1 <= "01001100000011001011110001001111"; -- 36892987
in2 <= "00000000010000000000000000000000"; -- 2**-127
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
cmd <= "0100"; -- 32 to 16 conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= (others => '0');
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3, no round
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
cmd <= "0101"; -- conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000000000000000000000000000"; -- opcode zero
wait for clock_period;
in1 <= "01000010001010000000000000000000"; -- 42.0
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
in1 <= "10111111100000000000000000000000"; -- -1.0
in2 <= "00000000000000000000000000000010"; -- 2
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000011"; -- 3
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "00000000000000000000000000000110"; -- 6 to_sfixed
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000111"; -- 7 to_sfixed
wait for clock_period;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "00000000000000000000000000000011"; -- 3
in2 <= "01000000000000000000000000000000"; -- mode 0
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000001"; -- 1
wait for clock_period;
in1 <= "00000000000000001111111111111110"; -- -2
in2 <= "01000000000000000000000000000010"; -- 2 to_float(signed)
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000011"; -- mode 3
wait for clock_period;
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 ufixed
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000000000001111110111010101"; -- -4.333 sfixed
in2 <= "00000000000000000000000000000110"; -- 6
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 sfixed
in2 <= "00000000000000000000000000000111"; -- 7
wait for clock_period;
cmd <= "0111"; -- Mod
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1000"; -- rem
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1001"; -- constants conversion
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in2 <= "11000000000000000000000000000010"; -- command 2
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- command 4
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- command 5
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- command 6
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- command 7
wait for clock_period;
cmd <= "1010"; -- conversions
in1 <= to_float (1, in1);
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in1 <= to_float (-2, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "00010000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11110000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (0.25, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- 4 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- 5 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- 6 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- 7 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
cmd <= "1011"; -- copy sign
in1 <= to_float (2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= to_float (-3, in1);
in2 <= to_float (3, in1);
wait for clock_period;
in1 <= to_float (4, in1);
in2 <= to_float (-4, in1);
wait for clock_period;
in1 <= to_float (-5, in1);
in2 <= to_float (-5, in1);
wait for clock_period;
cmd <= "1100"; -- compare test
in1 <= to_float (15, in1);
in2 <= to_float (15, in1);
wait for clock_period;
in1 <= to_float (15.5, in1);
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= to_float (-2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000001"; -- NAN
in2 <= to_float (-2, in1);
wait for clock_period;
cmd <= "1101"; -- boolean test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0 , not
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and
wait for clock_period;
in1 <= "01111111000000000000000000000000"; -- + inf
in2 <= "00111111000000000000000000000010"; -- command 2, or
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000011"; -- command 3, nand
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000100"; -- command 4, nor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000101"; -- command 5, xor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000110"; -- command 6, xnor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000111"; -- command 7, xor '1'
wait for clock_period;
cmd <= "1110"; -- reduce and vector test test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0,
wait for clock_period;
in1 <= "11111111111111111111111111111111"; -- all 1
wait for clock_period;
in1 <= "10000000000000000000000000000000"; -- -0
wait for clock_period;
in1 <= "00000000000000000000000000000000"; -- 0
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, and '1'
wait for clock_period;
in2 <= "00111111100000000000000000000010"; -- command 2, or '0'
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, or '1'
wait for clock_period;
in2 <= "00111111100000000000000000000011"; -- command 3, nand '0'
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, nand '1'
wait for clock_period;
in2 <= "00111111100000000000000000000100"; -- command 4, nor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, nor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000101"; -- command 5, xor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, xor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000110"; -- command 6, xnor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, xnor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000111"; -- command 7, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, and '1'
wait for clock_period;
cmd <= "1111"; -- add and mult by constant
in2 <= "10111111100000000000000000000000"; -- command 0, + 1
in1 <= to_float (2, in1);
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, 1 +
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, + 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, 1.0 +
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, * 1
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, 1 *
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, * 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, 1.0 *
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest : process is
variable out16, out16t : fp16; -- 16 bit fp variables
variable out1t, out2t : float32; -- 32 bit float
variable s16, s16t : SIGNED(7 downto 0); -- 7 bit SIGNED
variable latency : INTEGER := 0;
begin -- process checktest
wait for clock_period/2.0;
floop3: for i in 1 to 100 loop
wait for clock_period;
end loop floop3;
latency := 0;
out2t := "01000000100010101100000000000000";
wl1: while out1 /= out2t loop
wait for clock_period;
latency := latency + 1;
assert latency /= 100 report "After 100 loops, pattern never found"
severity failure;
end loop wl1;
report "Latency was " & INTEGER'image(latency) severity note;
floop4: for i in 1 to 100 loop
wait for clock_period;
end loop floop4;
report_error ("42 * 6.5 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1'high, -out1'low));
wait for clock_period;
report_error ("Multiply 42.25 miscompare",
out1,
"01000010001010010000000000000000"); -- 42.25
wait for clock_period;
report_error ("Multiply 84 miscompare",
out1,
"01000010101010000000000000000000"); -- 84
wait for clock_period;
report_error ("Multiply 2/3 miscompare",
out1,
"00111111001010101010101010101011"); -- 2/3
wait for clock_period;
report_error ("Multiply -273 miscompare",
out1,
"11000011100010001000000000000000"); -- -273
wait for clock_period;
report_error ("mult 2**-148 test miscompare",
out1,
reverse("01000000000000000000000000000001")); -- -2*-148
wait for clock_period;
report_error ("Multiply 2**-129 miscompare",
out1,
reverse("00000000000000000000100000000000")); -- 2**-129
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("Subtract 30303033 - 30303030 miscompare",
out1,
"01000000000000000000000000000000"); -- 2 (not 3, rounding)
wait for clock_period;
report_error ("Subtract 6.5 - 4 miscompare",
out1,
"01000000001000000000000000000000"); -- 2.5
wait for clock_period;
report_error ("Subtract 4 - 6.5 miscompare",
out1,
"11000000001000000000000000000000"); -- -2.5
wait for clock_period;
report_error ("Subtract 4.333 - 1/3 miscompare",
out1,
"01000000100000000000000000000000"); -- 4
wait for clock_period;
report_error ("Add 2.333 miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 2.333 rev miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 4 + miscompare",
out1,
"01000000100000000000000000000001"); -- 4
wait for clock_period;
report_error ("div 1/3 test miscompare",
out1,
"00111110101010101010101010101011"); -- 1/3
wait for clock_period;
report_error ("div 369297/2**-126 test miscompare",
out1,
"01111111100000000000000000000000");
wait for clock_period;
report_error ("-1/6 test miscompare",
out1, "10111110001010101010101010101011"); -- -1/6
wait for clock_period;
-- resize function
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (1, out16t);
report_error16 ("1.0 fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (arg => -1.0/3.0, size_res => out16t,
round_style => round_zero);
report_error16 ("-1/3 not rounded fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (-1.0/3.0, out16t);
report_error16 ("-1/3 fp16 converserion",
out16, out16t);
-- conversion test
wait for clock_period;
report_error ("1.0 to unsigned miscompare",
out1, "00000000000000000000000000000001");
wait for clock_period;
report_error ("42 to unsigned miscompare",
out1, "00100000000000000000000000101010");
wait for clock_period;
report_error ("-1.0 to signed miscompare",
out1, "01000000000000001111111111111111");
wait for clock_period;
report_error ("1.0 to signed miscompare",
out1, "01100000000000000000000000000001");
wait for clock_period;
report_error ("4.33 to ufixed miscompare",
out1, "10000000000000000000001000101011");
wait for clock_period;
report_error ("1.0 to ufixed miscompare",
out1, "10100000000000000000000010000000");
wait for clock_period;
report_error ("4.333 to sfixed miscompare",
out1, "11000000000000001111110111010101");
wait for clock_period;
report_error ("1.0 to sfixed miscompare",
out1, "11100000000000000000000010000000");
wait for clock_period;
report_error ("unsigned 3 to float miscompare",
out1, to_float(3, out1));
wait for clock_period;
report_error ("unsigned 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("signed -2 to float miscompare",
out1, to_float(-2, out1));
wait for clock_period;
report_error ("signed 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("ufixed 4.333 to float miscompare",
out1, "01000000100010101100000000000000"); -- 4.333333
wait for clock_period;
report_error ("ufixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("sfixed -4.333 to float miscompare",
out1, "11000000100010101100000000000000"); -- -4.333333
wait for clock_period;
report_error ("sfixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("denormal mod denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large mod large miscompare",
out1, zero0);
wait for clock_period;
report_error ("-4.333 mod 4 miscompare",
out1,
from_string ("01000000011010101010101010101010", out1));
wait for clock_period;
report_error ("denormal rem denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large rem large miscompare",
out1, zero0);
wait for clock_period;
out1t := "10111110101010101010101010110000";
report_error ("-4.333 rem 4 miscompare",
out1, out1t);
wait for clock_period;
report_error ("to_float(0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(0.0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(8) miscompare",
out1, to_float(8.0, out1));
wait for clock_period;
report_error ("to_float(8.0) miscompare",
out1, to_float(8, out1));
wait for clock_period;
report_error ("to_float(-8) miscompare",
out1, to_float(-8.0, out1));
wait for clock_period;
report_error ("to_float(-8.0) miscompare",
out1, to_float(-8, out1));
wait for clock_period;
report_error ("to_float(27000) miscompare",
out1, to_float(27000.0, out1));
wait for clock_period;
report_error ("to_float(PI) miscompare",
out1, to_float(3.141592653589, out1));
-- Conversion test
wait for clock_period;
report_error ("-1 miscompare",
out1, to_float(-1, out1));
wait for clock_period;
report_error ("-(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(1) miscompare",
out1, to_float(1, out1));
wait for clock_period;
report_error ("scalb (1, 1) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("scalb (1, -1) miscompare",
out1, to_float(0.5, out1));
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = 0) report "logb (1) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = -2) report "logb (0.25) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, 1.5)", out1, out1t);
wait for clock_period;
out1t := "01000000011111111111111111111111";
report_error ("nextafter (4, 1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, -1.5)", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111";
report_error ("nextafter (-4, -1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, inf)", out1, out1t);
wait for clock_period;
out1t := "01000000100000000000000000000001";
report_error ("nextafter (4, inf)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, neginf)", out1, out1t);
wait for clock_period;
out1t := "11000000100000000000000000000001";
report_error ("nextafter (-4, neginf)", out1, out1t);
wait for clock_period;
report_error ("Copysign (2,2)", out1, to_float(2, out1));
wait for clock_period;
report_error ("Copysign (-3,3)", out1, to_float(3, out1));
wait for clock_period;
report_error ("Copysign (4,-4)", out1, to_float(-4, out1));
wait for clock_period;
report_error ("Copysign (-5,-5)", out1, to_float(-5, out1));
wait for clock_period;
out1t := "10001110000000000000000000000000";
report_error ("compare test 15, 15", out1, out1t);
wait for clock_period;
out1t := "01101001000000000000000000000000";
report_error ("compare test 15.5, -2", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000";
report_error ("compare test -2, 2", out1, out1t);
wait for clock_period;
out1t := "01101000010000000000000000000000";
report_error ("compare test inf, -2", out1, out1t);
wait for clock_period;
out1t := "01000000101000000000000000000000";
report_error ("compare test NAN, -2", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- not + inf
report_error ("not +inf", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000000"; -- and
report_error ("and +inf", out1, out1t);
wait for clock_period;
out1t := "01111111000000000000000000000010"; -- or
report_error ("or +inf", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111"; -- nand
report_error ("nand +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111011"; -- nor
report_error ("nor +inf", out1, out1t);
wait for clock_period;
out1t := "01000000000000000000000000000101"; -- xor
report_error ("xor +inf", out1, out1t);
wait for clock_period;
out1t := "10111111111111111111111111111001"; -- xnor
report_error ("xnor +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- xnor '1'
report_error ("+inf xor '1'", out1, out1t);
wait for clock_period;
out1t := "01100100000000000000000000000000"; -- reduce test
report_error ("_reduce test", out1, out1t);
wait for clock_period;
out1t := "10100100000000000000000000000000"; -- reduce test
report_error ("_reduce all 1 test", out1, out1t);
wait for clock_period;
out1t := "01101000000000000000000000000000"; -- reduce test
report_error ("_reduce -0 test", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000"; -- reduce test
report_error ("_reduce 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("or 0 test", out1, out1t);
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "or 1 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "nand 0 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nand 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nor 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("nor 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xor 0 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xor 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xnor 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xnor 1 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := to_float(3, out1t);
report_error ("2 + 1 test", out1, out1t);
wait for clock_period;
report_error ("1 + 2 test", out1, out1t);
wait for clock_period;
report_error ("2 + 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 + 2 test", out1, out1t);
wait for clock_period;
out1t := to_float(2, out1t);
report_error ("2 * 1 test", out1, out1t);
wait for clock_period;
report_error ("1 * 2 test", out1, out1t);
wait for clock_period;
report_error ("2 * 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 * 2 test", out1, out1t);
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
-- todo: optimize
entity Ram is
Port
(
clk : in std_logic;
re : in std_logic_vector (1 downto 0);
we : in std_logic_vector (1 downto 0);
addr : in integer range 0 to 16#1FFFF#;
dat_r : out std_logic_vector (15 downto 0);
dat_w : in std_logic_vector (15 downto 0)
);
end Ram;
architecture Behavioral of Ram is
component Mem is
port
(
clka : in std_logic;
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(16 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0)
);
end component;
signal ram_en : std_logic := '0';
signal ram_we : std_logic := '0';
signal ram_addr : std_logic_vector(16 downto 0) := (others => '0');
signal ram_dat_in : std_logic_vector(7 downto 0) := (others => '0');
signal ram_dat_out : std_logic_vector(7 downto 0) := (others => '0');
begin
mem0: Mem
port map (
clka => clk,
ena => ram_en,
wea(0) => ram_we,
addra => ram_addr,
dina => ram_dat_in,
douta => ram_dat_out
);
--process (clk)
-- type state_type is (S0, S1, S2, S3);
-- variable state : state_type := S0;-- The current/next state
-- variable tmp : std_logic_vector(15 downto 0) := (others => '0');
--begin
-- if rising_edge(clk) then
-- ram_en <= '1';
-- ram_we <= '0';
-- case state is
-- when S0 =>
-- state := S1;
-- when S1 =>
-- ram_addr <= conv_std_logic_vector(addr, 17);
-- state := S2;
-- when S2 =>
-- ram_addr <= conv_std_logic_vector(addr + 1, 17);
-- -- Write first byte if required
-- if we(1) = '1' then
-- ram_we <= '1';
-- ram_dat_in <= dat_w(15 downto 8);
-- end if;
-- -- Read fist byte if required
-- if re(1) = '1' then
-- tmp(15 downto 8) := ram_dat_out;
-- else
-- tmp(15 downto 8) := (others => 'U');
-- end if;
-- state := S3;
-- when S3 =>
-- -- Write second byte if required
-- if we(0) = '1' then
-- ram_we <= '1';
-- ram_dat_in <= dat_w(7 downto 0);
-- end if;
-- -- Read second byte if required
-- if re(0) = '1' then
-- tmp(7 downto 0) := ram_dat_out;
-- else
-- tmp(7 downto 0) := (others => 'U');
-- end if;
-- dat_r <= tmp;
-- state := S0;
-- end case;
-- end if;
--end process;
process (clk)
type state_type is (S0, S1, S2, S3, S4, S5);
variable state : state_type := S0;-- The current/next state
variable tmp : std_logic_vector(15 downto 0) := (others => '0');
begin
if rising_edge(clk) then
ram_en <= '1';
ram_we <= '0';
case state is
when S0 =>
state := S1;
when S1 =>
dat_r <= (others => 'U');
ram_addr <= conv_std_logic_vector(addr, 17);
state := S2;
when S2 =>
-- Write first byte if required
if we(1) = '1' then
ram_we <= '1';
ram_dat_in <= dat_w(15 downto 8);
end if;
state := S3;
when S3 =>
-- Read fist byte if required
if re(1) = '1' then
tmp(15 downto 8) := ram_dat_out;
else
tmp(15 downto 8) := (others => 'U');
end if;
state := S4;
ram_addr <= conv_std_logic_vector(addr + 1, 17);
when S4 =>
-- Write second byte if required
if we(0) = '1' then
ram_we <= '1';
ram_dat_in <= dat_w(7 downto 0);
end if;
state := S5;
when S5 =>
-- Read second byte if required
if re(0) = '1' then
tmp(7 downto 0) := ram_dat_out;
else
tmp(7 downto 0) := (others => 'U');
end if;
dat_r <= tmp;
state := S0;
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1598.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01598ent IS
END c08s11b00x00p03n01i01598ent;
ARCHITECTURE c08s11b00x00p03n01i01598arch OF c08s11b00x00p03n01i01598ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable done : boolean := false;
BEGIN
L1 : for i in boolean loop
while not done loop
done := true ;
exit ;
p := 0;
end loop ;
p := p + 1;
end loop L1;
assert NOT( p=2 )
report "***PASSED TEST: c08s11b00x00p03n01i01598"
severity NOTE;
assert ( p=2 )
report "***FAILED TEST: c08s11b00x00p03n01i01598 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01598arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1598.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01598ent IS
END c08s11b00x00p03n01i01598ent;
ARCHITECTURE c08s11b00x00p03n01i01598arch OF c08s11b00x00p03n01i01598ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable done : boolean := false;
BEGIN
L1 : for i in boolean loop
while not done loop
done := true ;
exit ;
p := 0;
end loop ;
p := p + 1;
end loop L1;
assert NOT( p=2 )
report "***PASSED TEST: c08s11b00x00p03n01i01598"
severity NOTE;
assert ( p=2 )
report "***FAILED TEST: c08s11b00x00p03n01i01598 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01598arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1598.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01598ent IS
END c08s11b00x00p03n01i01598ent;
ARCHITECTURE c08s11b00x00p03n01i01598arch OF c08s11b00x00p03n01i01598ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable done : boolean := false;
BEGIN
L1 : for i in boolean loop
while not done loop
done := true ;
exit ;
p := 0;
end loop ;
p := p + 1;
end loop L1;
assert NOT( p=2 )
report "***PASSED TEST: c08s11b00x00p03n01i01598"
severity NOTE;
assert ( p=2 )
report "***FAILED TEST: c08s11b00x00p03n01i01598 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01598arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_top
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_top-struct-conf-c.vhd,v 1.2 2004/08/18 10:46:56 wig Exp $
-- $Date: 2004/08/18 10:46:56 $
-- $Log: vgca_top-struct-conf-c.vhd,v $
-- Revision 1.2 2004/08/18 10:46:56 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vgca_top_struct_conf / vgca_top
--
configuration vgca_top_struct_conf of vgca_top is
for struct
-- Generated Configuration
for i_adc : vgca_video_adcs
use configuration work.vgca_video_adcs_struct_conf;
end for;
for i_cadc : vgca_cadc8_vin6
use configuration work.vgca_cadc8_vin6_struct_conf;
end for;
for i_dac : vgca_dac
use configuration work.vgca_dac_struct_conf;
end for;
for i_padframe : padframe
use configuration work.padframe_empty_conf;
end for;
for i_vgca : vgca
use configuration work.vgca_struct_conf;
end for;
for i_vgca_dcs_shell : vgca_dcs_shell
use configuration work.vgca_dcs_shell_struct_cfg;
end for;
for i_vgca_mcc_shell : vgca_mcc_shell
use configuration work.vgca_mcc_shell_struct_cfg;
end for;
for i_vgca_tc : vgca_tc
use configuration work.vgca_tc_struct_conf;
end for;
end for;
end vgca_top_struct_conf;
--
-- End of Generated Configuration vgca_top_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package int_types is
type small_int is range 0 to 255;
end package int_types;
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